Graphene integrated electrode LED epitaxial structure and chip preparation method

Abstract

The application discloses a graphene integrated electrode LED epitaxial structure and a chip preparation method, wherein the epitaxial structure comprises, from bottom to top, a GaAs substrate, an n-type GaAs buffer layer, an n-type confinement layer, an undoped quantum well structure, a p-type spacer layer, a p-type electron blocking layer and a p-type GaP ohmic contact layer; the preparation method comprises the whole process of epitaxial structure growth, p-type ITO transparent conductive layer preparation, bonding and substrate removal, mesa structure preparation, passivation isolation, graphene interconnection layer preparation and n-type electrode preparation; the graphene is used to replace the traditional n-type GaAs ohmic contact layer and ITO electrode, the problems of red light absorption, poor heat dissipation and mechanical brittleness of the traditional structure are solved, the red light transmittance of the chip is improved, the junction temperature is greatly reduced under a current of 3, the chip can withstand a tensile strain of more than 20%, is suitable for flexible scenes and is applicable to the high-performance and large-scale production of red light Micro LED.

Description

Technical Field

[0001] This invention relates to the field of LED chip manufacturing technology, specifically to a graphene integrated electrode LED epitaxial structure and chip fabrication method, which is particularly suitable for red Micro LED chips in the 620-650nm wavelength band. Background Technology

[0002] With the widespread application of Micro LED technology in displays, lighting, and wearable devices, performance optimization of red Micro LED chips has become a hot research topic in the industry. Currently, the mainstream quaternary AlGaInP red Micro LED chip epitaxial design still uses the traditional combination structure of n-type GaAs ohmic contact layer and n-type ITO transparent electrode, but this structure has significant technical defects:

[0003] 1. Severe loss of optical output power: The absorption coefficient of the n-type GaAs ohmic contact layer in the 620-650nm red light band is as high as > This results in a loss of more than 10% in light output power, which restricts the chip's luminous efficiency.

[0004] 2. Insufficient thermal management performance: The thermal conductivity of n-type ITO is only 10-15. , in 3 Under normal operating current, the junction temperature of the device is likely to exceed 85°C, which can cause significant thermal degradation and shorten the device's lifespan.

[0005] 3. Poor mechanical stability: n-type ITO has a fracture strain of <1.5%, and is significantly mechanically brittle, making it unsuitable for the flexibility requirements of new application scenarios such as curved displays and wearable devices.

[0006] In addition, the AlGaInP red LED targeted by this invention adopts a vertical structure with the light-emitting surface located on the n-type side, and the n-type ITO is a full array interconnect electrode (the p-type ITO has been divided into pixel-level sections). Therefore, the light absorption problem of the n-type GaAs ohmic contact layer, the heat dissipation bottleneck of the n-type ITO, and the mechanical brittleness have a more prominent impact on the overall performance of the device. Existing technologies cannot solve the above three core defects at the same time. Summary of the Invention

[0007] The purpose of this invention is to provide a graphene integrated electrode LED epitaxial structure and chip fabrication method, overcoming the technical defects of existing AlGaInP red light Micro LED chips, specifically solving the parasitic light absorption problem of traditional n-type GaAs ohmic contact layers in the red light band; the serious thermal decay problem caused by the poor thermal conductivity of traditional n-type ITO transparent electrodes; and the application scenarios limited by the mechanical brittleness of traditional n-type ITO.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] A graphene integrated electrode LED epitaxial structure comprises, from bottom to top, seven epitaxial functional layers that constitute the core carrier transport and light emission basis of the LED chip, specifically including:

[0010] GaAs substrate;

[0011] An n-type GaAs buffer layer is epitaxially grown on the GaAs substrate;

[0012] n-type epitaxially grown on the n-type GaAs buffer layer Constraint layer;

[0013] Epitaxial growth on the n-type Undoped InGaP / on confinement layer Quantum well structure;

[0014] p-type epitaxially grown on the quantum well structure Spacer layer;

[0015] Epitaxial growth on the p-type p-type on spacer layer Electron blocking layer;

[0016] Epitaxial growth on the p-type p-type GaP ohmic contact layer on electron blocking layer.

[0017] In a preferred embodiment, the GaAs substrate has the following parameters: wafer size 2-12 inches, thickness 350-650 μm, and bevel angle 2-15°.

[0018] In a preferred embodiment, the n-type GaAs buffer layer has the following doping source: silane, and the doping concentration is... Thickness 100-300nm; the n-type Confinement layer: The doping source is silane, and the doping concentration is... Thickness 150-500nm.

[0019] In a preferred embodiment, the quantum well structure has 1-5 quantum well pairs and an InGaP well layer thickness of 1.5-4.5 nm. The barrier layer thickness is 4-10 nm.

[0020] In a preferred embodiment, the p-type Spacer layer: doped source magnesium pyrocene, concentration Thickness 30-100nm; p-type Electron blocking layer: doped source magnesia, concentration Thickness 200-900nm; p-type GaP ohmic contact layer: doping source is magnesia-dicenocene and carbon tetrabromide in a molar ratio of 1:0.8-1.2, concentration Thickness 50-300nm.

[0021] This application also provides a method for fabricating a graphene integrated electrode LED epitaxial structure chip, comprising the following steps:

[0022] S1, Epitaxial Structure Growth: An n-type GaAs buffer layer and an n-type epitaxial structure are grown from bottom to top on a GaAs substrate using an MOCVD system. Confinement layer, undoped InGaP / Quantum well structure, p-type Spacer layer, p-type An electron blocking layer and a p-type GaP ohmic contact layer are used to obtain an epitaxial wafer.

[0023] S2, Preparation of p-type ITO transparent conductive layer: On the p-type GaP ohmic contact layer of the epitaxial wafer, a p-type ITO transparent conductive layer is deposited using EB, and then subjected to thermal annealing to improve conductivity and adhesion.

[0024] S3, Bonding and GaAs Substrate Removal: A bonding metal layer is deposited on a p-type ITO transparent conductive layer, and a bonding metal layer of the same composition is deposited on the front side of a Si-based CMOS driving circuit. After high-temperature and high-pressure bonding, the GaAs substrate is removed by a wet solution.

[0025] S4, Micro LED mesa structure fabrication: Patterned mesa is formed on the structure after substrate removal through photolithography and ICP etching to achieve device partitioning;

[0026] S5, Sidewall passivation and device isolation: Deposited using PECVD A sidewall passivation layer is then used, followed by IBE etching through the ITO transparent conductive layer and the bonding metal layer to achieve electrical isolation between devices;

[0027] S6, Graphene interconnect layer fabrication: fabrication of patterned layers Mask layer to expose n-type The confinement layer is formed by preparing a graphene film via CVD and then transferring it to the exposed area via a wet process to form a graphene interconnect layer.

[0028] S7, n-type electrode fabrication: On the graphene interconnect layer, n-type metal electrodes are deposited by photolithography and EB, and patterning is completed by a lift-off process to obtain a complete LED chip.

[0029] In a preferred embodiment, the MOCVD growth parameters in step S1 are as follows:

[0030] n-type GaAs buffer layer: growth temperature 620-700℃, growth rate 0.2-0.7nm / s, growth source is trimethylgallium + arsenide, carrier gas is hydrogen with purity ≥99.999%;

[0031] n-type Confinement layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylaluminum + trimethylgallium + trimethylindium + phosphine, carrier gas is hydrogen;

[0032] Undoped InGaP / Quantum well structure: growth temperature 700-780℃, growth rate 0.1-0.2nm / s, growth source is trimethylaluminum + trimethylgallium + trimethylindium + phosphine, carrier gas is hydrogen;

[0033] p-type Spacer layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylaluminum + trimethylgallium + trimethylindium + phosphine, carrier gas is hydrogen;

[0034] p-type Electron blocking layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylaluminum + trimethylindium + phosphine, carrier gas is hydrogen;

[0035] p-type GaP ohmic contact layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylgallium + phosphine, and carrier gas is hydrogen.

[0036] In a preferred embodiment, in step S2, the thickness of the ITO transparent conductive layer is 150 nm, the molar ratio of indium to tin in the target material is 9:1, and the EB deposition rate is 0.1-5 nm / s; the annealing temperature is 350-450℃, and the time is 160-200 s; in step S3, the bonding metal layer consists of 300 nm of Cr, 300 nm of Pt, and 200 nm of Au, with an EB deposition rate of 0.1-5 nm / s; the bonding temperature is 400-700℃, the pressure is 3000-9000 kg, and the time is 10-60 minutes; the wet solution is 10% ammonia water + 10% hydrogen peroxide in a volume ratio of 4:1, and the treatment time is 30-50 minutes.

[0037] In a preferred embodiment, in step S4, the photolithography uses spin-coating of positive resist with a resist thickness of 500-3000 nm and an ultraviolet exposure dose of 100-300 nm. The developer was a 2.38% TMAH aqueous solution, and the etching time was 100-140 seconds; the ICP etching gas was... + In step S5, PECVD deposition... The thickness is 10-100 nm, and the reactant gas is... and The power is 80-120W, the temperature is 230-270℃; the IBE etching power is 280-320W, the rate is 1-3nm / s, and the time is 550-650s.

[0038] In a preferred embodiment, in step S6, graphene is prepared by CVD using copper / nickel foil as the substrate, methane at a flow rate of 200-500 sccm as the reaction gas, at a temperature of 900-1100℃, and at a pressure of 0.1-10 Torr; the transfer is assisted by PMMA. The substrate is etched by solution and then annealed at 200-400℃ after transfer. In step S7, the n-type electrode is composed of 300nm Cr, 300nm Pt and 200nm Au. The EB deposition rate is 0.1-5nm / s. The photoresist is removed by immersion in acetone / isopropanol during the stripping process.

[0039] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0040] This invention achieves the following significant advantages by replacing the traditional n-type GaAs ohmic contact layer and n-type ITO transparent electrode with graphene, combined with optimized epitaxial structure and fabrication process:

[0041] 1. Significantly improved light output power: Graphene has a significantly improved light transmittance in the 620-650nm red light band compared to the traditional GaAs+ITO structure, resulting in a substantial increase in light output power and effectively solving the parasitic light absorption problem of the traditional structure.

[0042] 2. Significantly optimized heat dissipation performance: Graphene's in-plane thermal conductivity is two orders of magnitude higher than that of ITO. By constructing in-plane lateral heat conduction channels, the device achieves significantly improved heat dissipation performance. The junction temperature under current is significantly reduced, the device lifespan is greatly extended, and the thermal decay effect is effectively suppressed.

[0043] 3. Significantly enhanced mechanical stability: Graphene can withstand tensile strain of >20%, far exceeding the 1.5% limit of ITO; after 100,000 cycles at a bending radius of 1mm, the resistance change rate is <4.2%, while ITO has failed under the same conditions, making it suitable for flexible applications such as curved displays and wearable devices.

[0044] 4. Stable electrical performance: By optimizing the doping concentration, thickness, and process parameters of each epitaxial layer, the stability of graphene and n-type electrochemical bonding is ensured. The confinement layer forms a good ohmic contact while reducing the overall series resistance, ensuring stable current transport of the device. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a graphene integrated electrode LED epitaxial structure according to the present invention;

[0047] Figure 2 This is a flowchart of a chip fabrication method for a graphene integrated electrode LED epitaxial structure according to the present invention;

[0048] Figure 3 This is a schematic diagram of a graphene integrated electrode LED epitaxial structure according to the present invention.

[0049] Among them, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. n-type Confinement layer; 4. Undoped InGaP / Quantum well structure; 5. p-type Spacer layer; 6. p-type 7. Electron blocking layer; 8. p-type GaP ohmic contact layer; 9. Epitaxial wafer; 10. p-type ITO transparent conductive layer; 11. Bonding metal layer; 12. Si-based CMOS driving circuit; 13. Sidewall passivation layer; 14. Graphene interconnect layer; 15. n-type electrode. Detailed Implementation

[0050] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0052] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0053] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0054] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0055] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0056] Example 1

[0057] Please see Figure 1 This application provides a graphene integrated electrode LED epitaxial structure, consisting of 7 core epitaxial functional layers from bottom to top, forming the basis for carrier transport and light emission of the LED chip. Each layer works together to achieve carrier confinement, light emission, transport, and ohmic contact functions, as detailed below:

[0058] GaAs substrate 1: As the growth substrate of the entire epitaxial structure, it provides mechanical support and crystal orientation reference. Its parameters are wafer size 2-12 inches, thickness 350-650μm, and bevel angle 2-15°, providing a flat, low-defect surface for the growth of the upper epitaxial layer.

[0059] n-type GaAs buffer layer 2: Epitaxially grown on GaAs substrate 1, the doping source is silane, and the doping concentration is... With a thickness of 100-300 nm, it is used to provide a flat, low-defect epitaxial growth surface, so that the dislocation density of subsequent epitaxial layers is reduced from that of the substrate surface. Down to The following provides a fundamental guarantee for device performance.

[0060] n-type Confinement layer 3: Epitaxially grown on n-type GaAs buffer layer 2, where 0.7 ≤ ≤1, =0.5, doping source is silane, doping concentration With a thickness of 150-500nm, its core function is to restrict the diffusion of electrons out of the luminescent region and increase the recombination probability of charge carriers in the luminescent region.

[0061] Undoped InGaP / Quantum well structure 4: Epitaxially grown on n-type On layer 3, where 0.6≤ ≤0.9, =0.5, quantum well pair number 1-5 pairs, InGaP well layer thickness 1.5-4.5nm, The barrier layer, with a thickness of 4-10nm, is the core light-emitting region of the LED. It achieves red light emission in the 620-650nm band through the radiative recombination of electron-hole pairs within the quantum well.

[0062] p-type Spacer layer 5: Epitaxially grown on undoped InGaP / On quantum well structure 4, where 0.8≤ ≤0.9, =0.5, doping source is magnesia-dicenocene, doping concentration With a thickness of 30-100 nm, it is used to guide efficient transport of holes from the p-type region to the quantum well region, while isolating the electron blocking layer 6 from the quantum well to avoid the generation of interfacial nonradiative recombination centers from direct contact between the two layers. The choice of Al composition is also related to the p-type... Electron barrier layer 6 is adapted to avoid abrupt changes in the potential barrier that could hinder carrier transport.

[0063] p-type Electron blocking layer 6: Epitaxially grown on p-type On the spacer layer 5, among which =0.5, doping source is magnesia-dicenocene, doping concentration With a thickness of 200-900 nm, a high barrier is constructed to prevent electrons in the quantum well from leaking into the p-type region, further improving carrier recombination efficiency.

[0064] p-type GaP ohmic contact layer 7: Epitaxially grown on p-type On electron blocking layer 6, the doping sources are magnesium diacene and carbon tetrabromide in a molar ratio of 1:0.8-1.2, and the doping concentration is... With a thickness of 50-300nm, it is used to form a low-resistance ohmic contact with the transparent conductive layer, reducing contact resistance loss during current injection.

[0065] Example 2

[0066] Please see Figure 2-3 This application provides a method for fabricating a graphene integrated electrode LED epitaxial structure chip, including the entire process from epitaxial structure growth to the fabrication of the complete chip functional layer, with the following steps in sequence:

[0067] S1, Epitaxial Structure Growth: Using a metal-organic chemical vapor deposition (MOCVD) system, n-type GaAs buffer layer 2 and n-type GaAs layer 3 are sequentially grown from bottom to top on GaAs substrate 1. Confinement layer 3, undoped InGaP / Quantum well structure 4, p-type Spacer layer 5, p-type Electron blocking layer 6 and p-type GaP ohmic contact layer 7 are used to obtain epitaxial wafer 8.

[0068] Core MOCVD growth parameters for each layer: The carrier gas is hydrogen with a purity ≥ 99.999%; the growth temperature of the n-type GaAs buffer layer 2 is 620-700℃, the growth rate is 0.2-0.7 nm / s, and the growth source is trimethylgallium + arsenide; n-type Restriction layer 3, p-type Spacer layer 5 is grown at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s, using a growth source of trimethylaluminum + trimethylgallium + trimethylindium + phosphine; undoped InGaP / The quantum well structure 4 was grown at a temperature of 700-780℃ and a growth rate of 0.1-0.2 nm / s, using a growth source of trimethylaluminum + trimethylgallium + trimethylindium + phosphine; p-type. The electron blocking layer 6 is grown at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s, with the growth source being trimethylaluminum + trimethylindium + phosphine; the p-type GaP ohmic contact layer 7 is grown at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s, with the growth source being trimethylgallium + phosphine.

[0069] S2, Preparation of p-type ITO transparent conductive layer 9: On the p-type GaP ohmic contact layer 7 of the epitaxial wafer 8, a p-type ITO transparent conductive layer 9 with a thickness of 150 nm is deposited by electron beam evaporation (EB), with an indium-tin molar ratio of 9:1 and an EB deposition rate of 0.1-5 nm / s; After deposition, thermal annealing is performed at a temperature of 350-450℃ for 160-200 s to improve the conductivity and adhesion of the ITO transparent conductive layer.

[0070] S3, Bonding and Removal of GaAs Substrate 1: A bonding metal layer 10 is deposited on the p-type ITO transparent conductive layer 9. This bonding metal layer 10 consists of 300 nm of Cr, 300 nm of Pt, and 200 nm of Au, with an EB deposition rate of 0.1-5 nm / s. Simultaneously, a bonding metal layer 10 of the same composition is deposited on the front side of the Si-based CMOS driving circuit 11. The two bonding metal layers 10 are aligned and bonded together. High-temperature and high-pressure bonding is performed under conditions of 400-700℃ and 3000-9000 kg pressure for 10-60 minutes to allow the metals to fuse together and form a stable electromechanical connection. Subsequently, the GaAs substrate 1 is removed using a wet solution, which is a 4:1 volume ratio of 10% ammonia water + 10% hydrogen peroxide, for 30-50 minutes.

[0071] S4, Micro LED mesa structure fabrication: Patterned mesa structures are fabricated using photolithography and inductively coupled plasma (ICP) etching processes to achieve device partitioning; in the photolithography step, positive photoresist is spin-coated with a thickness of 500-3000 nm and an ultraviolet exposure dose of 100-300 nm. The developer was a 2.38% tetramethylammonium hydroxide (TMAH) aqueous solution, and the development time was 100-140 seconds; ICP etching was performed using... + As an etching gas, residual photoresist is removed after etching using organic solvents such as acetone / isopropanol.

[0072] S5, Sidewall passivation and device isolation: Deposited using plasma-enhanced chemical vapor deposition (PECVD). Sidewall passivation layer 12, Layer thickness 10-100nm, reactant gas is and The PECVD system has a power of 80-120W and a deposition temperature of 230-270℃. Subsequently, the ITO transparent conductive layer and the bonding metal layer 10 are etched through by ion beam etching (IBE). The IBE etching power is 280-320W, the etching rate is 1-3nm / s, and the etching time is 550-650s, so as to achieve electrical isolation between devices.

[0073] S6, Graphene interconnect layer 13 preparation: first deposited by PECVD The mask layer is then used to fabricate a pattern through photolithography and etching processes. Mask layer, exposing n-type Confinement layer 3; Graphene films were prepared on copper / nickel foil substrates using chemical vapor deposition (CVD). The CVD reaction gas was methane, with a flow rate of 200-500 sccm, a growth temperature of 900-1100℃, and a growth pressure of 0.1-10 Torr; Solution etching of the metal substrate, combined with PMMA-assisted transfer, allows for the complete transfer of the graphene film to the exposed n-type substrate. The surface of the confinement layer 3 is transferred and then annealed at 200-400℃ to enhance adhesion, forming the graphene interconnect layer 13.

[0074] S7, n-type electrode 14 fabrication: Photoresist is spin-coated on the graphene interconnect layer 13. After UV exposure and development, an n-type metal electrode is deposited using EB. The electrode consists of 300nm Cr, 300nm Pt and 200nm Au. The EB deposition rate is 0.1-5nm / s. Finally, the photoresist is removed by lift-off process and soaking in acetone / isopropanol. The remaining metal forms the patterned n-type electrode 14, resulting in a complete LED chip.

[0075] Example 3

[0076] This application provides a method for fabricating a graphene integrated electrode LED epitaxial structure chip, specifically including:

[0077] S1, Epitaxial structure growth: A GaAs substrate 1 with a wafer size of 4 inches, a thickness of 400 μm, and a bevel angle of 8° is selected and placed in the MOCVD reaction chamber.

[0078] Growth of n-type GaAs buffer layer 2: Carrier gas was hydrogen (99.999% purity), growth temperature was 650℃, growth rate was 0.5 nm / s, and trimethylgallium, arsenide, and disilane were introduced (flow rate 10 sccm). The growth thickness was 200 nm, and the doping concentration was... .

[0079] n-type growth Restriction layer 3 ( =0.8, =0.5): Temperature increased to 750℃, growth rate 0.3nm / s, trimethylaluminum, trimethylgallium, trimethylindium, phosphine, and silane were introduced (flow rate 15 sccm), growth thickness 300nm, doping concentration... .

[0080] Growth of undoped InGaP / Quantum well structure 4 ( =0.7, =0.5): Maintain a temperature of 750℃, a growth rate of 0.15nm / s, and alternately introduce InGaP well and barrier growth sources to grow 3 pairs of quantum wells with a well layer thickness of 3nm and a barrier layer thickness of 7nm.

[0081] growth p-type Spacer layer 5 ( =0.85, =0.5): Trimethylaluminum, trimethylgallium, trimethylindium, phosphine, and magnesium pyrocene were introduced (flow rate 12 sccm), growth rate 0.3 nm / s, growth thickness 60 nm, doping concentration .

[0082] growth p-type Electron blocking layer 6 ( =0.5): Trimethylaluminum, trimethylindium, phosphine, and magnesia-dicenocene (flow rate 20 sccm), growth rate 0.3 nm / s, growth thickness 500 nm, doping concentration... .

[0083] Growth of p-type GaP ohmic contact layer 7: Trimethylgallium, phosphine, magnesium pyrocene (flow rate 25 sccm), and carbon tetrabromide (flow rate 25 sccm, molar ratio 1:1) were introduced. The growth rate was 0.3 nm / s, the growth thickness was 150 nm, and the doping concentration was... , thus obtaining epitaxial wafer 8.

[0084] S2, Preparation of p-type ITO transparent conductive layer 9: A 150 nm thick p-type ITO transparent conductive layer 9 was deposited on the p-type GaP ohmic contact layer 7 using EB deposition, with an indium-tin molar ratio of 9:1 and a deposition rate of 1 nm / s; then annealed at 400 °C for 180 s.

[0085] S3, Bonding and Substrate Removal: A bonding metal layer 10 consisting of 300 nm of Cr, 300 nm of Pt, and 200 nm of Au is deposited on the p-type ITO transparent conductive layer 9 at a deposition rate of 1 nm / s; a bonding metal layer 10 of the same composition is deposited on the front side of the Si-based CMOS driving circuit 11, and bonded for 30 minutes at 500 °C and 4500 kg pressure; the GaAs substrate 1 is removed by treating with a mixed solution of 10% ammonia and 10% hydrogen peroxide in a volume ratio of 4:1 for 40 minutes.

[0086] S4, Mesa structure fabrication: Spin-coating 1500nm thick 5214 positive adhesive, UV exposure dose 200 Developed with 2.38% TMAH aqueous solution for 120 seconds; + ICP etching is performed using etching gas to form a mesa structure with a diameter of 20μm and a pixel pitch of 50μm. Residual photoresist is removed with acetone.

[0087] S5, Sidewall Passivation and Device Isolation: 50nm thick layer deposited using PECVD. passivation layer Flow rate 1200 sccm The flow rate was 300 sccm, the power was 100 W, and the temperature was 250 °C. Isolation was achieved by etching through the ITO transparent conductive layer and the bonding metal layer 10 using IBE etching (power 300 W, speed 2 nm / s, time 600 s).

[0088] S6, Graphene interconnect layer 13 fabrication: 300nm thick PECVD deposition The mask layer, after photolithography and development, is used... +Ar etching exposes n-type Confinement layer 3; monolayer graphene was prepared by CVD at 1000℃ and 3 Torr on a copper foil substrate using methane (flow rate 350 sccm) as the reactant gas; PMMA-assisted transfer was employed. The copper foil was etched with solution and then transferred and annealed at 300°C for 30 minutes.

[0089] S7, n-type electrode 14 fabrication: spin-coating photoresist and patterning, EB deposition of n-type electrode 14 composed of 300nm Cr / 300nm Pt / 200nm Au, acetone soaking to remove photoresist, obtaining complete chip.

[0090] Example 4

[0091] The difference from Example 3 is as follows:

[0092] The quantum wells have 2 pairs, the well layer thickness is 2nm, and the barrier layer thickness is 6nm.

[0093] The bonding temperature is 450℃, the bonding pressure is 4000kg, and the bonding time is 25 minutes.

[0094] The methane flow rate was 300 sccm and the growth pressure was 2 Torr during graphene growth.

[0095] Example 5

[0096] The difference from Example 3 is as follows:

[0097] In the p-type GaP ohmic contact layer 7, the molar ratio of magnesia to carbon tetrabromide is 1:0.9;

[0098] The annealing temperature of the ITO transparent conductive layer is 420℃, and the annealing time is 170s.

[0099] The passivation layer thickness is 80 nm, and the IBE etching time is 620 s.

[0100] The chips prepared in the above embodiments were tested and found to have a transmittance >97% in the 620-650nm red light band. With a junction temperature ≤68℃ under current and a resistance change rate <4.2% after 100,000 cycles with a 1mm bending radius, it meets the high performance and flexible application requirements of red Micro LED.

[0101] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A graphene integrated electrode LED epitaxial structure, characterized in that, From bottom to top, there are 7 epitaxial functional layers that constitute the core carrier transport and light emission basis of the LED chip, specifically including: GaAs substrate; An n-type GaAs buffer layer is epitaxially grown on the GaAs substrate; n-type epitaxially grown on the n-type GaAs buffer layer Constraint layer; Epitaxial growth on the n-type Undoped InGaP / on confinement layer Quantum well structure; p-type epitaxially grown on the quantum well structure Spacer layer; Epitaxial growth on the p-type p-type on spacer layer Electron blocking layer; Epitaxial growth on the p-type p-type GaP ohmic contact layer on electron blocking layer.

2. The graphene integrated electrode LED epitaxial structure according to claim 1, characterized in that, The parameters of the GaAs substrate are: wafer size 2-12 inches, thickness 350-650μm, and bevel angle 2-15°.

3. The graphene integrated electrode LED epitaxial structure according to claim 1, characterized in that, The n-type GaAs buffer layer: the doping source is silane, and the doping concentration is... Thickness 100-300nm; the n-type Confinement layer: The doping source is silane, and the doping concentration is... Thickness 150-500nm.

4. The graphene integrated electrode LED epitaxial structure according to claim 1, characterized in that, The quantum well structure has 1-5 quantum well pairs and an InGaP well layer thickness of 1.5-4.5 nm. The barrier layer thickness is 4-10 nm.

5. The graphene integrated electrode LED epitaxial structure according to claim 1, characterized in that, The p-type Spacer layer: doped source magnesium pyrocene, concentration Thickness 30-100nm; p-type Electron blocking layer: doped source magnesia, concentration Thickness 200-900nm; p-type GaP ohmic contact layer: doping source is magnesia-dicenocene and carbon tetrabromide in a molar ratio of 1:0.8-1.2, concentration Thickness 50-300nm.

6. A method for fabricating a chip based on the graphene integrated electrode LED epitaxial structure according to any one of claims 1-5, characterized in that, Includes the following steps: S1, Epitaxial Structure Growth: An n-type GaAs buffer layer and an n-type epitaxial structure are grown from bottom to top on a GaAs substrate using an MOCVD system. Confinement layer, undoped InGaP / Quantum well structure, p-type Spacer layer, p-type An electron blocking layer and a p-type GaP ohmic contact layer are used to obtain an epitaxial wafer. S2, Preparation of p-type ITO transparent conductive layer: On the p-type GaP ohmic contact layer of the epitaxial wafer, a p-type ITO transparent conductive layer is deposited using EB, and then subjected to thermal annealing to improve conductivity and adhesion. S3, Bonding and GaAs Substrate Removal: A bonding metal layer is deposited on a p-type ITO transparent conductive layer, and a bonding metal layer of the same composition is deposited on the front side of a Si-based CMOS driving circuit. After high-temperature and high-pressure bonding, the GaAs substrate is removed by a wet solution. S4, Micro LED mesa structure fabrication: Patterned mesa is formed on the structure after substrate removal through photolithography and ICP etching to achieve device partitioning; S5, Sidewall passivation and device isolation: Deposited using PECVD A sidewall passivation layer is then used, followed by IBE etching through the ITO transparent conductive layer and the bonding metal layer to achieve electrical isolation between devices; S6, Graphene interconnect layer fabrication: fabrication of patterned layers Mask layer to expose n-type The confinement layer is formed by preparing a graphene film via CVD and then transferring it to the exposed area via a wet process to form a graphene interconnect layer. S7, n-type electrode fabrication: On the graphene interconnect layer, n-type metal electrodes are deposited by photolithography and EB, and patterning is completed by a lift-off process to obtain a complete LED chip.

7. The chip fabrication method of the graphene integrated electrode LED epitaxial structure according to claim 6, characterized in that, MOCVD growth parameters in step S1: n-type GaAs buffer layer: growth temperature 620-700℃, growth rate 0.2-0.7nm / s, growth source is trimethylgallium + arsenide, carrier gas is hydrogen with purity ≥99.999%; n-type Confinement layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylaluminum + trimethylgallium + trimethylindium + phosphine, carrier gas is hydrogen; Undoped InGaP / Quantum well structure: growth temperature 700-780℃, growth rate 0.1-0.2nm / s, growth source is trimethylaluminum + trimethylgallium + trimethylindium + phosphine, carrier gas is hydrogen; p-type Spacer layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylaluminum + trimethylgallium + trimethylindium + phosphine, carrier gas is hydrogen; p-type Electron blocking layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylaluminum + trimethylindium + phosphine, carrier gas is hydrogen; p-type GaP ohmic contact layer: growth temperature 700-780℃, growth rate 0.2-0.5nm / s, growth source is trimethylgallium + phosphine, and carrier gas is hydrogen.

8. The chip fabrication method of the graphene integrated electrode LED epitaxial structure according to claim 6, characterized in that, In step S2, the thickness of the ITO transparent conductive layer is 150 nm, the molar ratio of indium to tin in the target is 9:1, and the EB deposition rate is 0.1-5 nm / s; the annealing temperature is 350-450℃, and the time is 160-200 s; in step S3, the bonding metal layer consists of 300 nm of Cr, 300 nm of Pt, and 200 nm of Au, with an EB deposition rate of 0.1-5 nm / s; the bonding temperature is 400-700℃, the pressure is 3000-9000 kg, and the time is 10-60 minutes; the wet solution is 10% ammonia water + 10% hydrogen peroxide in a volume ratio of 4:1, and the treatment time is 30-50 minutes.

9. The chip fabrication method of the graphene integrated electrode LED epitaxial structure according to claim 6, characterized in that, In step S4, photolithography uses spin-coating of positive resist with a resist thickness of 500-3000 nm and an ultraviolet exposure dose of 100-300 nm. The developer was a 2.38% TMAH aqueous solution, and the etching time was 100-140 seconds; the ICP etching gas was... + In step S5, PECVD deposition... The thickness is 10-100 nm, and the reactant gas is... and The power is 80-120W, the temperature is 230-270℃; the IBE etching power is 280-320W, the speed is 1-3nm / s, and the time is 550-650s.

10. The chip fabrication method of the graphene integrated electrode LED epitaxial structure according to claim 6, characterized in that, In step S6, graphene is prepared by CVD using copper / nickel foil as the substrate. The reaction gas is methane at a flow rate of 200-500 sccm, the temperature is 900-1100℃, and the pressure is 0.1-10 Torr. Transfer is assisted by PMMA. The substrate is etched by solution and then annealed at 200-400℃ after transfer. In step S7, the n-type electrode is composed of 300nm Cr, 300nm Pt and 200nm Au. The EB deposition rate is 0.1-5nm / s. The photoresist is removed by immersion in acetone / isopropanol during the stripping process.

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