Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first substrate, and the first substrate comprises a first opening; the first signal transmission layer comprises a first signal transmission part, and the first signal transmission part and the first opening are at least partially overlapped in the thickness direction of the display panel; the second substrate comprises a second opening; the light shielding layer comprises a light shielding part and a switching part, and the switching part at least partially covers the second opening; the active layer comprises an active part, and the active part and the shading part are at least partially overlapped in the thickness direction of the display panel; the second signal transmission layer is located on the side, away from the first substrate, of the active layer, and the second signal transmission layer comprises a second signal transmission part; the second signal transmission part is electrically connected with the switching part through the via hole, and the switching part is electrically connected with the first signal transmission part, so that the size of the lower frame can be reduced, and the display effect of the display panel can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of information technology, display panels are widely used in the fields of automobile electronics, industry and medical treatment, smart home and Internet, etc.

[0003] At present, the fan-out wires of the lower edge of the display panel are bent by 180 degrees to the back surface and are bound to the driving chip by binding. However, the lower frame size of the display panel is still large by using this method, and therefore, it is necessary to continue to improve the lower frame size of the display panel. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device to reduce the lower frame of the display panel and realize the miniaturization of the display panel.

[0005] In a first aspect, embodiments of the present application provide a display panel, comprising: a first substrate, the first substrate comprising a first opening;

[0006] a first signal transmission layer located on one side of the first substrate, the first signal transmission layer comprising a first signal transmission part, the first signal transmission part at least partially overlapping the first opening in the thickness direction of the display panel;

[0007] a second substrate located on the side of the first signal transmission layer away from the first substrate, the second substrate comprising a second opening;

[0008] a light shielding layer located on the side of the second substrate away from the first signal transmission layer, the light shielding layer comprising a light shielding part and a switching part, the switching part at least partially covering the second opening;

[0009] an active layer located on the side of the light shielding layer away from the first substrate, the active layer comprising an active part, the active part at least partially overlapping the light shielding part in the thickness direction of the display panel;

[0010] a second signal transmission layer located on the side of the active layer away from the first substrate, the second signal transmission layer comprising a second signal transmission part;

[0011] wherein the second signal transmission part is electrically connected to the switching part through a via hole, and the switching part is electrically connected to the first signal transmission part.

[0012] In a second aspect, embodiments of the present application further provide a display device comprising the display panel of the first aspect.

[0013] The technical solution provided by this invention includes a display panel comprising a light-shielding layer. An active layer is located on the side of the light-shielding layer away from the first substrate, and the active portion and the light-shielding portion at least partially overlap along the thickness direction of the display panel. Thus, the light-shielding portion can serve as a light-shielding structure for the channel region, preventing light from entering the channel region and causing light leakage, thereby improving the display effect of the display panel. Furthermore, a second signal transmission portion is electrically connected to a transition portion via a via, and the transition portion is electrically connected to a first signal transmission portion. This allows signal transmission between the first and second signal transmission layers through the transition portion. Therefore, the display panel can be displayed normally without bending it, and the bezel size of the display panel can be reduced, which is beneficial for miniaturization and integration of the display panel. Attached Figure Description

[0014] Figure 1 A top view schematic diagram of a first type of display panel provided in an embodiment of the present invention;

[0015] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the provided display panel along section line A-A';

[0016] Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the provided display panel along section line B-B';

[0017] Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure of the provided display panel along section line C-C';

[0018] Figure 5 for Figure 1 A schematic diagram of the cross-sectional structure of the provided display panel along the second direction;

[0019] Figure 6 An electrical schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0020] Figure 7 for Figure 6 The diagram shows the driving timing of the pixel circuit during one driving cycle.

[0021] Figure 8 A top view schematic diagram of a second type of display panel provided in an embodiment of the present invention;

[0022] Figure 9 for Figure 8 A schematic diagram of the cross-sectional structure of the corresponding display panel along section line D-D';

[0023] Figure 10 An electrical schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0026] Figure 1 This is a top view schematic diagram of the first type of display panel provided in an embodiment of the present invention. Figure 2 for Figure 1 The provided schematic diagram shows the cross-sectional structure of the display panel along section line A-A', as follows: Figure 1 and Figure 2 As shown, the display panel 100 includes a first substrate 10, the first substrate 10 including a first opening 101; a first signal transmission layer 20, located on one side of the first substrate 10, the first signal transmission layer 20 including a first signal transmission portion 201, extending along the thickness direction of the display panel (e.g., ...). Figure 2 (In the Z direction shown), the first signal transmission section 201 at least partially overlaps with the first opening 101; the second substrate 30 is located on the side of the first signal transmission layer 20 away from the first substrate 10, and the second substrate 30 includes the second opening 301; the light-shielding layer 40 is located on the side of the second substrate 30 away from the first signal transmission layer 20, and the light-shielding layer 40 includes a light-shielding section 401 and a transition section 402, the transition section 402 at least partially covering the second opening 301; the active layer 50 is located on the side of the light-shielding layer 40 away from the first signal transmission layer 101. On one side of a substrate 10, an active layer 50 includes an active portion 501, which overlaps at least partially with a light-shielding portion 401 along the thickness direction Z of the display panel; a second signal transmission layer 60 is located on the side of the active layer 50 away from the first substrate 10, and the second signal transmission layer 60 includes a second signal transmission portion 601; wherein the second signal transmission portion 601 is electrically connected to a transition portion 402 through a via 70, and the transition portion 402 is electrically connected to a first signal transmission portion 201.

[0027] Specifically, a plurality of light emitting elements 200, pixel circuits 300 and signal lines 400 can be arranged in the display area AA. The pixel circuit 300 is electrically connected to the light emitting element 200 and configured to provide a display signal to the light emitting element 200 to realize the display function of the display panel 100. The signal line 400 can be electrically connected to the pixel circuit 300 or serve as a signal line for other auxiliary functions. For example, the signal line 400 can include a scan signal line 401 and a data signal line 402. The scan signal line 401 can provide a scan signal to the pixel circuit 300 to control the on and off of the transistor in the pixel circuit 300. The data signal line 402 can provide a data signal to the pixel circuit 300 to control the transistor in the pixel circuit 300 to generate a driving current signal based on the data signal and write the driving current signal into the first electrode (e.g., anode) in the light emitting element 200 to realize the normal light emission or light emission of the light emitting element 200 and realize the display function of the display panel.

[0028] Specifically, continuing to refer to Figures 1-4 , the first signal transmission layer 20 includes a plurality of independently arranged first signal transmission parts 201. For example, the first signal transmission part 201 can include a first clock signal transmission part CK for transmitting a clock signal ck, a second clock signal transmission part XCK for transmitting a reverse clock signal xck, a first level power signal transmission part VGH for transmitting a high-level signal vgh, a second level power signal transmission part VGL for transmitting a low-level signal vgl, and a data signal transmission part Vdata for transmitting a data signal data.

[0029] Continuing to refer to Figure 2 , the first signal transmission part 201 can be the data signal transmission part Vdata. The data signal data output by the driving structure 80 is transmitted to the pixel circuit 300 through the data signal transmission part Vdata so that the pixel circuit 300 outputs a display signal to the light emitting element 200 based on the data signal data.

[0030] Figure 3 For Figure 1 the display panel provided by the embodiment of the present application, a cross-sectional structure schematic view along the cross-sectional line B-B’ is shown in FIG. 4, Figure 4 for Figure 1 the display panel provided by the embodiment of the present application, a cross-sectional structure schematic view along the cross-sectional line C-C’ is shown in FIG. 5, as Figure 3 and Figure 4As shown, the first signal transmission part 201 can be one or more of a first clock signal transmission part CK, a second clock signal transmission part XCK, a first level power signal transmission part VGH, and a second level power signal transmission part VGL. The display driving signal output by the driving structure 80 is transmitted to the pixel driving circuit 90 through at least one first signal transmission part 201, so that the pixel driving circuit 90 drives the pixel circuit 300 to provide the display signal to the light emitting element 200.

[0031] For example, the pixel driving circuit 90 can be a vertical shift register (VSR). The driving mode of the pixel driving circuit 90 can be divided into single-side driving and double-side driving according to the position and working mode of the driving circuit. The single-side driving (not shown in the figure) is to arrange the pixel driving circuit 90 on one side of the display panel, and output the scanning signal row by row through the single-side driving mode to realize the scanning driving of the pixel circuit in the display panel. Figure 1 As shown, the driving circuits arranged on both sides of the display panel output the scanning signal at the same time or at different times to realize the scanning driving of the pixel circuit in the display panel.

[0032] Specifically, continuing to refer to Figure 2 The first substrate 10 can support the film structure above the film layer. The second substrate 30 is located on the side of the first signal transmission layer 20 away from the first substrate 10, and the second substrate 30 includes a second opening 301, so that the adapter part 402 is in contact and electrically connected with the first signal transmission part 201 through the second opening 301. For example, the materials of the first substrate 10 and the second substrate 30 can both be polyimide. On the one hand, the polyimide material has high temperature resistance, which can meet the needs of high temperature process in the preparation process of the display panel. On the other hand, the polyimide material has good ductility, which can ensure the bendable setting of the display panel.

[0033] Specifically, continuing to refer to Figure 2 The light shielding layer 40 is located on the side of the second substrate 30 away from the first signal transmission layer 20, and the light shielding layer 40 includes a light shielding part 401 and an adapter part 402. The light shielding part 401 and the adapter part 402 can be prepared at the same time, so that the preparation process is simple. The active layer 50 is located on the side of the light shielding layer 40 away from the first substrate 10, and the active layer 50 includes an active part 501. The active layer 50 can be understood as an active layer in the transistor in the pixel circuit 300. Along the thickness direction Z of the display panel, the active part 501 at least partially overlaps with the light shielding part 401, so that the light shielding part 401 can be used as a light shielding structure of the channel region to avoid light from entering the channel region to form light leakage, thereby improving the display effect of the display panel.

[0034] Specifically, with continued reference to Figure 2 The second signal transmission layer 60 is located on the side of the active layer 50 away from the first substrate 10, and the second signal transmission layer 60 includes a second signal transmission part 601, that is, the second signal transmission part 601 is used to write a driving current signal into a first electrode (such as an anode) in the light-emitting element 200, so as to realize normal light emission or light emission of the light-emitting element 200, and realize the display function of the display panel. The second signal transmission part 601 is electrically connected to the switching part 402 through the via hole 70, and the switching part 402 is electrically connected to the first signal transmission part 201. In this way, the first signal transmission part 201 can sequentially transmit signals to the first electrode in the light-emitting element 200 through the switching part 402, the via hole 70 and the second signal transmission part 601. That is, the signal transmission between the first signal transmission part 201 and the second signal transmission part 601 can be realized through the switching part 402 and the via hole 70, so as to realize the normal light emission or light emission of the light-emitting element 200. In this way, the display panel does not need to be bent, and the normal display of the display panel can be realized, and the small frame size of the display panel can be reduced. The size of the lower frame of the display panel in the prior art can be reduced from 0.8 mm to less than 0.5 mm, thereby facilitating the miniaturization and integration of the display panel.

[0035] The display panel provided by the embodiment of the present application is at least partially overlapped with the active part and the light shielding part in the thickness direction of the display panel. In this way, the light shielding part can be used as a light shielding structure of the channel region, so as to avoid light from being incident on the channel region to form a light leakage current, thereby improving the display effect of the display panel. In addition, the second signal transmission part is electrically connected to the switching part through the via hole, and the switching part is electrically connected to the first signal transmission part. In this way, the signal transmission between the first signal transmission layer and the second signal transmission layer can be realized through the switching part. In this way, the display panel does not need to be bent, and the normal display of the display panel can be realized, and the small frame size of the display panel can be reduced, thereby facilitating the miniaturization and integration of the display panel.

[0036] Optionally, with continued reference to Figure 2 In the thickness direction Z of the display panel, the first opening 101 and the second opening 103 are arranged in a staggered manner.

[0037] Specifically, if the first opening 101 and the second opening 103 are arranged in an overlapping manner in the thickness direction Z of the display panel, deformation will occur in the overlapping area due to the poor mechanical properties, which will cause damage to the display panel. The embodiment of the present application arranges the first opening 101 and the second opening 103 in a staggered manner in the thickness direction Z of the display panel, that is, the first opening 101 and the second opening 103 are not overlapped. In this way, the display panel can be prevented from deforming or being damaged, thereby prolonging the service life of the display panel.

[0038] Optionally, with continued reference to Figure 2The adapter 402 includes a first adapter sub-portion 4021, a second adapter sub-portion 4022, and a third adapter sub-portion 4023. The first adapter sub-portion 4021 is located on the side of the second substrate 30 away from the first substrate 10 and is connected to the second signal transmission layer 60. The second adapter sub-portion 4022 and the third adapter sub-portion 4023 are both located in the second opening 301. The second adapter sub-portion 4022 is connected to the first adapter sub-portion 4021 and the third adapter sub-portion 4023. The third adapter sub-portion 4023 is connected to the first signal transmission layer 20. The plane on which the first adapter sub-portion 4021 is located is parallel to the plane on which the first substrate 10 is located. The plane on which the second adapter sub-portion 4022 is located intersects the plane on which the first substrate 10 is located. The plane on which the third adapter sub-portion 4023 is located is parallel to the plane on which the first substrate 10 is located.

[0039] Specifically, the adapter 402 includes a first adapter sub-portion 4021, a second adapter sub-portion 4022, and a third adapter sub-portion 4023. The first adapter sub-portion 4021 is located on the upper surface of the second substrate 30 and is electrically connected to the second signal transmission layer 60. The second adapter sub-portion 4022 and the third adapter sub-portion 4023 are both located in the second opening 301. The first end of the second adapter sub-portion 4022 is in contact with and electrically connected to the first adapter sub-portion 4021. The second end of the second adapter sub-portion 4022 is in contact with and electrically connected to the third adapter sub-portion 4023. The third adapter sub-portion 4023 is in contact with and electrically connected to the first signal transmission layer 20.

[0040] For example, continuing to refer to Figure 2 The first signal transmission portion 201 can be a data signal transmission portion Vdata. The data signal data output by the driving structure 80 is transmitted to the pixel circuit 300 through the data signal transmission portion Vdata, so that the pixel circuit 300 outputs a display signal to the light emitting element 200 based on the data signal data. Thus, the second adapter sub-portion 4022 can be an adapter sub-portion covering the side wall on one side of the second opening 301. The third adapter sub-portion 403 can be an adapter sub-portion covering the bottom of the second opening 301. That is, the shape of the adapter 402 can be similar to a “Z” shape.

[0041] For example, continuing to refer to Figure 3The first signal transmission unit 201 can be a first-level power signal transmission unit VGH and / or a second-level power signal transmission unit VGL. Furthermore, the first-level power signal transmission unit VGH can transmit a high-level power signal to the input terminal of the first-level power transistor through the adapter 402, and the second-level power signal transmission unit VGL can transmit a low-level power signal to the input terminal of the second-level power transistor through the adapter 402, so that the transistor in the pixel driving circuit 90 outputs a scanning signal to the pixel circuit 300, thereby controlling the conduction and cutoff of the transistor in the pixel circuit 300 to realize the display function of the display panel. Thus, the second transition section 4022 can be a transition section covering one side wall of the second opening 301, and the third transition section 403 can be a transition section covering the bottom of the second opening 301. Taking the pixel driving circuit 90 located in the non-display area NA as an example, the transition section 402 located in the display area AA needs to extend to the non-display area NA in order to make electrical connection with the pixel driving circuit 90 located in the non-display area NA. Thus, the shape of the transition section 402 can be similar to an inverted "V" shape.

[0042] For example, continue to refer to Figure 4 The first signal transmission unit 201 can be a first clock signal transmission unit CK or a second clock signal transmission unit XCK. The first clock signal or the second clock signal output by the driving structure 80 can be transmitted to the gate of the pixel driving circuit 90 through the first signal transmission unit 201, such as the bottom gate 9024 of the pixel driving circuit 90. By controlling the change of the gate voltage, the transistor in the pixel driving circuit 90 can be turned on and off, thereby completing the timing control and signal driving of the circuit.

[0043] Optional, continue to refer to Figure 2 The first transition section 4021 includes a first side a1; along a first direction (such as... Figure 2 (As shown in the X direction), the first side surface a1 is the surface of the first transition portion a1 away from the second transition portion 4022; the second transition portion 4022 includes a second side surface a2; along the first direction X, the second side surface a2 is the surface of the second transition portion 4022 away from the first transition portion 4021; along the first direction X, the maximum distance D1 between the first side surface a1 and the second side surface a2 satisfies: D1 > 1 μm; the first direction X is parallel to the plane where the first substrate 10 is located and intersects with the thickness direction Z of the display panel.

[0044] Specifically, along the first direction X, the maximum distance between the first side a1 and the second side a2 can be understood as the distance between the leftmost end of the first transition section 4021 and the rightmost end of the second transition section 4022.

[0045] For example, when D1<1 μm, that is, the maximum distance D1 between the first side surface a1 and the second side surface a2 in the first direction X is small, it is difficult to manufacture, and the signal transmission effect between the first signal transmission part 201 and the second signal transmission part 601 is poor due to the small size of the adapter part 402. In the embodiment of the present application, D1>1 μm is set, so that on the one hand, the manufacturing process is matched, and on the other hand, the signal adapter effect of the quasi-adapter part 402 between the first signal transmission part 201 and the second signal transmission part 601 is ensured, thereby being beneficial to ensuring the display performance of the display panel.

[0046] Optionally, continuing to refer to Figure 2 , the angle θ between the second adapter part 4022 and the first direction X satisfies: 70°≤θ≤80°; the first direction X is parallel to the plane in which the first substrate 10 is located, and intersects the thickness direction Z of the display panel.

[0047] Specifically, in the process of manufacturing the adapter part 402, the second opening 301 is first manufactured in the second substrate 30, then the adapter part 402 is manufactured on the side of the second opening 301 away from the first substrate 10, and then the buffer layer is manufactured on the side of the adapter part 402 away from the first substrate 10. In this way, in the process of manufacturing the adapter part 402, the second adapter part 4022 covers the sidewall of the second opening 301, that is, the angle between the second adapter part 4022 and the first direction X is related to the inclination angle of the sidewall of the second opening 301. The angle θ between the second adapter part 4022 and the first direction X satisfies: 70°≤θ≤80°, so that on the one hand, the manufacturing process of the second opening 301 is matched, and on the other hand, the stability of the mutual connection between the first adapter part 4021, the second adapter part 4022 and the third adapter part 4023 is ensured, thereby ensuring the signal adapter effect of the adapter part 402 between the first signal transmission part 201 and the second signal transmission part 601, and thereby ensuring the display effect of the display panel.

[0048] Optionally, Figure 5 For Figure 1 The display panel provided has a cross-sectional structure along the second direction, as shown in Figure 1 and 5 , along the second direction (such as the Y direction shown in Figure 5 , the distance D2 between two adjacent adapter parts 402 satisfies: 0.3mm≤D2≤0.5mm; the second direction Y intersects the plane in which the first substrate 10 is located, and intersects the thickness direction Z of the display panel.

[0049] Specifically, referring to Figure 1The second direction is a direction perpendicular to the paper, and the distance between the two adjacent transition portions 402 along the second direction Y is related to the distance between the two adjacent second openings 301. For example, when D2<0.3 mm, the distance between the two adjacent transition portions 402 is small, that is, the distance between the two adjacent second openings 301 along the second direction Y is small, that is, the second openings 301 are densely arranged, so that the stability and reliability of the display panel are poor. For example, when D2>0.5 mm, the distance between the two adjacent transition portions 402 is large, that is, the distance between the two adjacent second openings 301 along the second direction Y is large, so that the integration and miniaturization of the display panel cannot be realized.

[0050] The embodiment of the present application sets 0.3 mm≤D2≤0.5 mm, so that the distance between the two adjacent transition portions 402 is moderate, that is, the distance between the two adjacent second openings 301 along the second direction Y is moderate, which can ensure the stability and reliability of the display panel on the one hand, and can realize the integration and miniaturization of the display panel on the other hand.

[0051] Optionally, continuing to refer to Figure 2 The light shielding portion 401 includes a gate, that is, the light shielding portion 401 can be a bottom gate of the transistor in the pixel circuit 300, so that the bottom gate can be used as a light shielding structure of the channel region to avoid light from entering the channel region to form light leakage, thereby improving the display effect of the display panel. In addition, it is beneficial to realize the diversification of the light shielding portion 401 and the display panel. Moreover, the transistor in the pixel circuit 300 adopts a top-bottom double-gate structure, so that the channel charge distribution can be more accurately controlled through the synergistic effect of the two gates, realizing higher switching speed, lower leakage current and better device performance.

[0052] Optionally, continuing to refer to Figure 1 and Figure 2 The display panel 100 further includes a pixel circuit 300; the pixel circuit is located in the display area AA; the pixel circuit 300 includes a first transistor 3001, the first transistor 3001 includes a first input electrode 301, a first output electrode 302 and a first gate 303; the first input electrode 301 is electrically connected with the transition portion 402.

[0053] Specifically, the pixel circuit 300 includes a first transistor 3001, the first transistor 3001 includes a first input electrode 301, a first output electrode 302, and a first gate 303. For example, the first input electrode 301 can be a source electrode, and the first output electrode 302 can be a drain electrode. The first gate 303 is arranged corresponding to a channel region of the active layer 50, the source electrode is arranged corresponding to a source region of the active layer 50, and the drain electrode is arranged corresponding to a drain region of the active layer 50. Under the action of the first gate 303 signal, the channel region is turned on and changes from a non-conductor state to a conductor state, a path is formed between the corresponding source electrode and the drain electrode, and a data signal can be sequentially written into the drain electrode through the source electrode and the channel region. For example, the first gate 303 provided by the embodiment of the present application can be located on a side of the active layer 50 away from the substrate 10, that is, the first gate 303 can be a top gate.

[0054] Specifically, the first input electrode 301 is electrically connected with the adapter 402, so that the data signal output by the driving structure 80 is sequentially transmitted to the first input electrode 301 through the first signal transmission part 201, the adapter 402, the via hole 70, and the second signal transmission part 601, so as to make the pixel circuit 300 output a display signal to the light emitting element 200 based on the data signal data.

[0055] Optionally, continuing to refer to Figure 2 , the first signal transmission part 201 includes a data signal transmission part Vdata, and the adapter 402 includes a data signal adapter 402-11.

[0056] Specifically, the data signal data output by the driving structure 80 is transmitted to the data signal adapter 402-11 through the data signal transmission part Vdata, and then transmitted to the first input electrode 301 by the data signal adapter 402-11, so as to make the pixel circuit 300 output a display signal to the light emitting element 200 based on the data signal data.

[0057] For example, Figure 6 is an electrical principle diagram of a pixel circuit provided by the embodiment of the present application, Figure 7 is Figure 6 is a driving timing diagram of the pixel circuit shown in the embodiment of the present application in a driving period. Figure 6 and Figure 7 As shown in FIG. 7, the types of the transistors in the pixel circuit 300 can be diverse. For example, the transistors can include a low temperature poly-silicon transistor (LTPS), which has advantages of high switching speed, high carrier mobility, and small power. The transistors can also include an oxide transistor (IGZO), which has an advantage of small leakage current. Figure 6For example, the pixel circuit is a "7T1C" pixel circuit, where "T" represents a transistor and "C" represents a capacitor. The embodiments of the present application are described by way of example only, and other pixel circuits, such as a "6T1C" pixel circuit, an "8T1C" pixel circuit, and the like, are within the scope of the technical solutions protected by the embodiments of the present application.

[0058] For example, continuing to refer to Figure 6 and Figure 7 , the pixel circuit can include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization transistor T5, a second light-emitting control transistor T6, a reset transistor T7, and a storage capacitor Cst. For example, for the working process of the pixel circuit, refer to Figure 6 and Figure 7 , the first scan signal line S1 can control the on and off of the initialization transistor T5 of the pixel circuit, and reset the gate potential of the driving transistor T3 when the initialization transistor T5 is turned on, that is, the initialization signal of the initialization signal line VREF1 is transmitted to the initialization transistor T5 and the connection node (first node N1) of the driving transistor T3, the initialization transistor T5, the threshold compensation transistor T4, and the storage capacitor Cst is reset. The third scan signal line SP* controls the on and off of the data writing transistor T2 of the pixel circuit, and writes the data signal on the data signal line Data to the gate of the driving transistor T3 when the data writing transistor T2 is turned on. The second scan signal line S2 can control the on and off of the threshold compensation transistor T4, and compensate the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is turned on. At the same time, the fourth scan signal line SP controls the on and off of the reset transistor T7, and resets the anode of the light-emitting element connected to the pixel circuit when the reset transistor T7 is turned on, that is, the reset signal of the reset signal line VREF2 is transmitted to the anode of the light-emitting element. The light-emitting control signal line EMIT controls the on and off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6, and the power signal transmitted by the power signal line PVDD is transmitted to the light-emitting element when the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are controlled to be turned on, thereby realizing the display and light emission of the light-emitting element.

[0059] For example, continuing to refer to Figure 6 and Figure 7, the initialization transistor T5 and the threshold compensation transistor T4 in the pixel circuit are N-type transistors, and the rest of the transistors are P-type transistors. The enable level can make the transistor turn on, and the non-enable level can make the transistor turn off (or cut off). Among them, the non-enable level of the light-emitting control signal EMIT is high, and the enable level is low; the enable level of the signals transmitted by the first scan signal line S1 and the second scan signal line S2 is high, and the non-enable level is low; the enable level of the signals transmitted by the fourth scan signal line SP and the fourth scan signal line SP* is low, and the non-enable level is high. Specifically, in a driving period Y of the pixel circuit, the gate signal transmitted by the light-emitting control signal line EMIT includes a plurality of non-enable level stages and a plurality of enable level stages, and the plurality of non-enable level stages and the plurality of enable level stages are arranged alternately, wherein when the light-emitting control signal line EMIT is in the non-enable level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are cut off, and when the light-emitting control signal line EMIT is in the enable level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on.

[0060] Further, in a driving period Y of the pixel circuit, it includes a data writing stage Y1, a light-emitting stage Y2 and a light-emitting maintaining stage Y3, wherein the data writing stage Y1 includes a non-enable level stage of the light-emitting control signal EMIT, the light-emitting stage Y2 includes an enable level stage of the light-emitting control signal EMIT, and in the light-emitting maintaining stage Y3, the light-emitting control signal EMIT includes a plurality of non-enable level stages and at least one enable level stage (for example, in the middle of the enable level stage). Figure 7 The level size of the bias voltage signal line DVH in the data writing stage Y1 and the light-emitting stage Y2 can be the same as or different from the level size of the bias voltage signal line DVH in the light-emitting maintaining stage Y3 (for example, as shown in the middle). Figure 7

[0061] ​Further, the data writing stage Y1 includes a first bias adjusting stage Y11, in which the signal transmitted by the fourth scan signal line SP includes at least one low level period, and the signal transmitted by the second scan signal line S2 includes at least one high level period. That is, in the first bias adjusting stage Y11, the bias signal can perform bias adjusting on both the first node N1 and the second node N2. The data writing stage Y1 further includes an initialization and second bias adjusting stage Y12, in which the signal transmitted by the second scan signal line S2 includes at least one high level period, and there is also at least one high level period of the signal transmitted by the second scan signal line S2, in other words, in the initialization and second bias adjusting stage Y12, the initialization transistor T5 is turned on, and the threshold compensation transistor T4 is also turned on, the initialization signal line VREF1 can adjust the gate of the driving transistor T3 through the initialization transistor T5, and the initialization signal line VREF1 can also adjust the second node N2 through the initialization transistor T5 and the threshold compensation transistor T4.

[0062] The data writing stage Y1 further includes a data signal writing stage Y13, in which the signal transmitted by the second scan signal line S2 includes a high level period, and the signal transmitted by the third scan signal line SP* includes at least one low level period, in other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4. The data writing stage Y1 further includes a third bias adjusting stage Y14, in which the signal transmitted by the fourth scan signal line SP includes at least one low level period, and the second node N2 can be further biased and adjusted through the bias transistor T8 in this period.

[0063] Further, if a driving period Y of the pixel circuit is a low frequency period, the driving period Y includes the data writing stage Y1, the light emitting stage Y2 and the light emitting maintaining stage Y3, and if a driving period Y of the pixel circuit is a high frequency period, the driving period Y includes the data writing stage Y1 and the light emitting stage Y2.

[0064] Exemplarily, the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, and the reset transistor T7 can be PMOS transistors; the threshold compensation transistor T4 and the initialization transistor T5 can be at least one PMOS transistor or at least one NMOS transistor, and the embodiments of the present application are only described by taking the threshold compensation transistor T4 and the initialization transistor T5 as NMOS transistors. Based on the specific type of the display panel, the embodiments of the present application are not limited, and can be adaptively adjusted according to the actual production needs.

[0065] In addition, the threshold compensation transistor T4 and the initialization transistor T5 can be single-gate transistors or double-gate transistors. When the double-gate transistors are adopted, the leakage current of the transistor is reduced, and the display effect of the display panel is improved. The present application only takes the threshold compensation transistor T4 and the initialization transistor T5 as top-bottom double-gate transistors as an example.

[0066] As shown in FIG. 1, Figure 6 The reset transistor T7 and the second light-emitting control transistor T6 are connected to the anode of the light-emitting element, and the connection node of the reset transistor T7, the second light-emitting control transistor T6 and the anode of the light-emitting element is the third node N3. The pixel circuit is connected to the anode of the light-emitting element through the third node N3. The connection node of the light-emitting element 200 and the pixel circuit 300 is the third node N3. The anode of the light-emitting element 200 is connected to the third node N3 of the corresponding pixel circuit 300.

[0067] Optionally, Figure 8 A top view schematic diagram of a second display panel provided by the embodiments of the present application is shown in FIG. 2, Figure 9 is Figure 8 A cross-sectional structure schematic diagram of the corresponding display panel along the cross-sectional line D-D' is shown in FIG. 3, Figure 8 and Figure 9 The display panel 100 further includes a pixel driving circuit 90; the pixel driving circuit 90 is located in the display area AA; the pixel driving circuit 90 includes a second transistor 901, and the second transistor 901 includes a second input electrode 9011, a second output electrode 9012 and a second gate 9013; the second input electrode 9011 is electrically connected with the adapter 402.

[0068] Specifically, in the prior art, the pixel driving circuit is usually arranged in the non-display area, so that the frame of the display panel is large, and the narrow frame design of the display panel cannot be realized. However, the embodiments of the present application change the arrangement position of the pixel driving circuit 90 in the prior art, that is, the pixel driving circuit 90 is arranged in the display area AA, that is, the pixel driving circuit 90 is arranged in the display area instead of the non-display area, so that the size of the non-display area NA can be reduced, which is beneficial to realize the narrow frame design of the display panel.

[0069] Specifically, the second input electrode 9011 is electrically connected to the adapter 402. Thus, the high-level signal vgh output by the driving structure 80 is transmitted to the second input electrode 901 in sequence through the first level power signal transmission unit VGH and the adapter 402, or the low-level signal vgl output by the driving structure 80 is transmitted to the second input electrode 9011 in sequence through the second level power signal transmission unit VGL and the adapter 402, and then transmitted to the pixel driving circuit 90, so that the pixel driving circuit 90 drives the pixel circuit 300 to provide display signals to the light-emitting element 200.

[0070] Optional, continue to refer to Figure 1 and Figure 3 The display panel 100 also includes a non-display area NA; the non-display area NA surrounds at least a portion of the display area AA; the display panel 100 also includes a pixel driving circuit 90; the pixel driving circuit 90 is located in the non-display area NA; the pixel driving circuit includes a third transistor 902; the third transistor 902 includes a third input electrode 9021, a third output electrode 9022 and a third gate 9023; the transition section 402 includes a first transition unit 402-1 located in the non-display area NA and a second transition unit 402-2 located in the display area AA; the first transition unit 402-1 is electrically connected to the third input electrode 9021 and the second transition unit 402-2 respectively.

[0071] Specifically, the display panel 100 also includes a pixel driving circuit 90; the pixel driving circuit 90 is located in the non-display area NA, and the adapter 402 includes a first adapter unit 402-1 located in the non-display area NA and a second adapter unit 402-2 located in the display area NA. That is, in order to realize the electrical connection with the input terminal of the pixel driving circuit 90 located in the non-display area NA, the adapter 402 needs to extend to the non-display area NA, that is, it is electrically connected to the third input electrode 9021 through the first adapter unit 402-1 located in the non-display area NA. Since the first adapter unit 402-1 and the second adapter unit 402-2 are connected and arranged, the shape of the adapter 402 is similar to an inverted "V" shape. In this way, the high-level signal vgh output by the driving structure 80 can be transmitted sequentially through the first level power signal transmission unit VGH and the adapter 402 to the third input electrode 9021, or the low-level signal vgl output by the driving structure 80 can be transmitted sequentially through the second level power signal transmission unit VGL and the adapter 402 to the third input electrode 9021, and then transmitted to the pixel driving circuit 90, so that the pixel driving circuit 90 drives the pixel circuit 300 to provide display signals to the light-emitting element 200.

[0072] Optional, Figure 10 This is an electrical schematic diagram of a pixel driving circuit provided in an embodiment of the present invention, such as... Figure 10As shown, the pixel driving circuit 90 includes a clock control transistor M1, a reverse clock control transistor M2, a first level power supply transistor M3, and a second level power supply transistor M4; the first signal transmission part 201 includes a first clock signal transmission part CK, a second clock signal transmission part XCK, a first level power supply signal transmission part VGH, and a second level power supply signal transmission part VGL; the first clock signal transmission part CK is electrically connected with the clock control transistor M1; the second clock signal transmission part XCK is electrically connected with the reverse clock control transistor M2; the first level power supply signal transmission part VGH is electrically connected with the first level power supply transistor M3; and the second level power supply signal transmission part VGL is electrically connected with the second level power supply transistor M4, which is conducive to transmitting the electrical signal output by the driving structure to the pixel driving circuit 90, so that the pixel driving circuit 90 drives the pixel circuit 300 to provide a display signal to the light emitting element 200, and the display panel function is realized.

[0073] Optionally, continuing to refer to Figure 2 , the display panel 100 further includes a driving structure 80; along the thickness direction Z of the display panel, the first opening 101 penetrates through the first substrate 10, and the driving structure 80 and the first signal transmission layer 20 both overlap the first opening 101; the display panel 100 further includes a conductive structure 110 located in the first opening 101, and the conductive structure 110 connects the driving structure 80 and the first signal transmission layer 20.

[0074] Specifically, the first opening 101 is arranged in the first substrate 10, and along the thickness direction Z of the display panel, the first opening 101 penetrates through the first substrate 10, and the driving structure 80 and the first signal transmission layer 20 both overlap the first opening 101, so that in the first opening 101, the driving structure 80 and the first signal transmission layer 20 can be electrically connected through the conductive structure 110, so that the signal output by the driving structure 80 is transmitted to the pixel driving circuit 90 and the pixel circuit 300 through the conductive structure 110. In addition, when the first opening 101 is prepared, the first opening 101 can expose part of the first signal transmission layer 20, which is conducive to realizing the electrical connection between the driving structure 80 and the first signal transmission layer 20 at the position overlapping the first opening 101, and ensuring that the connection mode of the driving structure 80 and the first signal transmission layer 20 is simple.

[0075] Specifically, the display panel 100 further comprises a conductive structure 110 located in the first opening 101, the conductive structure 110 can be arranged corresponding to the pad pin in the driving structure 80 and the first signal transmission part 201 in the first signal transmission layer 20, so as to realize the electrical connection between the driving structure 80 and the first signal transmission layer 20 through the conductive structure 110, and transmit the electrical signal output by the driving structure 80 to the first signal transmission layer 20, so as to ensure that the electrical signal is transmitted to the pixel driving circuit 90 and / or the pixel circuit 300 through the first signal transmission layer 20 subsequently, and further ensure the display function of the display panel.

[0076] Specifically, the material of the conductive structure 110 can be conductive ink, so that the cost of the conductive structure 110 is low and the preparation process is simple.

[0077] Optionally, continuing to refer to Figure 2 The driving structure 80 comprises a chip on film 801 and a driving chip 802; the driving chip 802 is bonded to the chip on film 801; and the conductive structure 110 connects the chip on film 801 and the first signal transmission layer 20.

[0078] Specifically, the chip on film (Chip On Flex, or, Chip On Film, COF) is a technology of bonding the pad on the driving chip 802 to the pin on the flexible circuit board through hot pressing. The chip on film 801 comprises a plurality of gold fingers, and the plurality of gold fingers are bonded to the pad on the driving chip 802, so as to realize the signal transmission between the driving chip 802 and the chip on film 801. Further, the driving structure comprises the chip on film 801 and the driving chip 802, and the chip on film 801 serves as a connecting structure between the driving chip 802 and the conductive structure 110, which can reduce the connection difficulty between the driving chip 802 and the conductive structure 110, and ensure the connection stability between the driving chip 802 and the conductive structure 110.

[0079] Specifically, the chip on film technology can be completed by using a low-temperature process, so as to reduce the influence of thermal stress on the performance of the transistors in the pixel circuit and the pixel driving circuit, and further ensure the stability and reliability of the display panel.

[0080] Optionally, continuing to refer to Figure 2 The display panel 100 comprises a plurality of first signal transmission parts 201, and the conductive structure 110 comprises a plurality of conductive subparts 1101; and the conductive subpart 1101 is arranged corresponding to the first signal transmission part 201.

[0081] As a feasible implementation, the number of the conductive sub-sections 1101 is the same as that of the first signal transmission sections 201, and the conductive sub-sections 1101 are arranged one by one in correspondence with the first signal transmission sections 201, that is, each conductive sub-section 1101 corresponds to one first signal transmission section 201, so that the driving signal output by the driving structure 80 is transmitted to the corresponding first signal transmission section 201 through the conductive sub-section 1101.

[0082] As another feasible implementation, the number of the conductive sub-sections 1101 can be greater than that of the first signal transmission sections 201. For example, the number of the conductive sub-sections 1101 can be twice that of the first signal transmission sections 201, that is, one conductive sub-section 1101 corresponds to two first signal transmission sections 201, so as to ensure the stability of the electrical signal transmission between the driving structure 80 and the first signal transmission sections 201, and improve the stability and reliability of the display panel.

[0083] It should be noted that, continuing to refer to Figure 2 The exposed conductive sub-sections 1101 are surrounded by the encapsulation 130, so as to protect the conductive sub-sections 1101 from pollution or damage to the conductive performance of the conductive sub-sections 1101.

[0084] It should be further noted that, continuing to refer to Figure 2 The driving structure 80 and the first signal transmission layer 20 can be fixed by the adhesive structure 140, that is, the adhesive structure 140 is arranged between the driving structure 80 and the first signal transmission layer 20. For example, the adhesive structure 140 can be a pressure-sensitive adhesive. Since the pressure-sensitive adhesive is used to realize the adhesion between the driving structure 80 and the first signal transmission layer 20, a high temperature is not required, so as to prevent the high temperature from affecting the performance of the first substrate, the transistors in the pixel circuit, and the transistors in the pixel driving circuit, and improve the performance of the display panel.

[0085] Optionally, continuing to refer to Figure 2 The display panel further comprises a virtual wiring 120, and the virtual wiring 120 is arranged in the same layer as the first signal transmission layer 20.

[0086] Specifically, the virtual wiring 120 is arranged in the same layer as the first signal transmission layer 20. On the one hand, the virtual wiring 120 can play a role of planarization, so as to ensure the stability of the virtual wiring 120 and the film layer structure above the first signal transmission layer 20, prevent warping and other problems, and improve the stability and reliability of the display panel. On the other hand, the virtual wiring 120 can adjust the metal density of the edge of the display panel, ensure the consistency of the optical performance of the display panel, and realize the display uniformity of the display panel.

[0087] Further, a virtual trace 120 can also be arranged at a position in the same layer as the third gate electrode 9023, or the virtual trace 120 can also be arranged at a position in the same layer as the third input electrode 9021 and the third output electrode 9022. In this way, on the one hand, the virtual trace 120 can be prepared at the same time as the metal electrode in the same layer, and the preparation method is simple. On the other hand, by arranging the virtual trace 120, the effect of planarization can be achieved, and the consistency of the optical performance of the display panel can be ensured, and the display uniformity of the display panel can be realized.

[0088] Based on the same inventive concept, the embodiment of the present application also provides a display device, Figure 11 A structural schematic diagram of a display device provided by the embodiment of the present application is shown in the figure, and the display device 1000 includes the display panel 100 described in any of the above embodiments. Therefore, the display device 1000 provided by the embodiment of the present application has the corresponding beneficial effects in the above embodiments, and will not be described here. For example, the display device 1000 can be a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, and the like. Figure 11

[0089] Note that the above are only the preferred embodiments of the present application and the applied technical principles. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.​

Claims

1. A display panel, characterized by, The display panel comprises: a first substrate comprising a first opening; a first signal transmission layer located on one side of the first substrate, the first signal transmission layer comprising a first signal transmission portion, the first signal transmission portion at least partially overlapping the first opening in the thickness direction of the display panel; a second substrate located on the side of the first signal transmission layer away from the first substrate, the second substrate comprising a second opening; a light shielding layer located on the side of the second substrate away from the first signal transmission layer, the light shielding layer comprising a light shielding portion and a transfer portion, the transfer portion at least partially covering the second opening; an active layer located on the side of the light shielding layer away from the first substrate, the active layer comprising an active portion, the active portion at least partially overlapping the light shielding portion in the thickness direction of the display panel; a second signal transmission layer located on the side of the active layer away from the first substrate, the second signal transmission layer comprising a second signal transmission portion; wherein the second signal transmission portion is electrically connected to the transfer portion through a via, and the transfer portion is electrically connected to the first signal transmission portion.

2. The display panel of claim 1, wherein, The first opening and the second opening are staggered in the thickness direction of the display panel.

3. The display panel of claim 1, wherein, The transfer portion comprises a first transfer sub-portion, a second transfer sub-portion, and a third transfer sub-portion. The first transfer sub-portion is located on the side of the second substrate away from the first substrate and connected to the second signal transmission layer, the second transfer sub-portion and the third transfer sub-portion are both located in the second opening, the second transfer sub-portion is connected to the first transfer sub-portion and the third transfer sub-portion, and the third transfer sub-portion is connected to the first signal transmission layer. The plane on which the first transfer sub-portion is located is parallel to the plane on which the first substrate is located, the plane on which the second transfer sub-portion is located intersects the plane on which the first substrate is located, and the plane on which the third transfer sub-portion is located is parallel to the plane on which the first substrate is located.

4. The display panel of claim 3, wherein, The first transfer sub-portion comprises a first side surface, which is the surface of the first transfer sub-portion away from the second transfer sub-portion in a first direction, and the second transfer sub-portion comprises a second side surface, which is the surface of the second transfer sub-portion away from the first transfer sub-portion in the first direction. The maximum distance D1 between the first side surface and the second side surface in the first direction satisfies D1>1μm, the first direction is parallel to the plane on which the first substrate is located, and intersects the thickness direction of the display panel.

5. The display panel of claim 3, wherein, The angle θ between the second transfer sub-portion and the first direction satisfies 70°≤θ≤80°, the first direction is parallel to the plane on which the first substrate is located, and intersects the thickness direction of the display panel.

6. The display panel of claim 3, wherein, The distance D2 between two adjacent transfer portions in a second direction satisfies 0.3mm≤D2≤0.5mm, the second direction intersects the plane on which the first substrate is located, and intersects the thickness direction of the display panel.

7. The display panel of claim 6, wherein, The light shielding portion comprises a gate electrode.

8. The display panel of claim 1, wherein, The display panel further comprises a pixel circuit, and the pixel circuit is located in the display area. The pixel circuit comprises a first transistor, the first transistor comprising a first input electrode, a first output electrode and a first gate electrode; The first input electrode is electrically connected with the adapter.

9. The display panel of claim 8, wherein, The first signal transmission part comprises a data signal transmission part, and the adapter comprises a data signal adapter.

10. The display panel of claim 1, wherein, The display panel further comprises a pixel driving circuit; the pixel driving circuit is located in the display area; The pixel driving circuit comprises a second transistor, the second transistor comprising a second input electrode, a second output electrode and a second gate electrode; The second input electrode is electrically connected with the adapter.

11. The display panel of claim 1, wherein, The display panel further comprises a non-display area; the non-display area surrounds at least part of the display area; The display panel further comprises a pixel driving circuit; the pixel driving circuit is located in the non-display area; the pixel driving circuit comprises a third transistor; the third transistor comprising a third input electrode, a third output electrode and a third gate electrode; The adapter comprises a first adapter unit located in the non-display area and a second adapter unit located in the display area; The first adapter unit is electrically connected with the third input electrode and the second adapter unit respectively.

12. The display panel according to claim 10 or 11, characterized in that, The display panel comprises a plurality of first signal transmission parts, the plurality of first signal transmission parts comprising a first clock signal transmission part, a second clock signal transmission part, a first level power signal transmission part and a second level power signal transmission part.

13. The display panel of claim 1, wherein, The display panel further comprises a driving structure; In the thickness direction of the display panel, the first opening penetrates through the first substrate, and the driving structure and the first signal transmission layer both overlap with the first opening; The display panel further comprises a conductive structure located in the first opening, the conductive structure connecting the driving structure and the first signal transmission layer.

14. The display panel of claim 13, wherein, The driving structure comprises a chip on film and a driving chip; The driving chip is bonded with the chip on film; the conductive structure connects the chip on film and the first signal transmission layer.

15. The display panel of claim 14, wherein, The display panel comprises a plurality of first signal transmission parts, and the conductive structure comprises a plurality of conductive subparts; The conductive subparts are arranged corresponding to the first signal transmission parts.

16. The display panel of claim 1, wherein, The display panel further comprises a virtual wire; The virtual wire is arranged in the same layer as the first signal transmission layer.

17. A display device comprising: The display panel comprises the display panel of any one of claims 1-16. The display panel comprises the display panel of any one of claims 1-16.

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