Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a second output sub-circuit, a first control sub-circuit and a second control sub-circuit, the first control sub-circuit is configured to transmit a first clock signal to the pull-down node in response to the potential of the pull-up control node, and output a working level signal to the pull-down node in response to the first clock signal; the second control sub-circuit is configured to write a non-working level signal into the pull-up control node in response to a second clock signal and the potential of the pull-down node; the first output sub-circuit is configured to output a second clock signal through the signal output end in response to the potential of the pull-up control node; the second output sub-circuit is configured to respond to the potential of the pull-down node and output a non-working level signal through the signal output end.

Description

Shift register, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display device. BACKGROUND

[0002] In recent years, flat panel displays, such as thin film transistor liquid crystal display (TFT-LCD) and active matrix organic light emitting diode display panel (AMOLED), are widely used in electronic products such as televisions and mobile phones due to their advantages of light weight, thin thickness and low power consumption.

[0003] With the development of display technology, high-resolution and narrow-frame display panels have become a development trend. Therefore, the gate driver on array (GOA) technology has emerged. The GOA technology directly integrates the gate driving circuit of the display panel on the array substrate to replace the external driving chip, and has the advantages of low cost, few processes and high production capacity. The GOA circuit is usually realized by a shift register, which converts a clock signal into an on / off voltage and outputs it to each gate line of the display panel.

[0004] SUMMARY

[0005] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit and a display device.

[0006] The shift register provided by the present disclosure comprises a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a second output sub-circuit, a first control sub-circuit and a second control sub-circuit.

[0007] The first input sub-circuit is configured to output a first scan signal to a pull-up control node in response to a first input signal.

[0008] The second input sub-circuit is configured to output a second scan signal to the first pull-up control node in response to a second input signal.

[0009] The first control sub-circuit is configured to transmit a first clock signal to a pull-down node in response to the potential of the pull-up control node, and output a working level signal to the pull-down node in response to the first clock signal.

[0010] The second control sub-circuit is configured to write a non-working level signal into the pull-up control node in response to the second clock signal and the potential of the pull-down node;

[0011] The first output sub-circuit is configured to output a second clock signal through a signal output terminal in response to the potential of the pull-up control node;

[0012] The second output sub-circuit is configured to output the non-working level signal through the signal output terminal in response to the potential of the pull-down node.

[0013] The shift register further comprises an anti-leakage electronic circuit configured to connect the pull-up control node and a pull-up node in response to the working level signal, the pull-up node being a connection node between the anti-leakage electronic circuit and the output sub-circuit.

[0014] The anti-leakage sub-circuit comprises a ninth transistor.

[0015] The first electrode of the ninth transistor is connected to the pull-up node, the second electrode is connected to the pull-up control node, and the control electrode is connected to a working level signal terminal.

[0016] The first control sub-circuit comprises a fifth transistor and an eighth transistor.

[0017] The first electrode of the fifth transistor is connected to a first clock signal terminal, the second electrode is connected to the pull-down node, and the control electrode is connected to the pull-up control node.

[0018] The first electrode of the eighth transistor is connected to a working level signal terminal, the second electrode is connected to the pull-down node, and the control electrode is connected to the first clock signal terminal.

[0019] The second control sub-circuit comprises a sixth transistor and a seventh transistor.

[0020] The first electrode of the sixth transistor is connected to the pull-up control node, the second electrode is connected to the first electrode of the seventh transistor, and the control electrode is connected to a second clock signal terminal.

[0021] The second electrode of the seventh transistor is connected to a non-working level signal terminal, and the control electrode is connected to the pull-down node.

[0022] The first input sub-circuit comprises a first transistor.

[0023] The first electrode of the first transistor is connected to a first scan signal terminal, the second electrode is connected to the pull-up control node, and the control electrode is connected to a first input signal terminal.

[0024] The second input sub-circuit comprises a second transistor.

[0025] The first electrode of the second transistor is connected with a second scan signal end, the second electrode is connected with the pull-up node, and the control electrode is connected with a second input signal end.

[0026] The first output sub-circuit comprises a third transistor and a first storage capacitor.

[0027] The first electrode of the third transistor is connected with a second clock signal end, the second electrode is connected with the signal output end, the control electrode is connected with the first end of the first storage capacitor and the pull-up control node, and the second end of the first storage capacitor is connected with the signal output end.

[0028] The second output sub-circuit comprises a fourth transistor and a second storage capacitor.

[0029] The first electrode of the fourth transistor is connected with the signal output end, the second electrode is connected with a non-working level signal end and the second end of the second storage capacitor, and the control electrode is connected with the pull-down node and the first end of the second storage capacitor.

[0030] The embodiments of the present disclosure further provide a gate drive circuit comprising a plurality of cascaded shift registers, wherein the shift registers adopt any of the above-described shift registers.

[0031] In the reverse scanning, the first input signal end of the last shift register in the row is connected with the signal output end of the shift register in the next row.

[0032] For each shift register except the last shift register, the first input signal end of the shift register in the row is connected with the signal output end of the shift register in the next row.

[0033] In the forward scanning, the second input signal end of the first shift register in the row is connected with a frame start signal end.

[0034] For each shift register except the first shift register, the second input signal end of the shift register in the row is connected with the signal output end of the shift register in the next row.

[0035] The gate drive circuit further comprises a redundant shift register which has the same structure as the shift register.

[0036] In the reverse scanning, for each shift register except the first shift register, the second input signal end of the shift register in the row is connected with the signal output end of the shift register in the next row.

[0037] The second input end of the first shift register is connected with the signal output end of the redundant shift register.

[0038] The gate drive circuit further comprises a redundant shift register identical to the shift register structure.

[0039] In forward scanning, for each shift register except the last one, the second input signal terminal of the shift register is connected to the signal output terminal of the next shift register.

[0040] The second input terminal of the last shift register is connected to the signal output terminal of the redundant shift register.

[0041] The first clock signal written by the shift register at odd-numbered stages and the shift register at even-numbered stages is opposite, and the second clock signal written by the shift register at odd-numbered stages and the shift register at even-numbered stages is opposite.

[0042] The display device comprises the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0043] FIG. 1 is a circuit diagram of an exemplary shift register.

[0044] FIG. 2 is a timing diagram of the shift register in FIG. 1 in reverse scanning.

[0045] FIG. 3 is a circuit diagram of a shift register according to an embodiment of the present disclosure.

[0046] FIG. 4 is a timing diagram of the shift register in FIG. 3 in reverse scanning.

[0047] FIG. 5 is a cascade diagram of a gate drive circuit in reverse scanning according to an embodiment of the present disclosure.

[0048] FIG. 6 is a cascade diagram of a gate drive circuit in forward scanning according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] To make the skilled in the art better understand the technical solutions of the present application, the present application is described in further detail below in conjunction with the drawings and specific embodiments.

[0050] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, which can change when the absolute positions of the described objects change.

[0051] It should be noted that the transistor used in the embodiments of the present application can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In the embodiments of the present application, one of the poles is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, the transistor can be divided into N-type and P-type according to its characteristics. In the following embodiments, an N-type transistor is used for illustration. When an N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate is inputted with a high level, so that the source and drain are turned on. The P-type is the opposite. It is conceivable that a P-type transistor can be used to achieve the same result without creative effort, and therefore it is also within the scope of protection of the embodiments of the present application.

[0052] In the embodiments of the present application, since the transistor used is an N-type transistor, the working level signal in the embodiments of the present application refers to a high level signal, the non-working level signal is a low level signal, the working level signal end is a high level signal end, and the non-working level signal end is a low level signal end.

[0053] Generally, a display panel includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are arranged in a cross manner to define a plurality of pixel regions, and each pixel region is provided with a pixel unit. Taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example, the structure of the display panel is described. When driving the display panel to display, a gate scanning signal can be written into the gate lines row by row according to the picture to be displayed, and a data voltage signal is written into each data line at the same time, so that the pixel units in the display panel are lit row by row.

[0054] The gate scanning signal is provided by a gate driving circuit, and the data voltage signal is provided by a source driving circuit. In the related art, the gate driving circuit can be integrated in a gate driving chip, and the source driving circuit can be integrated in a source driving chip. Currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology of integrating the gate driving circuit on an array substrate (Gate On Array; GOA) is provided. The gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate. The signal output end of each shift register is connected to a gate line one by one, and is configured to provide a gate scanning signal for the gate line connected thereto.

[0055] In order to more clearly show how the shift register outputs the gate scanning signal, the following describes the shift register with specific examples.

[0056] FIG. 1 is an example of a shift register. As shown in FIG. 1, the shift register includes a first input sub-circuit 1, a second output sub-circuit 4, a first output sub-circuit 3, a second output sub-circuit 4, a first control sub-circuit 7, a second control sub-circuit 8, a feedback sub-circuit 6, and an anti-leakage electronic circuit 5. The connection node between the first input sub-circuit 1, the second output sub-circuit 4, the first control sub-circuit 7, and the anti-leakage electronic circuit 5 is an upper pull control node PU CN. The node between the anti-leakage electronic circuit 5 and the first output sub-circuit 3 is an upper pull node PU. The connection node between the first control sub-circuit 7, the second control sub-circuit 8, the second output sub-circuit 4, and the feedback sub-circuit 6 is a lower pull node PD.

[0057] With reference back to FIG. 1, the first input sub-circuit 1 is configured to output a first scan signal to the pull-up control node PU CN in response to a first input signal. The second input sub-circuit 2 is configured to output a second scan signal to the pull-up control node PU CN in response to a second input signal. The first control sub-circuit 7 is configured to pull down the potential of the pull-down node PD by a low-level signal in response to the potential of the pull-up control node PU CN, and to control the potential of the pull-down node PD by the first clock signal in response to the first clock signal. The second control sub-circuit 8 is configured to pull down the potential of the pull-up control node PU CN by a low-level signal under the control of the potential of the pull-down node PD. The leakage prevention sub-circuit 5 is configured to transmit the potential of the pull-up control node PU CN to the pull-up node PU under the control of a high-level signal, which can effectively avoid the impact on the first output sub-circuit 3 and the second output sub-circuit 4 when the current flowing through the pull-up control node PU CN is too large. The feedback sub-circuit 6 is configured to control the potential of the pull-down node PD by a low-level signal according to the output of the signal output terminal OUT. The first output sub-circuit 3 is configured to output the second clock signal through the signal output terminal OUT according to the potential of the pull-up node PU. The second output sub-circuit 4 is configured to output a low-level signal through the signal output terminal OUT according to the potential of the pull-down node PD. It should be noted that the shift register in the embodiment of the present disclosure can realize forward scanning and reverse scanning, i.e., bidirectional scanning. Among them, the above-mentioned first scan signal is taken as an example of a reverse scan signal, and the corresponding second scan signal is taken as an example of a forward scan signal. The forward scan signal and the reverse scan signal are a pair of opposite signals. For example, the forward scan signal represents scanning row by row from the first row to the last row, and the reverse scan signal represents scanning row by row from the last row to the first row. In the embodiment of the present disclosure, only the first scan signal is taken as an example of a reverse scan signal. When reverse scanning, the first input sub-circuit 1 is used for pre-charging the pull-up control node PU CN, and the second input sub-circuit 2 is used for resetting the pull-up control node PU CN; when forward scanning, the first input sub-circuit 1 is used for resetting the pull-up control node PU CN, and the second input sub-circuit 2 is used for pre-charging the pull-up control node PU CN. The specific combination is described below.

[0058] In some examples, with reference back to FIG. 1, the first input sub-circuit 1 includes a first transistor T1, a source of the first transistor T1 is connected to the first scan signal terminal CN_1, a drain of the first transistor T1 is connected to the pull-up control node PU CN, and a gate of the first transistor T1 is connected to the first input signal terminal STV_R.

[0059] Specifically, when scanning in reverse, the first input signal written into the first input signal terminal STV_R is a high level signal, the first scan signal written into the first scan signal terminal CN_1 is a high level signal, at this time, the first transistor T1 is turned on, and the high level signal written into the first scan signal terminal CN_1 is used to pre-charge the pull-up control node PU_CN. When scanning in forward, the first input signal written into the first input signal terminal STV_R is a high level signal, the first scan signal written into the first scan signal terminal CN_1 is a low level signal, at this time, the first transistor T1 is turned on, and the low level signal written into the first scan signal terminal CN_1 is used to reset the pull-up control node PU_CN.

[0060] In some examples, continuing to refer to FIG. 1, the second input sub-circuit 2 includes a second transistor T2, a source of the second transistor T2 is connected to the second scan signal terminal CN_2, a drain of the second transistor T2 is connected to the pull-up control node PU_CN, and a gate of the second transistor T2 is connected to the second input signal terminal STV_F.

[0061] Specifically, when scanning in reverse, the second input signal written into the second input signal terminal STV_F is a high level signal, the second scan signal written into the second scan signal terminal CN_2 is a low level signal, at this time, the second transistor T2 is turned on, and the low level signal written into the second scan signal terminal CN_2 is used to reset the pull-up control node PU_CN. When scanning in forward, the second input signal written into the second input signal terminal STV_F is a high level signal, the second scan signal written into the second scan signal terminal CN_2 is a high level signal, at this time, the second transistor T2 is turned on, and the high level signal written into the second scan signal terminal CN_2 is used to pre-charge the pull-up control node PU_CN.

[0062] In some examples, continuing to refer to FIG. 1, the leakage prevention electronic circuit 5 includes a ninth transistor T9, a source of the ninth transistor T9 is connected to the pull-up node PU, a drain of the ninth transistor T9 is connected to the pull-up control node PU_CN, and a gate of the ninth transistor T9 is connected to the high level signal terminal VGH.

[0063] Specifically, the high level signal terminal VGH continuously loads a high level signal, the ninth transistor T9 is always on, and the potential of the pull-up control node PU_CN is transmitted to the pull-up node PU through the ninth transistor T9.

[0064] In some examples, continuing to refer to FIG. 1, the first output sub-circuit 3 includes a third transistor T3 and a first storage capacitor C1. The source of the third transistor T3 is connected to the second clock signal end CLK_2, the drain of the third transistor T3 is connected to the signal output end OUT, and the gate of the third transistor T3 is connected to the pull-up node PU. The first end of the first storage capacitor C1 is connected to the pull-up node PU, and the second end of the first storage capacitor C1 is connected to the signal output end OUT.

[0065] Specifically, when the potential of the pull-up node PU is a high level signal, the third transistor T3 is opened, and the second clock signal written by the second clock signal end CLK_2 is output through the signal output end OUT.

[0066] In some examples, continuing to refer to FIG. 1, the second output sub-circuit 4 includes a fourth transistor T4 and a second storage capacitor C2. The source of the fourth transistor T4 is connected to the signal output end OUT, the drain of the fourth transistor T4 is connected to the low level signal end VGL, and the gate of the fourth transistor T4 is connected to the pull-down node PD. The first end of the second storage capacitor C2 is connected to the pull-down node PD, and the second end of the second storage capacitor C2 is connected to the low level signal end VGL.

[0067] Specifically, when the potential of the pull-down node PD is a high level signal, the fourth transistor T4 is opened, and the low level signal written by the low level signal end VGL is output through the signal output end OUT.

[0068] In some examples, continuing to refer to FIG. 1, the feedback sub-circuit 6 includes an eighth transistor T8. The source of the eighth transistor T8 is connected to the pull-down node PD, the drain of the eighth transistor T8 is connected to the low level signal end VGL, and the gate of the eighth transistor T8 is connected to the signal output end OUT.

[0069] Specifically, when the signal output end OUT outputs a high level signal, the eighth transistor T8 is opened, and the low level signal written by the low level signal end VGL pulls down the potential of the pull-down node PD.

[0070] In some examples, the first control sub-circuit 7 includes a sixth transistor T6 and a seventh transistor T7. The source and the gate of the sixth transistor T6 are both connected to the first clock signal end CLK_1, and the drain of the sixth transistor T6 is connected to the pull-down node PD. The source of the seventh transistor T7 is connected to the pull-down node PD, the drain of the seventh transistor T7 is connected to the low level signal end VGL, and the gate of the seventh transistor T7 is connected to the pull-up control node PU_CN.

[0071] Specifically, when the first clock signal enables the sixth transistor T6, the potential of the pull-down node PD is pulled up by the first clock signal, and when the pull-up control node PU CN is at a high level, the seventh transistor T7 is turned on to pull down the potential of the pull-down node PD by a low-level signal.

[0072] In some examples, the second control sub-circuit 8 includes a fifth transistor T5. The source of the fifth transistor T5 is connected to the pull-up control node PU CN, the drain of the fifth transistor T5 is connected to the low-level signal end VGL, and the control electrode of the fifth transistor T5 is connected to the pull-down node PD.

[0073] Specifically, when the potential of the pull-down node PD is at a high level, the fifth transistor T5 is turned on to reduce noise on the pull-up control node PU CN by a low-level signal.

[0074] When the shift register in the embodiment of the disclosure shown in FIG. 1 is applied to a gate drive circuit, during reverse scanning, the gate drive circuit needs to meet that, except for the first stage shift register, the first input signal end STV R of the current stage shift register is connected to the signal output end OUT of the previous stage shift register, and except for the last stage shift register, the second input signal end STV F of the current stage shift register is connected to the signal output end OUT of the next stage shift register. For the first input end of the first stage shift register, it is connected to the frame opening signal end. For the second input signal end STV F of the last stage shift register, it is connected to the signal output end OUT of the redundant stage shift register. Wherein, the redundant shift register is completely consistent with other shift registers. Correspondingly, during forward scanning, the gate drive circuit needs to meet that, except for the first stage shift register, the second input signal end STV F of the current stage shift register is connected to the signal output end OUT of the previous stage shift register, and except for the last stage shift register, the first input signal end STV R of the current stage shift register is connected to the signal output end OUT of the next stage shift register. For the second input end of the first stage shift register, it is connected to the frame opening signal end. For the first input signal end STV R of the last stage shift register, it is connected to the signal output end OUT of the redundant stage shift register. Referring to FIG. 2, FIG. 2 is a timing diagram of the shift register shown in FIG. 1 during reverse scanning. Wherein the direct current signals of the circuit of the shift register include: high-level signal, low-level signal, first scanning signal, second scanning signal; alternating current signals include: first clock signal, second clock signal, second input signal, first input signal; the output signal of the shift register is an alternating current signal. Referring to FIG. 2, the shift register specifically includes the following processes:

[0075] The first stage (a): the first input signal terminal STV_R is written with a high level signal, the first transistor T1 is opened, the first scanning signal is a high level signal, the pull-up control node PU_CN is pre-charged, and since the ninth transistor T9 is always open under the control of the high level signal, the pull-up node PU is also pre-charged. In this stage, since the first clock signal written in the first clock signal terminal CLK_1 is a high level signal, the sixth transistor T6 is opened, and at this time, the high level of the pull-up control node PU_CN will also open the seventh transistor T7, so the pull-down node PD is under the voltage difference of (VGH-VGL) of the open-state resistance of the sixth transistor T6 and the seventh transistor T7, and the width-length ratio of the sixth transistor T6 is controlled to be much larger than that of the seventh transistor T7, so that the pull-down node PD is closer to the low level, and the fourth transistor T4 is closed; and since the pull-up node PU is at a high level, the third transistor T3 is opened, so that the signal output terminal OUT outputs a low level signal of the second clock signal.

[0076] The second stage (b): the first clock signal and the second clock signal are both low level signals, at this time, the sixth transistor T6 is closed, the pull-up node PU remains at a high level, the seventh transistor T7 and the third transistor T3 are opened, the pull-down node PD is maintained at a low level, and the signal output terminal OUT continuously outputs a low level of the second clock signal CLK_2.

[0077] The third stage (c): the first clock signal is a low level signal, and the second clock signal is a high level signal,

[0078] The signal output terminal OUT changes from the low level of the second clock signal CLK_2 to the high level, and through the coupling effect of the first storage capacitor C1, the pull-up node PU is further pulled up, the opening degree of the third transistor T3 is further improved, and the signal output terminal OUT outputs the high level of the second clock signal CLK_2. At the same time, the eighth transistor T8 is opened by the high level signal output by the signal output terminal OUT, and the pull-down node PD is continuously written with a low level signal, and the eighth transistor T8 and the seventh transistor T7 maintain the low level of the pull-down node PD as a double protection, so that the fourth transistor T4 is turned off, and the high level output of the signal output terminal OUT is avoided.

[0079] The fourth stage (d) : similar to the second stage (b), the first clock signal and the second clock signal are low signals, the pull-up node PU maintains a high signal to continuously open the third transistor T3, and the signal output end OUT outputs a low level of the second clock signal CLK_2; although the seventh transistor T7 and the eighth transistor T8 are both closed, the pull-down node PD still maintains a low signal to maintain the fourth transistor T4 off. The fifth stage (e) : the second input signal end STV_F is written with a high signal due to being connected with the signal output end OUT of the next stage, the second transistor T2 is opened, the low level of the second scan signal CN_2 is written into the pull-up control node PU_CN, at this time, the pull-up control node PU_CN and the pull-up node PU are discharged and reset, so that the third transistor T3 is closed. The first clock signal CLK_1 is a high signal, the sixth transistor T6 is opened, the potential of the pull-down node PD is pulled high, the fourth transistor T4 and the fifth transistor T5 are both opened, the fifth transistor T5 is opened to maintain the pull-up control node PU_CN to maintain a low level, and the fourth transistor T4 is opened to make the signal output end OUT continuously output a low level of the low signal end VGL.

[0080] The inventor finds that: the sixth transistor T6 and the seventh transistor T7 constitute the pull-up node PU and the pull-down node PD, and the inverter of the two nodes is utilized. When the pull-up node PU is a high level signal, the on-state resistance of the sixth transistor T6 and the seventh transistor T7 is used for voltage division to make the pull-down node PD maintain a low potential (the stage a in the timing diagram in FIG. 2). This design requires a suitable proportional relationship of W / L (width-length ratio) of the sixth transistor T6 and the seventh transistor T7, and a stable loop is formed between the periodic high level and low level of the first clock signal and the low level of the signal end VGL, which has greater persistent heat loss, and is not conducive to the power consumption of the chip IC and the stability of the transistor device.

[0081] In view of the above problems, the technical scheme is provided in the embodiment of the present disclosure.

[0082] The embodiment of the present disclosure provides a shift register, which comprises a first input sub-circuit 1, a second input sub-circuit 2, a first output sub-circuit 3, a second output sub-circuit 4, a first control sub-circuit 7 and a second control sub-circuit 8. The first input sub-circuit 1 is configured to output a first scan signal to a pull-up control node PU CN in response to a first input signal; the second input sub-circuit 2 is configured to output a second scan signal to the first pull-up control node PU CN in response to a second input signal; the first control sub-circuit 7 is configured to transmit a first clock signal to a pull-down node PD in response to a potential of the pull-up control node PU CN, and output an operating level signal to the pull-down node PD in response to the first clock signal; the second control sub-circuit 8 is configured to write a non-operating level signal to the pull-up control node PU CN in response to a second clock signal and a potential of the pull-down node PD; the first output sub-circuit 3 is configured to output the second clock signal through a signal output end OUT in response to the potential of the pull-up control node PU CN; and the second output sub-circuit 4 is configured to output the non-operating level signal through the signal output end OUT in response to the potential of the pull-down node PD.

[0083] In this example, also taking the reverse scan as an example, when the pull-up control node PU CN is at a high level, the pull-down node PD is not pulled down at the first time, and the first output sub-circuit 3 and the second output sub-circuit 4 are both in an operating state, and the signal output end OUT outputs a low level signal of the second clock signal and a low level signal output by the second output sub-circuit 4. When the first clock signal becomes a low level at a subsequent time, the pull-down node PD is pulled down, and until the first clock signal is at a high level again, the pull-down control node is pulled up, and the signal output end OUT outputs a high level. The specific advantages of the shift register are described in detail in combination with the specific circuit and working process described below.

[0084] In some examples, still referring to FIG. 3, the first input sub-circuit 1 comprises a first transistor T1, a source of the first transistor T1 is connected to a first scan signal end CN_1, a drain of the first transistor T1 is connected to the pull-up control node PU CN, and a gate of the first transistor T1 is connected to a first input signal end STV_R.

[0085] Specifically, when scanning in reverse, the first input signal written into the first input signal terminal STV_R is a high level signal, the first scan signal written into the first scan signal terminal CN_1 is a high level signal, at this time, the first transistor T1 is turned on, and the high level signal written into the first scan signal terminal CN_1 is used to pre-charge the pull-up control node PU_CN. When scanning in forward, the first input signal written into the first input signal terminal STV_R is a high level signal, the first scan signal written into the first scan signal terminal CN_1 is a low level signal, at this time, the first transistor T1 is turned on, and the low level signal written into the first scan signal terminal CN_1 is used to reset the pull-up control node PU_CN.

[0086] In some examples, continuing to refer to FIG. 3, the second input sub-circuit 2 includes a second transistor T2, a source of the second transistor T2 is connected to the second scan signal terminal CN_2, a drain of the second transistor T2 is connected to the pull-up control node PU_CN, and a gate of the second transistor T2 is connected to the second input signal terminal STV_F.

[0087] Specifically, when scanning in reverse, the second input signal written into the second input signal terminal STV_F is a high level signal, the second scan signal written into the second scan signal terminal CN_2 is a low level signal, at this time, the second transistor T2 is turned on, and the low level signal written into the second scan signal terminal CN_2 is used to reset the pull-up control node PU_CN. When scanning in forward, the second input signal written into the second input signal terminal STV_F is a high level signal, the second scan signal written into the second scan signal terminal CN_2 is a high level signal, at this time, the second transistor T2 is turned on, and the high level signal written into the second scan signal terminal CN_2 is used to pre-charge the pull-up control node PU_CN.

[0088] In some examples, continuing to refer to FIG. 3, the leakage prevention electronic circuit 5 includes a ninth transistor T9, a source of the ninth transistor T9 is connected to the pull-up node PU, a drain of the ninth transistor T9 is connected to the pull-up control node PU_CN, and a gate of the ninth transistor T9 is connected to the high level signal terminal VGH.

[0089] Specifically, the high level signal terminal VGH continuously loads a high level signal, the ninth transistor T9 is always on, and the potential of the pull-up control node PU_CN is transmitted to the pull-up node PU through the ninth transistor T9.

[0090] In some examples, continuing to refer to FIG. 3, the first output sub-circuit 3 includes a third transistor T3 and a first storage capacitor C1. The source of the third transistor T3 is connected to the second clock signal end CLK_2, the drain of the third transistor T3 is connected to the signal output end OUT, and the gate of the third transistor T3 is connected to the pull-up node PU. The first end of the first storage capacitor C1 is connected to the pull-up node PU, and the second end of the first storage capacitor C1 is connected to the signal output end OUT.

[0091] Specifically, when the potential of the pull-up node PU is a high level signal, the third transistor T3 is opened, and the second clock signal written by the second clock signal end CLK_2 is output through the signal output end OUT.

[0092] In some examples, continuing to refer to FIG. 3, the second output sub-circuit 4 includes a fourth transistor T4 and a second storage capacitor C2. The source of the fourth transistor T4 is connected to the signal output end OUT, the drain of the fourth transistor T4 is connected to the low level signal end VGL, and the gate of the fourth transistor T4 is connected to the pull-down node PD. The first end of the second storage capacitor C2 is connected to the pull-down node PD, and the second end of the second storage capacitor C2 is connected to the low level signal end VGL.

[0093] Specifically, when the potential of the pull-down node PD is a high level signal, the fourth transistor T4 is opened, and the low level signal written by the low level signal end VGL is output through the signal output end OUT.

[0094] In some examples, continuing to refer to FIG. 3, the first control sub-circuit 7 includes a fifth transistor T5 and an eighth transistor T8. The source of the fifth transistor T5 is connected to the first clock signal end CLK_1, the drain of the fifth transistor T5 is connected to the pull-down node PD, and the gate of the fifth transistor T5 is connected to the pull-up control node PU_CN. The source of the eighth transistor T8 is connected to the working level signal end, the drain of the eighth transistor T8 is connected to the pull-down node PD, and the gate of the eighth transistor T8 is connected to the first clock signal end CLK_1.

[0095] Specifically, when the first clock signal is a high level signal, the eighth transistor T8 is opened, and the pull-down node PD is pulled up to a high level signal. When the pull-up control node PU_CN is a high level, the fifth transistor T5 is opened, and the potential of the pull-down node PD is the potential of the first clock signal.

[0096] In some examples, continuing to refer to FIG. 3, the second control sub-circuit 8 includes a sixth transistor T6 and a seventh transistor T7. The source of the sixth transistor T6 is connected to the pull-up control node PU CN, the drain of the sixth transistor T6 is connected to the source of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the second clock signal end CLK 2; the drain of the seventh transistor T7 is connected to the low working level signal end, and the gate of the seventh transistor T7 is connected to the pull-down node PD.

[0097] Specifically, when the sixth transistor T6 is opened by the second clock signal, and the seventh transistor T7 is opened by the pull-down node PD, the pull-down control node is pulled low by the low level signal.

[0098] Referring to FIG. 4, FIG. 4 is a timing diagram of the shift register in reverse scanning. The direct current signals of the circuit of the shift register include: high level signal, low level signal, first scan signal, second scan signal; the alternating current signals include: first clock signal, second clock signal, second input signal, first input signal; the output signal of the shift register is an alternating current signal. Referring to FIG. 4, the shift register specifically includes the following processes:

[0099] The first stage (a): the first input signal end STV R is written with a high level signal, the first transistor T1 is opened, the first scan signal is a high level signal, the pull-up control node PU CN is pre-charged, and since the ninth transistor T9 is always open under the control of the high level signal, the pull-up node PU is also pre-charged. In this stage, since the first clock signal end CLK 1 is written with a high level signal, the fifth transistor T5 and the eighth transistor T8 are both opened, at this time the pull-down node PD is a high level, at the same time, the fourth transistor T4 and the third transistor T3 are both opened, and the signal output end OUT outputs the low level signal of the second clock signal and the low level signal of the low level signal end VGL.

[0100] The second stage (b): the first clock signal and the second clock signal are both low level signals, the eighth transistor T8 is turned off, the pull-up control node PU CN is a high level signal, the fifth transistor T5 is opened, and the pull-down node PD is the potential of the first clock signal, that is, a low potential. At this time, the fourth transistor T4 is closed, and since the pull-up node PU still maintains the high level signal after charging, the third transistor T3 is opened, and the signal output end OUT continuously outputs the low level signal of the second clock signal.

[0101] The third stage (c): the first clock signal is a low level signal, the second clock signal is a high level signal, the fifth transistor T5 is maintained in an open state by the high level signal of the pull-up control node PU CN, so that the pull-down node PD also maintains the low potential of the first clock signal CLK 1, so that the fourth transistor T4 and the seventh transistor T7 are in a closed state; at this time, the second clock signal CLK 2 is switched from a high level to a low level, but the pull-up node PU still maintains a relatively high level signal to keep T3 open, and the signal output end OUT outputs a low level signal of the second clock signal.

[0102] The fourth stage (d): the first clock signal and the second clock signal are both low level signals, the pull-up control node PU CN maintains a high potential to keep T5 open, so that the pull-down node PD also maintains the low potential of the first clock signal CLK 1, so that the fourth transistor T4 and the seventh transistor T7 are in a closed state; at this time, the second clock signal CLK 2 is switched from a high level to a low level, but the pull-up node PU still maintains a relatively high level signal to keep T3 open, and the signal output end OUT outputs a low level signal of the second clock signal.

[0103] The fifth stage (e): the second input signal end STV F is written with a high level signal due to the connection of the signal output end OUT of the next stage, the second transistor T2 is opened, and the low level signal of the second scan signal CN 2 is written to the pull-up control node PU CN, at this time, the pull-up control node PU CN and the pull-up node PU are discharged and reset, so that the third transistor T3 is closed; the first clock signal is a high level signal, the eighth transistor T8 is opened, the potential of the pull-down node PD is pulled up, the fourth transistor T4 and the seventh transistor T7 are opened, and the signal output end OUT outputs a low level signal; and with the periodic pull-up of the second clock signal written by the second clock signal end CLK 2, the sixth transistor T6 is opened, and the seventh transistor T7 is always open, so that the pull-up control node PU CN and the pull-up node PU are periodically maintained and discharged.

[0104] As can be seen from the above working process, the pull-down node PD will not appear the case that the high level of the first clock signal and the low level of the low level signal end VGL are written into the pull-down node PD at the same time, and the case that the low level of the first clock signal end write CLK 1 and the high level of the high level signal end VGH are written into the pull-down node PD at the same time, at this time, the case that the pull-down node PD is opened by two transistors at the same time is avoided.

[0105] The process of forward scanning is basically the same as the above-mentioned reverse scanning process, and therefore will not be repeated here.

[0106] The embodiment of the present disclosure further provides a gate drive circuit, which comprises the plurality of cascaded shift registers.

[0107] In some examples, referring to FIG. 5, when performing reverse scanning, the gate drive circuit needs to satisfy that, except for the first stage shift register, the first input signal terminal STV_R of the current stage shift register is connected to the signal output terminal OUT of the previous stage shift register, and except for the last stage shift register, the second input signal terminal STV_F of the current stage shift register is connected to the signal output terminal OUT of the next stage shift register. The first input terminal of the first stage shift register is connected to the frame start signal terminal. The second input signal terminal STV_F of the last stage shift register is connected to the signal output terminal OUT of the redundant stage shift register. The redundant stage shift register is completely consistent with the structure of other shift registers.

[0108] In the embodiment, for the reverse scanning mode, the first scanning signal terminal CN_1 and the high-level signal terminal VGH keep inputting direct-current high potential, the second scanning signal terminal CN_2 and the low-level signal terminal VGL keep inputting direct-current low potential, and the leads of direct-current signals are not annotated in detail in FIG. 5. The first clock signal written by the first clock signal terminal CLK_1 and the second clock signal written by the second clock signal terminal CLK_2 are just opposite at the input signals of the odd stage shift register and the even stage shift register, so as to ensure that the output of the signal output terminal OUT of each stage shift register is the high potential of the alternating second clock signal / first clock signal / second clock signal, and the target of shifting the output high potential is achieved.

[0109] In some examples, referring to FIG. 5, when performing forward scanning, the gate drive circuit needs to satisfy that, except for the first stage shift register, the second input signal terminal STV_F of the current stage shift register is connected to the signal output terminal OUT of the previous stage shift register, and except for the last stage shift register, the first input signal terminal STV_R of the current stage shift register is connected to the signal output terminal OUT of the next stage shift register. The second input terminal of the first stage shift register is connected to the frame start signal terminal. The first input signal terminal STV_R of the last stage shift register is connected to the signal output terminal OUT of the redundant stage shift register.

[0110] For the forward scanning mode, the second scanning signal terminal CN_2 keeps inputting direct current high potential with the high potential signal terminal VGH, the first scanning signal terminal CN_1 keeps inputting direct current low potential with the low potential signal terminal VGL, and the direct current signal lead in FIG. 6 is not detailed. The first clock signal written by the first clock signal terminal CLK_1 and the second clock signal written by the second clock signal terminal CLK_2 are just opposite at the input signal of the odd level shift register and the even level shift register, which ensures that the output of the signal output terminal OUT of each level shift register is the high potential of the second clock signal / first clock signal / second clock signal…, and realizes the goal of shifting output high potential.

[0111] The display device includes the gate driving circuit.

[0112] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered within the protection scope of the present application.

Claims

1. A shift register comprising a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a second output sub-circuit, a first control sub-circuit and a second control sub-circuit; wherein, the first input sub-circuit is configured to output a first scan signal to a pull-up control node in response to a first input signal; the second input sub-circuit is configured to output a second scan signal to the first pull-up control node in response to a second input signal; the first control sub-circuit is configured to transmit a first clock signal to a pull-down node in response to a potential of the pull-up control node, and output an operating level signal to the pull-down node in response to the first clock signal; the second control sub-circuit is configured to write a non-operating level signal to the pull-up control node in response to the second clock signal and a potential of the pull-down node; the first output sub-circuit is configured to output a second clock signal through a signal output terminal in response to the potential of the pull-up control node; the second output sub-circuit is configured to output the non-operating level signal through the signal output terminal in response to the potential of the pull-down node.

2. The shift register of claim 1, wherein, Further comprising a leakage prevention electronic circuit configured to connect the pull-up control node and a pull-up node in response to the operating level signal, the pull-up node being a connection node between the leakage prevention electronic circuit and the output sub-circuit.

3. The shift register of claim 2, wherein, The leakage prevention sub-circuit comprises a ninth transistor; the first electrode of the ninth transistor is connected to the pull-up node, the second electrode is connected to the pull-up control node, and the control electrode is connected to the operating level signal terminal.

4. The shift register of claim 1, wherein, The first control sub-circuit comprises a fifth transistor and an eighth transistor; the first electrode of the fifth transistor is connected to a first clock signal terminal, the second electrode is connected to the pull-down node, and the control electrode is connected to the pull-up control node; the first electrode of the eighth transistor is connected to the operating level signal terminal, the second electrode is connected to the pull-down node, and the control electrode is connected to the first clock signal terminal. The second control sub-circuit comprises a sixth transistor and a seventh transistor; 5. The shift register of claim 1, wherein, the first electrode of the sixth transistor is connected to the pull-up control node, the second electrode is connected to the first electrode of the seventh transistor, and the control electrode is connected to a second clock signal terminal; the second electrode of the seventh transistor is connected to a non-operating level signal terminal, and the control electrode is connected to the pull-down node. The first input sub-circuit comprises a first transistor; 6. The shift register of claim 1, wherein, the first electrode of the first transistor is connected to a first scan signal terminal, the second electrode is connected to the pull-up control node, and the control electrode is connected to a first input signal terminal. The second input sub-circuit comprises a second transistor; 7. The shift register of claim 1, wherein, the first electrode of the second transistor is connected to a second scan signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to a second input signal terminal. The first output sub-circuit comprises a third transistor and a first storage capacitor; 8. The shift register of claim 1, wherein, the first electrode of the third transistor is connected to a second clock signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to a first terminal of the first storage capacitor and the pull-up control node, a second terminal of the first storage capacitor being connected to the signal output terminal. The second output sub-circuit comprises a fourth transistor and a second storage capacitor; 9. The shift register of claim 1, wherein, ​ The first electrode of the fourth transistor is connected to the signal output end, the second electrode is connected to a non-working level signal end and the second end of the second storage capacitor, and the control electrode is connected to the pull-down node and the first end of the second storage capacitor.

10. A gate drive circuit comprising a plurality of cascaded shift registers, the shift registers being the shift register of any one of claims 1-9. In reverse scanning: the first input signal end of the last stage of the shift register; 11. The gate drive circuit of claim 10, wherein, For each of the shift registers except the last stage of the shift register, the first input signal end of the shift register of the current row is connected to the signal output end of the next stage of the shift register. In forward scanning: the second input signal end of the first stage of the shift register is connected to a frame start signal end; 12. The gate drive circuit of claim 10, wherein, For each of the shift registers except the first stage of the shift register, the second input signal end of the shift register of the current row is connected to the signal output end of the next stage of the shift register. Further comprising a redundant shift register identical to the structure of the shift register; 13. The gate drive circuit of claim 10, wherein, In reverse scanning: for each of the shift registers except the first stage of the shift register, the second input signal end of the shift register of the current stage is connected to the signal output end of the next stage of the shift register; The second input end of the first stage of the shift register is connected to the signal output end of the redundant shift register. Further comprising a redundant shift register identical to the structure of the shift register; 14. The gate drive circuit of claim 10, wherein, In forward scanning: for each of the shift registers except the last stage of the shift register, the second input signal end of the shift register of the current stage is connected to the signal output end of the next stage of the shift register; The second input end of the last stage of the shift register is connected to the signal output end of the redundant shift register. The first clock signal written by the shift register at odd stages and the second clock signal written by the shift register at even stages are opposite.

15. The gate drive circuit of claim 10, wherein, 16. A display device comprising the gate drive circuit of any one of claims 10-15. ​

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