Package substrate having electronic component mounted with resin in cavity of core of package substrate

Abstract

In one aspect, an electronic device is disclosed that includes a substrate including a core having an upper planar surface and a lower planar surface, where the core includes a cavity extending through the core; an electronic component at least partially disposed in the cavity, where the electronic component has an upper planar surface with one or more electronic component terminals; a first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, where the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Description

[0001] Field of Disclosure

[0002] The present disclosure relates generally to packaging substrates, and more particularly to a packaging substrate having embedded electronic components mounted in a core of the packaging substrate.

[0003] BACKGROUND

[0004] Integrated circuit (IC) technology has made great strides in improving computing power through miniaturization of electronic components. ICs can be implemented in the form of IC chips having a collection of circuits integrated thereon. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where various power and signal nodes in the one or more IC chips can be electrically coupled to respective conductive terminals of the IC package via electrical paths formed in a packaging substrate of the IC package. Various packaging technologies can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, and the like. Advanced packaging and processing technologies can be used to implement complex devices, such as multi- electronic component devices and system on chip (SOC) devices, which can include multiple functional blocks, where each functional block is designed to perform a particular function, such as, for example, microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., WiFi, Bluetooth, and other communications), and the like.

[0005] In some implementations, embedded passive devices, such as deep trench capacitors, have been incorporated into IC packages for performance improvement and package size reduction. One factor driving the use of such embedded passive devices is the desire to obtain small form factor products with comparable or better electrical performance than their larger passive device counterparts. Depending on the size and / or thickness of the packaging substrate and the size and / or process node of the IC chip carried thereon, the process used to embed electronic components into the packaging substrate in one packaging task can not be applicable to another packaging task.

[0006] Accordingly, there is a need for improved methods of embedding electronic components into substrates, such as packaging substrates, that can be applicable to a wider range of packaging tasks.

[0007] SUMMARY

[0008] The following presents a simplified summary related to one or more aspects disclosed herein. Thus, the following summary should not be considered an introduction to all contemplated aspects, nor should the following summary be necessarily considered related to the most prevalent or significant aspects. Accordingly, the following summary is intended to provide a brief overview of certain concepts related to one or more aspects disclosed herein and is not intended to be used to narrow or frame the scope of the disclosure. The sole purpose of the following summary is to present some concepts related to one or more aspects in a simplified form as a prelude to the more detailed description presented later.

[0009] In an aspect, an electronic device includes a substrate including a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface of the core and the lower planar surface of the core; an electronic assembly at least partially disposed in the cavity, wherein the electronic assembly has an upper planar surface having one or more electronic assembly terminals; a first cured resin layer, wherein the upper planar surface of the electronic assembly is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more electrically conductive paths from the one or more electronic assembly terminals to one or more upper metal terminals of the upper metallization structure.

[0010] In an aspect, a substrate includes a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface of the core and the lower planar surface of the core; an electronic assembly at least partially disposed in the cavity, wherein the electronic assembly has an upper planar surface having one or more electronic assembly terminals; a first cured resin layer, wherein the upper planar surface of the electronic assembly is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more electrically conductive paths from the one or more electronic assembly terminals to one or more upper metal terminals of the upper metallization structure.

[0011] In an aspect, a method for manufacturing a substrate includes forming a cavity in a core, wherein the cavity extends between a first planar surface of the core and a second planar surface of the core; at least partially mounting an electronic assembly in the cavity, wherein the electronic assembly includes a first planar surface having one or more electronic assembly terminals, and wherein the first planar surface of the electronic assembly is at least partially embedded in a first cured resin layer at a first end of the cavity; and forming a first metallization structure over the first planar surface of the core, wherein the first metallization structure is configured to provide one or more electrically conductive paths from the one or more electronic assembly terminals to one or more metal terminals of the first metallization structure.

[0012] Other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0014] A more complete appreciation of the aspects of the disclosure and many of the attendant advantages thereof will be readily understood by reference to the following detailed description taken in connection with the accompanying drawings, which are presented solely for the purpose of illustration and are not intended to be a definition of the disclosure.

[0015] Figure 1 is a cross-sectional view of an example substrate with embedded electronic components according to aspects of the present disclosure.

[0016] Figure 2 is a cross-sectional view of an example substrate showing propagation of voids in dielectric material and resulting defects according to aspects of the present disclosure.

[0017] Figure 3 is a cross-sectional view of an example trench capacitor (DTC) according to aspects of the present disclosure.

[0018] Figure 4A and Figure 4B is a cross-sectional view of an example substrate according to aspects of the present disclosure.

[0019] Figures 5A to 5D Example operations that can be performed during fabrication of an example substrate according to aspects of the present disclosure are illustrated.

[0020] Figure 6A and Figure 6B is a cross-sectional view of an example substrate according to aspects of the present disclosure.

[0021] Figures 7A to 7E Example operations that can be performed during fabrication of an example substrate according to aspects of the present disclosure are illustrated.

[0022] Figure 8 is a flowchart illustrating an example method of fabricating a substrate according to aspects of the present disclosure.

[0023] Figure 9 Cross-sectional views of a package including a surface mount substrate, an integrated device, and an integrated passive device according to aspects of the present disclosure are illustrated.

[0024] Figure 10 Example methods for providing or fabricating a package including an integrated device including a package substrate according to aspects of the present disclosure are illustrated.

[0025] Figure 11 Various electronic devices that can be integrated with any of the described package substrates according to aspects of the present disclosure are illustrated.

[0026] According to convention, the features depicted in the drawings can not be drawn to scale. Accordingly, the dimensions of the depicted features can be arbitrarily enlarged or reduced for clarity. According to convention, certain drawings are simplified for clarity. As such, the drawings can not depict all components of a particular apparatus or method. Further, like reference numerals designate like features throughout the specification and drawings.

[0027] DETAILED DESCRIPTION

[0028] Aspects of the disclosure are illustrated by way of example in the following description and associated drawings, wherein: Alternate aspects can be devised without departing from the scope of the present teachings. Additionally, well-known elements of illustrative embodiments described herein can not be described in detail or can be omitted so as to not obscure the relevant details of the disclosure.

[0029] In certain described example implementations, instances are identified in which various component structures and portions of operations can be taken from known conventional techniques and then arranged in accordance with one or more example embodiments. In such instances, internal details of known conventional component structures and / or portions of operations can be omitted to help avoid potential obscuring of the concepts illustrated in the illustrative embodiments disclosed herein.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" and / or "containing," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] Figure 1 is a cross-sectional view of an example substrate 100 with embedded electronic components in accordance with aspects of the disclosure. In this example, the substrate 100 includes a core 102 having a cavity 104 that extends completely through the core 102. An electronic component 106 is disposed within the cavity 104. The electronic component 106 has an upper planar surface 108 having one or more electronic component terminals 110. In accordance with aspects of the disclosure, the electronic component 106 can be one or more of: an active electronic component, a passive electronic component (e.g., a deep trench capacitor (DTC)), a die, etc.

[0032] In accordance with various aspects of the disclosure, the substrates described herein (e.g., substrate 100) that include a core and embedded electronic components are related to package substrates. Package substrates are part of an integrated circuit package that give mechanical strength to the circuit board and allow it to be connected to external devices. Such package substrates are distinguished from other substrates, such as substrates that can be included in the embedded electronic component itself, dies that include substrates (e.g., silicon substrates or other similar electronic devices).

[0033] The substrate 100 further includes a plurality of dielectric layers 112 and patterned metallization layers 114 (in Figure 1only one such dielectric layer and corresponding patterned metal layer overlying the upper planar surface 116 is shown). The patterned metallization layer 118, including the via structure 120, is disposed at the upper planar surface 116 of the core 102 to provide electrical connections between the one or more electronic component terminals 110 and the patterned metallization layer 114.

[0034] In this example, one or more vias 122 extend through the core 102 and connect the patterned metallization layer 118 at the upper planar surface 116 of the core 102 with another patterned metallization layer 124 at the lower surface 126 of the core 102. An additional plurality of dielectric layers 128 and patterned metallization layers 130 are formed over the lower surface 126 of the core 102 (in Figure 1 only one such dielectric layer and corresponding patterned metal layer overlying the lower surface 126 is shown).

[0035] In an aspect, the same dielectric material used to form the dielectric layers 128 can be used to fill the cavity 104. Common dielectric materials include Ajinomoto Build-Up Film® (ABF), PPG® liquid resin, and the like. During fabrication of the substrate 100, the electronic component 106 is inserted into the cavity 104 prior to the dielectric resin being injected to fill the region 132 between the cavity 104 and the electronic component 106. During insertion, the electronic component 106 is carefully aligned within the cavity 104 to ensure that the one or more electronic component terminals 110 properly contact and electrically engage corresponding portions of the patterned metallization layer 118. Additionally, injection of the dielectric resin in the region 132 should be carefully performed so as not to disturb the initial alignment of the electronic component 106 within the cavity 104. In an aspect, once cured, the dielectric resin secures the electronic component 106 in its proper position within the cavity 104.

[0036] A current trend in substrate design involves applications that present unique design and fabrication issues (e.g., a need for reduced package substrate warpage, a need for cavities that accommodate large electronic components, a need for larger keep-out zones, etc.). These issues can be addressed, at least in part, by employing thick cores in the design and fabrication of such substrates. For example, warpage control can be more easily achieved with thick cores as compared to thin cores. Additionally, a need for larger cavity sizes and keep-out zones can be satisfied by employing such thick cores. In certain scenarios, it can be desirable for a core (e.g., both thick and thin cores) to accommodate a large embedded electronic component, where the electronic component occupies a large portion of the volume of the cavity in which the electronic component is embedded.

[0037] However, substrates that employ thick cores or that require large embedded electronic components can be difficult to manufacture using the same packaging techniques used to manufacture substrates with thin cores and / or smaller embedded electronic components. With thick cores, the increased depth of the cavity compared to the height of the electronic component (e.g., the thick core has a thickness that is greater than the height of the die) results in a significant gap between the electronic component and the cavity. In such thick core scenarios, it can be difficult or impossible to fill the cavity (e.g., especially the area between the exterior of the electronic component and the interior walls of the cavity) with a commonly used dielectric resin (e.g., Ajinomoto Build-Up Film® (ABF), PPG® liquid resin, etc.) without voids in the resulting dielectric material that embeds the electronic component. Similarly, when the electronic component occupies a large portion of the volume of the cavity, it can be difficult to fill the small area between the electronic component and the cavity with a commonly used dielectric resin sufficiently without voids in the resulting dielectric material that embeds the electronic component.

[0038] Figure 1 A void 134 in the dielectric material that fills the cavity 104 is shown, which occurs when the area between the interior surface of the cavity 104 and the exterior surface of the electronic component 106 is not sufficiently filled by the dielectric material. In Figure 1 the void 134 in the dielectric material has not yet immediately presented an issue with the connection between one or more electronic component terminals 110 and the patterned metallization layer 118. However, the void 134 can propagate through the dielectric material due to thermal and / or mechanical stresses that occur during the substrate’s use for its intended purpose.

[0039] Figure 2 is a cross-sectional view of an example substrate 100 that shows the propagation of a void 134 in the dielectric material and the resulting defect in accordance with aspects of the present disclosure. For simplicity, Figure 1 the reference numbers used in Figure 2 are also used to denote similar elements in

[0040] In Figure 2 the propagation of the void 134 has caused the electronic component 106 to move its position within the cavity 104, resulting in the electronic component 106 delaminating from the core 102. Such delamination can result in reduced performance and / or complete failure of the electronic device in which the substrate 100 is incorporated.

[0041] In accordance with certain aspects of the present disclosure, the electronic component can be a DTC. Figure 3 is a cross-sectional view of an example DTC 300 in accordance with aspects of the present disclosure. In Figure 3In this process, capacitor 310 is deposited in trench 320 of insulator 304 on substrate 302. Capacitor 310 may include metal layer 312, dielectric layer 314, and metal layer 316. Dielectric layer 314 separates metal layer 312 from metal layer 316. Metal layers 312 and 316 form electrodes of capacitor 310 and may be connected to terminals, for example, at the surface (see example...). Figure 1 The upper planar surface 108 of the electronic component terminal 110 with electronic component 106 shown. In some scenarios, the capacitor is formed by an array of deep trenches in the substrate, with an electrical insulator (e.g., a dielectric) filling the space between the electrode layers. In some scenarios, the capacitor is attached to the pad side under the shadow of the integrated circuit die (pad-side capacitor: LSC) or adjacent to the die side (die-side capacitor: DSC).

[0042] Some aspects of this disclosure are achieved in recognition of the problems associated with fabricating substrates with thick cores and / or cavities that accommodate large embedded electronic components using existing processing techniques and materials. According to some aspects of this disclosure, electronic components can be embedded in cavities using a liquid resin, which is applied within the cavity and subsequently cured to secure the electronic components within the cavity. Some aspects of this disclosure are achieved in recognition of the fluid and other material properties of such liquid resins, such as low viscosity that facilitates the filling of large cavities, allowing the liquid resin to adequately fill the area between the inner surface of the cavity and the outer surface of the electronic component without voids, thereby providing a more robust embedding of the electronic components within the core of the substrate. From a process perspective, for large cavities, liquid resin filling is superior to dielectric layer lamination filling because dielectric layer lamination filling may require high voltage and high temperature conditions that can cause displacement of the electronic components within the cavity. According to certain aspects of this disclosure, once the electronic component is embedded in the liquid resin, the liquid resin applied to the cavity during substrate manufacturing can be at least partially cured, thereby retaining the electronic component in place while the remainder of the cavity is filled with a filler material (e.g., a dielectric material, an additional amount of resin material, etc.). According to certain aspects of this disclosure, and without limitation, liquid resins (such as the THP-100DX1 series liquid resins available from Taiyo America and the PHP900 series liquid resins available from San-Ei Kagaku LLC) are suitable for securing the electronic component within the cavity.

[0043] Figure 4A and Figure 4B This is a cross-sectional view of an example substrate 400 according to various aspects of this disclosure. (See figure) Figure 4A As shown, the substrate 400 includes an array of electronic components 402 embedded in the core 404. Figure 4B yes Figure 4A An exploded view of region 406 of the substrate 400 shown.

[0044] like Figure 4B As shown, the substrate 400 includes an electronic component 402 having a lower planar surface 408 and an upper planar surface 410. The lower planar surface 410 of the electronic component 402 includes one or more electronic component terminals 412 that provide electrical connections to the electronic component 402.

[0045] Core 404 includes a lower planar surface 414 and an upper planar surface 416. A cavity 418 extends through core 404 between the upper planar surface 416 and the lower planar surface 414. In this example, the thickness H1 of core 404 has substantially the same dimension as the height H2 of electronic component 402. According to various aspects of this disclosure, core 404 may be a thin core having a thickness H1 of less than or equal to 760 micrometers (µm). Alternatively, the core may be a thick core having a thickness H1 greater than 760 µm (e.g., equal to or greater than 820 µm, equal to or greater than 1240 µm, etc.).

[0046] According to various aspects of this disclosure, electronic component 402 is mounted on top of cavity 418 in cured resin layer 420. Figure 4B In the example shown, the cured resin layer 420 fills the region of cavity 418 between the upper planar surface 410 of the electronic component 402 and the lowest dielectric layer 422 of the upper metallized structure 424 disposed above the upper planar surface 416 of the core 404. In another aspect, the cured resin layer 420 also at least partially fills the region of cavity 418 between the inner sidewall of the core 404 and the outer sidewall of the electronic component 402.

[0047] exist Figure 4B In the example shown, the upper metallization structure 424 is configured to provide one or more conductive paths between one or more electronic component terminals 412 and one or more upper metal terminals 426 of the upper metallization structure 424. The conductive paths are provided by vias (e.g., vias 428) extending between one or more dielectric layers (e.g., dielectric layer 430) connecting one or more patterned metal layers (e.g., patterned metal layer 432). In one aspect, the upper metal terminals 426 may be configured for surface-mount electronic packaging (...). Figure 4B (Not shown in the diagram) Connection. Additionally or alternatively, the upper metal terminal 426 may be configured to connect the substrate 400 to other electronic components (e.g., active components, passive components, integrated circuits, etc.).

[0048] A core via (e.g., via 434) connects one or more of the patterned metal layers of the upper metallization structure 424 (e.g., patterned metal layer 436) with one or more patterned layers of the lower metallization structure 440 (e.g., patterned metal layer 438) to electrically connect the upper metallization structure 424 with the lower metallization structure 440. The lower metallization structure 440 provides one or more conductive paths between the patterned metal layer 438 and one or more terminals 442 of the lower metallization structure 440. The metal terminals 442 can be configured to connect the substrate 400 with other electronic components (e.g., active components, passive components, integrated circuits, etc.) including surface mount electronic packages (not shown in Figure 4B

[0049] The cured resin layer 420 holds the electronic component 402 in place in the cavity 418 and provides a substantially void-free solid material (e.g., having no voids, or having fewer voids and / or voids of smaller size than typically found in common dielectric fill used to embed electronic components under similar geometric fill constraints), thereby providing a robust mounting of the electronic component 402 in the cavity 418. In this manner, the electronic component 402 is held within the cavity 418 in a manner that limits the opportunity for the electronic component 402 to peel away from the core 404.

[0050] In an aspect, the cured resin layer 420 can be initially deposited in the cavity 418 as a liquid resin. The electronic component 402 can be at least partially embedded in the liquid resin prior to the liquid resin being cured to form the cured resin layer 420. In this manner, the electronic component 402 can remain in place in the cavity 418 as the remaining portion of the cavity 418 that is initially unfilled with resin is filled with the fill material 444. In an aspect, the fill material 444 can be deposited in the cavity 418 as a liquid and cured to form the fill material 444. Figure 4B In the illustrated example, the fill material 444 is a dielectric material. In an aspect, the dielectric material used as the fill material 444 can be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 446) of the lower metallization structure 440.

[0051] Although the dielectric layers of the upper metallization structure 424 are shown as separate layers in Figure 4B , it will be appreciated that multiple dielectric layers can be fused to appear and function as a single dielectric structure during the manufacturing process. Further, it will be appreciated that different layers of the dielectric layers of the upper metallization structure 424 can be formed from different dielectric materials during the manufacturing process. In an aspect, different dielectric materials can be used for different dielectric layers when the one or more dielectric layers are to have a different dielectric constant than another dielectric layer.

[0052] Similarly, the dielectric layers of the lower metallization structure 440 are shown as separate layers in Figure 4B ​The various dielectric layers are shown as separate layers. However, it will be understood that multiple dielectric layers can be fused to appear and function as a single dielectric structure during the manufacturing process. Further, it will be understood that different layers of the dielectric layers of the upper metallization structure 424 can be formed of different dielectric materials during the manufacturing process. In an aspect, different dielectric materials can be used for different dielectric layers when one or more dielectric layers will have a different dielectric constant than another dielectric layer.

[0053] Figures 5A to 5D Example operations that can be performed during manufacturing of an example substrate are illustrated in accordance with aspects of the present disclosure. Figure 5A A first intermediate state 500 of a substrate during an example manufacturing process is shown in accordance with aspects of the present disclosure. In this example, the first intermediate state 500 of the substrate includes a core 502 having an upper planar surface 504 and a lower planar surface 506. In an aspect, the core 502 is subjected to a drilling operation to form cavities 508 extending between the first planar surface 504 and the second planar surface 506 of the core 502. Layers of polyimide (PI) tape 510 are affixed to the second planar surface 506 of the core 502 over the openings of the cavities 508.

[0054] Figure 5B A second intermediate state 512 of a substrate during an example manufacturing process is shown in accordance with aspects of the present disclosure. In this example, vias have been drilled through the core 502. The vias have been subjected to a metallization and plating operation to form core vias (e.g., core via 514). Here, the core vias (e.g., core via 514) connect the patterned metallization layers (e.g., patterned metallization layers 516, 518) at the first planar surface 504 and the second planar surface 506 of the core 502. An amount of liquid resin 520 is placed on the planar surface of the PI tape 510 at a central location within each cavity 508.

[0055] Figure 5C A third intermediate state 522 of a substrate during an example manufacturing process is shown in accordance with aspects of the present disclosure. Here, electronic components 524 are inserted into each cavity 508. In this example, each electronic component 524 has a height H2 that is the same size as the thickness H1 of the core H1. The electronic components 524 can be one or more of the following: active electronic components, passive electronic components (e.g., deep trench capacitors (DTCs)), dies, etc., in accordance with various aspects of the present disclosure.

[0056] As shown, each electronic component 524 is inserted into the cavity 508 such that the planar surface 526 of the electronic component 524 and its corresponding electronic component terminal 528 are at least partially embedded in the liquid resin 520 of the cavity 508. In this example, the electronic component 524 displaces the liquid resin 520 such that the liquid resin 520 fills the area between the PI tape 510 and the planar surface 526 of the electronic component 524. Additionally, depending on the amount of liquid resin 520 applied in the cavity 508, the electronic component 524 can displace the liquid resin 520 to the extent that the liquid resin 520 fills portions of the sidewall of the cavity 508 adjacent to the electronic component 524 (e.g., fills the area between the outer lateral sidewall 532 of the electronic component 524 and the inner lateral sidewall 534 of the cavity 508). Once each electronic component 524 is positioned within its respective cavity 508, the liquid resin 520 is cured (e.g., thermally cured on a hot plate). The liquid resin 520 now forms a cured resin layer (still identified using reference number 520) in each cavity 508 that retains the electronic component 524 in place during subsequent substrate manufacturing operations (e.g., filling portions of the cavity 508 that have not yet been filled with the cured resin layer 520).

[0057] Figure 5D Formation of the complete substrate 538 in accordance with aspects of the present disclosure is shown. Here, the layer of PI tape 510 is removed. A first metallization structure 540 is formed over the first planar surface 504 of the core 502, while a second metallization structure 542 is formed over the second planar surface 506 of the core 502. In this example, portions of the cavity 508 that were not filled with the cured resin layer 520 have been filled with a dielectric material 544. In an aspect, the dielectric material 544 can be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 546) of the first metallization structure 540.

[0058] In accordance with certain aspects of the present disclosure, formation of the metallization layers 540 and 542 can include an initial dielectric lamination operation over each of the planar surfaces 504, 506 of the core 502. The initial dielectric lamination operation can be followed by one or more build-up operations. In an aspect, each build-up operation can be performed using a semi-additive process (SAP). In accordance with such a SAP, each dielectric layer is deposited and then laser-drilled to form vias that are subjected to a chemical plating process to deposit metal on the walls of the vias. If the via structures remain hollow after the chemical plating process, the via structures can be filled with via ink. During the build-up operations, patterned metallization layers can be formed on the dielectric layers using a pattern plating and seed etch process. Formation of the metallization layers 540 and 542 can also employ a surface roughness (SR) treatment, a surface treatment, and a solder on pad (SOP) operation.

[0059] Figure 6A andFigure 6B is a cross-sectional view of an example substrate 600 according to aspects of the present disclosure. As shown, the substrate 600 includes an array of electronic components 602 embedded in a core 604. Figure 6A Figure 6B is an exploded view of a region 606 of the substrate 600 shown in Figure 6A

[0060] As shown, the substrate 600 includes an electronic component 602 having a lower planar surface 608 and an upper planar surface 610. The lower planar surface 608 of the electronic component 602 includes one or more electronic component terminals 612 that provide electrical connections to the electronic component 602. Figure 6B

[0061] The core 604 includes a lower planar surface 614 and an upper planar surface 616. A cavity 618 extends through the core 604 between the upper planar surface 616 and the lower planar surface 614. In this example, the thickness HI of the core 604 is substantially greater than the height H2 of the electronic component 602. According to various aspects of the present disclosure, the core 604 can be a thin core having a thickness HI less than or equal to 760 micrometers (pm). Alternatively, the core can be a thick core having a thickness HI greater than 760 pm (e.g., equal to or greater than 820 pm, equal to or greater than 1240 pm, etc.).

[0062] According to various aspects of the present disclosure, the electronic component 602 is mounted in a cured resin layer 620 within the cavity 618. In the example shown, the cured resin layer 620 fills a region of the cavity 618 between the upper planar surface 610 of the electronic component 602 and a lowest dielectric layer 622 of an upper metallization structure 624 disposed above the upper planar surface 616 of the core 604. In an aspect, the cured resin layer 620 also at least partially fills a region of the cavity 618 between an inner sidewall of the core 604 and an outer sidewall of the electronic component 602. Figure 6B

[0063] ​​​​As mentioned, the thickness H1 of the core 604 (and thus, the depth of the cavity 618) is substantially greater than the height H2 of the electronic component 602. As such, a large portion of the cavity 618 is not filled by the layer of cured resin 620. For very thick core options (e.g., core thickness >= 820um), it can be difficult to sufficiently fill the remaining portion of the cavity 618 with the fill material 628 (e.g., a dielectric material), even in the presence of the layer of resin 620. In an aspect, a second layer of resin 626 can be used to reduce the volume of the cavity 618 prior to filling the remaining open portion of the cavity 618 with the fill material 628. Accordingly, the additional layer of cured resin 626 is formed over the layer of cured resin 620. In this example, the additional layer of cured resin 626 fills the area between the outer sidewall of the electronic component 602 and the inner sidewall of the core 604 that is not filled by the layer of cured resin 620. Additionally, the additional layer of cured resin 620 fills the portion of the cavity 618 that is below the lower planar surface 608 of the electronic component 602. In an aspect, the layer of cured resin 620 and the additional layer of cured resin 626 can be formed from the same resin material. Alternatively, the layer of cured resin 620 and the additional layer of cured resin 626 can be formed from different resin materials. In an aspect, any remaining portion of the cavity 618 that is not filled by the layer of cured resin 620 or the additional layer of cured resin 626 can be filled with the fill material 628 (e.g., a dielectric material).

[0064] In Figure 6B In the illustrated example, the upper metallization structure 624 is configured to provide one or more conductive paths between the one or more electronic component terminals 612 and one or more upper metal terminals 630 of the upper metallization structure 624. Here, the conductive paths are formed by vias (e.g., via 632) that extend between one or more dielectric layers (e.g., dielectric layer 634) that connect one or more patterned metal layers (e.g., patterned metal layer 636). In an aspect, the upper metal terminals 630 can be configured for connection of a surface mount electronic package (such as that shown in FIG. 6B). Figure 6B Additionally or alternatively, the upper metal terminals 630 can be configured for connection of the substrate 600 with other electronic components (e.g., active components, passive components, integrated circuits, etc.).

[0065] A core via (e.g., via 638) connects one or more of the patterned metal layers (e.g., patterned metal layer 640) of the upper metallization structure 624 with one or more patterned layers (e.g., patterned metal layer 642) of the lower metallization structure 644 to electrically connect the upper metallization structure 624 with the lower metallization structure 644. The lower metallization structure 644 provides one or more conductive paths between the patterned metal layer 642 and one or more metal terminals 646 of the lower metallization structure 644. The metal terminals 646 can be configured to connect the substrate 600 with other electronic components (e.g., active components, passive components, integrated circuits, etc.) including surface mount electronic packages (not shown) during assembly of the substrate 600. Figure 6B

[0066] The cured resin layer 620 and the additional cured resin layer 626 hold the electronic component 602 in place in the cavity 618 and provide a substantially void-free solid material (e.g., having no voids, or having fewer voids and / or smaller void sizes than typically found in common dielectric fill used to embed electronic components under similar geometric fill constraints), thereby providing robust mounting of the electronic component 602 in the cavity 618. In this manner, the electronic component 602 is held within the cavity 618 in a manner that limits the opportunity for the electronic component 602 to peel away from the core 604.

[0067] In an aspect, the cured resin layer 620 can be initially deposited as a liquid resin in the cavity 618. The electronic component 602 can be at least partially embedded in the liquid resin prior to the liquid resin being cured to form the cured resin layer 620. In this manner, the electronic component 602 can remain in place in the cavity 618 when the remainder of the cavity 618 that is initially unfilled with the cured resin layer 620 is filled to form the additional cured resin layer 626 and the fill material 628. In this manner, the electronic component 602 can be held in place in the cavity 618 by the cured resin layer 620 and the additional cured resin layer 626. Figure 6B In the illustrated example, the fill material 628 can be a dielectric material. In an aspect, the dielectric material used as the fill material 628 can be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 650) of the lower metallization structure 644.

[0068] Figures 7A to 7E Example operations that can be performed during fabrication of an example substrate in accordance with aspects of the disclosure are illustrated. Figure 7A ​A first intermediate state 700 of a substrate during an example fabrication process is shown in accordance with aspects of the present disclosure. In this example, the first intermediate state 700 of the substrate includes a core 702 having an upper planar surface 704 and a lower planar surface 706. In an aspect, the core 702 is subjected to a drilling operation to form cavities 708 extending between the first planar surface 704 and the second planar surface 706 of the core 702. A layer of polyimide (PI) tape 710 is affixed to the second planar surface 706 of the core 702 over the openings of the cavities 708.

[0069] Figure 7B A second intermediate state 712 of a substrate during an example fabrication process is shown in accordance with aspects of the present disclosure. In this example, vias have been drilled through the core 702. The vias have been subjected to a metallization and plating operation to form core vias (e.g., core via 714). Here, the core vias (e.g., core via 714) connect the patterned metallization layers (e.g., patterned metallization layers 716, 718) at the first planar surface 704 and the second planar surface 706 of the core 702. An amount of liquid resin 720 is placed on the planar surface of the PI tape 710 at a central location within each cavity 708.

[0070] Figure 7C A third intermediate state 722 of a substrate during an example fabrication process is shown in accordance with aspects of the present disclosure. Here, electronic components 724 are inserted into each cavity 708. In this example, each electronic component 724 has a height H2 that is substantially less than a thickness H1 of the core 702. In accordance with various aspects of the present disclosure, the electronic components 724 can be one or more of: active electronic components, passive electronic components (e.g., deep trench capacitors (DTCs)), dies, etc.

[0071] As shown, each electronic component 724 is inserted into the cavity 708 such that the planar surface 726 of the electronic component 724 and its corresponding electronic component terminal 728 are at least partially embedded in the liquid resin 720 of the cavity 708. In this example, the electronic component 724 displaces the liquid resin 720 such that the liquid resin 720 fills the area between the PI tape 710 and the planar surface 726 of the electronic component 724. Additionally, depending on the amount of liquid resin 720 applied in the cavity 708, the electronic component 724 can displace the liquid resin 720 to the extent that the liquid resin 720 surrounds portions of the side walls of the cavity 708 (e.g., fills the area between the outer exterior sidewall 732 of the electronic component 724 and the interior sidewall 734 of the cavity 708). Once each electronic component 724 is positioned within its respective cavity 708, the liquid resin 720 is cured (e.g., thermally cured on a hot plate). The liquid resin 720 now forms a cured resin layer (still identified using reference number 720) in each cavity 708 that retains the electronic component 724 in place during subsequent substrate manufacturing operations (e.g., filling portions of the cavity 708 that have not been filled with the cured resin layer 720).

[0072] Figure 7D A fourth intermediate state 735 of the substrate during an example manufacturing process is shown in accordance with aspects of the present disclosure. Here, an additional amount of liquid resin is applied in each cavity 708. The additional amount of liquid resin is cured to form an additional cured resin layer 736. In this example, the additional cured resin layer 736 fills portions of the cavity 708 that have not been filled with the cured resin layer 720, including portions of the cavity 708 overlying the upper planar surfaces 737 of the electronic components 724.

[0073] Figure 7E Formation of a complete substrate 738 is shown in accordance with aspects of the present disclosure. Here, the layers of the PI tape 710 are removed. A first metallization structure 740 is formed over the first planar surface 704 of the core 702, while a second metallization structure 742 is formed over the second planar surface 706 of the core 702. In this example, portions of the cavity 708 that have not been filled with the cured resin layer 720 or the additional cured resin layer 736 have been filled with a dielectric material 744. In an aspect, the dielectric material 744 can be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 746) of the first metallization structure 740.

[0074] According to certain aspects of the present disclosure, the formation of the metallized structures 740 and 742 can include an initial dielectric lamination operation over each of the planar surfaces 704, 706 of the core 702. The initial dielectric lamination operation can be followed by one or more build-up operations. In an aspect, each build-up operation can be performed using a semi-additive process (SAP). According to such a SAP, each dielectric layer is deposited and then laser-drilled to form vias, which are subjected to a chemical plating process to deposit metal on the walls of the vias. If the via structures remain hollow after the chemical plating process, the via structures can be filled with via ink. During the build-up operations, patterned metallization layers can be formed on the dielectric layers using a pattern plating and seed etch process. The formation of the metallized structures 740 and 742 can also employ a surface roughness (SR) treatment, a surface treatment, and a solder on pad (SOP) operation.

[0075] Figure 8 is a flowchart illustrating an example method 800 for manufacturing a substrate according to aspects of the present disclosure. At operation 802, a cavity is formed in a core, where the cavity extends between a first planar surface of the core and a second planar surface of the core. At operation 804, an electronic component is at least partially mounted in the cavity, where the electronic component includes a first planar surface having one or more electronic component terminals, and where the first planar surface is at least partially embedded in a first cured resin layer at a first end of the cavity. At operation 806, a first metallized structure is formed over the first planar surface of the core, where the first metallized structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more metal terminals of the first metallized structure.

[0076] In some aspects, mounting the electronic component includes placing a polyimide (PI) tape over an opening at the first end of the cavity, applying a liquid resin on the PI tape in the cavity, inserting the electronic component into the cavity such that the first planar surface of the electronic component is at least partially embedded into the liquid resin, and curing the liquid resin to form the first cured resin layer.

[0077] In some aspects, the method includes filling one or more regions of the cavity that are not filled by the first cured resin layer with a fill material, where the fill material includes a dielectric filler having a same dielectric material as at least one dielectric layer of the first metallized structure, an additional amount of liquid resin that is cured to form a second cured resin layer adjacent to the first cured resin layer, an additional amount of liquid resin that is cured to form a second cured resin layer adjacent to the first cured resin layer, or a combination thereof.

[0078] In some aspects, the electronic component includes a deep trench capacitor.

[0079] The technical advantage of the method 800 is that it can be used to form a substrate with embedded electronic components (e.g., deep trench capacitors) that are robustly mounted in the cavities of the substrate. The robustness of the mounting is not as dependent on the size of the electronic components or the thickness of the core as with conventional cavity fill electronic component embedding processes.

[0080] Figure 9 A cross-sectional view of a package 900 is illustrated in accordance with aspects of the present disclosure, the package 902 including a surface mount substrate 903, an integrated device 905, and an integrated passive device 805 (e.g., a substrate with embedded electronic components in a core). The package 900 can be coupled to a printed circuit board (PCB) 910 through a plurality of solder interconnections 906. The PCB 906 can include at least one board dielectric layer 960 and a plurality of board interconnections 962.

[0081] The surface mount substrate 902 includes at least one dielectric layer 920 (e.g., a substrate dielectric layer), a plurality of interconnections 922 (e.g., substrate interconnections), a solder resist layer 940, and a solder resist layer 942. The integrated device 903 can be coupled to the surface mount substrate 902 through a plurality of solder interconnections 930. The integrated device 903 can be coupled to the surface mount substrate 902 through a plurality of stud interconnections 932 and a plurality of solder interconnections 930. The integrated passive device 905 can be coupled to the surface mount substrate 902 through a plurality of solder interconnections 950. The integrated passive device 905 can be coupled to the surface mount substrate 902 through a plurality of stud interconnections 952 and a plurality of solder interconnections 950.

[0082] The package (e.g., 900) can be implemented in a radio frequency (RF) package. The RF package can be a radio frequency front end (RFFE) package. The package (e.g., 900) can be configured to provide wireless fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 6G, 5G). The package (e.g., 900) can be configured to support global system for mobile communications (GSM), universal mobile telecommunications system (UMTS), and / or long term evolution (LTE). The package (e.g., 900) can be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0083] Figure 10 An example method 1000 for providing or manufacturing a package including an integrated device is illustrated in accordance with aspects of the present disclosure, the integrated device including a package substrate (e.g., a package substrate with embedded electronic components in a core). In some implementations, Figure 10 The method 1000 can be used to provide or manufacture the packages 900 described in the present disclosure. Figure 9 However, the method 1000 can be used to provide or manufacture any of the packages described in the present disclosure.

[0084] It should be noted that, Figure 10The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package comprising an integrated device with a magnetic layer and / or an integrated passive device with a magnetic layer. In some implementations, the order of the processes may be changed or modified.

[0085] The method (at 1005) provides a substrate (e.g., 902). The substrate 902 may be supplied by a vendor or manufactured. The substrate 902 includes at least one dielectric layer 920 and a plurality of interconnects 922. The substrate 902 may include an embedded trace substrate (ETS). In some implementations, at least one dielectric layer 920 may include a prepreg layer.

[0086] This method (at 1010) couples at least one integrated device (e.g., 903) to a first surface of a substrate (e.g., 902). For example, the integrated device 903 may be coupled to the substrate 902 via a plurality of solder interconnects 932 and a plurality of solder interconnects 930. The plurality of solder interconnects 932 may be optional. The plurality of solder interconnects 930 are coupled to a plurality of interconnects 922. A solder reflow process may be used to couple the integrated device 903 to the plurality of interconnects via the plurality of solder interconnects 930.

[0087] The method also (at 1010) couples at least one integrated passive device (e.g., 905) to a first surface of a substrate (e.g., 902). For example, the integrated passive device 905 may be coupled to the substrate 902 via a plurality of solder interconnects 952 and a plurality of solder interconnects 950. The plurality of solder interconnects 952 may be optional. The plurality of solder interconnects 950 are coupled to a plurality of interconnects 922. A solder reflow process may be used to couple the integrated passive device 905 to the plurality of interconnects via the plurality of solder interconnects 950.

[0088] This method (at 1015) couples multiple solder interconnects (e.g., 910) to a second surface of a substrate (e.g., 902). A solder reflow process can be used to couple these multiple solder interconnects 910 to the substrate.

[0089] Figure 11 This describes various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, intermediate packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or motor vehicle 1110 may include device 1100 as described herein. Device 1100 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 11The devices 1102, 1104, 1106, and 1108, and vehicle 1110 illustrated in FIG. 11 are merely exemplary. Other electronic devices can also feature device 1100, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0090] Implementation examples are described in the following numbered clauses:

[0091] Clause 1. An electronic device, comprising: a substrate comprising a core having an upper planar surface and a lower planar surface, wherein the core comprises a cavity extending between the upper planar surface of the core and the lower planar surface of the core; an electronic component at least partially disposed in the cavity, wherein the electronic component has an upper planar surface having one or more electronic component terminals; a first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more electrically conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0092] Clause 2. The electronic device of clause 1, wherein: the first cured resin layer fills an area between the upper planar surface of the electronic component and a lower dielectric layer of the upper metallization structure.

[0093] Clause 3. The electronic device of any of clauses 1-2, wherein: the core comprises a plurality of inner sidewalls; the electronic component comprises a plurality of outer sidewalls facing the plurality of inner sidewalls of the core; and the first cured resin layer fills an area between the plurality of outer sidewalls of the electronic component and the plurality of inner sidewalls of the core.

[0094] Clause 4. The electronic device of clause 3, further comprising: a dielectric filler disposed in at least a portion of the cavity under the first cured resin layer.

[0095] Clause 5. The electronic device of clause 4, wherein: the electronic component has a height that is greater than or equal to a depth of the core.

[0096] Aspect 6. The electronic device of Aspect 5, wherein: the core has a thickness equal to or less than 760 microns.

[0097] Aspect 7. The electronic device of any of Aspects 4-6, further comprising: a lower metallization structure disposed below the lower planar surface of the core, wherein the lower metallization structure is configured to provide one or more conductive paths from the patterned metallization layer disposed above the lower planar surface of the core to one or more lower metal terminals of the lower metallization structure.

[0098] Aspect 8. The electronic device of Aspect 7, wherein: the dielectric filler comprises the same dielectric material as the at least one dielectric layer of the lower metallization structure.

[0099] Aspect 9. The electronic device of any of Aspects 1-8, further comprising: a second cured resin layer filling at least a portion of the cavity below the first cured resin layer and below the lower planar surface of the electronic assembly.

[0100] Aspect 10. The electronic device of Aspect 9, further comprising: a lower metallization structure disposed below the lower planar surface of the core and below the second cured resin layer, wherein the second cured resin layer fills the cavity between the first cured resin layer and an upper surface of the lower metallization structure.

[0101] Aspect 11. The electronic device of any of Aspects 9-10, wherein: the first cured resin layer and the second cured resin layer are formed of the same resin material.

[0102] Aspect 12. The electronic device of any of Aspects 9-11, wherein: the electronic assembly has a height that is less than a depth of the core.

[0103] Aspect 13. The electronic device of Aspect 12, wherein: the core has a thickness greater than 760 microns.

[0104] Aspect 14. The electronic device of any of Aspects 1-13, further comprising: one or more metal vias extending between the upper planar surface of the core and the lower planar surface of the core.

[0105] Aspect 15. The electronic device of any of Aspects 1-14, further comprising: an electronic circuit package mounted at the one or more upper metal terminals of the upper metallization structure.

[0106] Aspect 16. The electronic device of any of Aspects 1-15, wherein: the electronic assembly comprises a deep trench capacitor.

[0107] Aspect 17. The method of any of aspects 1 through 16, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in an automotive vehicle.

[0108] Aspect 18. A substrate comprising: a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface of the core and the lower planar surface of the core; an electronic assembly at least partially disposed in the cavity, wherein the electronic assembly has an upper planar surface having one or more electronic assembly terminals; a first cured resin layer, wherein the upper planar surface of the electronic assembly is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more electrically conductive paths from the one or more electronic assembly terminals to one or more upper metal terminals of the upper metallization structure.

[0109] Aspect 19. The substrate of aspect 18, wherein: the first cured resin layer fills an area between the upper planar surface of the electronic assembly and a lower dielectric layer of the upper metallization structure.

[0110] Aspect 20. The substrate of any of aspects 18 through 19, wherein: the core includes a plurality of inner sidewalls; the electronic assembly includes a plurality of outer sidewalls facing the plurality of inner sidewalls of the cavity; and the first cured resin layer fills an area between the plurality of outer sidewalls of the electronic assembly and the plurality of inner sidewalls of the core.

[0111] Aspect 21. The substrate of aspect 20, further comprising: a dielectric filler filling at least a portion of the cavity under the first cured resin layer.

[0112] Aspect 22. The substrate of aspect 21, wherein: the electronic assembly has a height that is greater than or equal to a depth of the core.

[0113] Aspect 23. The substrate of any of aspects 18 through 22, further comprising: a second cured resin layer filling at least a portion of the cavity under the first cured resin layer and under a lower planar surface of the electronic assembly.

[0114] Aspect 24. The substrate of aspect 23, wherein: the first cured resin layer and the second cured resin layer are formed of a same resin material.

[0115] Aspect 25. The substrate of any of aspects 23 through 24, wherein: the electronic assembly has a height that is less than a depth of the core.

[0116] Aspect 26. The substrate of any one of Aspects 18-25, wherein: the electronic component comprises a deep trench capacitor.

[0117] Aspect 27. A method for fabricating a substrate, comprising: forming a cavity in a core, wherein the cavity extends between a first planar surface of the core and a second planar surface of the core; mounting an electronic component at least partially in the cavity, wherein the electronic component comprises a first planar surface having one or more electronic component terminals, and wherein the first planar surface of the electronic component is at least partially embedded in a first cured resin layer at a first end of the cavity; and forming a first metallization structure over the first planar surface of the core, wherein the first metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more metal terminals of the first metallization structure.

[0118] Aspect 28. The method of Aspect 27, wherein mounting the electronic component comprises: placing a polyimide (PI) tape over an opening at the first end of the cavity; applying a liquid resin on the PI tape in the cavity; inserting the electronic component into the cavity such that the first planar surface of the electronic component is at least partially embedded into the liquid resin; and curing the liquid resin to form the first cured resin layer.

[0119] Aspect 29. The method of Aspect 28, further comprising: filling one or more regions of the cavity that are not filled by the first cured resin layer with a fill material, wherein the fill material comprises a dielectric filler having a same dielectric material as at least one dielectric layer of the first metallization structure; a further amount of liquid resin that is cured to form a second cured resin layer adjacent to the first cured resin layer; or a combination thereof.

[0120] Aspect 30. The method of any one of Aspects 28-29, wherein: the electronic component comprises a deep trench capacitor.

[0121] Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0122] Note that the figures in the present disclosure can represent actual and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the figures can not be to scale. In some instances, not all components and / or assemblies are shown for the sake of clarity. In some instances, the positioning, location, size, and / or shape of various components and / or assemblies in the figures can be exemplary. In some implementations, various components and / or assemblies in the figures can be optional.

[0123] The expression "example" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "example" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, a term "aspect" does not require that all aspects of the disclosure include the particular feature, advantage, or mode of operation described. The term "coupled" is used herein to express a direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically touches object B, and object B touches object C, then object A and C can still be considered coupled to one another, even though they are not in direct physical contact with one another. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that electrical current (e.g., signals, power, ground) can pass between the two objects. Two objects that are electrically coupled can or can not have electrical current passing between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any of the components described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "enclose" means that an object can partially enclose or completely enclose another object. The terms "top" and "bottom" are arbitrary. A component that is on top of another component can be above a component that is on the bottom. A top component can be considered a bottom component and vice versa. As described in the present disclosure, a first component that is "on" a second component can mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be on (e.g., above) a first surface of a second component, while a third component can be on (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that the term "on" as used in the present application in the context of a component being on another component can be used to mean that the component is on and / or in the other component (e.g., on a surface of the other component or embedded in the other component). Thus, for example, a first component being on a second component can mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on (e.g., on a surface of) the second component, and / or (3) the first component is in (e.g., embedded in) the second component. A first component that is "in" a second component can be partially in the second component or completely in the second component. The term "about 'value X'" or "approximately value X" as used in the present disclosure means within ten percent of 'value X.' For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0124] In some implementations, an interconnect is an element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect can include a trace, a via, a pad, a stud, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect can include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect can include more than one element or component. An interconnect can be defined by one or more interconnects. An interconnect can include one or more metal layers. An interconnect can be part of a circuit. Different implementations can use different processes and / or procedures to form an interconnect. In some implementations, an interconnect can be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray, and / or a plating process.

[0125] It should also be noted that various disclosures contained herein can be described as a process that is depicted as a flowchart, flow diagram, structure diagram, or block diagram. Although the flowchart can describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations can be re-arranged. A process is terminated when its operations are completed.

[0126] In the above detailed description, various features are grouped together in examples. This manner of disclosure should not be understood as a limitation of the example aspects to the features recited in each aspect. Rather, various aspects of the disclosure can include fewer than all the features of each disclosed example aspect. Accordingly, the appended aspects should not be considered exhaustive with respect to the scope of the disclosure. It should also be noted that although each dependent aspect can refer to a particular combination of features of an aspect, the dependent aspect(s) are not limited to that particular combination. It will be appreciated that other example aspects can include the dependent aspect(s) in combination with the subject matter of any other dependent aspect or independent aspect, or in combination with other dependent and independent aspects. The various aspects disclosed herein expressly include these combinations, unless expressly stated or readily apparent to those skilled in the art that a particular combination is not intended (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Further, it is also intended that aspects of an aspect can be included in any other independent aspect, even if the aspect is not directly dependent from that independent aspect.

[0127] While the forgoing disclosure shows illustrative aspects of the present disclosure, it should be noted that various changes and modifications could be made without departing from the scope of the present disclosure as defined in the appended claims. The functions, steps and / or actions of the methods claims in accordance with the aspects of the present disclosure described herein need not be performed in any particular order. Furthermore, although elements of the present disclosure can be described or claimed in particular combinations, each combination should be construed as if each and every subcombination of elements within that combination is explicitly claimed.

Claims

1. An electronic device, comprising: A substrate, the substrate comprising: A core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface and the lower planar surface of the core; An electronic component, which is at least partially disposed in the cavity, wherein the electronic component has an upper planar surface having one or more electronic component terminals; A first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at the upper portion of the cavity; and An upper metallization structure is disposed above the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

2. The electronic device as claimed in claim 1, wherein: The first cured resin layer fills the region between the upper planar surface of the electronic component and the lower dielectric layer of the upper metallized structure.

3. The electronic device as claimed in claim 1, wherein: The core includes multiple inner sidewalls; The electronic component includes a plurality of outer sidewalls facing the plurality of inner sidewalls of the core; and The first cured resin layer fills the area between the plurality of outer sidewalls of the electronic component and the plurality of inner sidewalls of the core.

4. The electronic device of claim 3, further comprising: A dielectric filler is disposed in at least a portion of the cavity beneath the first cured resin layer.

5. The electronic device as claimed in claim 4, wherein: The height of the electronic component is greater than or equal to the depth of the core.

6. The electronic device as claimed in claim 5, wherein: The core has a thickness of 760 micrometers or less.

7. The electronic device of claim 4, further comprising: A lower metallization structure disposed below the lower plane surface of the core, wherein the lower metallization structure is configured to provide one or more conductive paths from a patterned metallization layer disposed above the lower plane surface of the core to one or more lower metal terminals of the lower metallization structure.

8. The electronic device as claimed in claim 7, wherein: The dielectric filler comprises the same dielectric material as at least one dielectric layer of the lower metallization structure.

9. The electronic device of claim 1, further comprising: A second cured resin layer fills at least a portion of the cavity below the first cured resin layer and below the lower plane surface of the electronic component.

10. The electronic device of claim 9, further comprising: A lower metallized structure is disposed below the lower plane surface of the core and below the second cured resin layer, wherein the second cured resin layer fills the cavity between the first cured resin layer and the upper surface of the lower metallized structure.

11. The electronic device as claimed in claim 9, wherein: The first cured resin layer and the second cured resin layer are formed of the same resin material.

12. The electronic device of claim 9, wherein: The height of the electronic component is less than the depth of the core.

13. The electronic device of claim 12, wherein: The core has a thickness greater than 760 micrometers.

14. The electronic device of claim 1, further comprising: One or more metal through-holes extending between the upper surface of the core and the lower surface of the core.

15. The electronic device of claim 1, further comprising: An electronic circuit package is mounted at one or more upper metal terminals of the upper metallized structure.

16. The electronic device as claimed in claim 1, wherein: The electronic components include deep trench capacitors.

17. The electronic device of claim 1, wherein the electronic device comprises at least one of the following: Music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, or devices in motor vehicles.

18. A substrate, comprising: A core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface and the lower planar surface of the core; An electronic component, which is at least partially disposed in the cavity, wherein the electronic component has an upper planar surface having one or more electronic component terminals; A first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at the upper part of the cavity; as well as An upper metallization structure is disposed above the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

19. The substrate of claim 18, wherein The first cured resin layer fills the region between the upper planar surface of the electronic component and the lower dielectric layer of the upper metallized structure.

20. The substrate of claim 18, wherein The core includes multiple inner sidewalls; The electronic component includes multiple outer sidewalls facing the plurality of inner sidewalls of the cavity; and The first cured resin layer fills the area between the plurality of outer sidewalls of the electronic component and the plurality of inner sidewalls of the core.

21. The substrate of claim 20, further comprising: A dielectric filler that fills at least a portion of the cavity beneath the first cured resin layer.

22. The substrate of claim 21, wherein The height of the electronic component is greater than or equal to the depth of the core.

23. The substrate of claim 18, further comprising: A second cured resin layer fills at least a portion of the cavity below the first cured resin layer and below the lower plane surface of the electronic component.

24. The substrate of claim 23, wherein The first cured resin layer and the second cured resin layer are formed of the same resin material.

25. The substrate of claim 23, wherein The height of the electronic component is less than the depth of the core.

26. The substrate of claim 18, wherein The electronic components include deep trench capacitors.

27. A method for manufacturing a substrate, comprising: A cavity is formed in the core, wherein the cavity extends between a first planar surface of the core and a second planar surface of the core; An electronic component is at least partially mounted in the cavity, wherein the electronic component includes a first planar surface having one or more electronic component terminals, and wherein the first planar surface of the electronic component is at least partially embedded in a first cured resin layer at a first end of the cavity; as well as A first metallization structure is formed on the first planar surface of the core, wherein the first metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more metal terminals of the first metallization structure.

28. The method of claim 27, wherein installing the electronic component comprises: Place a polyimide (PI) tape over the opening at the first end of the cavity; Liquid resin is applied to the PI strip in the cavity; The electronic component is inserted into the cavity such that the first planar surface of the electronic component is at least partially embedded in the liquid resin; as well as The liquid resin is cured to form the first cured resin layer.

29. The method of claim 28, further comprising: The cavity is filled with one or more areas not filled by the first cured resin layer using a filler material, wherein the filler material comprises: Dielectric filler having at least one dielectric layer of the same dielectric material as the first metallized structure; A further amount of liquid resin is cured to form a second cured resin layer adjacent to the first cured resin layer; or Its combination.

30. The method of claim 28, wherein: The electronic components include deep trench capacitors.

Images