Trench junction field effect transistor including mesa region

Abstract

The invention provides a trench junction field effect transistor and a trench JFET (100). The trench JFET (100) includes: a mesa region (103) defined by first and second trenches (1061, 1062) spaced apart from each other in a first lateral direction (x1) of the semiconductor body (102), the first and second trenches (1061, 1062) extending from the first surface (108) into the semiconductor body (102); a mesa channel region (104) of the first conductivity type (103); a first control region (1101) of a second conductivity type complementary to the first conductivity type arranged in the mesa region (103) adjacent to the first trench (1061); and a second control region (1102) of a second conductivity type arranged in the mesa region (103) adjacent to the second trench (1062). The mesa channel region (104) is arranged in the first lateral direction (x1) between the first control region (1101) and the second control region (1102), and the first control region (1101) is electrically coupled to the source contact (S) and the second control region (1102) is electrically coupled to the gate contact (G).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and in particular to a trench junction field effect transistor, i.e., a trench JFET, including a mesa region. BACKGROUND

[0002] Technological development of new generations of semiconductor devices, such as junction field effect transistors (JFETs), aims to improve the characteristics of electronic devices and reduce costs by scaling down the geometry of the devices. While cost reduction can be achieved by scaling down the device geometry, various trade-offs and challenges must be met when increasing the device functionality per unit area. For example, the on-resistance R on Trade-offs between xA and, for example, reliability requirements affected by switching efficiency require design optimization.

[0003] Accordingly, there is a need for an improved junction field effect transistor. SUMMARY

[0004] One example relates to a trench junction field effect transistor JFET. The trench JFET includes a mesa region defined by a first trench and a second trench spaced apart from each other in a first lateral direction of a semiconductor body, the first trench and the second trench extending from a first surface into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type arranged in the mesa region adjacent to the first trench; and a second control region of the second conductivity type arranged in the mesa region adjacent to the second trench. The mesa channel region is arranged between the first control region and the second control region in the first lateral direction. The first control region is electrically coupled to a source contact, and the second control region is electrically coupled to a gate contact.

[0005] Another example relates to a trench junction field effect transistor JFET. The trench JFET includes a mesa region defined by a first trench and a second trench along a first lateral direction, the first trench and the second trench extending from a first surface of a semiconductor body into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type arranged in the mesa region adjacent to the first trench; and a second control region of the second conductivity type arranged in the mesa region adjacent to the second trench. The mesa channel region is arranged between the first control region and the second control region in the first lateral direction. Each of the first trench and the second trench includes a gate electrode or a source electrode and a bottom electrode, the gate electrode or the source electrode (1131, 1132) being arranged between the bottom electrode and the first surface.

[0006] Those skilled in the art will realize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of trench JFETs and, together with the description, serve to explain principles of the examples. Further examples are described in the detailed description and claims.

[0008] Figure 1 is a schematic and exemplary cross-sectional view of one example of a trench JFET with a mesa channel region defined by control regions electrically coupled to different contacts.

[0009] Figure 2 is a schematic and exemplary cross-sectional view of one example of a trench JFET with a top electrode and a bottom electrode in the trench.

[0010] Figure 3 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 1 and including a conductive liner abutting the control regions at a bottom portion of the trench.

[0011] Figure 4 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 2 and including a conductive liner abutting the control regions at a bottom portion and sidewalls of the trench.

[0012] Figure 5 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 1 and including a super junction structure.

[0013] Figure 6 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 1 and including measures for electrically deactivating the mesa channel region.

[0014] Figure 7 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 1 and including mesa regions with different widths.

[0015] Figure 8 is a schematic and exemplary cross-sectional view of another example of a trench JFET including a super junction structure.

[0016] Figure 9 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 8 .

[0017] Figure 10 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 9

[0018] Figure 11 is a schematic and exemplary cross-sectional view of another example of a trench JFET including a super junction structure.

[0019] Figure 12 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 11

[0020] Figure 13A-Figure 13F illustrates one example of a form of a method of forming a trench JFET according to Figure 12

[0021] Figure 14 is a schematic and exemplary cross-sectional view of one example of a trench JFET based on a trench JFET according to Figure 11 DETAILED DESCRIPTION

[0022] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific examples of trench JFETs. It is to be understood that other examples can be utilized, and that structural or logical changes can be made without departing from the scope of the present disclosure. For example, the specific examples illustrated and described herein can be used with other examples and that the phrases and terms used herein are not intended to exclude non-technical possibilities. It is intended that the disclosure include such modifications and variations. Specific language is used to describe these examples, but the use of specific language is not intended to limit the scope of the claims. The drawings are not scaled, and are for illustrative purposes only. If not otherwise specified, corresponding elements in different drawings are designated by like reference numerals.

[0023] The terms "have," "comprise," "include," "contain," and the like are open-ended and these terms mean that the structures, elements, or features that the described structure, element, or feature includes, but do not exclude additional elements or features. Unless otherwise specified, the articles "a," "an," and "the" are intended to include plural as well as singular. The terms "comprise," "comprising," "include," "including," and the like are open-ended, and each means that the described structure, element, or feature includes, but is not limited to, the recited structure, element, or feature.

[0024] ​​​​The term "electrically connected" describes a permanent low-resistance connection between electrically connected elements, for example a direct contact between the elements concerned or a low-resistance connection via a metal and / or a heavily doped semiconductor material. The term "electrically coupled" includes that one or more intervening elements suitable for signal and / or power transmission can be connected between the electrically coupled elements, for example elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.

[0025] A range given for a physical size includes the boundary values. For example, a parameter y ranging from a to b reads as a < y < b. The same applies to ranges having one boundary value, such as "at most" and "at least".

[0026] The terms "on" and "over" should not be interpreted as meaning "directly on" and "directly over" only. Rather, if an element is positioned "on" or "over" another element (for example, a layer "on" or "over" another layer or "on" or "over" a substrate), further components (for example, further layers) can be positioned between the two elements (for example, if a layer is "on" or "over" a substrate, further layers can be positioned between the layer and the substrate).

[0027] One example of a vertical junction field effect transistor VJFET includes a mesa region defined by a first trench and a second trench along a first lateral direction. This type of vertical JFET can also be referred to as a trench JFET. The first trench and the second trench extend from a first surface of a semiconductor body into the semiconductor body. The trench JFET further includes a mesa channel region of a first conductivity type, which can be defined along the first lateral direction by a first control region and a second control region of a second conductivity type. A first pn junction is defined by the mesa channel region and the first control region. A second pn junction is defined by the mesa channel region and the second control region. The first control region is electrically coupled to a source contact, and the second control region is electrically coupled to a gate contact.

[0028] The first lateral direction can be a lateral direction of the mesa region, which can be perpendicular to a second lateral direction. For example, the second lateral can be a longitudinal direction of the mesa region. For example, a width of the mesa region or a width of the first trench and the second trench can be measured, for example, along the first lateral direction.

[0029] For example, the trench JFET can be part of an integrated circuit, or can define a discrete semiconductor device or semiconductor module. For example, the trench JFET can be a trenched and implanted vertical channel JFET, i.e. a TI-VJFET. In a vertical channel JFET, the load current flows between a first load contact above a first surface of the semiconductor body and a second load contact above a second surface opposite the first surface along a vertical direction. In a vertical channel JFET, the load current can flow along a vertical direction perpendicular to the first surface and / or the second surface.

[0030] For example, the first surface can be a front surface or top surface of the semiconductor body, and the second surface can be a back surface or rear surface of the semiconductor body. For example, the semiconductor body can be attached to a lead frame via, for example, the second surface. For example, on the first surface of the semiconductor body, a bond pad can be arranged, and a bond wire can be bonded on the bond pad.

[0031] The semiconductor body can comprise or consist of a semiconductor material from a Group IV elemental semiconductor, a Group IV-IV compound semiconductor material, a Group III-V compound semiconductor material, or a Group II-VI compound semiconductor material. Examples of semiconductor materials from a Group IV elemental semiconductor include silicon (Si) and germanium (Ge), among others. Examples of Group IV-IV compound semiconductor materials include silicon carbide (SiC) and silicon germanium (SiGe), among others. Examples of Group III-V compound semiconductor materials include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs), among others. Examples of Group II-VI compound semiconductor materials include cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe), among others. For example, the semiconductor body can be a crystalline SiC semiconductor substrate on which no SiC layer is formed, one or more SiC layers are formed. For example, the silicon carbide crystal can have a hexagonal polytype, such as 4H or 6H. The silicon carbide semiconductor body can be uniformly doped or can comprise differently doped SiC layer portions. The silicon carbide semiconductor body can comprise one or more layers from another material. For example, the layer from another material can be embedded in the crystalline silicon carbide substrate. The silicon carbide semiconductor substrate can have two substantially parallel major surfaces of the same shape and size and a lateral surface region connecting edges of the two major surfaces.

[0032] A trench JFET can be configured to conduct currents greater than 1A, greater than 10A, or even greater than 100A. For example, a trench JFET can be designed as a transistor cell array comprising multiple transistor cells with the same or similar layout. The transistor cell array can be a one-dimensional or two-dimensional regular arrangement of multiple transistor cells. For example, multiple transistor cells in a transistor cell array can be electrically connected in parallel. For example, the source regions of multiple transistor cells in a trench JFET transistor cell array can be electrically connected together. Similarly, the drain regions of multiple transistor cells in a trench JFET transistor cell array can be electrically connected together. For example, the gate regions of multiple transistor cells in a trench JFET transistor cell array can be electrically connected together. The transistor cells of the transistor cell array, or a portion thereof, such as the gate region, can be designed as, for example, stripes, polygons, circles, or ellipses.

[0033] For example, the number of transistor cells in a transistor cell array can depend on the maximum load current. For example, the number of transistor cells in a transistor cell array can be greater than 100, or greater than 1000, or even greater than 10000. The trench JFET can be further configured to block voltages greater than 60V, 100V, 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, or 10kV between the load electrodes (e.g., between the drain and source of the trench JFET). For example, the blocking voltage can correspond to the voltage rating specified in the trench JFET's datasheet. The blocking voltage of the trench JFET can be adjusted by the impurity concentration and / or vertical extension of the drift band in the semiconductor body. The doping concentration of the drift band can vary along the lateral and / or vertical directions, for example, gradually changing or gradually increasing or decreasing, at least in its vertically extended portion, as the distance to the first surface increases. For example, in the case of superjunction devices, the doping type can vary along the lateral direction, such as alternating. According to other examples, the impurity concentration in the drift band can be approximately uniform. For silicon-based trench JFETs, the average impurity concentration in the drift band can be as high as 2 × 10⁻⁶. 12 cm -3 and 1×10 17 cm -3 Between, for example, in the range of 5×10 12 cm -3 Up to 1×10 15 cm -3 Or to 2×10 15 cm -3 Within a certain range. In the case of SiC-based trench JFETs, the average impurity concentration in the drift band can reach 5 × 10⁻⁶. 14 cm -3 and 1×10 17 cm-3 between, for example, 1 x 10 15 cm -3 and 5 x 10 16 cm -3 The vertical extension of the drift zone can depend on the voltage blocking requirements of the trench JFET, for example a specified voltage class. When operating the trench JFET in voltage blocking mode, the space charge region can extend partially or fully vertically through the drift zone, depending on the blocking voltage applied to the trench JFET.

[0034] The source contact and the drain contact can be part of a wiring region on top of the semiconductor body. The wiring region can comprise one or more, for example two, three, four or even more wiring levels. Each wiring level can be formed by a single conductive layer or a stack of conductive layers, for example a metal layer(s). For example, the wiring levels can be lithographically patterned. Between the stacked wiring levels, an interlayer dielectric structure can be arranged. A contact plug(s) or a contact line(s) can be formed in an opening in the interlayer dielectric structure to electrically connect parts, for example metal lines or contact areas, of different wiring levels to each other. The source contact can be formed by one or more elements of the wiring region on top of the first surface. Likewise, the drain contact can be formed by one or more elements of the wiring region on top of the second surface.

[0035] For example, when forming the semiconductor layer on the substrate, for example by a layer deposition technique, the doping concentration in the mesa channel region can be set by in-situ doping with dopants of the first conductivity type. In addition or as an alternative, the doping concentration in the mesa channel region can be set by ion implantation of dopants of the first conductivity type through the sidewalls of the first trench and / or the sidewalls of the second trench, for example by one or more tilted ion implantation processes.

[0036] For example, the first control region and the second control region of the second conductivity type can be formed by ion implantation of dopants of the second conductivity type through the sidewalls of each of the first trench and the second trench and, optionally, through the bottom side thereof.

[0037] For example, after forming the mesa channel region and the first control region and the second control region, a trench structure can be formed in each of the first trench and the second trench. The trench structure can include a contact material, which can be formed of one or more electrically conductive materials, such as a metal, a metal silicide, a metal compound, a highly doped semiconductor material such as highly doped polysilicon. For example, the contact material can be a single layer, such as a highly doped polysilicon layer, or a stack of layers. For example, the trench structure can further include a dielectric structure. For example, the dielectric structure can include a plurality of consolidated dielectric portions, which can be different in material. The dielectric structure can be or can include an insulating material, such as an oxide (e.g., Si02), a nitride (e.g., Si3N4), a high-k dielectric, or a low-k dielectric, or any combination thereof. For example, the dielectric structure can be formed as a tetraethyl orthosilicate (TEOS). The contact material of the trench structure in the first trench can be electrically connected to the first control region of the second conductivity type via a bottom side and / or a sidewall of the trench structure. For example, the contact material can be electrically connected to the first control region through an opening in the dielectric structure of the trench structure, such as at a bottom side of the trench structure. Likewise, the contact material of the trench structure in the second trench can be electrically connected to the second control region of the second conductivity type via a bottom side and / or a sidewall of the trench structure. For example, the contact material can be electrically connected to the second control region through an opening in the dielectric structure of the trench structure, such as at a bottom side of the trench structure. Although the trench structures in the first trench and the second trench can be processed together, the contact material of the trench structure in the first trench can be electrically coupled to a source contact or electrode, and the contact material of the trench structure in the second trench can be electrically coupled to a gate contact.

[0038] For example, for p-type doping, the dopant in the semiconductor body including SiC can include Al, B, Be, Ga, or any combination thereof, and for n-type doping, can include N, P, or any combination thereof. For example, for p-type doping, the dopant in the semiconductor body including Si can include Al, B, Ga, In, or any combination thereof, and for n-type doping, can include P, As, Sb, a hydrogen-related donor, or any combination thereof.

[0039] For example, the trench JFET can further include an edge termination region laterally separating the active trench JFET region and the field-free region, and can laterally completely surround the active trench JFET region. In the blocking mode or reverse bias mode of the trench JFET, the blocking voltage between the active trench JFET region and the field-free region laterally drops across termination structures in the edge termination region. The edge termination region can have a higher or slightly lower voltage blocking capability than the active trench JFET region. The termination structures in the edge termination region can include or can be junction termination extensions (JTEs) with or without lateral doping variations (VLDs), one or more laterally separated guard rings, or any combination thereof.

[0040] By electrically coupling the first control region to the source contact instead of, for example, the gate contact, the gate-drain capacitance Cgd and the ratio of Cgd to gate-source capacitance Cgs can be reduced. This can improve switching efficiency and switching speed by reducing the amount of gate charge that must be removed when switching. This can also allow for improved ease of use of the trench JFET.

[0041] For example, the first trench can include a dielectric trench fill structure.

[0042] The functional or structural configuration details described above with respect to the example trench JFET apply equally to another example of a trench junction field effect transistor that includes a mesa region defined by a first trench and a second trench along a first lateral direction. The first trench and the second trench extend from a first surface of a semiconductor body into the semiconductor body. The trench JFET further includes a mesa channel region of a first conductivity type defined by first and second control regions of a second conductivity type along the first lateral direction. A first pn junction is defined by the mesa channel region and the first control region. A second pn junction is defined by the mesa channel region and the second control region. Each of the first and second trenches includes a gate or source electrode and a bottom electrode. The gate or source electrode is arranged between the bottom electrode and the first surface.

[0043] For example, the trench JET further includes a dielectric separation region, such as an oxide, arranged between the bottom electrode and the gate or source electrode.

[0044] For example, each of the first and second control regions can be divided into a top portion and a bottom portion. The top and bottom portions can be vertically spaced apart from each other by an intermediate separation region of the first conductivity type. For example, this can allow for avoiding a short circuit between the bottom electrode and the gate or source electrode arranged above the bottom electrode.

[0045] For example, the intermediate separation region can adjoin the dielectric separation region along the first lateral direction.

[0046] For example, the trench JFET can further comprise a first conductive liner at a sidewall portion of at least one of the first trench and the second trench. The first conductive liner can be laterally arranged between the trench fill material (e.g., conductive material of the gate electrode or the source electrode) in at least one of the first trench and the second trench and the corresponding one of the first control region and the second control region. The first conductive liner can improve or enable ohmic contact between the trench fill material in at least one of the first trench and the second trench and the corresponding one of the first control region and the second control region. Further, the first conductive liner can improve transverse conductivity along a longitudinal direction of at least one of the first trench and the second trench. For example, this can help to reduce resistive losses from the gate electrode in the trench to the gate pad. For example, the first conductive liner can be formed of a metal such as Ni or Ti, which can further comprise an additive such as Al.

[0047] For example, the trench JFET can further comprise a second conductive liner at a bottom portion of at least one of the first trench and the second trench. The second conductive liner can be vertically arranged between the trench fill material in at least one of the first trench and the second trench and the corresponding one of the first control region and the second control region. The second conductive liner can improve ohmic contact between the trench fill material (e.g., conductive material of the bottom electrode) in at least one of the first trench and the second trench and the corresponding one of the first control region and the second control region. Further, the first conductive liner can improve transverse conductivity along a longitudinal direction of at least one of the first trench and the second trench. This can help to reduce resistive losses from the bottom electrode in the trench to the corresponding contact region (e.g., source contact or gate contact). For example, the second conductive liner can be formed of a metal such as Ni or Ti, which can further comprise an additive such as Al.

[0048] For example, the trench JFET can further comprise a super junction structure arranged between a bottom side of the first trench and the second trench and a second surface of the semiconductor body opposite the first surface of the semiconductor body.

[0049] For example, the super junction structure can comprise a first SJ region of a first conductivity type and a second SJ region of a second conductivity type. The first SJ region can be electrically coupled to the drain contact at the second surface of the semiconductor body and the source contact at the first surface of the semiconductor body. The second SJ region can be electrically coupled to the first control region and the second control region. For example, a top side of the second SJ region can abut a bottom side of the first control region and the second control region. For example, a doping concentration profile of the second SJ region and the first control region and the second control region can overlap one another.

[0050] For example, a range of vertical extension of the super junction structure can be from 50% to 2000% of a vertical extension of the first trench and the second trench.

[0051] For example, the trench JFET can further comprise a source region of the second conductivity type arranged on one of the opposite sidewalls of the mesa region adjoining the second trench. For example, this can allow to improve the ohmic contact between the mesa channel region and the source contact.

[0052] For example, the trench JFET can further comprise a second mesa region. The second mesa region can be wider than the mesa region. The second trench is laterally defined by the mesa region and the second mesa region. For example, the mesa regions with different widths can allow to counteract an offset of the pinch-off voltage resulting from different pinch-off behaviors which can be caused by control regions with different potentials.

[0053] For example, the extent of the mesa region along the first lateral direction can range from 200 nm to 2 pm.

[0054] For example, along the first lateral direction, the mesa channel region can comprise first, second and third mesa channel sub-regions having the same extent along the first lateral direction. The concentration of dopants of the first conductivity type averaged along the first lateral direction in the second mesa channel sub-region can be greater than the concentration of dopants of the first conductivity type averaged along the first lateral direction in each of the first and third mesa channel sub-regions. By providing a trench JFET with the above relationship with respect to the dopant concentration in the mesa channel region, the compensation of the channel charge amount caused by the overlap of the doping profiles of the first control region and the second control region and the mesa channel region can be reduced. This can allow to stabilize the charge amount in the mesa channel. As a result, the variability of the pinch-off voltage or threshold voltage of the trench JFET can be reduced. This can further improve the ease of use of the trench JFET.

[0055] The examples and features described above and below can be combined.

[0056] The functional and structural details described with respect to the above examples shall equally apply to the exemplary examples illustrated in the figures and further described below.

[0057] In the following, further examples of trench JFETs are explained in connection with the accompanying drawings. The functional and structural details described with respect to the above examples shall equally apply to the exemplary embodiments illustrated in the figures and further described below. In the illustrated examples, for n-channel trench JFETs, the first conductivity type is n-type, while the second conductivity type is p-type. However, for p-channel trench JFETs, the first conductivity type can also be p-type, while the second conductivity type can be n-type.

[0058] Figure 1 A cross-sectional view of a configuration example of a trench JFET 100 is schematically and exemplarily shown.

[0059] The trench JFET 100 includes a mesa region 103 defined by a first trench 1061 and a second trench 1062 along a first lateral direction x1 of the semiconductor body 100. The first trench 1061 and the second trench 1062 extend from a first surface 108 of the semiconductor body 102 into the semiconductor body 102. A doped mesa channel region 104 of a first conductivity type is defined along the first lateral direction x1 by a first control region 1101 and a second control region 1102 of a second conductivity type complementary to the first conductivity type. According to one example, the first conductivity type is n-type, such that the mesa channel region 104 is n-doped, and the second conductivity type is p-type, such that the control regions 1101, 1102 are p-doped.

[0060] In each case, the first pn junction 1121 is defined by the mesa channel region 104 and the first control region 1101, while the second pn junction 1122 is defined by the mesa channel region 104 and the second control region 1102. To form the first pn junction, the first control region 1101 may be adjacent to the mesa channel region 104. However, this is only one example. It is also possible that the first control region 1101 is spaced apart from the mesa channel region 104 in the first lateral direction x1, and a region having a lower doping concentration than either the first control region 1101 or the mesa channel region 104 is arranged between the first control region 1101 and the mesa channel region 104. The additional region may have a first conductivity type, a second conductivity type, or may be intrinsic. In each case, the pn junction is formed in the region between the first control region 1101 and the mesa channel region 104, such that the pn junction is arranged between the first control region 1101 and the mesa channel region 104.

[0061] Equivalently, to form the second PN junction, the second control region 1102 may be adjacent to the mesa test region 104. Alternatively, the second control region 1102 may be spaced apart from the mesa channel region 104 in the first lateral direction x1, such that a region having a lower doping concentration than either the second control region 1102 or the mesa channel region 104 is arranged between the second control region 1102 and the mesa channel region 104. The additional region may have a first conductivity type, a second conductivity type, or may be intrinsic. In each case, the pn junction is formed in the region between the second control region 1102 and the mesa channel region 104, such that the pn junction is arranged between the second control region 1102 and the mesa channel region 104.

[0062] The mesa channel region 104 is electrically coupled, for example, to a drain contact D at a second surface of the semiconductor body via a drift region 119. For example, the drift region 119 is of a first conductivity type. The mesa channel region 104 is also electrically coupled, for example, to a source contact S at a first surface 108 of the semiconductor body 102 via a source region 124 at a first surface 108. The source region 124 is of a first conductivity type and may have a higher doping concentration than the drift region 119.

[0063] For example, the extent wm of the mesa region 103 along the first lateral direction x1 can range from 200 nm to 2 µm, or from 300 nm to 1.6 µm, or from 400 nm to 1.2 µm.

[0064] The first control region 1101 is electrically coupled to the source contact S, for example, via a conductive material that is part of the filling material in the first trench 1061. Alternatively, the first control region 1101 may also be electrically coupled to the source contact S via a contact on the first control region 1101 at the first surface 108. In this case, for example, the first trench 1101 may include a dielectric trench filling structure.

[0065] The second control region 1102 is electrically coupled to the gate contact G via a conductive filling material (e.g., a gate electrode) in the second trench 1062.

[0066] Figure 2 A cross-sectional view of another configuration example of the trench JFET 100 is shown schematically and exemplary.

[0067] Each of the first trench 1061 and the second trench 1062 includes a gate electrode or source electrode 1131, 1132 and a bottom electrode 1141, 1142. The gate electrode or source electrode 1131, 1132 is disposed between the bottom electrode 1141, 1142 and the first surface 108 and is electrically coupled to the gate contact or source contact G / S.

[0068] The behavior of the capacitor can be adjusted by applying a potential to the bottom electrodes 1141 and 1142, for example, C. GDFor example, the bottom electrode 1141 in the first trench 1061 can be electrically coupled to the gate contact G, and the bottom electrode 1142 in the second trench 1062 can be electrically coupled to the source contact S, or vice versa. Both bottom electrodes 1141 and 1142 can also be electrically coupled to either the gate contact G or the source contact S. While capacitive behavior can be adjusted via the potential of each of the bottom electrodes in trenches 1061 and 1062, current behavior can also be adjusted via the potential (e.g., gate potential or source potential) applied to each of the gate or source electrodes 1131 and 1132 in the trench. For example, by applying a source potential to one of the gate or source electrodes 1131 and 1132, the corresponding trench can be deactivated relative to the control of channel conductivity.

[0069] Dielectric separation regions 1161, 1162 are arranged between bottom electrodes 1141, 1142 and gate or source electrodes 1131, 1132 for electrically separating the gate or source electrodes 1131, 1132 and the bottom electrodes 1141, 1142 in each of the trenches 1061, 1062.

[0070] Each of the first doped control region 1101 and the second p-doped control region 1102 has a top portion 1104 and a bottom portion 1105. The top portion 1104 and the bottom portion 1105 are perpendicularly spaced from each other by intermediate n-doped separation regions 1151 and 1152. A pn ​​junction is formed between the intermediate n-doped separation regions 1151 and 1152 and the p-doped first p-doped control region 1101 and the second p-doped control region 1102 to isolate and prevent short circuits between the source electrode or gate electrode 1131 and 1132 and the bottom electrode 1141 and 1142. The intermediate separation regions 1151 and 1152 are adjacent to the dielectric separation regions 1161 and 1162 along a first lateral direction x1.

[0071] Figure 3 The illustration and example show the relationship with Figure 1 The illustration shows a cross-sectional view of another configuration example of the trench JFET 100 associated with the example shown.

[0072] Figure 3The trench JFET 100 includes conductive pads 1181, 1182 at the bottom portions of a first trench 1061 and a second trench 1062. The conductive pads 1181, 1182 are vertically arranged between a gate electrode or source electrode 1131, 1132 in the first trench 1061 and the second trench 1062 and a corresponding one of a first control region 1101 and a second control region 1102. The first control region 1101 is electrically connected to a source contact S via the gate electrode or source electrode 1131 in the first trench 1061. The second control region 1102 is electrically connected to a gate contact S via the gate electrode or source electrode 1132 in the second trench 1062. Figure 3 (Not shown in the diagram). An interlayer dielectric 126 is disposed on the gate electrode or source electrode 1132. The mesa channel region 104 passes through n on the first surface 108. + The doped source region 124 is electrically coupled to the source contact S at the first surface 108 of the semiconductor body 102.

[0073] Along the first lateral direction x1, the mesa channel region 104 includes first, second, and third mesa channel sub-regions 1041, 1042, and 1043 having the same extension along the first lateral direction x1. The average concentration of n-type dopant along the first lateral direction x1 in the second mesa channel sub-region 1042 is greater than the average concentration of n-type dopant along the first lateral direction x1 in each of the first and third mesa channel sub-regions 1041 and 1043.

[0074] Figure 4 The illustration and example show the relationship with Figure 2 The illustration shows a cross-sectional view of another configuration example of the trench JFET 100 associated with the example shown.

[0075] Similar to Figure 3 Configuration example, Figure 4 The trench JFET 100 includes conductive pads 1181, 1182 at the bottom portions of the first trench 1061 and the second trench 1062. The conductive pads 1181, 1182 are vertically arranged between the bottom electrodes 1141, 1142 and a corresponding one of the first control region 1101 and the second control region 1102.

[0076] The trench JFET 100 further includes a mezzanine channel region 104, the mezzanine channel region 104 having a reference Figure 3 The configuration example describes the first, second, and third countertop channel sub-regions 1041, 1042, and 1043.

[0077] The trench JFET further includes conductive pads 1171, 1172 at the sidewall portions of the first trench 1061 and the second trench 1062. The conductive pads 1171, 1172 are laterally arranged between the trench filling material (e.g., gate electrode or source electrode 1131, 1132) in the first trench 1061 and the second trench 1062 and a corresponding one of the first control region 1101 and the second control region 1102.

[0078] Figure 1-Figure 4 Each illustration depicts only one mesa region 103 disposed between the first trench 1061 and the second trench 1062. This is for illustrative purposes only. It should be noted that the trench JFET according to each example explained herein may include a plurality of first trenches 1061 and second trenches 1062 arranged alternately in the first lateral direction x1, such that the trench JFET includes a plurality of mesa regions 103 spaced apart from each other in the first lateral direction x1. Adjacent mesa regions 103 are separated from each other by a first trench 1061 or a second trench 1062. Thus, the trench JFET includes a plurality of first control regions 1101 and a plurality of second control regions 1102, each first control region 1101 adjacent to a corresponding first trench 1061 and connected to a source contact S, and each second control region 1102 adjacent to a corresponding second trench 1062 and connected to a gate contact G.

[0079] Figure 5 The illustration and example show the relationship with Figure 1 The diagram shows a cross-sectional view of another example of a trench JFET 100 related to the example shown.

[0080] Instead of drift band 119 of only the first conductivity type, according to Figure 5 The trench JFET 100 includes a superjunction SJ structure 120 disposed between the bottom sides of a first trench 1061 and a second trench 1062 and a second surface 109 opposite a first surface 108 of the semiconductor body 102. More specifically, the SJ structure 120 may be disposed between the bottom of the first trench 1061 and the second trench 1062 and a drain region 130 of a first conductivity type. The drain region 130 is connected to a drain contact D.

[0081] The SJ structure 120 includes a first SJ region 121 of a first conductivity type and a second SJ region 122 of a second conductivity type. In the SJ structure 120, the first SJ region 121 may also be referred to as a drift region, and together they form at least a portion of the drift region band of the trench JFET. The second SJ region 122 may also be referred to as a compensation region. Between the drain region 130 and the SJ structure 120, a doped region 119' of the first conductivity type may be disposed. This doped region 119' may have a lower doping concentration than the drain region 130. The doped region 119' may form an additional portion of the drift region band and / or may form a buffer zone. The doped region 119' may include two or more different doped regions of the first conductivity type, disposed one above the other between the drain region 130 and the SJ region 120.

[0082] In the superjunction structure 120, a plurality of first SJ regions 121 of a first conductivity type and a plurality of second SJ regions 122 of a second conductivity type are alternately arranged in a first lateral direction x1. Each first SJ region 121 is electrically coupled to a drain region 130 and a drain contact D connected to the drain region 130. Figure 5 As illustrated, the first SJ region 121 can be coupled to the drain region 130 via a doped region 119' of a first conductivity type. Furthermore, each first SJ region 121 is electrically coupled to the source contact S at the first surface 108 of the semiconductor body 102 via a mesa channel region 104 and a source region 124.

[0083] exist Figure 5 In the example illustrated, the second SJ region 122 includes a first group of second SJ regions and a second group of second SJ regions. Each second SJ region 122 in the first group is electrically coupled to a corresponding first control region 1101, and each second SJ region in the second group is electrically coupled to a corresponding second control region 1102.

[0084] For example, the vertical extension t1 of the superjunction structure 120 can range from 50% to 2000% of the vertical extension t2 of the first trench 1061 and the second trench 1062.

[0085] according to Figure 5 The operating principle of the trench JFET is briefly explained below. For illustrative purposes, it is assumed that the first conductivity type—which is the conductivity type of the mesa channel region 124, the first SJ region 121, the drain region 130, and the region 119′ between the drain region 130 and the superjunction region 120—is n-type, and the second conductivity type—which is the conductivity type of the first control region 1101, the second control region 1102, and the second SJ region 122—is p-type.

[0086] In this example, when the gate contacts G ( Figure 5When the drive voltage (gate-source voltage) between the drain contact D and the source contact S is higher than the negative threshold voltage of the trench JFET, the JFET is in the on state (conduction state), allowing current to flow from the drain contact D through the drain region 130, region 119', first SJ region 121, mesa channel region 104, and source region 124 to the source contact S. When the drive voltage is lower than the threshold voltage (more negative), the JFET is in the off state (blocking stage). In this case, the space charge region (depletion region) expands in the mesa channel region 104, starting at the pn junction between the mesa channel region 104 and the second control region 1102, which is the one of the first control region 1101 and the second control region 1102 connected to the gate contact G. When the drive voltage causes the mesa channel region 104 to completely deplete the charge carriers between the first control region 1101 and the second control region 1102, the JFET is in the off state.

[0087] Furthermore, in the off state, each first SJ region 121 is depleted of charge carriers because one of the adjacent second SJ regions 122 is coupled to the source contact S via the first control region 1101, and the other of the adjacent second SJ regions 122 is coupled to the gate contact G via the second control region 1102.

[0088] Compared to a conventional trench JFET, where the control regions along both sidewalls of the mesa region are connected to the gate node, according to Figure 5 The threshold voltage of the transistor device is more negative. On the other hand, according to Figure 5 The transistor device has a low gate-drain capacitance because not every control region is connected to the gate contact G, but some of the control regions (first control region 1101) are connected to the source node.

[0089] Figure 6 The illustration and example show the relationship with Figure 1 The illustration shows a cross-sectional view of another configuration example of the trench JFET 100 associated with the example shown.

[0090] n + The doped source region 124 is arranged only on one of the opposite sidewalls of the mesa region 103 adjacent to the second trench 1062. Therefore, n is omitted on the sidewall and top portion of the mesa region 103 adjacent to the first trench 1061. + The doped source region 124 has a first trench 1061 adjacent to the source contact S. Therefore, since the source region 124 is adjacent to the intermediate dielectric 126 but not to the source contact S, control over channel conductivity is deactivated in the mesa region 103 on the sidewall of the second trench 1062.

[0091] Figure 7 The illustration and example show the relationship withFigure 1 The illustration shows a cross-sectional view of another configuration example of the trench JFET 100 associated with the example shown.

[0092] The trench JFET 100 includes a second mesa region 1032 with a width of wm2. The second mesa region 1032 is wider than mesa region 103, i.e., wm2 > wm. The second mesa region 1032 is adjacent to a second control region 1102 and a third control region 1103. The second control region 1102 and the third control region 1103 are electrically coupled to the gate contact G. Therefore, a second mesa channel region 1042 in the second mesa region 1032 is pinched off from the opposite sidewalls of the second mesa region 1032 via a space charge region. In mesa region 103, the mesa channel region 104 is pinched off only via one of the opposite space charge regions because the first control region 1101 is electrically coupled to the source contact S, and the expansion of the associated space charge region cannot be controlled by the voltage applied to the gate contact G.

[0093] Figure 6 and Figure 7 The configuration example illustrates measures to offset offsets in the pinch-off voltage (threshold voltage), which can occur when different voltages are applied to the control region defining the mesa channel region. For example, different voltages (e.g., gate voltage or source voltage) can be applied to the control region to adjust the capacitive behavior of the trench JFET.

[0094] According to Figure 5 In the superjunction trench JFET, a first SJ region 121 is adjacent to the mesa channel region 104 along its entire width, wherein current flows between the mesa channel region 104 and the drain region 130 in the on-state. The width of the mesa channel region 104 is its dimension in the first lateral direction x1. To operate the JFET in the off-state, by applying a suitable negative drive voltage between the gate contact G connected to the second control region 1102 and the source contact S connected to the mesa channel region 104, the mesa channel region 104 will deplete charge carriers across its entire width.

[0095] Figure 8 The diagram illustrates the following: Figure 5 Modification of the trench JFET. Figure 5 trench JFET and according to Figure 8 The difference between the trench JFET and the conventional one is that the first SJ region 121 and the second SJ region 122 of the superjunction structure 120 are offset (displaced) relative to the mesa channel region 104, such that the pn junction formed between adjacent first SJ regions 121 and second SJ regions 122 is arranged below the mesa channel region 104 in the vertical direction z of the semiconductor body 102. The "vertical direction z" is the direction in which the semiconductor body 102 is substantially perpendicular to the first surface 108 and the second surface 109. Therefore, according to...Figure 8 In the trench JFET, each mesa channel region 104 is adjacent to a portion of the first SJ region 121 and a portion of the adjacent second SJ region 122 in the vertical direction z. Furthermore, according to... Figure 8 In the trench JFET, each first SJ region 121 is disposed below a corresponding second trench 1062 in which a gate electrode 1132 is disposed, and each second SJ region 122 is disposed below a corresponding first trench 1061 in which a source electrode 1131 is disposed.

[0096] The source electrode 1131 is connected to the source metallization 1091, which is connected to or forms the source contact S, for example. The gate electrode 1132 is connected to the gate contact G. Figure 8 (Not shown in the image).

[0097] exist Figure 8 In the example illustrated, adjacent first SJ regions 121 and second SJ regions 122 are adjacent to each other. However, this is only one example. According to another example (not illustrated), adjacent first SJ regions 121 and second SJ regions 122 are spaced apart from each other in the first lateral direction x1, wherein they are of the first or second conductivity type and have a lower doping concentration than each of the first SJ regions and second SJ regions 121 (such as below 5E15 cm⁻¹). -3 The region (with the highest doping concentration) or intrinsic region can be arranged between adjacent first SJ regions 121 and second SJ regions 122. In each case, the mesa channel region 104 is adjacent to a portion of a first SJ region 121 and a portion of a second SJ region 122.

[0098] Furthermore, refer to Figure 8 Each second SJ region 122 is connected to the source contact S via a corresponding one in the first control region 1101 and a corresponding source electrode 1131. For this purpose, the first control region 1101 can be arranged not only along the sidewall of the first trench 1061 but also along the bottom of the first trench 1061. Each second SJ region 122 is spaced apart from the second control region 1102.

[0099] according to Figure 8 The operating principle of the trench JFET is similar to that of... Figure 5 The operating principle of a trench JFET. In the on state, current flows between the drain contact D and the source contact S, particularly through the first SJ region 121 and the mesa channel region 104.

[0100] The JFET is in the off state when the mesa channel region 104 is depleted of charge carriers. The JFET may already be in the off state when the portions of the mesa channel region 104 adjacent to the first SJ region 121 are depleted of charge carriers. Current flow through the portions of the mesa channel region 104 adjacent to the second SJ region 122 is blocked by the pn junction formed between the second SJ region 122 and the mesa channel region 104. This can have the effect that, according to... Figure 8 The threshold voltage of a trench JFET can have a higher voltage than that of a standard JFET. Figure 5 The threshold voltage of the trench JFET has a lower amplitude (which can be a smaller negative value).

[0101] Furthermore, in the off state, since the first SJ region 121 is electrically coupled to the drain region 130 and the drain node D, and the second SJ region 122 is coupled to the source node S, each of the first SJ regions 121 is depleted of charge carriers. Figure 5 The examples shown in the illustrations are different from those in the text, and are based on... Figure 8 In the trench JFET, each second control region 1102 is spaced apart from the SJ region 122 and arranged adjacent to the corresponding first SJ region 121, so that the pn junction can be arranged between the second control region 1102 and the first SJ region 121. Figure 5 Compared to the JFET illustrated, this may help reduce gate-drain capacitance.

[0102] According to Figure 8 In a trench JFET, a superjunction structure 120 having a first SJ region 121 and a second SJ region 122 alternately arranged in a first lateral direction x1 can be generated by a conventional multiple epitaxial multiple implantation (MEMI) process. This process includes forming two or more epitaxial layers, one on top of the other, implanting first and second type dopant atoms into each epitaxial layer using appropriate implantation masks, and an annealing process to activate the implanted first and second type dopant atoms to form the first SJ region 121 and the second SJ region 122. A first trench 1061 and a second trench 1062 can be formed in the uppermost epitaxial layer, which is formed on top of the epitaxial layer including the superjunction structure 120. A mesa channel region 104 can be formed by implanting first conductivity type dopant atoms into the uppermost epitaxial layer. A first control region 1101 and a second control region 1102 can be formed by implanting second conductivity type dopant atoms into the sidewalls and bottom of the first trench 1061 and the second trench 1062.

[0103] As from Figure 8As can be seen, each countertop area 102 includes a countertop channel area 104 arranged between the first control area 1101 and the second control area 1102. The first control area 1101 is arranged along the two sidewalls (and bottom) of the first channel 1061, while the second control area 1102 is arranged along the two sidewalls (and bottom) of the second channel 1062.

[0104] exist Figure 8 In the examples illustrated in the figure and the following examples, conductive pads 1181 and 1182 are optional and are therefore shown in dashed lines.

[0105] Figure 9 The diagram illustrates the following: Figure 8 Modification of the transistor device. In this example, each mesa channel region 104 includes a first region 1045 arranged adjacent to a first control region 1101 in the first lateral direction x1, and a second region 1046 arranged adjacent to a second control region 1102 in the first lateral direction x1. In the vertical direction z, the first region 1045 is adjacent to a corresponding second control region 122, and the second region 1046 is adjacent to a corresponding first control region 121. The first region 1045 and the second region 1046 are spaced apart from each other in the first lateral direction x1. Between the first region 1045 and the second region 1046, a region 105 is arranged, which is of a first or second conductivity type and has a lower doping concentration than each of the first region 1045 and the second region 1046, such as below 5E15 cm⁻¹. -3 Or, intrinsically. The first region 1045 may be adjacent to the first control region 1101, or, as illustrated, may be spaced apart from the first control region 1101. Similarly, the second region 1046 may be adjacent to the second control region 1102, or, as illustrated, may be spaced apart from the second control region 1102. According to... Figure 9 In the trench JFET, in both the on and off states, the pn junction between the first region 1045 and the second SJ region 122 of the mesa channel region 104 prevents the current from flowing through the first region 1045 of the mesa channel region 104.

[0106] The first mesa channel region 1045 can be generated by implanting dopant atoms into the sidewalls of the mesa region before forming electrodes 1131, 1132 in the first trench 1061 and the second trench 1062. In this type of process, dopant atoms are implanted into each sidewall of each mesa region 103 to form the first mesa channel region 1045 and the second mesa channel region 1046, instead of implanting dopant atoms only into the sidewalls of the mesa region adjacent to the second trench 1062 to form only the second mesa channel region 1046, which can save costs.

[0107] When a gate-source voltage is applied between the gate node G and the source node S, according toFigure 9 The trench JFET is in the off state, which causes the second control region 1102 to deplete the charge carriers of the second mesa channel region 1046.

[0108] Figure 10 It shows that according to Figure 9 Modification of the trench JFET. (Based on...) Figure 9 Compared to trench JFETs, according to Figure 10 The trench JFET further includes a current diffusion region 106 disposed between a first mesa channel region 1045 and a second mesa channel region 1046 in each mesa region 103. The current diffusion region 106 is of a first conductivity type and, in the on-state of the JFET, allows current to flow from the first mesa channel region 1045 to the second mesa channel region 1046. This can help reduce the on-resistance, which is the resistance between the drain contact D and the source contact S in the on-state of the trench JFET.

[0109] According to Figure 8-Figure 10 In the trench JFET, the first SJ region 121 and the second SJ region 122 are arranged alternately in the first lateral direction x1, such that each first SJ region 121 is arranged between two second SJ regions 122, and each second SJ region 122 is arranged between two first SJ regions 121. Figure 11 The diagram illustrates another way of alternating the arrangement of the first SJ zone 121 and the second SJ zone 122.

[0110] Figure 11 It shows that according to Figure 10 A modification of the trench JFET. In this trench JFET, first SJ regions 121 and second SJ regions 122 are arranged alternately in the first lateral direction x1 such that pairs of adjacent first SJ regions 121 and pairs of adjacent second SJ regions 122 are arranged alternately. Each pair of first SJ regions 121 is spaced apart from each other in the first lateral direction x1, and each pair of second SJ regions 122 is spaced apart from each other in the first lateral direction x1, wherein a semiconductor region 123 is arranged between each pair of SJ regions 121, 122. The semiconductor region 123 is of a first or second conductivity type and has a lower doping concentration than each of the first SJ regions 121 and second SJ regions 122, or is intrinsic.

[0111] refer to Figure 11Each of the first SJ regions 121 is adjacent to a corresponding second mezzanine channel region 1046 in the vertical direction z, such that in the on state, current can flow between the drain contact D and the source contact S, specifically via the second mezzanine channel region 1046 and the first SJ region 121. Furthermore, each of the second SJ regions 122 is adjacent to a corresponding first mezzanine channel region 1045. In both the on and off states, the pn junction between the second SJ regions 122 and the corresponding first mezzanine channel region 1045 prevents current flow through the first mezzanine channel region 1045.

[0112] According to Figure 11 In a trench JFET, adjacent first SJ regions 121 and second SJ regions 122 may be adjacent to each other. According to another example, as illustrated, adjacent first SJ regions 121 and second SJ regions 122 may be spaced apart from each other in a first lateral direction x1, wherein a semiconductor region 124 is disposed between adjacent first and second SJ regions. The semiconductor region 124 is of a first or second conductivity type and has a lower doping concentration than each of the first SJ regions 121 and second SJ regions 122, or is intrinsic.

[0113] Figure 12 It shows that according to Figure 11 Modification of the trench JFET. Figure 12 The trench JFET includes only one mezzanine channel region 104 in each mezzanine region 103, and the mezzanine channel region 104 is adjacent to both the first SJ region 121 and the second SJ region 122 arranged below the corresponding mezzanine region 103 in the vertical direction z.

[0114] Figure 13A-Figure 13F The schematic diagram illustrates the process of forming Figure 11 An example of a trench JFET method of the type illustrated in the figure. Figure 13A-Figure 13F Each of these shows a vertical cross-sectional view of the semiconductor body 102 during different process steps.

[0115] refer to Figure 13A The method is based on a semiconductor body 102, which includes a drain region 130, a region 119' of a first conductivity type, and an epitaxial layer 1240 formed on top of the region 119'. For example, the drain region 130 is formed from a semiconductor substrate. The region 119' may be formed from one or more epitaxial layers formed on top of the substrate. For example, the epitaxial layer 1240 formed on top of the region 119' is lightly doped. According to one example, this includes a basic doping concentration of the epitaxial layer 1240 of less than 1E16 cm⁻¹. -3 Below 5E15 cm -3 or below 1E15 cm -3 .

[0116] refer to Figure 13A The method includes forming a first trench 1071 and a second trench 1072 in an epitaxial layer 1240. The first trench 1071 and the second trench 1072 can extend through the epitaxial layer 1240 into region 119'. Forming the first trench 1071 and the second trench 1072 can include a conventional etching process using an etching mask. Figure 13A (Not shown in the image). Figure 13A The diagram only shows one first trench 1071 and one second trench 1072. It should be noted that multiple first trenches 1071 and multiple second trenches 1072 are formed, wherein the first trenches 1071 and the second trenches 1072 are arranged alternately in the first lateral direction x1.

[0117] refer to Figure 13B The method further includes implanting second (conductive) type dopant atoms into the opposite sidewalls of the first trench 1071 during a tilted implantation process to form a second implantation region 122' along the sidewalls. The method further includes covering the upper surface of the epitaxial layer 1240 and the sidewalls and bottom of the second trench 1072 with a first protective layer 1081 to prevent second type dopant atoms from being implanted into the sidewalls and bottom of the second trench 1072.

[0118] refer to Figure 13C The method further includes implanting first (conductive) type dopant atoms into the opposite sidewalls of the second trench 1072 during a tilted implantation process to form a first implantation region 121' along the sidewalls. The method further includes covering the upper surface of the epitaxial layer 1240 and the sidewalls and bottom of the first trench 1071 with a second protective layer 1082 to prevent second type dopant atoms from being implanted into the sidewalls and bottom of the first trench 1071.

[0119] refer to Figure 13D The method further includes at least partially filling the first trench 1071 and the second trench 1072 with a single-crystal semiconductor material. According to one example, the single-crystal semiconductor material is of the same type as the remainder of the semiconductor body 102. At least partially filling the first trench 1071 and the second trench 1072 may include an epitaxial growth process.

[0120] refer to Figure 13E The method further includes forming a first trench 1061 and a second trench 1062 defining a mesa region 103, such that a second injection region 122' extends along opposite sidewalls of the first trench 1061 and a first injection region 121' extends along opposite sidewalls of the second trench 1062. The first trench 1061 and the second trench 1062 can be formed by the same etching process.

[0121] refer to Figure 13EThe method further includes implanting first-type dopant atoms into the opposing sidewalls of the first trench 1061 and the second trench 1062, and implanting second-type dopant atoms into the opposing sidewalls and bottom of the first trench 1061 and the second trench 1062. The method further includes an annealing process to activate the implanted dopant atoms. After the annealing process, the first implantation region 121' forms a first SJ region 121, the second implantation region 122 forms a second SJ region 122, the first-type dopant atoms implanted into the sidewalls of the first trench 1061 and the second trench 1062 form a mesa channel region 104, and the second-type dopant atoms implanted into the sidewalls and bottom of the first trench 1061 and the second trench 1062 form a first control region 1101 and a second control region 1102.

[0122] refer to Figure 13F The trench JFET is completed by forming a source region 124, a source electrode 1131 in a first trench 1061, a gate electrode 1132 in a second trench 1062, and forming a source metallization 1091 that is insulated from the gate electrode 1132 by an insulating layer 126.

[0123] According to Figure 13F In the trench JFET, the semiconductor region 123 separating each pair of first SJ regions 121 and second SJ regions 122 has a basic doping concentration of the single-crystal semiconductor layer formed in the first trench 1071 and the second trench 1072. Furthermore, the semiconductor region 124 disposed between adjacent first SJ regions 121 and second SJ regions 122 has a basic doping concentration of the epitaxial layer 1240 formed on top of region 119'.

[0124] Referring to the above, the first trench 1071 and the second trench 1072, in which dopant atoms for forming the first SJ region 121 and the second SJ region 122 are implanted, are at least partially filled. Figure 14 It shows that according to Figure 13F Modification of the trench JFET. Figure 14 trench JFET and according to Figure 13F The difference of the trench JFET is that the first trench 1071 and the second trench 1072 are only partially filled, such that the corresponding gap 125 is left below each of the first trench 1061 and the second trench 1062 and between each pair of first SJ regions 121 and second SJ regions 122.

[0125] Some of the aspects explained above are briefly summarized below with reference to the numbered examples.

[0126] Example A1. A trench junction field-effect transistor (JFET) includes: a mesa region defined by a first trench and a second trench spaced apart from each other in a first lateral direction of a semiconductor body, the first trench and the second trench extending from a first surface into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type disposed in the mesa region adjacent to the first trench; and a second control region of the second conductivity type disposed in the mesa region adjacent to the second trench, wherein the mesa channel region is disposed between the first control region and the second control region in the first lateral direction, and wherein the first control region is electrically coupled to a source contact, and the second control region is electrically coupled to a gate contact.

[0127] Example A2. A trench JFET according to Example A1, wherein a first pn junction is disposed between a mesa channel region and a first control region, and wherein a second pn junction is disposed between a mesa channel region and a second control region.

[0128] Example A3. According to the trench JFET of Example A1, the mezzanine channel region is spaced apart from the first control region in the first lateral direction, and / or the mezzanine channel region is spaced apart from the second control region in the first lateral direction.

[0129] Example A4. According to the trench JFET of Example A3, a semiconductor region having a lower doping concentration than each of the mesa channel region and the first control region is arranged between the mesa channel region and the first control region, and / or a semiconductor region having a lower doping concentration than each of the mesa channel region and the second control region is arranged between the mesa channel region and the second control region.

[0130] Example A5. According to any one of Examples A1 to A4, the trench JFET includes a first and a second trench region spaced apart from each other in a first lateral direction, wherein the first trench region is arranged adjacent to a first control region and the second trench region is arranged adjacent to a second control region.

[0131] Example A6. A trench JFET according to any of the preceding claims, wherein the first trench includes a dielectric trench-filled structure.

[0132] Example A7. A trench junction field-effect transistor, a trench JFET, includes: a mesa region defined by a first trench and a second trench along a first lateral direction, the first trench and the second trench extending from a first surface of a semiconductor body into the semiconductor body; a mesa channel region of a first conductivity type; a first control region of a second conductivity type complementary to the first conductivity type disposed in the mesa region adjacent to the first trench; and a second control region of the second conductivity type disposed in the mesa region adjacent to the second trench, wherein the mesa channel region is disposed between the first control region and the second control region in the first lateral direction, and wherein each of the first trench and the second trench includes a gate electrode or a source electrode and a bottom electrode, the gate electrode or source electrode being disposed between the bottom electrode and the first surface.

[0133] Example A8. The trench JFET according to Example A7 further includes a dielectric separation region disposed between the bottom electrode and the gate electrode.

[0134] Example A9. A trench JFET according to Example A7 or A8, wherein each of the first control region and the second control region is divided into a top portion and a bottom portion, wherein the top portion and the bottom portion are perpendicularly spaced from each other by an intermediate separation region of a first conductivity type.

[0135] Example A10. A trench JFET according to Example A9, wherein the intermediate separation region is adjacent to the dielectric separation region along a first lateral direction.

[0136] Example A11. The trench JFET according to any one of Examples A1 to A10 further includes a first conductive pad at a sidewall portion of at least one of the first trench and the second trench, the first conductive pad being laterally disposed between the trench filling material in at least one of the first trench and the corresponding one of the first control region and the second control region.

[0137] Example A12. The trench JFET according to any one of Examples A1 to A11 further includes a second conductive pad at the bottom portion of at least one of the first trench and the second trench, the second conductive pad being vertically disposed between the trench filling material in at least one of the first trench and the corresponding one of the first control region and the second control region.

[0138] Example A13. The trench JFET according to any one of Examples A1 to A12 further includes a superjunction SJ structure disposed between the bottom sides of the first trench and the second trench and a second surface opposite to the first surface of the semiconductor body.

[0139] Example A14. According to the trench JFET of Example A13, the superjunction structure includes a first SJ region of a first conductivity type disposed between two second SJ regions of a second conductivity type, wherein the first SJ region is electrically coupled to a drain contact at a second surface of the semiconductor body and a source contact at a first surface of the semiconductor body, wherein one of the two second SJ regions is electrically coupled to a first control region, and wherein the other of the two second SJ regions is electrically coupled to a second control region.

[0140] Example A15. According to the trench JFET of Example A13, the superjunction structure includes a first SJ region of a first conductivity type and a second SJ region of a second conductivity type arranged adjacent to each other in a first lateral direction, wherein the first SJ region is electrically coupled between a mesa channel region and a drain region of the first conductivity type, and wherein the second SJ region is electrically coupled to a first control region and spaced apart from the second control region.

[0141] Example A16. According to the trench JFET described in Example A15, the mesa channel region is arranged adjacent to a portion of the first SJ region and a portion of the second SJ region in the vertical direction of the semiconductor body.

[0142] Example A17. According to the trench JFET of Example A16, the mezzanine channel region includes a first mezzanine channel region arranged adjacent to a first control region and a second mezzanine channel region arranged adjacent to a second control region, wherein the first mezzanine channel region and the second mezzanine channel region are spaced apart from each other in a first lateral direction, wherein the first mezzanine channel region is arranged adjacent to a portion of the second SJ region in a vertical direction, and wherein the second mezzanine channel region is arranged adjacent to a portion of the first SJ region in a vertical direction.

[0143] Example A18. A trench JFET according to any one of Examples A14 to A17, wherein the JFET includes a plurality of first trenches and second trenches alternately arranged in a first lateral direction, and a plurality of first SJ regions and second SJ regions alternately arranged in the first lateral direction.

[0144] Example A19. The trench JFET according to Example A18, wherein each first SJ region is arranged below a corresponding second trench in the vertical direction, and wherein each second SJ region is arranged below a corresponding first trench in the vertical direction.

[0145] Example A20. According to the trench JFET of Example A18, two first SJ regions are arranged adjacent to each other, spaced apart from each other in a first lateral direction, and at least partially arranged below a corresponding second trench in a vertical direction, and two second SJ regions are arranged adjacent to each other, spaced apart from each other in a first lateral direction, and at least partially arranged below a corresponding first trench in a vertical direction.

[0146] Example A21. According to Example A19 or A20, the trench JFET, wherein the vertical extension of the superjunction structure ranges from 50% to 2000% of the vertical extension of the first trench and the second trench.

[0147] Example A22. The trench JFET according to any one of Examples A1 to A21 further includes a source region of a second conductivity type, the source region being disposed on one of the opposite sidewalls of the mesa region adjacent to the second trench.

[0148] Example A23. The trench JFET according to any one of Examples A1 to A22 further includes a second mezzanine region, the second mezzanine region being wider than the mezzanine region, and wherein the second trench is laterally defined by the mezzanine region and the second mezzanine region.

[0149] Example A24. A trench JFET according to any one of Examples A1 to A23, wherein the mesa region extends from 200 nm to 2 µm along the first lateral direction.

[0150] Example A25. A trench JFET according to any one of Examples A1 to A24, wherein, along a first lateral direction, the mesa channel region includes first, second, and third mesa channel sub-regions having the same extension along the first lateral direction, and the average dopant concentration of a first conductivity type in the second mesa channel sub-region along the first lateral direction is greater than the average dopant concentration of the first conductivity type in each of the first and third mesa channel sub-regions along the first lateral direction.

[0151] Example B1. A trench junction field-effect transistor, i.e., a trench JFET, includes: a mesa region defined by a first trench and a second trench along a first lateral direction, the first trench and the second trench extending from a first surface of a semiconductor body into the semiconductor body; a mesa channel region of a first conductivity type defined along the first lateral direction by a first control region and a second control region of a second conductivity type, a first pn junction defined by the mesa channel region and the first control region, and a second pn junction defined by the mesa channel region and the second control region, wherein the first control region is electrically coupled to a source contact and the second control region is electrically coupled to a gate contact.

[0152] Example B2. The trench JFET according to Example B1, wherein the first trench includes a dielectric trench-filled structure.

[0153] Example B3. A trench junction field-effect transistor, i.e., a trench JFET, includes: a mesa region defined by a first trench and a second trench along a first lateral direction, the first trench and the second trench extending from a first surface of a semiconductor body into the semiconductor body; a mesa channel region of a first conductivity type defined along the first lateral direction by a first control region and a second control region of a second conductivity type, a first pn junction defined by the mesa channel region and the first control region, and a second pn junction defined by the mesa channel region and the second control region, wherein each of the first trench and the second trench includes a gate electrode or a source electrode and a bottom electrode, the gate electrode or source electrode being disposed between the bottom electrode and the first surface.

[0154] Example B4. The trench JFET according to Example B3 further includes a dielectric separation region disposed between the bottom electrode and the gate electrode.

[0155] Example B5. A trench JFET according to any one of Examples B1 to B4, wherein each of the first control region and the second control region is divided into a top portion and a bottom portion, wherein the top portion and the bottom portion are perpendicularly spaced apart from each other by an intermediate separation region of a first conductivity type.

[0156] Example B6. A trench JFET according to Example B5, wherein the intermediate separation region is adjacent to the dielectric separation region along a first lateral direction.

[0157] Example B7. The trench JFET according to any one of Examples B1 to B6 further includes a first conductive pad at a sidewall portion of at least one of the first trench and the second trench, the first conductive pad being laterally disposed between the trench filling material in at least one of the first trench and the corresponding one of the first control region and the second control region.

[0158] Example B8. The trench JFET according to any one of Examples B1 to B7 further includes a second conductive pad at the bottom portion of at least one of the first trench and the second trench, the second conductive pad being vertically disposed between the trench filling material in at least one of the first trench and the corresponding one of the first control region and the second control region.

[0159] Example B9. The trench JFET according to any one of Examples B1 to B8 further includes a superjunction structure disposed between the bottom sides of the first trench and the second trench and a second surface opposite to the first surface of the semiconductor body.

[0160] Example B10. According to the trench JFET of Example B9, the superjunction structure includes a first SJ region of a first conductivity type and a second SJ region of a second conductivity type, wherein the first SJ region is electrically coupled to a drain contact at a second surface of the semiconductor body and a source contact at a first surface of the semiconductor body, and the second SJ region is electrically coupled to a first control region and a second control region.

[0161] Example B11. A trench JFET according to any one of Examples B1 to B10, wherein the vertical extension of the superjunction structure ranges from 50% to 2000% of the vertical extension of the first trench and the second trench.

[0162] Example B12. The trench JFET according to any one of Examples B1 to B11 further includes a source region of a second conductivity type, the source region being disposed on one of the opposite sidewalls of the mesa region adjacent to the second trench.

[0163] Example B13. The trench JFET according to any one of Examples B1 to B12 further includes a second mezzanine region, the second mezzanine region being wider than the mezzanine region, and wherein the second trench is laterally defined by the mezzanine region and the second mezzanine region.

[0164] Example B14. A trench JFET according to any one of Examples B1 to B13, wherein the mesa region extends from 200 nm to 2 µm along the first lateral direction.

[0165] Example B15. A trench JFET according to any one of Examples B1 to B14, wherein, along a first lateral direction, the mesa channel region includes first, second, and third mesa channel sub-regions having the same extension along the first lateral direction, and the concentration of a dopant of a first conductivity type averaged along the first lateral direction in the second mesa channel sub-region is greater than the concentration of a dopant of the first conductivity type averaged along the first lateral direction in each of the first and third mesa channel sub-regions.

[0166] Aspects and features mentioned and described together with the previously described examples and one or more of the figures may also be combined with one or more of the other examples in order to replace similar features in other examples or to additionally introduce features into other examples.

[0167] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent implementations can be used instead of the illustrated and described embodiments without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A trench junction field-effect transistor (JFET (100)) comprising: The mesa region (103) is defined by a first trench and a second trench (1061, 1062) spaced apart from each other in a first lateral direction (x1) of the semiconductor body (102), the first trench and the second trench (1061, 1062) extending from the first surface (108) into the semiconductor body (102); The mezzanine channel region (104) of the first conductivity type (103). A first control region (1101) of a second conductivity type complementary to the first conductivity type, arranged in the platform area (103) adjacent to the first trench (1061); and A second control area (1102) of the second conductivity type is arranged in the platform area (103) adjacent to the second trench (1062). The platform channel area (104) is arranged in the first lateral direction (x1) between the first control area (1101) and the second control area (1102), and The first control region (1101) is electrically coupled to the source contact (S), and the second control region (1102) is electrically coupled to the gate contact (G).

2. The trench JFET according to claim 1, The first pn junction is arranged between the platform channel region (104) and the first control region (1101), and The second pn junction (1122) is arranged between the platform channel region (104) and the second control region (1102).

3. The trench JFET according to claim 1, The platform channel area (104) is separated from the first control area (1101) in the first lateral direction (x1), and / or The platform channel area (104) is separated from the second control area (1102) in the first lateral direction (x1).

4. The trench JFET according to claim 3, A semiconductor region (105) having a lower doping concentration than either the mesa channel region (104) or the first control region (1101) is disposed between the mesa channel region (104) and the first control region (1101), and / or A semiconductor region (105) having a lower doping concentration than each of the mesa channel region (104) and the second control region (1102) is arranged between the mesa channel region (104) and the second control region (1102).

5. The trench JFET according to any one of claims 1 to 4, The countertop channel area (104) includes a first countertop channel area (1045) and a second countertop channel area (1046) that are spaced apart from each other in the first lateral direction (x1). The first platform trench area (1045) is located adjacent to the first control area (1101), and The second platform trench area (1046) is located adjacent to the second control area (1102).

6. The trench JFET according to any one of the preceding claims, wherein the first trench (1061) includes a dielectric trench filling structure.

7. A trench junction field-effect transistor, a trench JFET (100), comprising: The mesa region (103) is defined by a first trench and a second trench (1061, 1062) along a first lateral direction (x1), the first trench and the second trench (1061, 1062) extending from a first surface (108) of the semiconductor body (102) into the semiconductor body (102); First type of conductive mezzanine channel region (104); A first control region (1101) of a second conductivity type complementary to the first conductivity type, arranged in the platform area (103) adjacent to the first trench (1061); and A second control area (1102) of the second conductivity type is arranged in the platform area (103) adjacent to the second trench (1062). The platform channel area (104) is arranged in the first lateral direction (x1) between the first control area (1101) and the second control area (1102), and Each of the first trench and the second trench (1061, 1062) includes a gate electrode or source electrode (1131, 1132) and a bottom electrode (1141, 1142), wherein the gate electrode or source electrode (1131, 1132) is arranged between the bottom electrode (1141, 1142) and the first surface (108).

8. The trench JFET of claim 7, further comprising a dielectric separation region (1161, 1162) disposed between the bottom electrode (1141, 1142) and the gate electrode (1131, 1132).

9. The trench JFET according to claim 7 or 8, wherein each of the first control region and the second control region (1101, 1102) is divided into a top portion (1104) and a bottom portion (1105), wherein the top portion (1104) and the bottom portion (1105) are perpendicularly spaced apart from each other by intermediate separation regions (1151, 1152) of a first conductivity type.

10. The trench JFET of claim 9, wherein the intermediate separation region (1151, 1152) is adjacent to the dielectric separation region (1141, 1142) along a first lateral direction (x1).

11. The trench JFET according to any of the preceding claims, further comprising a first conductive pad (1171, 1172) at a sidewall portion of at least one of the first trench and the second trench (1061, 1062), the first conductive pad (1171, 1172) being laterally disposed between the trench filling material of the at least one of the first trench and the second trench (1061, 1062) and a corresponding one of the first control region and the second control region (1101, 1102).

12. The trench JFET according to any one of the preceding claims, further comprising a second conductive pad (1181, 1182) at the bottom portion of at least one of the first trench and the second trench (1061, 1062), the second conductive pad (1181, 1182) being vertically disposed between the trench filling material in at least one of the first trench and the second trench (1061, 1062) and a corresponding one of the first control region and the second control region (1101, 1102).

13. The trench JFET according to any one of the preceding claims further includes a superjunction SJ structure (120) disposed between the bottom sides of the first trench and the second trench (1061, 1062) and the second surface (109) opposite to the first surface (108) of the semiconductor body (102).

14. The trench JFET according to claim 13, The superjunction structure (120) includes a first SJ region (121) of a first conductivity type arranged between two second SJ regions (122) of a second conductivity type. The first SJ region (121) is electrically coupled to the drain contact (D) at the second surface (109) of the semiconductor body (102) and the source contact (S) at the first surface (108) of the semiconductor body (102). One of the two second SJ regions (122) is electrically coupled to the first control region (1101), and The other of the two second SJ regions (122) is electrically coupled to the second control region (1102).

15. The trench JFET according to claim 13, The superjunction structure (120) includes a first SJ region (121) of a first conductivity type and a second SJ region (122) of a second conductivity type arranged adjacent to each other in the first transverse direction (x1). The first SJ region (121) is electrically coupled between the mesa channel region (104) and the drain region (130) of the first conductivity type. The second SJ region is electrically coupled to the first control region (1101) and spaced apart from the second control region (1102).

16. The trench JFET according to claim 15, The mesa channel region (104) is arranged adjacent to a portion of the first SJ region (121) and a portion of the second SJ region (122) in the vertical direction (z) of the semiconductor body (102).

17. The trench JFET according to claim 16, The platform trench area (104) includes a first platform trench area (1045) arranged adjacent to the first control area (1101) and a second platform trench area (1046) arranged adjacent to the second control area (1102). The first and second platform channel areas (1045, 1046) are spaced apart from each other in the first lateral direction (x1). The first platform channel area (1045) is arranged adjacent to a portion of the second SJ area (122) in the vertical direction (z), and The second platform channel area (1046) is arranged adjacent to a portion of the first SJ area (122) in the vertical direction (z).

18. The trench JFET according to any one of claims 14 to 17, The JFET includes a plurality of first trenches and second trenches (1061, 1062) arranged alternately in the first lateral direction (x1) and a plurality of first SJ regions and second SJ regions (121, 122) arranged alternately in the first lateral direction (x1).

19. The trench JFET according to claim 18, Each of the first SJ regions (121) is arranged in the vertical direction (z) below the corresponding second trench (1062), and Each of the second SJ regions (122) is arranged below the corresponding first trench (1062) in the vertical direction (z).

20. The trench JFET according to claim 18, Two first SJ regions (121) are arranged adjacent to each other, spaced apart in the first lateral direction (x1), and at least partially arranged below the corresponding second trench (1062) in the vertical direction (z). Two second SJ regions (121) are arranged adjacent to each other, spaced apart from each other in the first lateral direction (x1), and at least partially arranged below the corresponding first groove (1062) in the vertical direction (z).

21. The trench JFET according to any one of the preceding two claims, wherein the vertical extension (t1) of the superjunction structure (120) ranges from 50% to 2000% of the vertical extension (t2) of the first trench and the second trench (1061, 1062).

22. The trench JFET according to any one of the preceding claims further includes a source region (124) of a second conductivity type, said source region (124) being disposed on one of the opposite sidewalls of the mesa region (103) adjacent to the second trench (1062).

23. The trench JFET according to any one of the preceding claims further includes a second mezzanine region, the second mezzanine region being wider than the mezzanine region (103), and wherein the second trench is laterally defined by the mezzanine region (103) and the second mezzanine region.

24. The trench JFET according to any one of the preceding claims, wherein the mesa region (103) has an extension (wm) ranging from 200 nm to 2 µm along a first lateral direction (x1).

25. The trench JFET according to any one of the preceding claims, wherein, Along the first lateral direction (x1), the mesa channel region (104) includes first, second, and third mesa channel subregions (1041, 1042, 1043) having the same extension (w) along the first lateral direction (x1), and the concentration of dopant of the first conductivity type averaged along the first lateral direction (x1) in the second mesa channel subregion (1042) is greater than the concentration of dopant of the first conductivity type averaged along the first lateral direction (x1) in each of the first and third mesa channel subregions (1041, 1043).

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