Optoelectronic co-encapsulation glass substrate, processing technology thereof and optoelectronic co-encapsulation module

Abstract

The application belongs to the technical field of semiconductor packaging and optical communication, and particularly relates to an optoelectronic co-packaging glass substrate, a processing technology thereof and an optoelectronic co-packaging module. The optoelectronic co-packaging glass substrate comprises a glass substrate, at least one electrically interconnected through hole penetrating through the glass substrate, at least one re-routed layer arranged on the surface of the glass substrate and electrically connected with the electrically interconnected through hole, the electrically interconnected through hole and the re-routed layer forming an electrically interconnected structure for vertical transmission and horizontal routing of electric signals, at least one optical waveguide channel embedded in the glass substrate, an optical path turning groove structure arranged in the interior of the glass substrate and connected with the optical waveguide channel, and a microlens array arranged on the upper surface of the glass substrate, wherein each microlens corresponds to a light signal port of the optical waveguide channel in the spatial position, and the microlens array is configured to couple the divergent light beam perpendicular to the surface of the glass substrate to the optical waveguide channel.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging and optical communication technology, and particularly relates to an optoelectronic co-packaging glass substrate, its processing technology, and an optoelectronic co-packaging module. Background Technology

[0002] With the rapid development of applications such as cloud computing, large data centers, and artificial intelligence, the market's requirements for data transmission bandwidth, latency, and power consumption are becoming increasingly stringent. Traditional pluggable optical modules on the board are gradually becoming unable to meet the needs of future ultra-high-speed optical interconnects due to their limitations in power consumption, integration density, and signal integrity. Against this backdrop, Co-Packaged Optics (CPO) technology has emerged as a new high-density integrated packaging architecture. This technology aims to shorten the transmission path of electrical signals by integrating optical engines and core electrical chips such as switching chips on the same packaging substrate, thereby significantly reducing system power consumption and improving transmission performance.

[0003] In the selection and implementation of materials for optoelectronic co-packaging platforms, glass substrates are becoming a focus of industry attention due to their excellent low dielectric constant, low loss factor, low coefficient of thermal expansion, and good dimensional stability. Existing technologies typically utilize glass substrates as carriers for electrical interconnects, fabricating through-glass vias (TGVs) within them and redistribution layers (RDLs) on their surface to achieve high-density vertical and horizontal electrical signal transmission between electrical chips or between chips and the packaging substrate. For optical signal transmission, external fiber optic arrays or independent optical modules are typically used to interface with the packaging substrate, or optical waveguide structures are fabricated on independent polymer or silicon substrates and then integrated with the glass substrate. For optical signal generation, vertical-cavity surface-emitting lasers (VCSELs) are... With its advantages such as low cost, ease of two-dimensional arraying, and wafer-level testing, VCSEL is widely used in short-distance optical interconnect scenarios. However, the beam output by VCSEL typically has a large divergence angle of 8° to 30°. If it is directly aligned and coupled with an optical waveguide or optical fiber, it will generate huge coupling loss due to severe mode mismatch. To solve this problem, existing solutions usually require the introduction of an independent beam shaping element, such as a discrete microlens array, between the VCSEL and the optical waveguide. This element needs to be precisely positioned and fixed by a high-precision active alignment device during the packaging process. This process not only significantly increases the complexity and time cost of assembly, but the additional assembly errors and thermal mismatch problems introduced may also affect the long-term reliability and optical performance of the final product.

[0004] In summary, existing optoelectronic packaging technologies still face challenges in achieving high integration. On the one hand, electrical interconnects and optical interconnects are often implemented on different carriers or integrated through complex processes, making it difficult to achieve true integration and miniaturization on a single substrate. This results in a large overall package size and a lengthy manufacturing process. On the other hand, and this is a key bottleneck for current technologies, even if optoelectronic pathway integration is achieved, solving the problem of efficient and low-cost coupling between surface-emitting light sources and internal optical waveguides remains a major technical challenge. The reliance of existing technologies on external independent optical components and high-precision active alignment processes directly leads to high packaging costs, low assembly efficiency, and limits further improvements in optoelectronic channel density, becoming one of the main obstacles restricting the performance and commercial potential of optoelectronic co-packaging technology. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned shortcomings and provide an optoelectronic co-packaging glass substrate, its processing technology, and an optoelectronic co-packaging module.

[0006] Firstly, an optoelectronic co-encapsulation glass substrate adopts the following technical solution:

[0007] An optoelectronic co-packaging glass substrate, comprising:

[0008] Glass substrate;

[0009] At least one electrical interconnect via penetrating the glass substrate;

[0010] At least one redistribution layer is disposed on the surface of the glass substrate and electrically connected to the electrical interconnect vias, wherein the electrical interconnect vias and the redistribution layer constitute an electrical interconnection structure for vertical transmission and horizontal wiring of electrical signals;

[0011] At least one optical waveguide channel is embedded inside the glass substrate for transmitting optical signals;

[0012] An optical path steering groove structure is disposed inside the glass substrate and connected to the optical waveguide channel to change the propagation direction of the optical signal; and

[0013] A microlens array is disposed on the upper surface of the glass substrate, wherein each microlens corresponds in spatial position to an optical signal port of the optical waveguide channel, and the microlens array is configured to couple a diverging beam perpendicular to the surface of the glass substrate to the optical waveguide channel.

[0014] Furthermore, the redistribution layers are respectively disposed on the upper and lower surfaces of the glass substrate, and interlayer electrical signals are connected through the electrical interconnect vias.

[0015] Furthermore, the optical path steering groove structure is a V-shaped groove, with a highly reflective metal film or dielectric film deposited on its inclined surface, and the interior of the groove is filled with a transparent organic material that matches the refractive index of the glass substrate. The angle of the inclined surface is configured to change the beam propagation direction by 90°.

[0016] Furthermore, each microlens in the microlens array is a spherical or aspherical lens with a surface roughness of less than 50 nm, and its optical focal point position matches the position of the optical signal port.

[0017] Secondly, a processing technology for an optoelectronic co-packaging glass substrate adopts the following technical solution:

[0018] A processing technology for an optoelectronic co-packaging glass substrate includes the following steps:

[0019] Step (1), provide a glass substrate;

[0020] Step (2): Using femtosecond laser direct writing technology, at least one optical waveguide channel and an optical path steering groove structure connected to the optical waveguide channel are formed on a predetermined depth and three-dimensional path inside the glass substrate.

[0021] Step (3): Form at least one through-hole electrical interconnect on the glass substrate, and prepare a redistribution layer communicating with the electrical interconnect by depositing and patterning a metal layer on at least one surface of the glass substrate; and

[0022] Step (4): On the upper surface of the glass substrate, at the position corresponding to the optical signal port of the optical waveguide channel, a microlens array is formed in situ through at least two laser processing steps to obtain the optoelectronic co-encapsulated glass substrate.

[0023] Furthermore, after step (2), the processing technology further includes an annealing process for the laser-rewritten glass substrate. The annealing process includes the following steps: heating the laser-rewritten glass substrate to a set annealing temperature according to a predetermined heating curve and maintaining the temperature at a constant temperature, and then slowly cooling it down to eliminate local thermal stress generated during the laser processing process.

[0024] Further, in step (3), a nanosecond pulsed laser is used to modify a preset area of ​​the glass substrate to form an easily etchable active area; the active area is removed by wet etching to form a through-hole electrical interconnect; a conductive metal seed layer is deposited sequentially on the inner wall of the through-hole, a highly conductive material is filled by electroplating, and excess metal is removed by chemical mechanical polishing to obtain a smooth surface.

[0025] Further, in step (3), a physical vapor deposition attachment layer / conductive seed layer is performed on the surface of the glass substrate, wherein the attachment layer / conductive seed layer is selected from Ti / Cu or Cr / Cu; then, an upper redistribution circuit is fabricated on the surface of the glass substrate by photolithography, residual photoresist is stripped off, and the conductive seed layer of the non-wired area is removed by etching.

[0026] Further, in step (4), the laser processing technology includes a first laser ablation process and a second laser thermal reconstruction process; the first laser ablation process uses a femtosecond laser to ablate and remove material layer by layer through a dot matrix or spiral trajectory scanning to form a cylindrical micropillar array; the second laser thermal reconstruction process uses a carbon dioxide laser to rapidly and locally heat the micropillar array, and utilizes the melting of the glass surface and the surface tension to automatically reconstruct it into a microlens array with a smooth optical surface having a preset radius of curvature and numerical aperture.

[0027] Thirdly, an optoelectronic co-packaged module adopts the following technical solution:

[0028] An optoelectronic co-packaged module, comprising:

[0029] Such as the optoelectronic co-packaging glass substrate mentioned above; and

[0030] The optoelectronic chip array is integrated onto the upper surface of the glass substrate using flip-chip or surface mount technology. Multiple optical transceiver units on the array correspond one-to-one with the microlenses of the microlens array, and the electrical contact points on the array are connected to external circuits through the electrical interconnect vias.

[0031] The beneficial effects of this invention are:

[0032] This invention provides a photoelectric co-packaging glass substrate. By simultaneously integrating electrical interconnect structures, optical waveguide channels, optical path steering groove structures, and microlens arrays on a single glass substrate, a highly integrated photoelectric hybrid interconnect platform is constructed. This invention directly integrates a microlens array, precisely corresponding to the internal optical waveguide ports, onto the upper surface of the glass substrate. This makes the optical coupling interface an inherent component of the glass substrate itself. Since the microlens array and the optical waveguide channel form an inherent, high-precision positional correspondence during substrate manufacturing, the subsequent photoelectric chip mounting process eliminates the need for complex and expensive active alignment operations on individual optical components. This greatly simplifies the overall assembly process of the photoelectric co-packaging module, shortens the production cycle, and reduces manufacturing costs. Furthermore, this native, high-precision alignment structure ensures that the microlenses can efficiently collimate and focus large divergence angle beams generated by external surface-emitting light sources. This significantly improves the coupling efficiency of the optical signal from the chip into the internal optical path of the substrate, effectively reducing optical path loss and lowering the overall system power consumption of the photoelectric co-packaging module. Attached Figure Description

[0033] Figure 1 This is a process flow diagram of a photoelectric co-packaging glass substrate provided in an embodiment of the present invention.

[0034] Figure 2 A simulation diagram of the optical path transmission of a microlens array on the surface of a photoelectric co-packaged glass substrate provided in an embodiment of the present invention;

[0035] Figure 3 This is a simulation diagram of optical path transmission on the surface of a glass substrate without a microlens array, provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of the optoelectronic co-packaging module structure provided in an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of a VCSEL array for an optoelectronic co-packaged module provided in an embodiment of the present invention.

[0038] Figure 6 This is a schematic diagram of the waveguide-V-groove-microlens coupling structure of the optoelectronic co-packaged module provided in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the present application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0040] In the following description, references to "some embodiments" refer to a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. Unless otherwise defined, all technical and scientific terms used in the embodiments of the invention have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the invention pertain. The terminology used in the embodiments of the invention is for the purpose of describing the embodiments of the invention only and is not intended to limit the invention.

[0041] Those skilled in the art should understand that, in the following description of the embodiments of the present invention, the sequence of numbers does not imply the order of execution. Some or all steps may be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0042] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0043] Those skilled in the art will understand that the numerical ranges in the embodiments of the present invention should be understood to specifically disclose each intermediate value between the upper and lower limits of the range. Each smaller range between any stated value and an intermediate value within the stated range, as well as any other stated value or an intermediate value within the stated range, is also included within the present invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0044] Unless otherwise stated, the technical / scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials are described herein, any methods and materials similar or equivalent to those described herein may be used in embodiments or test cases of the invention. All references to this specification are generally incorporated herein by reference to disclose and describe methods and / or materials associated with said references. In the event of any conflict with any incorporated reference, the contents of this application shall prevail.

[0045] This embodiment provides an optoelectronic co-packaging glass substrate. The core of the substrate is a 4-inch borosilicate glass wafer with a thickness of 500µm.

[0046] Electrical interconnect vias: fabricated using laser-induced selective etching technology, with a hole diameter of 50µm and a center-to-center spacing of 200µm. The vias are filled with oxygen-free copper through electroplating and the surface is planarized by chemical mechanical polishing, achieving a surface roughness Ra of less than 5nm.

[0047] Redundancy layers: These are fabricated on the upper and lower surfaces of the glass substrate, respectively. A 20nm titanium layer is sputtered as an adhesion layer and a 100nm copper layer as a seed layer using physical vapor deposition. Copper wires with a thickness of 5µm are then formed through photolithography and electroplating processes, with a linewidth / spacing of up to 10µm / 10µm.

[0048] Optical waveguide channel: A femtosecond laser with a center wavelength of 1030nm and a pulse width of 250fs is used to perform direct writing at a scanning speed of 200mm / s at a depth of 150µm below the surface of the glass substrate through multiphoton absorption effect, forming a single-mode optical waveguide core with an increase in refractive index of about 0.005. Its mode field diameter is about 10.4µm at a wavelength of 1550nm.

[0049] Optical path steering groove structure: At a predetermined turning point in the optical waveguide path, a precise 45° tilted reflective surface is formed internally using the same femtosecond laser through layer-by-layer ablation. This reflective surface is then coated with a 100nm thick gold film by magnetron sputtering to enhance reflectivity.

[0050] Microlens array: Integrated on the surface of a glass substrate through a two-step laser process. The optical axis of each microlens is precisely aligned with the central axis of the optical waveguide port 150µm below, and its positional accuracy is guaranteed by the high-precision three-dimensional motion platform of the laser direct writing system (repeatability <±0.5µm).

[0051] Because this embodiment integrates all passive functional components for electrical and optical interconnects on a single, homogeneous glass substrate using an integrated, wafer-level manufacturing method, it fundamentally eliminates the inherent interfacial stress, thermal expansion coefficient mismatch, and cumulative tolerance problems introduced by multi-step bonding processes that are present in existing technologies when using mixed integration of different materials (such as silicon, polymers, and glass). This significantly improves the structural integrity, mechanical strength, and long-term operational reliability of the entire substrate over a wide temperature range (-40°C to 85°C). In particular, since the microlens array is not a separately packaged component but rather becomes a structural part of the glass substrate itself through micro- and nano-fabrication techniques, it forms an inherent, permanent, submicron-level high-precision alignment relationship with the internal optical waveguide. This allows the entire substrate to function as a whole, providing a highly consistent and stable ready-to-use optocoupler interface, ultimately completely avoiding the performance degradation and reliability risks caused by the precision assembly, curing, and aging of discrete components in traditional packaging.

[0052] In some embodiments, the redistribution layer on the upper surface is designed as a fine-pitch pad array that matches the optoelectronic chip (such as a VCSEL array), for connection to the chip's microbumps via thermosetting bonding or flip-chip bonding. The redistribution layer on the lower surface is designed as a ball grid array pad pattern with a pitch of 500µm conforming to JEDEC standards. The TGV penetrating the glass substrate serves as a high-frequency coaxial transmission structure, connecting the RDLs on the upper and lower surfaces to enable signal transmission from the chip to the external packaging substrate.

[0053] Because electrical signals can be transmitted vertically and redistributed horizontally along a complete three-dimensional path from "upper-layer fine-pitch RDL → TGV → lower-layer wide-pitch RDL," this embodiment achieves a high-frequency, low-loss electrical signal fan-out function in its physical structure. This allows high-density, fine-pitch electrical signals (analog signals exceeding 25GHz or digital signals exceeding 100Gbps) from the upper-layer optoelectronic chip to be efficiently rerouted within the glass substrate and converted into a more relaxed, standardized BGA pad interface. Ultimately, this structure enables advanced optoelectronic chips requiring high-density interfaces to be reliably connected to standard organic packaging substrates or printed circuit boards with mature manufacturing processes and low costs, perfectly solving the major technical challenge of interface mismatch between advanced chips and the traditional electronics manufacturing ecosystem.

[0054] In this embodiment, the optical path steering groove structure is a V-shaped groove. This V-shaped groove is formed by ablating glass material layer by layer along a predetermined path using a femtosecond laser. The angle between its two inclined inner walls is precisely controlled at 90°±0.5°, and each inner wall forms a 45°±0.25° angle with the glass substrate surface. A 100nm gold film is deposited on the inner walls using magnetron sputtering, forming a reflector with a reflectivity exceeding 99% at a wavelength of 1550nm and an incident angle of 45°. Finally, using UV-curable optical adhesive with a refractive index of 1.457 (matching p-Silicate glass), the V-shaped groove cavity is completely filled and sealed using vacuum infusion.

[0055] Because the V-groove is directly fabricated within the glass substrate using a femtosecond laser with submicron resolution, its 45° tilt angle and nanometer-level surface flatness are precisely controlled. This ensures the beam can be redirected 90° with near-diffraction-limited precision, minimizing beam pointing errors and mode mismatch losses caused by angular deviations. Furthermore, since the groove is filled with a material whose refractive index precisely matches the substrate, Fresnel reflection losses caused by abrupt changes in refractive index when the beam enters and exits the redirection structure are completely eliminated. Ultimately, compared to existing technologies that use discrete components such as external microprisms or 45° polished optical fibers, this integrated redirection structure exhibits significantly lower optical insertion loss and unparalleled structural integration and stability.

[0056] Each microlens in this embodiment is an aspherical lens, and its surface parameters are defined by a high-order polynomial and are based on the target VCSEL at 1 / e 2 The 20° divergence angle and the numerical aperture of the target single-mode waveguide (0.14) were optimized through reverse tracing to completely eliminate spherical aberration. The surface roughness was controlled to below 5 nm using a subsequent CO2 laser thermal polishing process. The optical focus was precisely designed 150 µm below the interior of the glass substrate, with an error of less than ±1 µm in the Z-axis direction relative to the end face position of the waveguide channel.

[0057] Because the microlens employs a precisely optimized aspherical design, it effectively corrects spherical aberration introduced by simple spherical lenses, shaping the non-ideal Gaussian beam from the VCSEL into a diffraction-limited, perfectly Airy disk with a flat wavefront at the focal point. Simultaneously, its optical-grade surface roughness (<5nm) minimizes beam scattering losses on the lens surface. Furthermore, the precise three-dimensional matching between its focal position and the physical location of the optical waveguide port enables near-perfect matching between the diameter and shape of the focused beam mode field and the waveguide mode field. Ultimately, these structural optimizations work together to increase the optical signal coupling efficiency from less than 55% without lenses to over 90% of the theoretical limit. This means that the same optical output can be achieved with significantly lower drive power, directly reducing the core operating power of the entire optoelectronic module.

[0058] This embodiment provides a processing technology for borosilicate glass wafer substrates, including the following steps:

[0059] Step (1): Select a 4-inch diameter, 500µm thick borosilicate glass wafer and perform standard cleaning in a cleanroom.

[0060] Step (2): Using a femtosecond laser direct writing system equipped with a high-precision three-dimensional motion stage (repeat positioning accuracy < ±0.5µm), all designed optical waveguides and steering groove networks are batch-processed inside the wafer.

[0061] Step (3): Transfer the wafer to a nanosecond laser processing equipment and a wet etching stage to batch fabricate TGV vias. Then, RDLs are fabricated on both sides of the wafer using standard semiconductor thin film and electroplating processes.

[0062] Step (4): The wafer with the electrical structure processed is sent back into the femtosecond laser direct writing system. After global alignment by the system through the preset alignment marks, self-aligned microlens arrays are mass-produced above each optical waveguide port through a two-step laser process.

[0063] This process integrates embedded waveguide fabrication, surface microlens fabrication, and TGV / RDL electrical fabrication—originally belonging to different technical fields and requiring different equipment and process chains—into a single, ordered manufacturing process based on a single glass wafer. This achieves a high degree of integration of optoelectronic functions and true wafer-level parallel mass production. The core innovation of this process lies in the fact that the embedded optical waveguide (step 2) and the surface microlens (step 4) are processed sequentially under the same high-precision positioning system and software control. This enables sub-micron level passive self-alignment between the two without any external intervention. This fundamentally replaces the costly, time-consuming, low-yield, and difficult-to-mass-produce active alignment and assembly process of existing technologies, paving the way for the commercial production of low-cost, high-performance optoelectronic co-packaged modules.

[0064] In some embodiments, after the femtosecond laser direct writing in step (2) is completed, the entire glass wafer is placed in a precisely temperature-controlled tube annealing furnace. Under a nitrogen protective atmosphere, the temperature is increased from room temperature to 600°C at a rate of 10°C per minute, held at that temperature for 2 hours, and then slowly cooled to room temperature at a rate of 50°C per hour (i.e., <1°C per minute).

[0065] Because femtosecond laser direct writing non-thermally alters the refractive index by inducing micro-explosions and material densification within the glass, this drastic process introduces significant, highly localized residual thermal stresses into the glass matrix surrounding the waveguide core. If these stresses are not eliminated, they can induce stress birefringence, leading to polarization-dependent losses in the optical signal. Furthermore, they may slowly dissipate during subsequent thermal processing or long-term use, causing degradation of the waveguide's optical performance and even inducing microcracks, threatening the device's mechanical integrity. The annealing process in this embodiment effectively and globally eliminates these harmful residual stresses by providing sufficient thermal energy to allow the glass network structure to overcome the energy barrier, enabling adequate relaxation and reconstruction. Ultimately, this results in a high-quality optical waveguide with polarization insensitivity and long-term stable optical properties, while also significantly enhancing the mechanical strength and thermal shock resistance of the entire glass substrate.

[0066] In some embodiments, step (3) is implemented as follows:

[0067] TGV formation: A nanosecond ultraviolet laser with a pulse width of 30ns and a wavelength of 355nm is focused on the glass surface to form a modified dot matrix. Then, the wafer is immersed in a 10% hydrofluoric acid solution, and the modified areas are selectively etched at a speed more than 100 times faster than the unmodified areas to form the prototype of TGV.

[0068] RDL fabrication: A 20nm titanium layer as an adhesion layer and a 100nm copper layer as a seed layer were sequentially sputtered onto both sides of the entire wafer using PVD. Subsequently, a 10µm thick layer of AZ-series positive photoresist was spin-coated, and exposure was performed using a mask aligner to define the circuit pattern of the RDL. After development, copper sulfate electroplating was performed to thicken the circuit pattern and the copper layer inside the TGV to 5µm. Finally, the photoresist was removed with acetone, and the exposed copper and titanium seed layers were rapidly and selectively removed using a dedicated etchant.

[0069] This process combines the high selectivity of laser modification with the high efficiency of wet etching, enabling the economical and efficient fabrication of TGV structures with a high aspect ratio (10:1) on glass, a traditionally difficult-to-process and chemically inert material. Furthermore, the seamless integration of mature, stable, and low-cost PVD, photolithography, and electroplating processes from the semiconductor industry allows for the formation of low-resistance, high-adhesion, and high-reliability copper interconnect networks on the three-dimensional glass morphology (including hole walls and dual surfaces). This complete and optimized combined process enables the glass to carry high-speed electrical signals while maintaining its excellent optical properties, providing a technically feasible and economically scalable manufacturing pathway for achieving the ultimate fusion of optoelectronic functions on a single substrate.

[0070] In some embodiments, step (4) is implemented as follows:

[0071] Step 1 (Ablation): Using a femtosecond laser with a pulse width of 200 fs, a cylindrical micropillar array with a diameter of 100 µm, a height of 30 µm, and steep sidewalls was ablated on the glass surface through multi-layer, concentric ring scanning.

[0072] The second step (thermal reconstruction polishing): Using a continuous wave (CW) or long-pulse carbon dioxide laser with a spot diameter of 500µm, the top of each micropillar in the micropillar array is precisely irradiated with a single pulse (10ms pulse width, 5W power), causing the glass layer about 2µm deep on its surface to melt instantaneously into a viscous flow state. Under the action of surface tension, the molten glass automatically contracts, forming a spherical or aspherical cap with the lowest energy and the smoothest surface.

[0073] This process decouples and connects the seemingly contradictory processing requirements of precise control over volume and position with perfect shaping of surface morphology, thus combining the unique advantages of both types of lasers. Femtosecond lasers ensure the precision of critical dimensions such as the diameter, height, and position of the microlenses, while CO2 lasers utilize the fundamental physical properties of glass to act as a perfect, non-contact polishing tool. This method not only fundamentally avoids defects such as surface roughness, heat-affected zones, and recast layers caused by traditional laser ablation, but also eliminates the need for any mechanical contact polishing that could introduce damage and contamination. Ultimately, it enables the in-situ fabrication of self-aligned microlens arrays with near-theoretical optical quality on a substrate in a non-contact, highly efficient, and highly repeatable manner.

[0074] This embodiment provides a co-packaged optoelectronic (CPO) module. The core of this module is the aforementioned co-packaged optoelectronic glass substrate. Multiple 1x4 channel VCSEL array chips (channel pitch 250µm) are aligned with their light-emitting units to a precision of ±1.5µm directly above the microlens array on the glass substrate using a fully automated flip-chip bonding machine. Lead-free solder microbumps form electrical and mechanical connections after reflow soldering. External high-speed electrical signals from the module enter the glass substrate through a high-frequency packaging carrier and a lower RDL, powering the VCSEL chips and transmitting data. The beam emitted by the VCSEL is coupled into the interior of the glass substrate through microlenses, routed to the side of the substrate via embedded waveguides and steering mirrors, and finally output through a multi-core fiber optic connector actively aligned and fixed to the edge of the substrate.

[0075] Because this module uses the highly integrated optoelectronic co-packaged glass substrate as its core interconnecting medium, the key optical interfaces (VCSEL to waveguide) and electrical interfaces between the optoelectronic chip and the substrate are implemented in a high-density, high-performance, and pre-aligned manner. This greatly simplifies the entire module packaging process, moving the most complex and expensive active optical alignment step forward to the substrate manufacturing stage. The final module assembly is almost simplified to a standard electronic chip packaging process. Compared with existing technologies, because the electrical path (from chip to substrate) and optical path (from chip to fiber) are significantly shortened and optimized, the overall module size is reduced by more than 50%, power consumption is reduced by about 30%, and signal integrity and optical performance stability are fundamentally enhanced under different operating temperatures. Ultimately, this embodiment provides an optoelectronic co-packaged module product with a more compact structure, superior performance, lower cost, and easier automated mass production.

[0076] This embodiment provides a specific optoelectronic co-packaging glass substrate, which adopts a wafer-level mass production process. The complete processing steps are as follows: Figure 1 As shown, it includes the following steps:

[0077] Step 1: Glass Cleaning

[0078] A 4-inch, 700µm thick borosilicate glass wafer was selected as the initial substrate. The wafer was placed in an ultrasonic cleaner and ultrasonically cleaned for 20 minutes using deionized water and a specialized cleaning agent to remove surface particles, oil, and organic residues. After cleaning, it was repeatedly rinsed with high-purity deionized water and then placed in a 120°C oven for 2 hours of hot air drying to provide a clean, contamination-free substrate for subsequent precision machining.

[0079] Step 2: Laser direct-write waveguide

[0080] A clean glass wafer is loaded into a femtosecond laser 3D direct writing system. This system uses a laser with a center wavelength of 1030 nm and a pulse width of 250 fs. The laser beam is focused to a depth of 100 µm below the surface of the glass substrate using a high numerical aperture (NA=0.9) objective lens. Figure 6 (waveguide depth in the middle). A high-precision three-dimensional motion platform (repeat positioning accuracy < ±0.5µm) is controlled to scan according to a preset three-dimensional path map, forming a single-mode optical waveguide core network inside the glass with a refractive index approximately 0.005 higher than that of the substrate material through multiphoton absorption effect.

[0081] Step 3: Annealing to relieve stress

[0082] The laser-written glass wafer is placed in a programmable tube furnace. Under a nitrogen protective atmosphere, the temperature is raised to 600°C according to a preset heating curve and held at this temperature for 2 hours. Subsequently, it is slowly cooled to room temperature at a rate of 50°C per hour. This step aims to completely release the localized thermal stress introduced in the waveguide region during the femtosecond laser writing process, ensuring the long-term stability of the optical waveguide's optical performance and enhancing the overall mechanical strength of the substrate.

[0083] Step 4: Laser-induced drilling / etching

[0084] A nanosecond ultraviolet laser with a pulse width of 30 ns is used to perform focused scanning at a predetermined position on the surface of the glass wafer, locally modifying the glass material to form active regions that are easily chemically etched. Subsequently, the wafer is immersed in a 10% hydrofluoric acid solution for wet etching, and the active regions are rapidly and selectively removed to form TGV prototype holes with good perpendicularity that penetrate the entire glass substrate.

[0085] Step 5: Seed layer / electroplating / CMP

[0086] Using physical vapor deposition (PVD), a 20 nm titanium layer as an adhesion layer and a 100 nm copper layer as an electroplating seed layer are sequentially sputtered onto the entire front side of the wafer (including the walls of the TGV vias). Subsequently, highly conductive oxygen-free copper is electroplated to completely fill the TGV vias. Finally, excess metal is removed from the surface using chemical mechanical polishing, resulting in a highly planarized metallized TGV array flush with the glass surface.

[0087] Step 6: PVD / Photolithography / Electroplating

[0088] On the flat surface after TGV filling, a Ti / Cu seed layer is deposited again using a PVD process. Next, the redistribution layer circuit pattern on the front side is defined using standard photolithography (spin-coating photoresist, mask alignment and exposure, development). Electroplating is then performed to thicken the copper conductors to 5µm.

[0089] Step 7: Remove adhesive / etch

[0090] After electroplating, residual photoresist is removed using chemical solvents, and copper and titanium seed layers in areas not covered by the circuit are quickly removed using a special etching solution.

[0091] Step 8: Pi lithography

[0092] A layer of polyimide is spin-coated onto the front side of the wafer as a passivation protection layer. Then, photolithography is used again to open the PI layer at the pads where electrical connections are required, forming windows.

[0093] Step 9: External front-side Ni / Pd / Au protection

[0094] Finally, nickel / palladium / gold (Ni / Pd / Au) is sequentially deposited on the exposed copper pads through outsourcing or internal chemical plating to form a surface treatment with excellent solderability and oxidation resistance.

[0095] Step 10: Return to factory for temporary bonding on the front side

[0096] The glass wafer, after all front-side processing has been completed, is bonded to a support wafer (such as a silicon wafer or glass wafer) of matching size and morphology using temporary bonding adhesive. The purpose of this step is to provide mechanical support and protection for the complex glass wafer during subsequent back-side thinning and processing.

[0097] Step 11: Thinning / CMP

[0098] After bonding, the wafer pairs are flipped, and the back side of the glass wafer is mechanically ground using a precision wafer thinner to obtain an optical-grade flat surface.

[0099] Step 12: Fabricate microgrooves / polish / coat reflective film

[0100] On the thinned back side, a femtosecond laser is used to fabricate V-shaped microgrooves for optical path steering at positions corresponding to the embedded optical waveguide through layer-by-layer ablation. After ablation, selective local chemical polishing can be performed to further reduce the roughness of the groove inner wall. Finally, a high-reflectivity metal film (such as a gold film) or dielectric film is deposited on the inclined surface of the V-shaped groove using ion beam assisted deposition technology.

[0101] Step 13: Fill with organic material

[0102] Using precision dispensing equipment, UV-curable optical adhesive, matching the refractive index of the glass substrate, is precisely filled into the cavities of the V-shaped microgrooves. After filling, it is fully cured by UV irradiation. This step aims to eliminate air interfaces in the optical path and reduce Fresnel reflection loss.

[0103] Step 14: Overall Annealing Stress Relief

[0104] To eliminate the accumulated stress introduced by a series of processes such as back-side thinning and laser processing, the bonded wafer pairs are subjected to an overall, low-temperature annealing treatment.

[0105] Step 15: Thinning / CMP (230μm)

[0106] The back side of the glass wafer is mechanically ground using a precision wafer thinner until its thickness approaches the target value. Then, it undergoes fine polishing using a CMP process, ultimately precisely controlling the thickness of the glass substrate to 230µm (corresponding to...). Figure 6 (the final thickness in the process), and obtain an optically grade flat surface.

[0107] Step 16: Backside PVD / Photolithography / Electroplating / Resist Removal / Etching

[0108] On the back side of the glass wafer, a Ti / Cu seed layer is deposited again using a PVD process. Next, the redistribution layer circuit pattern on the back side is defined using standard photolithography (spin-coating photoresist, mask alignment and exposure, development). Electroplating is then performed to thicken the copper conductors to 5µm. After electroplating, residual photoresist is removed using chemical solvents, and the copper and titanium seed layers in areas not covered by the circuitry are rapidly removed using a specialized etching solution.

[0109] Step 17: Pi lithography

[0110] A layer of polyimide is spin-coated onto the back of the wafer as a passivation protective layer. Then, photolithography is used again to open the PI layer at the pads where electrical connections are required, forming windows.

[0111] Step 18: External backside Ni / Pd / Au protection and debonding

[0112] Finally, nickel / palladium / gold (Ni / Pd / Au) is sequentially deposited on the exposed copper pads via outsourcing or internal chemical plating to form a surface treatment with excellent solderability and oxidation resistance. After all back-side processing is completed, the processed glass wafer is safely separated from the support wafer by heating or chemical dissolution to obtain an independent, double-sided structured optoelectronic co-packaging glass substrate wafer.

[0113] After completing all the above glass substrate processing steps, the glass wafer undergoes final cleaning. Then, it is fed into a laser processing system, where it is precisely positioned using preset alignment marks for microlens array integration.

[0114] To further illustrate the technical effects of this embodiment, Figure 2 The simulation results of optical path transmission are presented. The simulation simulates the propagation of a light beam from an optical waveguide channel (located at Y≈200µm) inside a glass substrate, and its propagation after being redirected by 90° via an optical path redirection groove structure (located at X≈200µm).

[0115] Figure 3 The comparison optical path is shown without the microlens array. In this case, the beam directly coupled into the optical waveguide from the light source diverges severely. After reaching the optical path steering groove structure, although the optical path is turned 90°, the beam energy is dispersed during subsequent vertical propagation, and the diffraction effect and stray light are very obvious. Finally, a clear light spot is not formed at the light exit (Y≈400µm), and the energy concentration is extremely low.

[0116] Figure 2 The optical path is illustrated when the microlens array described in this embodiment is configured. In this case, the diverging beam from the light source is first collimated and shaped by the microlenses, forming a high-quality collimated beam that enters the optical waveguide. After being deflected 90° by the optical path steering groove structure, the collimated beam still maintains a high degree of collimation and excellent energy concentration, with almost no side lobes or stray light energy loss, ultimately forming a highly concentrated, clear, and sharp light spot at the light exit.

[0117] By comparison Figure 2 and Figure 3 It is clearly evident that the microlens array in this embodiment plays a crucial role in beam shaping and collimation, significantly improving the beam transmission quality within the substrate. Because all passive functional components required for both electrical and optical operations are integrated into a single, homogeneous glass substrate, bonding interfaces and thermal mismatch issues between different materials are avoided, thereby significantly improving the structural stability and long-term reliability of the substrate. In particular, since the microlens array is an integral part of the glass substrate itself, it forms an inherent and permanent high-precision alignment relationship with the internal optical waveguide. This allows the entire substrate to function as a whole, providing a highly efficient and stable optical coupling interface. Ultimately, this structure not only fundamentally eliminates the performance degradation and reliability risks caused by discrete component assembly errors in traditional packaging, but also increases the coupling and transmission efficiency of optical signals from below 55% to over 90%, validating the significant technological advancements of this invention.

[0118] This embodiment utilizes the optoelectronic co-packaging glass substrate prepared by the above process to construct a high-speed, high-density optoelectronic co-packaging (CPO) module for data centers.

[0119] 1. Module Components

[0120] Core interconnect platform: A photoelectric co-packaging glass substrate manufactured according to the above process, its overall layout is as follows. Figure 4 As shown.

[0121] Electrical core: A high-performance switching chip (ASIC).

[0122] Optical engine: Multiple 1x4 channel vertical-cavity surface-emitting laser (VCSEL) array chips (such as...) Figure 5 (as shown) and photodetector (PD) array chip.

[0123] Package substrate: An organic package carrier board with a ball grid array (BGA) interface.

[0124] External fiber optic interface: A multi-core fiber optic (MCF) array connector that matches the optical port array on the side of the glass substrate.

[0125] 2. Module Assembly Process

[0126] Chip mounting: Using high-precision flip-chip bonding equipment, the microbumps of the switching ASIC, VCSEL array, and PD array are aligned and thermo-bonded to the corresponding pads on the RDL layer of the upper surface of the glass substrate. The mounting positions of the VCSEL and PD arrays are precisely aligned with the underlying microlens array.

[0127] Underfill: An underfill material is injected into the gap between the chip and the glass substrate and cured after heating to protect the solder joints and disperse thermal stress.

[0128] Substrate mounting: The glass substrate assembly with the chip mounted is then connected to the corresponding pads on the organic packaging substrate below by flip-chip bonding, with the RDL pads on its back side connected to the corresponding pads on the substrate below.

[0129] Fiber optic coupling: Using a six-axis precision alignment platform, the end face of the multi-core fiber array connector is actively aligned with the optical port (i.e., the light output position of the V-groove) on the side of the glass substrate. After achieving maximum coupling efficiency, it is permanently fixed using a low-shrinkage UV-curing adhesive.

[0130] Heat dissipation and sealing: An integrated heat sink is installed on the back of the ASIC and light engine chip, and a metal casing is added to seal the entire module to provide electromagnetic shielding and environmental protection.

[0131] 3. Working principle and signal path

[0132] Electro-optical conversion (emission path):

[0133] High-speed electrical signals from the outside enter the module through the BGA package carrier board and are transmitted upward to the front RDL via the back RDL and TGV of the glass substrate.

[0134] The signal is routed to the switching ASIC on the front RDL for processing, and the processed drive signal is then distributed to the VCSEL array through the front RDL.

[0135] The VCSEL array converts high-speed electrical signals into modulated vertical beams.

[0136] The vertical beam is collimated and focused by the microlens array directly above, and efficiently coupled into the optical waveguide channel 100µm below the glass substrate.

[0137] The optical signal is transmitted horizontally to the edge of the substrate in the optical waveguide.

[0138] At the edge, the optical signal is deflected by 90° by the reflective surface of the V-groove steering structure, becoming horizontally emitted.

[0139] Finally, a multi-core optical fiber is coupled into the outside from the side of the glass substrate to complete the long-distance transmission of optical signals.

[0140] Photoelectric conversion (receiving path):

[0141] The workflow is the reverse of the transmission path. External optical signals enter the side of the glass substrate through optical fiber, are deflected 90° by the V-groove, and then coupled into the embedded optical waveguide. After being focused onto the PD array by microlenses, they are converted into electrical signals and sent to the ASIC for processing.

[0142] Through this embodiment, a compact and high-performance CPO module was successfully constructed using the invented optoelectronic co-packaging glass substrate, realizing ultra-short distance, high efficiency, and high density optoelectronic interconnection between the electrical chip and the optical engine.

[0143] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A processing technology for an optoelectronic co-packaging glass substrate, characterized in that, Includes the following steps: Step (1), provide a glass substrate; Step (2): The glass substrate is loaded into a femtosecond laser direct writing system equipped with a high-precision three-dimensional motion stage. Using femtosecond laser direct writing technology, at least one optical waveguide channel and an optical path steering groove structure connected to the optical waveguide channel are processed on the preset depth and three-dimensional path inside the glass substrate. The laser-rewritten glass substrate is heated to the set annealing temperature according to the predetermined heating curve and kept at a constant temperature. Then it is slowly cooled down to eliminate the local thermal stress generated during the laser processing process. Step (3): Modify a preset area of ​​the glass substrate using a nanosecond pulsed laser to form an easily etchable active area; combine with wet etching to remove the active area to form a through-hole electrical interconnect. Conductive metal seed layers are sequentially deposited on the inner wall of the via, and highly conductive material is filled using an electroplating process. Excess metal is removed by chemical mechanical polishing to obtain a smooth surface. A physical vapor deposition attachment layer / conductive seed layer is then performed on the surface of the glass substrate. The attachment layer / conductive seed layer is selected from Ti / Cu or Cr / Cu. Subsequently, an upper redistribution circuit is fabricated on the surface of the glass substrate using a photolithography process. Residual photoresist is stripped, and the conductive seed layer in the non-wireless area is removed using an etching process to prepare a redistribution layer that communicates with the electrical interconnect via. as well as Step (4): The glass substrate that has been processed in step (3) is sent back into the femtosecond laser direct writing system described in step (2). After global alignment by the system through the preset alignment mark, a microlens array is formed in situ on the upper surface of the glass substrate and at the position corresponding to the optical signal port of the optical waveguide channel through at least two laser processing steps, thus obtaining the optoelectronic co-encapsulated glass substrate. The laser processing technology includes a first laser ablation process and a second laser thermal reconstruction process. The first laser ablation process uses a femtosecond laser to ablate and remove material layer by layer through dot matrix or spiral trajectory scanning to form a cylindrical micropillar array. The second laser thermal reconstruction process uses a carbon dioxide laser to rapidly and locally heat the micropillar array. By utilizing the melting of the glass surface and the effect of surface tension, the surface of the micropillar array melts and automatically shrinks, automatically reconstructing it into a microlens array with a smooth optical surface having a preset radius of curvature and numerical aperture. The optical axis of the microlens array and the central axis of the optical signal port of the optical waveguide channel are passively self-aligned through the femtosecond laser direct writing system.

2. A photoelectric co-encapsulation glass substrate, characterized in that, The optoelectronic co-encapsulation glass substrate, manufactured using the processing technology described in claim 1, comprises: Glass substrate; At least one electrical interconnect via penetrating the glass substrate; At least one redistribution layer is disposed on the surface of the glass substrate and electrically connected to the electrical interconnect vias, wherein the electrical interconnect vias and the redistribution layer constitute an electrical interconnection structure for vertical transmission and horizontal wiring of electrical signals; At least one optical waveguide channel is embedded inside the glass substrate for transmitting optical signals; An optical path steering groove structure is disposed inside the glass substrate and connected to the optical waveguide channel to change the propagation direction of the optical signal; and A microlens array is disposed on the upper surface of the glass substrate, wherein each microlens corresponds in spatial position to an optical signal port of the optical waveguide channel, and the microlens array is configured to couple a diverging beam perpendicular to the surface of the glass substrate to the optical waveguide channel.

3. The optoelectronic co-packaging glass substrate according to claim 2, characterized in that, The redistribution layers are respectively disposed on the upper and lower surfaces of the glass substrate, and the interlayer electrical signals are connected through the electrical interconnect vias.

4. The optoelectronic co-packaging glass substrate according to claim 3, characterized in that, The optical path steering groove structure is a V-shaped groove, with a highly reflective metal film or dielectric film deposited on its inclined surface, and the interior of the groove is filled with a transparent organic material that matches the refractive index of the glass substrate. The angle of the inclined surface is configured to change the beam propagation direction by 90°.

5. The optoelectronic co-packaging glass substrate according to claim 4, characterized in that, Each microlens in the microlens array is a spherical or aspherical lens with a surface roughness of less than 50 nm, and its optical focal point is matched with the position of the optical signal port.

6. A photoelectric co-packaged module, characterized in that, include: Optoelectronic co-encapsulation glass substrate as described in any one of claims 2 to 5; as well as The optoelectronic chip array is integrated onto the upper surface of the glass substrate using flip-chip or surface mount technology. Multiple optical transceiver units on the array correspond one-to-one with the microlenses of the microlens array, and the electrical contact points on the array are connected to external circuits through the electrical interconnect vias.

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