Method and device for correcting array image of light-emitting device and storage medium

Abstract

The invention discloses a method and a device for correcting a light-emitting device array image and a storage medium, which are used for converting an irregular light-emitting device array into an array image with a fixed repetition period so as to facilitate defect detection and improve the defect detection efficiency. The method comprises the following steps: acquiring a chip array diagram for shooting a target screen, and acquiring coordinate positions of chips in the target screen and the number of rows and columns of the chips; constructing a chip coordinate matrix according to the coordinate position of the chip; according to the coordinate positions of the chips and preset chip size parameters, the row and column spacing between the chips is obtained through calculation; according to preset chip size parameters, the number of rows and columns of the chips and the row and column spacing between the chips, theoretical dot matrix coordinates are constructed; dividing the chip coordinate matrix into a first area coordinate group; according to the theoretical dot matrix coordinates and the first region coordinate group, performing regional calculation to obtain a region transformation matrix; and processing the first region coordinate group according to the region transformation matrix to obtain a corrected image.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, and in particular to a light emitting device array image correction method and device and storage medium. BACKGROUND

[0002] In the field of display technology, display technologies such as MiniLED / MicroLED / OLED with light emitting device arrays are gaining more and more favor in the market due to their unique advantages.

[0003] In the generation and manufacturing process of these display technologies, a key and common step is to transplant a large number of light emitting chips onto the corresponding substrate. However, in actual operation, it is difficult to ensure that each chip or pixel point can be transplanted accurately according to the predetermined position, regardless of the technology. This results in a deviation in the spacing between the chips or pixel points, resulting in an irregular arrangement.

[0004] The conventional light-up detection algorithm is based on the early LCD\OLED array generated with the help of a mask with a fixed period. The distance between the pixels in this array is fixed and almost no deviation, so the algorithm only needs to set the appropriate period to effectively highlight the defects. However, when using this conventional light-up detection algorithm to detect irregularly arranged MiniLED / MicroLED / OLED light emitting device arrays, it is not possible to accurately extract defect information according to the fixed spacing. Some otherwise normal chips may be incorrectly identified as defects by the algorithm due to the non-compliance of the spacing with the surrounding chips with the fixed pattern, resulting in over-detection; while some chips with real defects may be missed due to the irregular arrangement of the surrounding chips, resulting in under-detection. This over-detection and under-detection phenomenon has a serious impact on the production and quality control of display screens. Over-detection increases unnecessary detection costs and subsequent processing workload, while under-detection allows defective products to flow into the market, reducing product qualification rates and increasing production costs. SUMMARY

[0005] The present application discloses a light emitting device array image correction method, device and storage medium for converting irregular light emitting device arrays into arrays with fixed arrangement rules for defect detection and improving defect detection efficiency.

[0006] The first aspect of the present application discloses a light emitting device array image correction method, comprising: obtaining a chip array image taken of a target screen, and obtaining the coordinate positions of a plurality of chips and the number of rows and columns of the chips in the target screen according to the chip array image; constructing a chip coordinate matrix according to the coordinate positions of the plurality of chips; The row and column spacing between the chips is calculated based on the coordinate positions of several chips and preset chip size parameters. Theoretical dot matrix coordinates are constructed based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips; The chip coordinate matrix is ​​divided into several first region coordinate groups, each first region coordinate group being a set of four coordinates in two adjacent rows and two columns. Based on the theoretical lattice coordinates and several sets of coordinates of the first region, several region transformation matrices are calculated by region. The first region coordinate group is processed according to the region transformation matrix to obtain the corrected image.

[0007] Optionally, the step of obtaining the coordinate positions of several chips in the target screen and the number of rows and columns of the chips according to the chip array diagram specifically includes: Step 1: Obtain the number of rows and columns of the chips in the chip array diagram; Step 2: Set a global threshold and extract the chip region based on the global threshold; Step 3: Obtain the connected components of the chip region, and filter out the valid connected components by the feature values ​​of the connected components; Step 4: Obtain the coordinate positions of the chips in the effective connected domain, and calculate the number of coordinate positions of the chips.

[0008] Optionally, the step of constructing a chip coordinate matrix based on the coordinate positions of the plurality of chips specifically includes: Based on the preset interval threshold and the chip array diagram, the coordinate positions of the chips are sorted and summarized into a chip coordinate matrix; If there are missing coordinates in the chip coordinate matrix, the missing coordinates are placed in the fitting matrix, and the corresponding positions of the missing coordinates in the fitting matrix are filled with negative numbers. The missing coordinates are the coordinate positions of the chips that were not detected in the chip array diagram. The missing coordinates are calculated by performing coordinate fitting on the fitted matrix and then summarizing the missing coordinates into the chip coordinate matrix.

[0009] Optionally, after step four, the correction method further includes: Step 5: If the difference between the product of the number of coordinate positions and the number of rows and columns is greater than a preset error value, then return to Step 2.

[0010] Optionally, the step of constructing theoretical matrix coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips specifically includes: The theoretical resolution of the target screen is calculated based on the preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. Based on the theoretical resolution and the preset chip size parameters, determine the range of values ​​for the theoretical dot matrix coordinates and the coordinates of the first point; The complete theoretical matrix coordinates are calculated based on the coordinates of the first point and the row and column spacing between the chips.

[0011] Optionally, the step of calculating the theoretical resolution of the target screen based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips specifically includes: The theoretical resolution of the target screen is calculated according to the following formula 1: Formula 1; Where Z is the theoretical resolution, W represents the number of pixels in width, H represents the number of pixels in height, Mr_X is the length of the chip, Mr_Y is the width of the chip, Dist_R is the row spacing between the chips, Dist_C is the column spacing between the chips, Num_R is the number of chips per row, and Num_C is the number of chips per column.

[0012] Optionally, the step of processing the first region coordinate set according to the region transformation matrix to obtain the corrected image specifically includes: Based on the preset compensation value, the first region coordinate group is updated to the second region coordinate group; The second region coordinate group is corrected according to the region transformation matrix to obtain the first corrected region image; Based on the first region coordinate set, the first correction region image is segmented to obtain the second correction region image; The second correction region image is sorted and merged according to the theoretical dot matrix coordinates to obtain a complete correction image.

[0013] Optionally, after the step of processing the first region coordinate group according to the region transformation matrix to obtain the corrected image, the correction method further includes: Based on the chip size parameters, the gaps between the chips in the corrected image are eliminated, and a second theoretical coordinate matrix and a first gapless corrected image are generated; Based on the second theoretical coordinate matrix, extract the chip grayscale value of the chip's coordinate position in the first gapless correction image; Set a zero-grayscale image and fill the corresponding positions of the chip grayscale values ​​into the zero-grayscale image to generate the final second gapless correction image. The zero-grayscale image is an image with the same size as the first gapless correction image and all grayscale values ​​are 0.

[0014] A second aspect of this application provides a correction apparatus for an image of a light-emitting device array, comprising: The acquisition unit is used to acquire a chip array diagram of the target screen captured by the image, and to acquire the coordinate positions and the number of rows and columns of several chips in the target screen based on the chip array diagram. The first construction unit is used to construct a chip coordinate matrix based on the coordinate positions of the chips. The first calculation unit is used to calculate the row and column spacing between the chips based on the coordinate positions of the chips and preset chip size parameters. The second construction unit is used to construct theoretical lattice coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. A partitioning unit is used to divide the chip coordinate matrix into several first region coordinate groups, wherein the first region coordinate group is a set of four coordinates in two adjacent rows and two columns. The second calculation unit is used to calculate several regional transformation matrices by region based on the theoretical lattice coordinates and several sets of first region coordinates. The processing unit is used to process the first region coordinate group according to the region transformation matrix to obtain the corrected image.

[0015] A third aspect of this application provides a computer-readable storage medium on which a program is stored, which, when executed on a computer, performs the methods described in the first aspect and any optional methods of the first aspect.

[0016] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: By acquiring captured chip array images and extracting chip coordinate positions and row / column numbers, the actual chip distribution on the target screen can be accurately determined, providing accurate foundational data for subsequent calibration work. Merging several acquired coordinate positions to construct a chip coordinate matrix improves data processing efficiency and standardization. Calculating the row / column spacing between chips quantifies their positional relationships, providing crucial spacing parameters for constructing theoretical dot matrix coordinates and performing calibration. Theoretical dot matrix coordinates are calculated based on preset chip size parameters, the number of rows and columns, and the row / column spacing between chips. These coordinates represent the ideal chip distribution, providing a clear reference standard for the calibration of actual chip coordinates. Theoretical dot matrix coordinates provide an important reference standard for subsequent calibration of irregularly arranged chips.

[0017] The chip coordinate matrix is ​​divided into several first-region coordinate groups, consisting of four adjacent coordinate sets of two rows and two columns. The irregular arrangement of the chips may exhibit certain regularities or relatively stable deviation patterns within local areas; this regional division takes into account the local characteristics of the chip arrangement. Several regional transformation matrices are calculated based on the theoretical lattice coordinates and the first-region coordinate groups. Since the chip arrangement deviations may differ in different regions, calculating the transformation matrices by region can more accurately capture the coordinate transformation relationship of each region, improving the correction accuracy. Simultaneously, this approach enhances the adaptability of the correction method to different irregular arrangement conditions.

[0018] By processing the first region coordinate group using the calculated region transformation matrix, the actual chip coordinates can be adjusted to a position closer to the theoretical dot matrix coordinates, thereby achieving precise image correction. The corrected image makes the chips appear in a more regular arrangement, better conforming to the fixed-pitch array pattern adapted to conventional dot-matrix inspection algorithms. Using conventional dot-matrix inspection algorithms, defect information can be extracted more accurately according to the fixed spacing, effectively reducing over-detection and under-detection phenomena, improving the accuracy of display defect detection, thereby increasing the product yield and reducing production costs. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of an embodiment of the image correction method for the light-emitting device array in this application; Figure 2 This is a schematic diagram of an embodiment of the method for obtaining the coordinate position of a chip and constructing a chip coordinate matrix in this application; Figure 3 This is a schematic diagram of an embodiment of the method for calculating theoretical lattice coordinates in this application; Figure 4 This is a schematic diagram of an embodiment of the method for obtaining corrected images in this application; Figure 5 This is a schematic diagram of an embodiment of the method for eliminating gaps between chips in a corrected image according to this application; Figure 6 This is a schematic diagram of the structure of the image correction device for the light-emitting device array in this application; Figure 7This is a schematic diagram illustrating the missed detection phenomenon caused by the abnormal array arrangement in this application; Figure 8 This is a chip array diagram and a partial chip array diagram of the target screen in this application; Figure 9 This is a schematic diagram of obtaining the chip coordinate matrix in this application; Figure 10 This is a schematic diagram of the theoretical lattice coordinates and the first region coordinate set in this application; Figure 11 This is a schematic diagram of the first correction area before and after correction in this application; Figure 12 This is a partial schematic diagram of the corrected image and a schematic diagram of the corrected image in this application; Figure 13 This is a partial schematic diagram and a schematic diagram of the second gapless correction diagram in this application. Detailed Implementation

[0021] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0022] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0023] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0025] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not an embodiment," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0027] In the field of display technology, display technologies with arrays of light-emitting devices, such as MiniLED, MicroLED, and OLED, are gaining increasing market favor due to their unique advantages.

[0028] In the manufacturing process of these display technologies, a key and common step is to transplant a large number of light-emitting chips onto a corresponding substrate. However, in practice, regardless of the technology used, it is difficult to guarantee that each chip or pixel can be precisely transplanted to its predetermined position. This results in deviations in the spacing between chips or pixels, leading to an irregular arrangement.

[0029] Conventional LED inspection algorithms are based on early LCD / OLED arrays generated using masks with fixed periods. In these arrays, the distance between pixels is constant with almost no deviation, so the algorithm only needs to set an appropriate period to effectively highlight defects. However, when using this conventional algorithm to inspect irregularly arranged MiniLED / MicroLED / OLED light-emitting device arrays, it cannot accurately extract defect information according to the fixed spacing. Some normally functioning chips may be incorrectly identified as defects by the algorithm because their spacing from surrounding chips does not conform to the fixed pattern, resulting in over-detection; while some truly defective chips may be missed because the irregular arrangement of surrounding chips makes it difficult for the algorithm to accurately capture their abnormal features. Figure 7 As shown, Figure 7 This is a schematic diagram illustrating the missed detection phenomenon caused by abnormal display array arrangement during the detection process. Figure 7 (a) in the diagram shows that when checking the lights, the search for regular regions starts from the top left corner of the array, which causes missed detections. Figure 7(b) shows the process of checking the LEDs by searching a regular area starting from the bottom right corner of the array, verifying the complete chip layout. Figure 7 This contrasts sharply with (a) in the text. This phenomenon of over-inspection and under-inspection has a serious impact on the production and quality control of displays. Over-inspection increases unnecessary testing costs and subsequent processing workload, while under-inspection allows defective products to enter the market, reducing the product pass rate and increasing production costs.

[0030] Based on this, this application discloses a method, apparatus and storage medium for correcting an image of a light-emitting device array, which is used to convert an irregular light-emitting device array into an array image with a fixed repetition period to facilitate defect detection and improve defect detection efficiency.

[0031] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0032] The method of this application can be applied to servers, devices, terminals, or other devices with logical processing capabilities; therefore, this application does not limit its application. For ease of description, the following description uses a system as the executing entity.

[0033] Please see Figure 1 This application provides an embodiment of a method for correcting an image of a light-emitting device array, comprising the following steps: 101. Obtain a chip array diagram of the target screen, and obtain the coordinate positions and row and column numbers of several chips in the target screen based on the chip array diagram.

[0034] By using image acquisition equipment, such as a professional industrial camera, to photograph the target screen, an intuitive image of the chip distribution, i.e., a chip array diagram, can be obtained. Figure 8 As shown, Figure 8 (a) in the image is a chip array diagram of the target screen captured by the camera. Figure 8 (b) in the diagram is a partial array diagram of the chip in the chip array diagram.

[0035] The process involves acquiring a chip array image of the target screen and analyzing it using image processing algorithms (such as edge detection and feature extraction). The position of each chip is accurately identified from the chip array image, allowing the acquisition of the coordinates of several chips on the target screen. By analyzing the chip coordinates, the number of chips in the horizontal and vertical directions is counted. This can be achieved by iterating through the coordinate data according to certain rules (such as horizontal first, then vertical), determining the chip distribution and thus the number of rows and columns.

[0036] 102. Construct a chip coordinate matrix based on the coordinate positions of several chips.

[0037] Based on the coordinates of several chips obtained in step 101, these coordinates are arranged according to certain rules to construct a chip coordinate matrix. This matrix can systematically represent the position information of all chips, facilitating subsequent unified calculations and processing.

[0038] 103. Based on the coordinate positions of several chips and the preset chip size parameters, calculate the row and column spacing between the chips.

[0039] By combining preset chip size parameters (including the chip's length, width, size, and number of pixels in the image) and the coordinates of several chips, the average of the row and column spacing between multiple sets of chips is calculated to obtain the final row and column spacing between the chips. Specifically, the actual average distance between adjacent chips in the horizontal and vertical directions can be calculated using the difference in coordinates and chip size.

[0040] 104. Construct theoretical dot matrix coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips.

[0041] Based on the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacing between the chips calculated in step 103, a theoretical lattice coordinate system is constructed according to the principle of uniform distribution. The theoretical lattice coordinate system represents the ideal positional distribution of the chips, providing a reference standard for subsequent comparison and correction with the actual chip coordinates. The specific construction details are described in detail in subsequent embodiments and will not be repeated here.

[0042] 105. Divide the chip coordinate matrix into several first region coordinate groups. The first region coordinate group is a set of four coordinates in two adjacent rows and two columns.

[0043] To more accurately correct the chip coordinates, the chip coordinate matrix constructed in step 102 is divided into regions. The top left corner of the chip coordinate matrix is ​​the coordinate of the first point. Starting from the first point, the four coordinates in adjacent rows and columns are divided into sets, forming several first region coordinate groups. This division method decomposes the chip coordinates of the entire screen into multiple local regions, and performs independent correction matrix calculations for each local region. This better adapts to possible local differences in different areas of the screen and improves the accuracy of correction.

[0044] 106. Based on the theoretical lattice coordinates and several first region coordinate sets, several region transformation matrices are calculated for each region.

[0045] according to Figure 10 As shown, Figure 10 This is a schematic diagram of the theoretical lattice coordinates and the coordinate system of the first region. Figure 10 (a) in the diagram is a schematic diagram of the theoretical lattice coordinates. Figure 10 (b) in the diagram is a schematic diagram of the first region coordinate group. Because the chips in the chip array diagram are irregularly arranged, directly calculating the transformation matrix using two sets of coordinate matrices cannot unify the spacing between the chips to the same value. Therefore, a region-by-region transformation matrix is ​​used. For each first region coordinate group, its coordinates are compared and analyzed with the coordinates of the corresponding region in the theoretical lattice coordinates. A fitting algorithm is then used to calculate the transformation matrix of that region, i.e., the region transformation matrix.

[0046] The region transformation matrix describes the transformation relationship between the actual coordinates and the theoretical coordinates within each local region. Different regions may have different transformation matrices due to factors such as manufacturing processes and installation errors.

[0047] 107. Based on the region transformation matrix, process the coordinate group of the first region to obtain the corrected image.

[0048] Using the transformation matrices of each region calculated in step 105, the corresponding first region coordinate groups are processed. The coordinates in each first region coordinate group are transformed region by region according to the corresponding region transformation matrix, so that the position coordinates of these chips are adjusted to positions close to the theoretical coordinates. After processing all the first region coordinate groups, the coordinates in the entire chip coordinate matrix are corrected. Based on the corrected coordinates, an image is regenerated, resulting in a corrected image. The corrected image is a chip array diagram with a fixed, regular arrangement, formed after the transformation of an irregular MiniLED / MicroLED / OLED light-emitting device array.

[0049] In this embodiment, by acquiring a captured chip array image and extracting the chip coordinate positions and row and column numbers, the actual distribution of chips on the target screen can be accurately determined, providing accurate basic data for subsequent correction work. Merging several acquired coordinate positions to construct a chip coordinate matrix improves the efficiency and standardization of data processing. By calculating the row and column spacing between chips, the positional relationship of the chips is quantified, providing key spacing parameters for subsequent construction of theoretical dot matrix coordinates and correction. Theoretical dot matrix coordinates are calculated based on preset chip size parameters, the number of rows and columns of the chips, and the row and column spacing between the chips. These theoretical dot matrix coordinates represent the ideal positional distribution of the chips, providing a clear reference standard for the correction of actual chip coordinates. The theoretical dot matrix coordinates provide an important reference standard for subsequent correction of irregularly arranged chips.

[0050] The chip coordinate matrix is ​​divided into several first-region coordinate groups, consisting of four adjacent coordinate sets of two rows and two columns. The irregular arrangement of the chips may exhibit certain regularities or relatively stable deviation patterns within local areas; this regional division takes into account the local characteristics of the chip arrangement. Several regional transformation matrices are calculated based on the theoretical lattice coordinates and the first-region coordinate groups. Since the chip arrangement deviations may differ in different regions, calculating the transformation matrices by region can more accurately capture the coordinate transformation relationship of each region, improving the correction accuracy. Simultaneously, this approach enhances the adaptability of the correction method to different irregular arrangement conditions.

[0051] By processing the first region coordinate group using the calculated region transformation matrix, the actual chip coordinates can be adjusted to a position closer to the theoretical dot matrix coordinates, thereby achieving precise image correction. The corrected image makes the chips appear in a more regular arrangement, better conforming to the fixed-pitch array pattern adapted to conventional dot-matrix inspection algorithms. Using conventional dot-matrix inspection algorithms, defect information can be extracted more accurately according to the fixed spacing, effectively reducing over-detection and under-detection phenomena, improving the accuracy of display defect detection, thereby increasing the product yield and reducing production costs.

[0052] Please see Figure 2 This application provides an embodiment of a method for obtaining the coordinate position of a chip and constructing a chip coordinate matrix, including the following steps: 201. Obtain the number of rows and columns of chips in the chip array diagram.

[0053] 202. Set a global threshold and extract the chip region based on the global threshold.

[0054] 203. Obtain the connected components of the chip region, and filter out the valid connected components by the feature values ​​of the connected components.

[0055] 204. Obtain the coordinate positions of the chips in the valid connected domains and calculate the number of chip coordinate positions.

[0056] 205. If the difference between the number of coordinate positions and the product of the number of rows and columns is greater than the preset error value, then return to step 202.

[0057] 206. Based on the preset interval threshold and chip array diagram, sort the coordinate positions of the chips and summarize them into a chip coordinate matrix.

[0058] 207. If there are missing coordinates in the chip coordinate matrix, the missing coordinates are put into the fitting matrix, and the corresponding positions of the missing coordinates in the fitting matrix are filled with negative numbers. The missing coordinates are the coordinate positions of the chips that were not detected in the chip array diagram.

[0059] 208. Perform coordinate fitting on the fitted matrix, calculate the missing coordinates, and summarize the missing coordinates into the chip coordinate matrix.

[0060] After preprocessing the chip array image, an image edge detection algorithm is used to detect the edges of the chip array, highlighting its boundaries. Next, noise and minor edge fluctuations are removed from the edge-detected image, making the chip array boundaries clearer. Finally, by analyzing the processed image and statistically analyzing the patterns of chip arrangement in the horizontal and vertical directions, the number of rows and columns is obtained, determining the number of rows and columns of chips on the target screen.

[0061] A suitable global threshold is set, which can be determined based on the grayscale distribution range and the grayscale difference between the chip and the background. The preprocessed chip array image is then binarized using the global threshold. Morphological operations are performed on the binarized image to further remove noise and small isolated regions, making the chip region more complete and accurate.

[0062] The binarized image is processed using a connected component analysis algorithm to obtain all connected components. Feature values ​​for each connected component are calculated, such as area, perimeter, and aspect ratio. The area can be calculated by counting the number of pixels within the connected component; the perimeter can be calculated by counting the number of pixels on the boundary of the connected component; and the aspect ratio can be calculated by the length and width of the smallest bounding rectangle of the connected component.

[0063] Only connected components that meet the filtering criteria are considered valid connected components, representing potential chip regions. The filtering criteria can be set according to the actual characteristics of the chip, such as a range for area or aspect ratio. For each valid connected component, its centroid coordinates are calculated as the chip's coordinate position. The number of chip coordinate positions corresponding to all valid connected components is counted. Simultaneously, the difference between the number of chip coordinate positions and the product of the number of rows and columns is calculated.

[0064] Set a preset error value, which can be determined manually based on experience. If the calculated difference is greater than the preset error value, the detection result is considered to have a large error, and it is necessary to return to step two, reset the global threshold, and extract the chip area to optimize the detection result.

[0065] Analyze the arrangement pattern of chips in the chip array diagram to determine the spacing thresholds in the horizontal and vertical directions. This can be achieved by statistically analyzing the distances between adjacent chip coordinates and taking the average value as the spacing threshold. The chip coordinates are then sorted according to these thresholds. The sorted chip coordinates are then compiled into a matrix, i.e., the chip coordinate matrix, in row and column order. The number of rows and columns in this matrix corresponds to the number of rows and columns in the chip array diagram, respectively.

[0066] Iterate through the chip coordinate matrix, checking if each location has a corresponding chip coordinate. If a location has no coordinate, it is considered to have a missing coordinate. Create a fitting matrix of the same size as the chip coordinate matrix. Fill the fitting matrix with negative numbers for the missing coordinates; -1 can be used to represent a missing coordinate.

[0067] Based on the known chip coordinates, a coordinate fitting algorithm is used to fit the variation patterns of the chip coordinates in the horizontal and vertical directions. Using the fitted patterns, the coordinate values ​​of the missing coordinate positions are calculated. The calculated missing coordinates are then filled into the corresponding missing positions in the chip coordinate matrix. For example... Figure 9 As shown, Figure 9 A schematic diagram for obtaining the chip coordinate matrix.

[0068] In this embodiment, obtaining the number of rows and columns provides crucial reference for subsequent steps such as determining the reasonableness of the number of chip coordinates and constructing the chip coordinate matrix, ensuring the logic and accuracy of the entire process. Setting a global threshold separates the chip region from the complex background, reducing background noise interference with chip detection and improving the accuracy of chip region extraction, laying the foundation for obtaining accurate chip coordinates. Thresholding transforms the image into a binary image, simplifying its structure and features and improving processing speed.

[0069] Connected component analysis can accurately identify interconnected pixel regions in an image. Combined with feature value filtering, it can eliminate non-chip connected components, improving the accuracy of chip coordinate acquisition. Obtaining the chip's coordinate position provides crucial data for subsequent operations. Calculating the number of chip coordinate positions and comparing it with the number of rows and columns obtained in step one helps to promptly detect anomalies during the detection process. When the number of coordinates deviates significantly from the expected value, returning to step two to reset the global threshold and extract the chip region can avoid detection errors caused by improper initial threshold settings, thus improving the accuracy of the detection results.

[0070] The chip coordinates are sorted by row and column order and summarized into a matrix, giving the chip coordinates a clear spatial arrangement. By placing missing coordinates into the fitting matrix and filling them with negative numbers, the undetected chip locations in the chip array diagram can be clearly identified, providing a clear target for subsequent coordinate fitting and supplementation. The missing coordinates are calculated through coordinate fitting and summarized into the chip coordinate matrix, making the chip coordinate matrix more complete and accurate, thus ensuring a comprehensive analysis of the chips.

[0071] Please see Figure 3 This application provides an embodiment of a method for constructing theoretical lattice coordinates, comprising the following steps: 301. Calculate the theoretical resolution of the target screen based on the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacing between the chips.

[0072] 302. Based on the theoretical resolution and the preset chip size parameters, determine the range of values ​​for the theoretical dot matrix coordinates and the coordinates of the first point.

[0073] 303. Based on the coordinates of the first point and the row and column spacing between chips, the complete theoretical lattice coordinates are calculated.

[0074] According to Formula 1 below, based on the preset chip size parameters and the number of rows and columns of the chip specified in the foregoing embodiments, as well as the row and column spacing between the chips, the theoretical resolution of the target screen is calculated: Formula 1; Where Z is the theoretical resolution, W represents the number of pixels in width, H represents the number of pixels in height, Mr_X is the length of the chip, Mr_Y is the width of the chip, Dist_R is the row spacing between chips, Dist_C is the column spacing between chips, Num_R is the number of chips per row, and Num_C is the number of chips per column.

[0075] The theoretical range of pixel coordinates is [0, H*Mr_Y-1] for row coordinates, [0, W*Mr_X-1] for column coordinates, and (Mr_X / 2-1, Mr_Y / 2-1) for the first pixel. This is because resolution represents the number of pixels on the screen in the horizontal and vertical directions, and the coordinates are counted from 0 to resolution - 1.

[0076] For each chip in the chip array, the column spacing Dist_C and row spacing Dist_R are added sequentially to the coordinates of the first point to obtain several theoretical lattice coordinates corresponding to the number of rows and columns of the chip, forming a complete set of theoretical lattice coordinates.

[0077] In this embodiment, the theoretical resolution of the target screen is calculated. The result of the theoretical resolution calculation provides important basic parameters for subsequent operations. Determining the range of theoretical dot matrix coordinates and setting the coordinates of the first point provides clear boundaries for the chip, preventing coordinate calculations from exceeding the screen range and ensuring the rationality and effectiveness of the calculations. By calculating the complete theoretical dot matrix coordinates using the coordinates of the first point and the row and column spacing, an accurate theoretical dot matrix model of the chip can be constructed. The complete set of theoretical dot matrix coordinates can accurately describe the position of each chip in the target screen, providing a precise basis for chip positioning.

[0078] Please see Figure 4 This application provides an embodiment of a method for obtaining a corrected image, comprising the following steps: 401. Update the first region coordinate group to the second region coordinate group according to the preset compensation value.

[0079] 402. Based on the region transformation matrix, the coordinate group of the second region is corrected to obtain the image of the first corrected region.

[0080] 403. Based on the coordinate set of the first region, cut the first correction region image into a second correction region image.

[0081] 404. Arrange the second correction region image according to the theoretical dot matrix coordinate order to obtain the complete correction image.

[0082] The compensation value Bias is set empirically based on errors observed in similar past image processing projects, aiming to ensure overlap between adjacent regions. In practice, the compensation value is set to 10. For each coordinate point {X_per, Y_per} in the first region coordinate group, it is updated to the corresponding coordinate point {X_per±Bias, Y_per±Bias} in the second region coordinate group according to the compensation value. The same batch update is performed on all coordinate points in the first region coordinate group.

[0083] Based on the region transformation matrix calculated in the above embodiments, the second region coordinate group is corrected, and then the original image is interpolated using the corrected coordinate points to obtain the first corrected region image. Figure 11 As shown, Figure 11 This is a schematic diagram of the first correction area before and after correction.

[0084] Finally, based on the region boundaries and theoretical coordinates defined in the first region coordinate group, the first corrected region image is segmented into second corrected region images. The second decorrected region is the size of the original region image, i.e., the region size after removing the compensation value. The theoretical bitmap coordinate order is usually predetermined according to the chip array arrangement. An empty image container is created, its size determined by the total size of all the second corrected region images arranged together. Then, according to the theoretical bitmap coordinate order, each second corrected region image is placed in its corresponding position within the container to obtain the complete corrected image. Figure 12 As shown, Figure 12 This is a partial schematic diagram of the corrected image and a schematic diagram of the corrected image.

[0085] In this embodiment, updating the first region coordinate set with a preset compensation value can correct errors that may occur during image acquisition, providing a more accurate basis for subsequent image correction. Correcting the second region coordinate set based on the region transformation matrix can effectively eliminate geometric distortions in the image, such as inconsistent rotation and scaling, thereby improving image quality and usability.

[0086] The first corrected region image is segmented into a second corrected image based on the coordinates of the first region, which removes irrelevant parts of the image and improves processing efficiency. Arranging the second corrected region image according to the theoretical bitmap coordinates allows for the construction of a complete corrected image.

[0087] Please see Figure 5 This application provides an embodiment of a method for eliminating gaps between chips within a corrected image, comprising the following steps: 501. Based on the chip size parameters, eliminate the gaps between the chips in the corrected image, and generate a second theoretical coordinate matrix and a first gapless corrected image.

[0088] 502. Based on the second theoretical coordinate matrix, extract the chip grayscale value of the chip coordinate position in the first gapless correction image.

[0089] 503. Set a zero-grayscale image and fill the corresponding positions of the chip grayscale values ​​into the zero-grayscale image to generate the final second gapless correction image. The zero-grayscale image is an image with the same size as the first gapless correction image and all grayscale values ​​are 0.

[0090] Analyze the chip arrangement in the corrected image to determine the initial theoretical coordinates of each chip under ideal gapless conditions. The length and width of each chip are {Mr_X, Mr_Y}. To eliminate gaps, traverse every pixel within the range {[X', X'+Mr_X], [Y', Y'+Mr_Y]} to obtain the gapless theoretical image size with length and width {Num_R*Mr_Y, Num_C*Mr_X}.

[0091] To eliminate gaps between chips, the corrected image needs to be transformed. Image stitching and deformation methods can be used. Based on the chip size parameters and arrangement rules, the new position of each chip in a gap-free state is calculated. Then, an image interpolation algorithm is used to move the chip image to the new position, filling the gap area.

[0092] For each coordinate point in the second theoretical coordinate matrix, determine its position in the first gapless correction image. Based on the coordinate position, extract the grayscale value of the corresponding position.

[0093] A new image with all grayscale values ​​of 0 is generated according to the theoretical image size for gapless surfaces. Since the theoretical image is applicable to chips without gaps, the new image can be used to detect Mura defects. The coordinate positions in the second theoretical coordinate matrix corresponding to the first gapless corrected image are filled into the corresponding coordinate positions of the zero-grayscale image to generate the final second gapless corrected image. Figure 13 As shown, Figure 13 This is a partial schematic diagram of the second gapless correction diagram and a schematic diagram of the second gapless correction diagram.

[0094] In this embodiment, by eliminating the gaps between chips within the corrected image, the chip image becomes more compact, reducing the interference of gaps on chip feature extraction and analysis, and improving the accuracy of chip detection and recognition. The chip grayscale values ​​are filled into a zero-grayscale image to generate a second gapless corrected image, so that the image contains only the grayscale information of the chip, with a pure black background, making the image clearer and simpler, and facilitating the observation and analysis of chip features.

[0095] Please see Figure 6 This application provides an embodiment of a correction device for an image of a light-emitting device array, comprising: The acquisition unit 601 is used to acquire a chip array diagram of the target screen captured by the image, and to acquire the coordinate positions and the number of rows and columns of several chips in the target screen based on the chip array diagram. The first building unit 602 is used to build a chip coordinate matrix based on the coordinate positions of several chips; The first calculation unit 603 is used to calculate the row and column spacing between chips based on the coordinate positions of several chips and preset chip size parameters. The second building unit 604 is used to build theoretical lattice coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. Partitioning unit 605 is used to divide the chip coordinate matrix into several first region coordinate groups, where each first region coordinate group is a set of four coordinates in two adjacent rows and two columns. The second calculation unit 606 is used to calculate several regional transformation matrices by region based on the theoretical lattice coordinates and several first region coordinate groups. The processing unit 607 is used to process the first region coordinate group according to the region transformation matrix to obtain the corrected image.

[0096] Optionally, after the processing unit 607, the correction device further includes: Elimination unit 608 is used to eliminate gaps between chips in the corrected image according to the chip size parameters, and generate a second theoretical coordinate matrix and a first gapless corrected image; Extraction unit 609 is used to extract the chip grayscale value of the chip coordinate position in the first gapless correction image according to the second theoretical coordinate matrix; The filling unit 610 is used to set a zero-grayscale image and fill the corresponding positions of the chip grayscale values ​​into the zero-grayscale image to generate the final second gapless correction image. The zero-grayscale image is an image with the same size as the first gapless correction image and all grayscale values ​​are 0.

[0097] For detailed implementation methods, please refer to... Figures 1 to 5 Examples are not detailed here.

[0098] This application provides a computer-readable storage medium on which a program is stored, and when the program is executed on a computer, it performs the following... Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The method in the middle.

[0099] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0100] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0101] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0102] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0103] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for correcting an image of a light-emitting device array, characterized in that, include: Obtain a chip array diagram of the target screen captured by the image, and obtain the coordinate positions of several chips in the target screen and the number of rows and columns of the chips based on the chip array diagram; Construct a chip coordinate matrix based on the coordinate positions of several chips; The row and column spacing between the chips is calculated based on the coordinate positions of several chips and preset chip size parameters. Theoretical dot matrix coordinates are constructed based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips; The chip coordinate matrix is ​​divided into several first region coordinate groups, each first region coordinate group being a set of four coordinates in two adjacent rows and two columns. Based on the theoretical lattice coordinates and several sets of coordinates of the first region, several region transformation matrices are calculated by region. The first region coordinate group is processed according to the region transformation matrix to obtain the corrected image.

2. The correction method according to claim 1, characterized in that, The step of obtaining the coordinate positions and row and column numbers of several chips in the target screen based on the chip array diagram specifically includes: Step 1: Obtain the number of rows and columns of the chips in the chip array diagram; Step 2: Set a global threshold and extract the chip region based on the global threshold; Step 3: Obtain the connected components of the chip region, and filter out the valid connected components by the feature values ​​of the connected components; Step 4: Obtain the coordinate positions of the chips in the effective connected domain, and calculate the number of coordinate positions of the chips.

3. The correction method according to claim 2, characterized in that, The step of constructing a chip coordinate matrix based on the coordinate positions of several chips specifically includes: Based on the preset interval threshold and the chip array diagram, the coordinate positions of the chips are sorted and summarized into a chip coordinate matrix; If there are missing coordinates in the chip coordinate matrix, the missing coordinates are placed in the fitting matrix, and the corresponding positions of the missing coordinates in the fitting matrix are filled with negative numbers. The missing coordinates are the coordinate positions of the chips that were not detected in the chip array diagram. The missing coordinates are calculated by performing coordinate fitting on the fitted matrix and then summarizing the missing coordinates into the chip coordinate matrix.

4. The correction method according to claim 3, characterized in that, Following step four, the correction method further includes: Step 5: If the difference between the product of the number of coordinate positions and the number of rows and columns is greater than a preset error value, then return to Step 2.

5. The correction method according to claim 4, characterized in that, The step of constructing theoretical dot matrix coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips specifically includes: The theoretical resolution of the target screen is calculated based on the preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. Based on the theoretical resolution and the preset chip size parameters, determine the range of values ​​for the theoretical dot matrix coordinates and the coordinates of the first point; The complete theoretical matrix coordinates are calculated based on the coordinates of the first point and the row and column spacing between the chips.

6. The correction method according to claim 5, characterized in that, The step of calculating the theoretical resolution of the target screen based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips specifically includes: The theoretical resolution of the target screen is calculated according to the following formula 1: Formula 1: Where Z is the theoretical resolution, W represents the number of pixels in width, H represents the number of pixels in height, Mr_X is the length of the chip, Mr_Y is the width of the chip, Dist_R is the row spacing between the chips, Dist_C is the column spacing between the chips, Num_R is the number of chips per row, and Num_C is the number of chips per column.

7. The correction method according to claim 1, characterized in that, The step of processing the first region coordinate group according to the region transformation matrix to obtain the corrected image specifically includes: Based on the preset compensation value, the first region coordinate group is updated to the second region coordinate group; The second region coordinate group is corrected according to the region transformation matrix to obtain the first corrected region image; Based on the first region coordinate set, the first correction region image is segmented to obtain the second correction region image; The second correction region image is sorted and merged according to the theoretical dot matrix coordinates to obtain a complete correction image.

8. The correction method according to any one of claims 1 to 7, characterized in that, After the step of processing the first region coordinate group according to the region transformation matrix to obtain the corrected image, the correction method further includes: Based on the chip size parameters, the gaps between the chips in the corrected image are eliminated, and a second theoretical coordinate matrix and a first gapless corrected image are generated; Based on the second theoretical coordinate matrix, extract the chip grayscale value of the chip's coordinate position in the first gapless correction image; Set a zero-grayscale image and fill the corresponding positions of the chip grayscale values ​​into the zero-grayscale image to generate the final second gapless correction image. The zero-grayscale image is an image with the same size as the first gapless correction image and all grayscale values ​​are 0.

9. A correction device for an image of a light-emitting device array, characterized in that, include: The acquisition unit is used to acquire a chip array diagram of the target screen captured by the image, and to acquire the coordinate positions and the number of rows and columns of several chips in the target screen based on the chip array diagram. The first construction unit is used to construct a chip coordinate matrix based on the coordinate positions of the chips. The first calculation unit is used to calculate the row and column spacing between the chips based on the coordinate positions of the chips and preset chip size parameters. The second construction unit is used to construct theoretical lattice coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. A partitioning unit is used to divide the chip coordinate matrix into several first region coordinate groups, wherein the first region coordinate group is a set of four coordinates in two adjacent rows and two columns. The second calculation unit is used to calculate several regional transformation matrices by region based on the theoretical lattice coordinates and several sets of first region coordinates. The processing unit is used to process the first region coordinate group according to the region transformation matrix to obtain the corrected image.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains a program that, when executed on a computer, performs the correction method as described in any one of claims 1 to 8.

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