Analog demultiplexing circuit integrated with decision feedback equalization function

Abstract

The invention discloses an analog demultiplexing circuit integrated with a decision feedback equalization function, and relates to the field of high-speed analog integrated circuit design. The circuit comprises an input summation circuit, at least two parallel tracking and holding amplifier circuits controlled by alternating clocks, and an analog feedback path. The analog feedback path is direct conductive connection without a decision device, feeds back a soft decision signal output by the tracking and holding amplifier, and inputs the soft decision signal into the summing circuit for subtraction to eliminate interference between previous numbers; and a feed-through counteracting path containing a compensation transistor is arranged in the tracking and holding amplifier to counteract noise feed-through. The receiving system comprises the analog demultiplexing circuit and two half-rate decision devices, and a three-tap decision feedback equalizer is arranged in each decision device. According to the invention, the ultra-high-speed time sequence bottleneck is solved, the complexity and power consumption are reduced, the signal quality is improved, the rate of 112 Gb / s and above is adapted, and the reliability of a receiver is ensured.

Description

Technical Field

[0001] This invention belongs to the field of high-speed analog integrated circuit design technology, specifically relating to an analog demultiplexing circuit with integrated decision feedback equalization function. Background Technology

[0002] With the rapid development of applications such as data centers, artificial intelligence, and 5G communications, the data transmission rate of wired communication systems is evolving towards ultra-high speeds of 112Gb / s and even 200Gb / s or more per channel. At such high speeds, signals suffer severe loss and distortion when passing through transmission channels such as backplanes and cables, resulting in significant inter-symbol interference (ISI), which seriously affects the reliability of data transmission.

[0003] To compensate for channel loss and eliminate inter-symbol interference (ISI), the decision feedback equalizer (DFE) is a key technology widely used in high-speed receivers. The DFE effectively eliminates post-cursor ISI without amplifying noise. Among them, the first-tap DFE, used to eliminate the main interference caused by the previous data symbol, has the most stringent timing requirements for its feedback loop, such as... Figure 1 As shown, this loop requires the signal to complete a full closed-loop process—signal decision, feedback path transmission, and summation at the input—within one unit clock cycle (UI). At a rate of 112 Gb / s, one UI is only about 8.9 picoseconds (ps), which poses a significant challenge to traditional DFE architectures. This is because the core decision unit (Slicer) in the circuit itself has a delay of several picoseconds, making it difficult to close the timing of the entire feedback loop, thus constituting a core technical bottleneck in the design of ultra-high-speed receivers.

[0004] To circumvent this stringent timing bottleneck, existing technologies have proposed several solutions, such as loop-unrolling or speculative DFE architectures. These solutions bypass the tight timing loop by processing multiple data paths in parallel and pre-calculating all possible feedback results. However, the cost of such solutions is a sharp increase in circuit complexity, power consumption, and chip area. For example, the loop-unrolling architecture requires multiple sets of parallel decision units and selection logic for each post-tap, which is not ideal for power- and cost-sensitive modern communication systems. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an analog demultiplexing circuit with integrated decision feedback equalization function to address the shortcomings of the prior art, thereby solving the technical problem that the timing of the first tap feedback loop of the DFE is difficult to close at ultra-high speeds.

[0006] The present invention adopts the following technical solution: An analog demultiplexing circuit with integrated decision feedback equalization function includes: An input summing circuit has a signal input terminal, a feedback input terminal, and a summing output terminal. The signal input terminal is used to receive a high-speed serial data signal, the feedback input terminal is used to receive a feedback signal, and the input summing circuit is used to process the high-speed serial data signal and the feedback signal. At least two track-and-hold amplifier circuits are connected in parallel and controlled by an alternating clock signal. The input of each track-and-hold amplifier circuit is connected to the summation output of the input summation circuit for sampling and holding the signal output by the input summation circuit. An analog feedback path is provided, wherein the input of the analog feedback path is connected to the output of one of the at least two track-and-hold amplifier circuits, and the output of the analog feedback path is connected to the feedback input of the input summing circuit. This is used to feed back the signal output by the track-and-hold amplifier circuit to the input summing circuit, so as to subtract the inter-symbol interference caused by the previous data symbol from the high-speed serial data signal in the analog domain, thereby achieving the first tap decision feedback equalization for the next data symbol.

[0007] Preferably, the analog feedback path is a direct conductive connection without a decision circuit. The direct conductive connection is used to directly feed back the analog voltage signal output by the track-and-hold amplifier circuit to the input summing circuit, and the analog voltage signal serves as a soft decision signal for the previous data symbol.

[0008] Preferably, each of the tracking and holding amplifier circuits includes a sampling switch, a holding capacitor, and an output buffer; the sampling switch is used to control the tracking and holding amplifier circuit to switch between tracking mode and holding mode; the holding capacitor is used to store the sampled analog voltage signal in holding mode; the output buffer is used to buffer the analog voltage signal stored in the holding capacitor and then output it; the analog feedback path feeds back the analog voltage signal stored in the holding capacitor.

[0009] Preferably, the tracking and holding amplifier circuit further includes a feedthrough cancellation path, which includes a compensation path for generating a compensation signal. The compensation signal can cancel the noise feedthrough generated by the clock signal or input signal through the parasitic capacitance inside the tracking and holding amplifier circuit.

[0010] Preferably, the at least two track-and-hold amplifier circuits include a first track-and-hold amplifier circuit and a second track-and-hold amplifier circuit; the compensation path of the feedthrough cancellation path has its input connected to the output of the second track-and-hold amplifier circuit and its output coupled to an internal node of the first track-and-hold amplifier circuit, for canceling the cross-feedthrough noise generated by the output signal of the second track-and-hold amplifier circuit in the first track-and-hold amplifier circuit.

[0011] Preferably, the feedthrough cancellation path further includes a compensation transistor, which is matched with the parasitic capacitance characteristics of the noise feedthrough generated inside the tracking and holding amplifier circuit, and the compensation signal is coupled to the internal node of the first tracking and holding amplifier circuit through the compensation transistor.

[0012] Preferably, the alternating clock signal is a half-rate clock signal, including a CKP clock signal and a CKN clock signal. One of the at least two track-and-hold amplifier circuits is controlled by the CKP clock signal, and the other track-and-hold amplifier circuit is controlled by the CKN clock signal, so as to realize alternating sampling of the output signal of the input summing circuit.

[0013] Preferably, the input summing circuit processes the high-speed serial data signal and the feedback signal by a subtraction operation, that is, subtracting the inter-symbol interference signal represented by the feedback signal from the high-speed serial data signal. The inter-symbol interference signal is generated by the previous data symbol.

[0014] Preferably, the high-speed serial data signal is a signal after high-frequency compensation by a continuous-time linear equalizer, and the analog demultiplexing circuit is used to perform 1:2 demultiplexing processing on the high-speed serial data signal after high-frequency compensation.

[0015] Another technical solution of the present invention is a high-speed signal receiving system, comprising: The analog demultiplexing circuit with integrated decision feedback equalization function; At least one half-rate decision unit is provided, which is located after the analog demultiplexing circuit and is used to make digital decisions on the signal after equalization and demultiplexing by the analog demultiplexing circuit to obtain a digital signal. The half-rate decision unit is equipped with a multi-tap decision feedback equalizer circuit. The multi-tap decision feedback equalizer circuit is used to eliminate the remaining post-cursor code interference in the signal after equalization and demultiplexing by the analog demultiplexing circuit. The multi-tap decision feedback equalizer circuit is a 3-tap direct feedback type decision feedback equalizer circuit. The analog demultiplexing circuit outputs two half-rate analog signals. The at least one half-rate decision unit includes two half-rate decision units. The two half-rate decision units respectively receive the two half-rate analog signals and each makes a digital decision on the received half-rate analog signals.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: An analog demultiplexing circuit with integrated decision feedback equalization is presented. The core architecture of this circuit includes an input summing circuit, at least two parallel track-and-hold amplifier circuits controlled by alternating clocks, and an analog feedback path. The input summing circuit receives and processes high-speed serial data and feedback signals. The track-and-hold amplifiers sample and hold the processed signal, and the analog feedback path provides signal feedback to eliminate inter-symbol interference. Through a closed-loop design of summation-sample-and-hold-feedback, first-tap decision feedback equalization is achieved in the analog domain, eliminating the need for complex digital processing modules and fundamentally avoiding the timing bottleneck caused by decision delays in traditional architectures. This allows for processing of ultra-high-speed signals of 112Gb / s and above. Simultaneously, the parallel connection and alternating clock control of at least two track-and-hold amplifiers enables demultiplexing of high-speed signals, balancing equalization and demultiplexing functions, reducing the number of circuit modules, lowering system integration complexity, and laying the foundation for miniaturization of ultra-high-speed receivers.

[0017] Furthermore, the soft-decision signal retains the continuous amplitude information of the analog sampled values, and the feedback is direct without the need for quantization processing by the decision maker. Firstly, it eliminates the decision maker, completely removing the picosecond delay, so that the total feedback loop delay consists only of the TAH setup time and the summing circuit delay. This easily meets the timing closed-loop requirements at 112Gb / s, solving the timing bottleneck at ultra-high speeds. Secondly, the soft-decision signal retains more signal details, and compared to the hard-decision signal, it more accurately reflects the inter-symbol interference characteristics of the previous data symbol. The input summing circuit subtracts interference with higher accuracy, effectively improving the equalization effect, enhancing signal quality, and providing a better input signal for subsequent circuits.

[0018] Furthermore, the sampling switch control circuit switches between tracking and hold modes. In tracking mode, the output follows the input, while in hold mode, the sampled voltage is stored in a hold capacitor, and the output buffer ensures stable signal output. The mode switching function of the sampling switch, combined with an alternating clock, enables two TAH circuits to sample alternately, ensuring uninterrupted processing of high-speed signals and improving signal sampling continuity. The hold capacitor directly stores the analog sampled voltage, and the feedback voltage signal can retain the original sampled information to the greatest extent, avoiding distortion during signal transmission and improving the accuracy of the feedback signal. The output buffer can enhance the signal driving capability, reduce signal attenuation in the transmission to subsequent circuits or the feedback path, ensure signal integrity, and improve the overall stability of the circuit.

[0019] Furthermore, clock or input signals in the circuit can generate noise feedthrough through parasitic capacitance coupling. The compensation path generates a reverse compensation signal to cancel this noise. Noise feedthrough can interfere with the sampling voltage stored in the holding capacitor, leading to a decrease in sampling accuracy. The compensation signal can effectively suppress this interference, significantly improve the sampling accuracy of the track-and-hold amplifier, and ensure the signal quality fed back to the input summing circuit. Reducing the impact of noise feedthrough on the signal improves the signal-to-noise ratio of the circuit output signal, providing a cleaner signal for subsequent equalization processing and digital decision-making, reducing the system bit error rate, and improving the overall communication reliability of the receiver. This optimization is especially crucial for ensuring signal quality at ultra-high speeds.

[0020] Furthermore, when the two TAH circuits operate in parallel, the output signal of the second TAH will generate cross-feedthrough noise to the first TAH through parasitic capacitance. The compensation path generates a targeted cancellation signal to specifically solve the cross-interference problem when multiple TAH circuits operate in parallel. Compared with general feedthrough cancellation, this design is more accurate and has a better effect on canceling cross-feedthrough noise, avoiding distortion of the first TAH sampling signal due to cross-interference. It ensures that the two TAH circuits operate independently and stably, ensuring the accuracy and continuity of alternating sampling, and improving the working stability of the entire analog demultiplexing circuit. Especially when processing ultra-high-speed signals, it can reduce the impact of internal circuit interference on signal processing accuracy and further optimize the equalization and demultiplexing effects.

[0021] Furthermore, the characteristics of the compensation transistor are matched with the parasitic capacitance that generates the noise feedthrough, enabling the precise generation of a compensation signal with an amplitude comparable to but opposite in phase to the noise feedthrough. The matching characteristics of the compensation transistor ensure that the compensation signal and the noise feedthrough signal are highly compatible in parameters, achieving more thorough noise cancellation. Compared with mismatched compensation components, the cancellation accuracy is significantly improved, minimizing the impact of the noise feedthrough on the internal node signal of the first TAH. The introduction of the compensation transistor makes the feedthrough cancellation path structure more compact and easier to integrate into the TAH circuit without requiring a large amount of additional chip area, meeting the design requirements of miniaturization and high integration of ultra-high-speed integrated circuits, while reducing circuit design complexity.

[0022] Furthermore, the half-rate clock frequency is half the high-speed signal rate. The CKP and CKN clock phases alternate, driving the two TAH circuits to sample alternately. Compared with the full-rate clock, the half-rate clock has lower timing requirements for the circuit, reduces the difficulty of clock signal generation and transmission, reduces the impact of clock jitter on circuit operation, and improves circuit stability. The two TAH circuits sample alternately under the control of CKP and CKN, which can decompose one high-speed serial signal into two half-rate signals, realize 1:2 demultiplexing, reduce the processing rate of each signal, make it easier for subsequent circuits to process the signal, and at the same time ensure the overall processing efficiency of high-speed signals, balancing high speed and ease of implementation.

[0023] Furthermore, the feedback signal represents the inter-symbol interference generated by the previous data symbol, and the summing circuit directly eliminates this interference through subtraction. The advantage is that the subtraction operation directly targets the source of the inter-symbol interference, efficiently removing the influence of the previous data symbol on the current data symbol. Compared to other complex interference cancellation algorithms, this method is simple and direct, with low processing latency, and adapts to the real-time processing requirements of ultra-high-speed signals. It accurately eliminates the main inter-symbol interference, significantly improves the signal quality of the current data symbol, increases the signal eye diagram opening, and allows the subsequent decision unit to make more accurate digital decisions, reducing the bit error rate and improving the transmission reliability of the entire communication system.

[0024] Furthermore, CTLE can compensate for high-frequency loss in high-speed signal transmission. The analog demultiplexing circuit decomposes the high-speed signal into two low-speed signals through alternating sampling by two TAHs. CTLE's high-frequency compensation can repair the high-frequency attenuation of the signal caused by channel transmission, making the signal input to the analog demultiplexing circuit closer to the original signal, laying a good foundation for subsequent equalization processing and improving the overall equalization effect. 1:2 demultiplexing reduces the high-speed signal rate by half, significantly reducing the operating rate requirements of subsequent half-rate decision circuits, reducing the design difficulty and power consumption of subsequent circuits, while ensuring that the total signal transmission rate is not affected, achieving a balance between high-speed transmission and low-complexity design.

[0025] A high-speed signal receiving system includes the aforementioned analog demultiplexing circuit and two half-rate decision units. Each decision unit incorporates a 3-tap direct feedback DFE. The analog demultiplexing circuit performs first-tap equalization and demultiplexing, while the half-rate decision units make digital decisions on the signal. The internal 3-tap DFE eliminates residual post-signal inter-symbol interference. The system-level design integrates equalization, demultiplexing, and digital decision functions, forming a complete signal receiving and processing link. This eliminates the need for multiple external independent modules, improving system integration and reducing signal transmission loss between modules. The analog demultiplexing circuit eliminates the main inter-symbol interference, and the internal 3-tap DFE of the half-rate decision units further eliminates residual interference. This dual equalization processing significantly improves signal quality and reduces the bit error rate. The two half-rate decision units process two half-rate signals respectively, working in parallel to improve signal processing efficiency, adapting to ultra-high-speed signal reception requirements, and ensuring stable and reliable operation of the system at speeds of 112 Gb / s and above.

[0026] In summary, this invention removes decision delay by using soft-decision analog feedback, thus solving the timing bottleneck at ultra-high speeds; integrates equalization and demultiplexing functions to reduce power consumption, area, and complexity; incorporates a feedthrough cancellation path to improve sampling accuracy; and employs system-level dual equalization to reduce bit error rate, adapting to 112Gb / s+ rates and ensuring receiver performance and robustness.

[0027] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the following description of the relative embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of an existing high-speed receiver architecture that uses a loop-deployed DFE. Figure 2 This is a system architecture block diagram of the analog demultiplexing circuit integrating the first tap DFE function of the present invention; Figure 3 The detailed circuit diagram of the Track-Hold Amplifier (TAH) circuit of the present invention shows its internal feedthrough cancellation path; Figure 4 The timing diagram for the simulated demultiplexing circuit of this invention illustrates the principles of soft decision feedback and feedthrough cancellation. Figure 5 The results are simulated eye diagrams of the present invention under a 133Gb / s PAM4 signal, where (a) is the eye diagram before equalization and (b) is the eye diagram after equalization using the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0034] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0035] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] Terminology Explanation: A-DMUX: Analog Demultiplexer, used to decompose a single high-speed analog signal into multiple low-speed analog signals.

[0038] DFE: Decision Feedback Equalizer, an equalization technique used to eliminate post-cursor ISI.

[0039] TAH: Track-and-Hold Amplifier, a circuit unit that can output a signal that follows the input signal in "track" mode and hold the sampled value from the previous moment in "hold" mode.

[0040] Soft decision: refers to analog sampled values ​​that have not been processed by a quantizer (such as a decision quantizer / slicer), thus preserving continuous amplitude information.

[0041] Hard Decision: refers to the discrete digital value after being processed by a quantizer.

[0042] Feedthrough: refers to the non-ideal effect where, in a circuit switching or isolation state, the input signal is coupled to the output through paths such as parasitic capacitance.

[0043] A summer is a circuit used to add multiple signals (current or voltage).

[0044] Gm unit: Transconductance unit, a circuit that converts voltage signals into current signals.

[0045] This invention provides an analog demultiplexing circuit with integrated decision feedback equalization function.

[0046] Please see Figure 2 This invention discloses an analog demultiplexing circuit with integrated decision feedback equalization function, applicable to ultra-high-speed signal receivers, such as those processing 112Gb / s PAM4 signals. The circuit mainly comprises an input summing circuit (composed of S1 and S2) and two parallel track-and-hold amplifier circuits, TAH1 and TAH2. This circuit can be implemented using a 28nm CMOS process and is used to perform 1:2 demultiplexing of the signal and elimination of first tap inter-code interference at the receiver front end.

[0047] The circuit module of this invention includes an input summing circuit, two track-and-hold amplifiers TAH1 and TAH2, and an analog feedback path connected between the output of TAH and the input of the summing circuit. One end of the input summing circuit receives the equalized high-speed serial signal DIN from the front-end CTLE, and the other end receives the analog feedback signal from the output of TAH, used to subtract the two signals. The inputs of TAH1 and TAH2 are both connected to the output of the summing circuit and are controlled by a pair of half-rate alternating clock signals (CKP / CKN) to alternately sample and hold the summed signal.

[0048] In this circuit, the analog output signal of the TAH circuit is directly used as the "soft decision" signal and sent back to the input summing circuit through the analog feedback path. When TAH1 samples the current data symbol D0 and enters hold mode, its output analog voltage signal DO is sent to the summing circuit S2 through the feedback path. Before TAH2 samples the next data symbol D1, the summing circuit S2 subtracts the inter-symbol interference caused by D0 from the input signal. Similarly, after TAH2 completes sampling D1, its output analog voltage signal DE is also fed back to the summing circuit S1 to eliminate interference to the subsequent symbol D2.

[0049] The working principle of this feedback loop is as follows: Figure 4 As shown, the timing closed loop of the entire feedback loop Tloop no longer includes a high-latency decision circuit. The total loop delay consists only of the setup time Tck2q of the TAH circuit and the delay TDFE,sum of the summing circuit. In this embodiment, by optimizing the circuit design and increasing the power supply voltage of the TAH to 1.2V, the delay of Tck2q can be controlled within 9.6ps, and the delay of TDFE,sum is approximately 1.8ps. The total loop delay is much smaller than the UI of a 112Gb / s signal (approximately 8.9ps), thus fundamentally solving the timing bottleneck of the traditional DFE architecture.

[0050] like Figure 3As shown, the TAH circuit in this embodiment also includes an internal feedthrough cancellation path to improve signal sampling accuracy. This cancellation path includes a pair of compensation transistors MN12 and MN13. In the hold mode of the TAH circuit, the input signal generates noise feedthrough to the hold capacitor CH through the gate-source parasitic capacitance (Cgs) of the input transistors MN3 / MN4, affecting the accuracy of the sampled voltage. The feedthrough cancellation path precisely cancels this noise feedthrough by introducing compensation transistors MN12 / MN13 that match the characteristics of the feedthrough path and coupling an inverted compensation signal to the output node.

[0051] In this embodiment, the A-DMUX module integrating DFE functionality is followed by two half-rate decision slicers. These two slicers receive the two half-rate analog signals DE and DO from the A-DMUX output, respectively, and perform the final digital decision. Furthermore, each half-rate decision slicer can also integrate a 3-tap direct feedback DFE to eliminate residual inter-symbol interference caused by more distant back-cursors (such as the second, third, and fourth taps), thereby further improving the overall equalization capability of the receiver.

[0052] The overall workflow of the analog demultiplexing circuit with integrated decision feedback equalization function of the present invention is as follows: A 112Gb / s high-speed serial signal DIN, after high-frequency compensation by CTLE, enters the A-DMUX module of this invention; The summing circuit in the A-DMUX module first subtracts the inter-symbol interference generated by the previous symbol, and then TAH1 and TAH2 sample alternately to output two 56Gb / s half-rate analog signals DE and DO, which are equalized by the first tap. These two signals are fed into the subsequent half-rate decision unit for final digital decision and elimination of residual ISI. On the other hand, the analog values ​​of these two signals are sent back to the input summing circuit in real time through the analog feedback path for equalization of subsequent input signals.

[0053] A high-speed signal receiving system, comprising: The analog demultiplexing circuit with integrated decision feedback equalization function; At least one half-rate decision unit is provided, which is located after the analog demultiplexing circuit and is used to make digital decisions on the signal after equalization and demultiplexing by the analog demultiplexing circuit to obtain a digital signal. The half-rate decision unit is equipped with a multi-tap decision feedback equalizer circuit. The multi-tap decision feedback equalizer circuit is used to eliminate the remaining post-cursor code interference in the signal after equalization and demultiplexing by the analog demultiplexing circuit. The multi-tap decision feedback equalizer circuit is a 3-tap direct feedback type decision feedback equalizer circuit. The analog demultiplexing circuit outputs two half-rate analog signals. The at least one half-rate decision unit includes two half-rate decision units. The two half-rate decision units respectively receive the two half-rate analog signals and each makes a digital decision on the received half-rate analog signals.

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0055] This invention proposes an innovative architecture that deeply integrates analog demultiplexing with the first tap DFE function. By utilizing the analog sampling output of the TAH as a soft-decision signal for direct feedback, a key timing bottleneck in ultra-high-speed signal processing is solved without introducing an additional decision unit. Simulation analysis was conducted to verify the effectiveness of this technical approach.

[0056] Please see Figure 5 (a) and Figure 5 (b) When a 66.5 Gb / s PAM4 signal is input through a high-loss channel, the eye diagram before equalization is completely closed due to severe inter-symbol interference. After applying the technical solution of this embodiment, the eye diagram of the output signal is clearly opened, and the eye height is significantly improved, proving that the present invention can effectively eliminate inter-symbol interference of the first tap. This architecture not only solves the timing problem, but also takes into account the design requirements of low power consumption and low complexity, providing an efficient and feasible technical path for realizing wired communication receivers with higher data rates.

[0057] In summary, this invention presents an analog demultiplexing circuit integrating decision feedback equalization. Through an innovative soft-decision analog feedback mechanism, it removes the high-latency decision unit from the critical first-tap feedback loop, fundamentally solving the timing bottleneck problem at ultra-high data rates. This enables the DFE to operate reliably at data rates of 112Gb / s and even higher. Simultaneously, this design highly integrates demultiplexing and equalization functions, significantly reducing power consumption, chip area, and design complexity compared to complex schemes such as loop unrolling in existing technologies. Furthermore, by eliminating major inter-symbol interference in the analog domain in advance, it provides higher-quality signals for subsequent circuits, effectively improving the overall bit error rate of the system and enhancing the receiver's performance and robustness.

[0058] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. An analog demultiplexing circuit with integrated decision feedback equalization function, characterized in that, include: An input summing circuit has a signal input terminal, a feedback input terminal, and a summing output terminal. The signal input terminal is used to receive a high-speed serial data signal, the feedback input terminal is used to receive a feedback signal, and the input summing circuit is used to process the high-speed serial data signal and the feedback signal. At least two track-and-hold amplifier circuits are connected in parallel and controlled by an alternating clock signal. The input of each track-and-hold amplifier circuit is connected to the summation output of the input summation circuit for sampling and holding the signal output by the input summation circuit. An analog feedback path is provided, wherein the input of the analog feedback path is connected to the output of one of the at least two track-and-hold amplifier circuits, and the output of the analog feedback path is connected to the feedback input of the input summing circuit. This is used to feed back the signal output by the track-and-hold amplifier circuit to the input summing circuit, so as to subtract the inter-symbol interference caused by the previous data symbol from the high-speed serial data signal in the analog domain, thereby achieving the first tap decision feedback equalization for the next data symbol.

2. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 1, characterized in that, The analog feedback path is a direct conductive connection without a decision circuit. The direct conductive connection is used to directly feed back the analog voltage signal output by the track-and-hold amplifier circuit to the input summing circuit. This analog voltage signal serves as a soft decision signal for the previous data symbol.

3. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 1, characterized in that, Each of the tracking and holding amplifier circuits includes a sampling switch, a holding capacitor, and an output buffer; the sampling switch is used to control the tracking and holding amplifier circuit to switch between tracking mode and holding mode, the holding capacitor is used to store the sampled analog voltage signal in holding mode, and the output buffer is used to buffer the analog voltage signal stored in the holding capacitor before outputting it. The analog feedback path feeds back the analog voltage signal stored on the holding capacitor.

4. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 3, characterized in that, The tracking and holding amplifier circuit also has a feedthrough cancellation path, which includes a compensation path. The compensation path is used to generate a compensation signal, which can cancel the noise feedthrough generated by the clock signal or input signal through the parasitic capacitance inside the tracking and holding amplifier circuit.

5. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 4, characterized in that, The at least two track-and-hold amplifier circuits include a first track-and-hold amplifier circuit and a second track-and-hold amplifier circuit; the compensation path of the feedthrough cancellation path has its input connected to the output of the second track-and-hold amplifier circuit and its output coupled to an internal node of the first track-and-hold amplifier circuit, for canceling the cross-feedthrough noise generated by the output signal of the second track-and-hold amplifier circuit in the first track-and-hold amplifier circuit.

6. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 5, characterized in that, The feedthrough cancellation path also includes a compensation transistor, which is matched with the parasitic capacitance characteristics of the noise feedthrough generated inside the tracking and holding amplifier circuit. The compensation signal is coupled to an internal node of the first tracking and holding amplifier circuit through the compensation transistor.

7. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 1, characterized in that, The alternating clock signal is a half-rate clock signal, including a CKP clock signal and a CKN clock signal. One of the at least two track-and-hold amplifier circuits is controlled by the CKP clock signal, and the other track-and-hold amplifier circuit is controlled by the CKN clock signal, so as to realize alternating sampling of the output signal of the input summing circuit.

8. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 1, characterized in that, The input summing circuit processes the high-speed serial data signal and the feedback signal by subtraction, that is, it subtracts the inter-symbol interference signal represented by the feedback signal from the high-speed serial data signal. The inter-symbol interference signal is generated by the previous data symbol.

9. The analog demultiplexing circuit with integrated decision feedback equalization function according to claim 1, characterized in that, The high-speed serial data signal is a signal after high-frequency compensation by a continuous-time linear equalizer. The analog demultiplexing circuit is used to perform 1:2 demultiplexing processing on the high-speed serial data signal after high-frequency compensation.

10. A high-speed signal receiving system, characterized in that, include: The analog demultiplexing circuit with integrated decision feedback equalization function as described in any one of claims 1-9; At least one half-rate decision unit is provided, which is located after the analog demultiplexing circuit and is used to make digital decisions on the signal after equalization and demultiplexing by the analog demultiplexing circuit to obtain a digital signal. The half-rate decision unit is equipped with a multi-tap decision feedback equalizer circuit. The multi-tap decision feedback equalizer circuit is used to eliminate the remaining post-cursor code interference in the signal after equalization and demultiplexing by the analog demultiplexing circuit. The multi-tap decision feedback equalizer circuit is a 3-tap direct feedback type decision feedback equalizer circuit. The analog demultiplexing circuit outputs two half-rate analog signals. The at least one half-rate decision unit includes two half-rate decision units. The two half-rate decision units respectively receive the two half-rate analog signals and each makes a digital decision on the received half-rate analog signals.

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