Semiconductor structure and method of forming the same
By introducing a first barrier layer and a second barrier layer into the superjunction device, multiple contact sections are formed, which solves the problem of the inability to turn off due to excessive two-dimensional electron gas intensity, improves current density and withstand voltage performance, reduces process difficulty and cost, and achieves more efficient device manufacturing.
Patent Information
- Application Number
- CN202511408373.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-28
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2045-09-28
AI Technical Summary
Existing superjunction devices in gallium nitride structures suffer from the problem of excessively high two-dimensional electron gas intensity that cannot be completely consumed, leading to the inability to turn off. Furthermore, they are difficult to manufacture, costly, and have limited current density, making it impossible to effectively utilize the overall space size of gallium nitride devices.
A first barrier layer and a second barrier layer are introduced into each cell structure to form multiple contact sections between gallium nitride layers and barrier layers, providing transport channels for two-dimensional electron gas and two-dimensional hole gas, and allowing the barrier layer thickness to be appropriately increased. Multiple cell units are combined in parallel to make full use of the space in the horizontal and vertical directions.
It significantly improves the total current density of the device, optimizes electrical performance, reduces the difficulty of process control, improves production efficiency, achieves higher withstand voltage and current path capability, and reduces manufacturing costs.
Smart Images
Figure CN121194483B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] In the field of power semiconductors, as electronic devices continue to demand higher power conversion efficiency, switching speed and withstand voltage, traditional power devices have gradually revealed some limitations, which has provided a background for the birth and development of superjunction devices.
[0003] In high-voltage applications, traditional power MOSFETs (metal-oxide-semiconductor field-effect transistors) typically require a thick drift region to achieve withstand voltage performance. This results in a high on-resistance, which in turn increases power consumption in the on-state and affects overall energy efficiency. Superjunction devices, however, cleverly solve this problem through a unique structural design.
[0004] The fundamental idea behind superjunction devices stems from the optimization of electric field distribution in traditional power devices. In traditional structures, the high breakdown voltage requirement causes the electric field to concentrate mainly near the device surface, easily leading to breakdown. Superjunction devices, by forming alternating P-type and N-type columnar regions inside the device, allow these regions to interact in the blocking state, enabling a uniform electric field distribution and effectively extending the depletion layer. This, in turn, significantly reduces the drift region thickness and lowers the on-resistance while maintaining high breakdown voltage.
[0005] However, existing superjunction devices still have many problems. Summary of the Invention
[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve device structure performance, reduce process difficulty and increase production efficiency.
[0007] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a plurality of adjacent cell units arranged along a first direction, each cell unit comprising: a gallium nitride layer having opposing first and second sides; a first barrier layer and a second barrier layer separated from each other within the gallium nitride layer, the first barrier layer and the second barrier layer penetrating the gallium nitride layer from the first side to the second side; a modulated gallium nitride layer located on the first side, the modulated gallium nitride layer being doped with p-type ions, the modulated gallium nitride layer being located on the gallium nitride layer between the first barrier layer and the second barrier layer; and a gate electrode located on the first side. The first side comprises a gate electrode electrically connected to the modulated gallium nitride layer; source electrodes located on both sides of the gate electrode, wherein one source electrode is electrically connected to the gallium nitride layer on the side of the first barrier layer away from the second barrier layer, and the other source electrode is electrically connected to the gallium nitride layer on the side of the second barrier layer away from the first barrier layer; a metal layer located on the second side, the metal layer covering the surface of the gallium nitride layer on the second side; and a drain electrode located on the second side, the metal layer being located between the gallium nitride layer and the drain electrode, the drain electrode being electrically connected to the metal layer.
[0008] Optionally, adjacent cell units may share the source electrode.
[0009] Optionally, the metal layer covers the surface of all the cell units where the gallium nitride layer is located on the second side.
[0010] Optionally, all the cell units share one drain electrode.
[0011] Optionally, it further includes: a first conductive plug, wherein the gate electrode is electrically connected to the modulated gallium nitride layer through the first conductive plug; and a second conductive plug, wherein the source electrode is electrically connected to the gallium nitride layer through the second conductive plug.
[0012] Optionally, it further includes: a dielectric layer located on the first side, the dielectric layer being located on the gallium nitride layer and covering the modulated gallium nitride layer, and the first conductive plug and the second conductive plug being located within the dielectric layer.
[0013] Optionally, the materials of the first barrier layer and the second barrier layer include aluminum gallium nitride.
[0014] Optionally, along the first direction, the width of the first barrier layer and the second barrier layer is greater than 25 nanometers.
[0015] Optionally, the P-type ions include magnesium ions, zinc ions, or fluoride ions.
[0016] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a gallium nitride layer on the substrate, the gallium nitride layer having a first side and a second side opposite to each other, the substrate being located on the second side, the gallium nitride layer comprising a plurality of cell regions arranged along a first direction and adjacent to each other; forming a first barrier layer and a second barrier layer separated from each other in each cell region, the first barrier layer and the second barrier layer penetrating the gallium nitride layer from the first side to the second side; forming a modulated gallium nitride layer on each cell region, the modulated gallium nitride layer being located on the first side, the modulated gallium nitride layer being doped with p-type ions, the modulated gallium nitride layer being located on the gallium nitride layer between the first barrier layer and the second barrier layer; forming a plurality of gate electrodes, the gate electrodes being located on the first side, the gate electrodes being respectively connected to the corresponding gate electrodes. The modulated gallium nitride layer on the cell region is electrically connected; a plurality of source electrodes are formed, the source electrodes being located on the first side, and the gate electrodes being located between adjacent source electrodes, wherein the source electrodes on one side of the gate electrode are electrically connected to the gallium nitride layer on the side of the first barrier layer away from the second barrier layer, and the source electrodes on the other side of the gate electrode are electrically connected to the gallium nitride layer on the side of the second barrier layer away from the first barrier layer; after forming the gate electrode and the source electrode, the substrate is removed; a metal layer is formed on the surface of the gallium nitride layer located on the second side; a drain electrode is formed, the drain electrode being located on the second side, the metal layer being located between the gallium nitride layer and the drain electrode, and the drain electrode being electrically connected to the metal layer, to form a plurality of cell units arranged along the first direction and adjacent to each other.
[0017] Optionally, the method for forming the first barrier layer and the second barrier layer includes: forming a first barrier trench and a second barrier trench that are separated from each other in the cell region, the first barrier trench and the second barrier trench penetrating the gallium nitride layer from the first side to the second side; forming a barrier material layer in the first barrier trench and the second barrier trench and on the surface of the gallium nitride layer located on the first side; and planarizing the barrier material layer until the surface of the gallium nitride layer located on the first side is exposed, thereby forming the first barrier layer and the second barrier layer.
[0018] Optionally, the method for forming the modulated gallium nitride layer includes: forming a modulated gallium nitride material layer on the surface of the gallium nitride layer located on the first side; performing a patterned etching process on the modulated gallium nitride material layer to form the modulated gallium nitride layer on the surface of each of the cell regions.
[0019] Optionally, the gate electrode and the source electrode are formed simultaneously.
[0020] Optionally, adjacent cell units may share the source electrode.
[0021] Optionally, the metal layer covers the surface of all the cell units where the gallium nitride layer is located on the second side.
[0022] Optionally, all the cell units share one drain electrode.
[0023] Optionally, before forming the gate electrode and the source electrode, the method further includes: forming a first conductive plug, wherein the gate electrode is electrically connected to the modulated gallium nitride layer through the first conductive plug; and forming a second conductive plug, wherein the source electrode is electrically connected to the gallium nitride layer through the second conductive plug.
[0024] Optionally, before forming the gate electrode and the source electrode, the method further includes: forming a dielectric layer located on the first side, the dielectric layer being located on the gallium nitride layer and covering the modulated gallium nitride layer, and the first conductive plug and the second conductive plug being located within the dielectric layer.
[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0026] In the semiconductor structure of the present invention, a first barrier layer and a second barrier layer are introduced into the structure of each cell unit. This structural layout allows multiple contact cross-sections between the gallium nitride layer and the barrier layer to be constructed within each cell unit. The increase in contact cross-sections provides more channels for carrier transport, thereby significantly improving the total current density of the device and optimizing its electrical performance. The first barrier layer and the second barrier layer penetrate the gallium nitride layer from the first side to the second side, respectively. Therefore, the first barrier layer and the second barrier layer provide transport channels of uniform area for two-dimensional electron gas and two-dimensional hole gas at the surfaces of adjacent gallium nitride layers and at the interface between the barrier layer and the gallium nitride layer. This avoids the problem that the intensity of the two-dimensional electron gas is too high and cannot be completely consumed due to the excessive thickness of the first barrier layer and the second barrier layer, thus preventing the device from being effectively turned off. In actual device manufacturing, this design allows for a suitable increase in the thickness of the first and second barrier layers. This not only reduces the difficulty of process control but also improves device production efficiency, making the manufacturing process more stable and reliable, and providing a strong guarantee for large-scale production. Furthermore, based on the dual-channel high-current-density cell unit, multiple cell units can be connected in parallel in the first direction to achieve greater current conduction capability. This solves the problem in traditional planar gallium nitride (GaN) superjunction structures where the physical characteristics of the two-dimensional electron gas limit the utilization of GaN bulk thickness, restricting current flow only at the interface and thus limiting the total current capacity of the device. The device structure composed of multiple cell units can fully utilize the horizontal and vertical spatial dimensions, maximizing the current capacity of the device volume within a fixed size space. This provides a more effective solution for compressing the size of power control systems using GaN devices, offering higher voltage withstand capability and more current paths and current capacity within the same volume.
[0027] In the semiconductor structure formation method of the present invention, a first barrier layer and a second barrier layer are formed in the structure of each cell unit. This structural layout allows multiple contact cross-sections between the gallium nitride layer and the barrier layer to be constructed inside each cell unit. The increase in contact cross-sections provides more channels for carrier transport, thereby significantly improving the total current density of the device and optimizing the electrical performance of the device. The first barrier layer and the second barrier layer penetrate the gallium nitride layer from the first side to the second side, respectively. Therefore, the first barrier layer and the second barrier layer provide transport channels of uniform area for two-dimensional electron gas and two-dimensional hole gas at the surface of the adjacent gallium nitride layer and at the interface between the barrier layer and the gallium nitride layer. This avoids the problem that the intensity of the two-dimensional electron gas is too high due to the excessive thickness of the first barrier layer and the second barrier layer, which cannot be completely consumed, thus preventing the device from being effectively turned off. In actual device manufacturing, this design allows for a suitable increase in the thickness of the first and second barrier layers. This not only reduces the difficulty of process control but also improves device production efficiency, making the manufacturing process more stable and reliable, and providing a strong guarantee for large-scale production. Furthermore, based on the dual-channel high-current-density cell unit, multiple cell units can be connected in parallel in the first direction to achieve greater current conduction capability. This solves the problem in traditional planar gallium nitride (GaN) superjunction structures where the physical characteristics of the two-dimensional electron gas limit the utilization of GaN bulk thickness, restricting current flow only at the interface and thus limiting the total current capacity of the device. The device structure composed of multiple cell units can fully utilize the horizontal and vertical spatial dimensions, maximizing the current capacity of the device volume within a fixed size space. This provides a more effective solution for compressing the size of power control systems using GaN devices, offering higher voltage withstand capability and more current paths and current capacity within the same volume. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of a planar superjunction gallium nitride structure;
[0029] Figures 2 to 9 This is a schematic diagram of the steps in the semiconductor structure formation method in an embodiment of the present invention. Detailed Implementation
[0030] As described in the background section, existing superjunction devices still have many problems. These will be explained in detail below with reference to the accompanying drawings.
[0031] Figure 1 This is a schematic diagram of a planar superjunction gallium nitride structure.
[0032] A superjunction (SJ) is a device that introduces a P-type structure into an N-type semiconductor. It achieves high breakdown voltage by NP balance to deplete charge when the circuit is reverse-biased and low on-resistance by heavy N-type doping when the circuit is forward-biased.
[0033] There have been proposals to introduce superjunction structures into gallium nitride (GaN), but the principles of GaN differ from those of silicon, making direct application of superjunction structures impractical. The main reason is that GaN is a wide-bandgap semiconductor material, with a bandgap of approximately 3.4 eV, far exceeding silicon's 1.1 eV. This results in a higher breakdown field strength for GaN at high voltages, but also leads to significant differences in doping and carrier concentration control compared to silicon. Doping concentrations and carrier mobilities easily achievable in silicon are difficult to replicate directly in GaN. Furthermore, GaN exhibits strong polarization, especially in AlGaN / GaN heterojunctions, where the polarization leads to a high-density two-dimensional electron gas (2DEG) at the interface. This polarization effect is absent in silicon; therefore, superjunction designs based on silicon cannot directly account for GaN polarization, leading to design failures.
[0034] Please refer to Figure 1 Currently, some studies have proposed to realize planar superjunction gallium nitride structures by utilizing the depletion of two-dimensional hole gas (2DHG) and two-dimensional electron gas in silicon nitride. However, there are several drawbacks: the aluminum gallium nitride barrier layer cannot be too thick (the total amount of two-dimensional hole gas is insufficient to balance it), and it is difficult to control and realize in terms of process; the single-channel current surface density of two-dimensional electron gas is limited, and the current density is insufficient, making it unsuitable for high-power applications.
[0035] The reason for the above defects is that, due to the aluminum gallium nitride (AlGaNi) in the planar superjunction gallium nitride structure... Figure 1 Unoped-AlGaN and gallium nitride (GaN) Figure 1 Two-dimensional electron gas on the surface of undoped-GaN (in) Figure 1 The 2DEG (gallium nitride gate electrode) itself has a very high areal density, but excessive density can prevent it from being turned off, resulting in excessive leakage current when the device is normally on or reverse-biased to turn off, rendering it unusable. Therefore, the current approach is to apply a voltage to the gallium nitride side to increase the potential barrier and reduce the total amount of 2DEG. When the total amount of 2DEG is low enough, the gate electrode (GaN)... Figure 1The 2DEGs below the gate can polarize to form 2DHGs that mutually consume each other in the aluminum gallium nitride (AlGaN) layer. The total amount of 2DEGs below the gate decreases until they are completely depleted, resulting in turn-off. Because there are no 2DEGs below the gate at this point, the entire device can be completely turned off, preventing reverse leakage. However, this structure requires that the thickness of the AlGaN layer, which acts as a barrier, cannot be too thick. If the AlGaN layer is too thick (the thickness of AlGaN is related to the interface polarization intensity, and thus inversely proportional to the amount of 2DEGs), the 2DEGs will be too strong, affecting the p-type gallium nitride (GaN) layer. Figure 1 In the case of gallium nitride (GaN), gallium nitride (GaN), and aluminum gallium nitride (AlGaN), the 2DHG on one side cannot completely consume the 2DEG. Therefore, further adjustments are needed to the voltage applied to the GaN and AlGaN sides and the gate voltage to achieve balance between the 2DEG and 2DHG below the gate, causing difficulties in use or design. Thus, from a design and process control perspective, the best approach is to reduce the AlGaN thickness to the thinnest achievable in the process. This would reduce the 2DEG areal density and total amount to a level that can be easily turned off by the gate voltage. However, this also results in a significant decrease in the 2DEG areal density, limiting current capability. On the other hand, in the planar superjunction GaN structure, the current path exists at the contact surface between GaN and AlGaN. The formed 2DEG has only a few atomic layers perpendicular to the contact interface and can only flow in a horizontal plane, unlike silicon devices where the entire silicon material can conduct electricity. Therefore, the planar superjunction GaN structure suffers from insufficient current density, failing to effectively utilize the overall three-dimensional space of the GaN device, resulting in low volume utilization when current flows, greatly limiting the space for further miniaturization of power devices.
[0036] In planar superjunction gallium nitride (GaN) structures, the aluminum gallium nitride (AGaN) layer thickness is approximately 5 to 20 nanometers to prevent excessive two-dimensional electron gas from causing large leakage currents. However, when forming the upper layer of doped p-type GaN or the gate, etching the doped GaN or the gate will come into contact with the AGaN. If the AGaN layer is too thin, the etching cannot be stopped and it is easy to etch through the AGaN. Therefore, atomic layer etching (ALE) must be used to prevent excessive loss of AGaN. However, ALE is extremely expensive, with an etching rate of <10A per minute. An ALE machine can only etch a few wafers per day, resulting in extremely high device manufacturing costs.
[0037] Based on this, the present invention provides a semiconductor structure and a method for forming the same, incorporating a first barrier layer and a second barrier layer into the structure of each cell unit. This structural layout allows for the creation of multiple contact cross-sections between the gallium nitride layer and the barrier layer within each cell unit. The increased contact cross-sections provide more channels for carrier transport, thereby significantly improving the total current density of the device and optimizing its electrical performance. The first barrier layer and the second barrier layer penetrate the gallium nitride layer from the first side to the second side, respectively. Therefore, the first barrier layer and the second barrier layer provide transport channels of uniform area for two-dimensional electron gas and two-dimensional hole gas at the surfaces of adjacent gallium nitride layers and at the interface between the barrier layer and the gallium nitride layer. This avoids the problem that excessive thickness of the first barrier layer and the second barrier layer can lead to excessively high intensity of two-dimensional electron gas that cannot be completely consumed, thus preventing effective device turn-off. In actual device manufacturing, this design allows for a suitable increase in the thickness of the first and second barrier layers. This not only reduces the difficulty of process control but also improves device production efficiency, making the manufacturing process more stable and reliable, and providing a strong guarantee for large-scale production. Furthermore, based on the dual-channel high-current-density cell unit, multiple cell units can be connected in parallel in the first direction to achieve greater current conduction capability. This solves the problem in traditional planar gallium nitride (GaN) superjunction structures where the physical characteristics of the two-dimensional electron gas limit the utilization of GaN bulk thickness, restricting current flow only at the interface and thus limiting the total current capacity of the device. The device structure composed of multiple cell units can fully utilize the horizontal and vertical spatial dimensions, maximizing the current capacity of the device volume within a fixed size space. This provides a more effective solution for compressing the size of power control systems using GaN devices, offering higher voltage withstand capability and more current paths and current capacity within the same volume.
[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0039] Figures 2 to 9 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.
[0040] Please refer to Figure 2 Substrate 100 is provided.
[0041] In this embodiment, the substrate 100 serves as the base layer for the subsequent formation of several unit cells, and the substrate 100 is made of silicon.
[0042] In other embodiments, the substrate material may also be sapphire, ruby, spinel, or silicon carbide, etc.
[0043] Please refer to Figure 3 A gallium nitride layer 101 is formed on the substrate 100. The gallium nitride layer 101 has a first side 101a and a second side 101b opposite to each other. The substrate 100 is located on the second side 101b. The gallium nitride layer 101 includes a plurality of cell regions I arranged along a first direction X and adjacent to each other.
[0044] In this embodiment, the formation process of the gallium nitride layer 101 includes an epitaxial growth process.
[0045] In this embodiment, the gallium nitride layer 101 is made of intrinsic gallium nitride.
[0046] In other embodiments, the gallium nitride layer may also be made of gallium nitride doped with N-type ions.
[0047] In this embodiment, each of the cell regions I is used to subsequently form the corresponding cell unit.
[0048] Please refer to Figure 4 In each of the cell regions I, a first barrier layer 102 and a second barrier layer 103 are formed that are separated from each other. The first barrier layer 102 and the second barrier layer 103 penetrate the gallium nitride layer 101 from the first side 101a to the second side 101b.
[0049] In this embodiment, the method for forming the first barrier layer 102 and the second barrier layer 103 includes: forming a first barrier trench and a second barrier trench (not shown) that are separated from each other in the cell region I, wherein the first barrier trench and the second barrier trench penetrate the gallium nitride layer 101 from the first side 101a to the second side 101b; forming a barrier material layer (not shown) in the first barrier trench and the second barrier trench and on the surface of the gallium nitride layer 101 located on the first side 101a; and planarizing the barrier material layer until the surface of the gallium nitride layer 101 located on the first side 101a is exposed, thereby forming the first barrier layer 102 and the second barrier layer 103.
[0050] In this embodiment, the barrier material layer is formed using an epitaxial growth process.
[0051] In other embodiments, the barrier material layer may also be formed using atomic vapor deposition or chemical vapor deposition.
[0052] In this embodiment, the planarization of the barrier material layer is performed using a chemical mechanical polishing process.
[0053] In this embodiment, the materials of the first barrier layer 102 and the second barrier layer 103 are aluminum gallium nitride.
[0054] In this embodiment, along the first direction X, the width of the first barrier layer 102 and the second barrier layer 103 is greater than 25 nanometers.
[0055] Please refer to Figure 5 A modulated gallium nitride layer 104 is formed on each of the cell regions I. The modulated gallium nitride layer 104 is located on the first side 101a. The modulated gallium nitride layer 104 is doped with P-type ions. The modulated gallium nitride layer 104 is located on the gallium nitride layer 101 between the first barrier layer 102 and the second barrier layer 103.
[0056] In this embodiment, the method for forming the modulated gallium nitride layer 104 includes: forming a modulated gallium nitride material layer (not shown) on the surface of the gallium nitride layer 101 located on the first side 101a; performing a patterned etching process on the modulated gallium nitride material layer to form the modulated gallium nitride layer 104 on the surface of each of the unit cell regions I.
[0057] In this embodiment, the modulated gallium nitride material layer is formed using an epitaxial growth process.
[0058] In this embodiment, the P-type ions are doped into the modulated gallium nitride layer 104 through an in-situ doping process during epitaxial growth.
[0059] In other embodiments, the P-type ions can also be doped into the modulated gallium nitride layer using an ion implantation process.
[0060] In this embodiment, the P-type ion is a magnesium ion, a zinc ion, or a fluoride ion.
[0061] In this embodiment, the method for patterning the modulated gallium nitride material layer includes: forming a patterned layer (not shown) on the modulated gallium nitride material layer, the patterned layer exposing a portion of the top surface of the modulated gallium nitride material layer; etching the modulated gallium nitride material layer using the pattern as a mask until the surface of the gallium nitride layer 101 is exposed, thereby forming the modulated gallium nitride layer 104.
[0062] Please refer to Figure 6A plurality of gate electrodes 105 are formed, the gate electrodes 105 being located on the first side 101a and electrically connected to the modulated gallium nitride layer 104 on the corresponding cell region I; a plurality of source electrodes 106 are formed, the source electrodes 106 being located on the first side 101a and the gate electrodes 105 being located between adjacent source electrodes 106, wherein the source electrode 106 on one side of the gate electrode 105 is electrically connected to the gallium nitride layer 101 on the side of the first barrier layer 102 away from the second barrier layer 103, and the source electrode 106 on the other side of the gate electrode 105 is electrically connected to the gallium nitride layer 101 on the side of the second barrier layer 103 away from the first barrier layer 102.
[0063] In this embodiment, before forming the gate electrode 105 and the source electrode 106, the method further includes forming a dielectric layer 107, which is located on the first side 101a and is located on the gallium nitride layer 101 and covers the modulated gallium nitride layer 104.
[0064] In this embodiment, the dielectric layer 107 is made of silicon oxide.
[0065] In other embodiments, the dielectric layer may also be made of a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).
[0066] In this embodiment, before forming the gate electrode 105 and the source electrode 106, the method further includes: forming a first conductive plug 108 and a second conductive plug 109 within the dielectric layer 107; wherein, the method for forming the first conductive plug 108 and the second conductive plug 109 includes: forming a first plug opening and a second plug opening (not shown) within the dielectric layer 107; forming a conductive material layer (not shown) within the first plug opening and the second plug opening, and on the surface of the dielectric layer 107; and planarizing the conductive material layer until the top surface of the dielectric layer 107 is exposed, thereby forming the first conductive plug 108 and the second conductive plug 109.
[0067] In this embodiment, the gate electrode 105 is electrically connected to the modulated gallium nitride layer 104 through the first conductive plug 108; the source electrode 106 is electrically connected to the gallium nitride layer 101 through the second conductive plug 109.
[0068] In this embodiment, the gate electrode 105 and the source electrode 106 are formed simultaneously. The method for forming the gate electrode 105 and the source electrode 106 includes: forming a first electrode material layer (not shown) on the dielectric layer 107; and performing patterned etching on the first electrode material layer to form the gate electrode 105 and the source electrode 106.
[0069] Please refer to Figure 7 After the gate electrode 105 and the source electrode 106 are formed, the substrate 100 is removed.
[0070] In this embodiment, the substrate 100 is removed using a thinning process.
[0071] In this embodiment, the method of removing the substrate 100 by thinning includes: thinning the substrate 100 from the second side 101b to the first side 101a until the surfaces of the gallium nitride layer 101, the first barrier layer 102 and the second barrier layer 103 are exposed.
[0072] The process of thinning the substrate 100 from the second side 101b to the first side 101a includes physical mechanical polishing, chemical mechanical polishing, or wet etching.
[0073] In this embodiment, the process of thinning the substrate 100 from the second side 101b to the first side 101a is a chemical mechanical polishing process.
[0074] Please refer to Figure 8 A metal layer 110 is formed on the surface of the gallium nitride layer 101 located on the second side 101b.
[0075] In this embodiment, the metal layer 110 also covers the surfaces of the first barrier layer 102 and the second barrier layer 103.
[0076] In this embodiment, the metal layer 110 is formed using a chemical vapor deposition process.
[0077] Please refer to Figure 9 A drain electrode 111 is formed, the drain electrode 111 is located on the second side 101b, the metal layer 110 is located between the gallium nitride layer 101 and the drain electrode 111, and the drain electrode 111 is electrically connected to the metal layer 110 to form a plurality of cell units arranged along the first direction X and adjacent to each other.
[0078] In this embodiment, the method for forming the drain electrode 111 includes: forming a second electrode material layer on the surface of the metal layer 110; and performing patterned etching on the second electrode material layer to form the drain electrode 111.
[0079] In this embodiment, each of the formed cell units includes: a gallium nitride layer 101 having opposing first sides 101a and second sides 101b; a first barrier layer 102 and a second barrier layer 103 located within the gallium nitride layer 101 and separated from each other, the first barrier layer 102 and the second barrier layer 103 penetrating the gallium nitride layer 101 from the first side 101a to the second side 101b; a modulated gallium nitride layer 104 located on the first side 101a, the modulated gallium nitride layer 104 being doped with p-type ions, the modulated gallium nitride layer 104 being located on the gallium nitride layer 101 between the first barrier layer 102 and the second barrier layer 103; and a gate electrode 105 located on the first side 101a, the gate electrode 105 being connected to the modulated gallium nitride layer 101. Gallium nitride layer 104 is electrically connected; source electrodes 106 are located on both sides of the gate electrode 105, the source electrodes 106 are located on the first side 101a, wherein one side of the source electrode 106 is electrically connected to the gallium nitride layer 101 on the side of the first barrier layer 102 away from the second barrier layer 103, and the other side of the source electrode 106 is electrically connected to the gallium nitride layer 101 on the side of the second barrier layer 103 away from the first barrier layer 102; metal layer 110 is located on the second side 101b, the metal layer 110 covers the surface of the gallium nitride layer 101 on the second side 101b; drain electrode 111 is located on the second side 101b, the metal layer 110 is located between the gallium nitride layer 101 and the drain electrode 111, and the drain electrode 111 is electrically connected to the metal layer 110.
[0080] By forming the first barrier layer 102 and the second barrier layer 103 in the structure of each cell, this structural layout creates multiple contact sections between the gallium nitride layer 101 and the barrier layer within each cell. The increased contact sections provide more channels for carrier transport, significantly improving the total current density of the device and thus optimizing its electrical performance. The first barrier layer 102 and the second barrier layer 103 penetrate the gallium nitride layer 101 from the first side 101a to the second side 101b, respectively. Therefore, the first barrier layer 102 and the second barrier layer 103 provide transport channels of uniform area for two-dimensional electron gas and two-dimensional hole gas at the surfaces of adjacent gallium nitride layers 101 and at the interface between the barrier layer and the gallium nitride layer 101. This avoids the problem of excessively high two-dimensional electron gas intensity due to excessive thickness of the first barrier layer 101 and the second barrier layer 102, which cannot be completely consumed and thus prevents effective device turn-off. In actual device manufacturing, this design allows for an appropriate increase in the thickness of the first barrier layer 101 and the second barrier layer 102. This not only reduces the difficulty of process control but also improves the production efficiency of the device, making the device manufacturing process more stable and reliable, and providing a strong guarantee for large-scale production.
[0081] Furthermore, based on the dual-channel high-current-density cell unit, multiple cells can be connected in parallel in the first direction X to achieve greater current conduction capability. This solves the problem in traditional planar gallium nitride (GaN) superjunction structures where the physical properties of the two-dimensional electron gas limit the utilization of GaN bulk thickness, restricting current flow to the interface and thus limiting the total current capability of the device. The device structure composed of multiple cells can fully utilize the spatial dimensions in both horizontal and vertical directions, maximizing the current capability of the device volume within a fixed space. This provides a more effective solution for compressing the size of power control systems using GaN devices, offering higher voltage withstand capability and more current paths and current capacity within the same volume.
[0082] In this embodiment, adjacent cell units share the source electrode 106, that is, each of the second conductive plugs 109 is connected to the adjacent cell region I.
[0083] In this embodiment, the metal layer 110 covers the surface of the gallium nitride layer 101 located on the second side 101b in all the cell units.
[0084] In this embodiment, all the cell units share one drain electrode 111.
[0085] Accordingly, this invention also provides a semiconductor structure, please refer to the following embodiments. Figure 9The system includes: a plurality of adjacent cell units arranged along a first direction X, each cell unit including: a gallium nitride layer 101 having a first side 101a and a second side 101b; a first barrier layer 102 and a second barrier layer 103 located within the gallium nitride layer 101 and separated from each other, the first barrier layer 102 and the second barrier layer 103 penetrating the gallium nitride layer 101 from the first side 101a to the second side 101b; a modulation gallium nitride layer 104 located on the first side 101a, the modulation gallium nitride layer 104 being doped with p-type ions, the modulation gallium nitride layer 104 being located on the gallium nitride layer 101 between the first barrier layer 102 and the second barrier layer 103; and a gate electrode 105 located on the first side 101a, the gate electrode 105 being connected to the modulation gallium nitride layer 101 between the first barrier layer 102 and the second barrier layer 103. A gallium nitride layer 104 is electrically connected; source electrodes 106 are located on both sides of the gate electrode 105, the source electrodes 106 are located on the first side 101a, wherein one side of the source electrode 106 is electrically connected to the gallium nitride layer 101 on the side of the first barrier layer 102 away from the second barrier layer 103, and the other side of the source electrode 106 is electrically connected to the gallium nitride layer 101 on the side of the second barrier layer 103 away from the first barrier layer 102; a metal layer 110 is located on the second side 101b, the metal layer 110 covers the surface of the gallium nitride layer 101 on the second side 101b; a drain electrode 111 is located on the second side 101b, the metal layer 110 is located between the gallium nitride layer 101 and the drain electrode 111, and the drain electrode 111 is electrically connected to the metal layer 110.
[0086] By introducing the first barrier layer 102 and the second barrier layer 103 into the structure of each cell, this structural layout creates multiple contact sections between the gallium nitride layer 101 and the barrier layer within each cell. The increased contact sections provide more channels for carrier transport, significantly improving the overall current density of the device and thus optimizing its electrical performance. The first barrier layer 102 and the second barrier layer 103 penetrate the gallium nitride layer 101 from the first side 101a to the second side 101b, respectively. Therefore, the first barrier layer 102 and the second barrier layer 103 provide transport channels of uniform area for two-dimensional electron gas and two-dimensional hole gas at the surfaces of adjacent gallium nitride layers 101 and at the interface between the barrier layer and the gallium nitride layer 101. This avoids the problem of excessively high two-dimensional electron gas intensity due to excessive thickness of the first barrier layer 101 and the second barrier layer 102, which cannot be completely consumed and thus prevents effective device turn-off. In actual device manufacturing, this design allows for an appropriate increase in the thickness of the first barrier layer 101 and the second barrier layer 102. This not only reduces the difficulty of process control but also improves the production efficiency of the device, making the device manufacturing process more stable and reliable, and providing a strong guarantee for large-scale production.
[0087] Furthermore, based on the dual-channel high-current-density cell unit, multiple cells can be connected in parallel in the first direction X to achieve greater current conduction capability. This solves the problem in traditional planar gallium nitride (GaN) superjunction structures where the physical properties of the two-dimensional electron gas limit the utilization of GaN bulk thickness, restricting current flow to the interface and thus limiting the total current capability of the device. The device structure composed of multiple cells can fully utilize the spatial dimensions in both horizontal and vertical directions, maximizing the current capability of the device volume within a fixed space. This provides a more effective solution for compressing the size of power control systems using GaN devices, offering higher voltage withstand capability and more current paths and current capacity within the same volume.
[0088] In this embodiment, adjacent cell units share the source electrode 106.
[0089] In this embodiment, the metal layer 110 covers the surface of the gallium nitride layer 101 located on the second side 101b in all the cell units.
[0090] In this embodiment, all the cell units share one drain electrode 111.
[0091] In this embodiment, it further includes: a first conductive plug 108, through which the gate electrode 105 is electrically connected to the modulated gallium nitride layer 104; and a second conductive plug 109, through which the source electrode 106 is electrically connected to the gallium nitride layer 101.
[0092] In this embodiment, it further includes: a dielectric layer 107, the dielectric layer 107 being located on the first side 101a, the dielectric layer 107 being located on the gallium nitride layer 101 and covering the modulated gallium nitride layer 104, and the first conductive plug 108 and the second conductive plug 109 being located within the dielectric layer 107.
[0093] In this embodiment, the materials of the first barrier layer 102 and the second barrier layer 103 are aluminum gallium nitride.
[0094] In this embodiment, along the first direction X, the width of the first barrier layer 102 and the second barrier layer 103 is greater than 25 nanometers.
[0095] In this embodiment, the P-type ion is a magnesium ion, a zinc ion, or a fluoride ion.
[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: A plurality of adjacent cell units arranged along a first direction, each cell unit comprising: A gallium nitride layer having opposing first and second sides; A first barrier layer and a second barrier layer are located within the gallium nitride layer and are separated from each other, the first barrier layer and the second barrier layer penetrating the gallium nitride layer from the first side to the second side; A modulated gallium nitride layer is located on the first side, the modulated gallium nitride layer is doped with P-type ions, and the modulated gallium nitride layer is located on the gallium nitride layer between the first barrier layer and the second barrier layer; A gate electrode, located on the first side, is electrically connected to the modulated gallium nitride layer; The source electrodes are located on both sides of the gate electrode, and the source electrodes are located on the first side. One of the source electrodes is electrically connected to the gallium nitride layer on the side of the first barrier layer away from the second barrier layer, and the other source electrode is electrically connected to the gallium nitride layer on the side of the second barrier layer away from the first barrier layer. A metal layer is located on the second side, and the metal layer covers the surface of the gallium nitride layer located on the second side; A drain electrode is located on the second side, and a metal layer is located between the gallium nitride layer and the drain electrode, and the drain electrode is electrically connected to the metal layer.
2. The semiconductor structure as described in claim 1, characterized in that, The adjacent cell units share the source electrode.
3. The semiconductor structure as described in claim 1, characterized in that, The metal layer covers the surface of all the cell units where the gallium nitride layer is located on the second side.
4. The semiconductor structure as described in claim 1, characterized in that, All the aforementioned cell units share one drain electrode.
5. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first conductive plug is used to electrically connect the gate electrode to the modulated gallium nitride layer. The source electrode is electrically connected to the gallium nitride layer through the second conductive plug.
6. The semiconductor structure as described in claim 5, characterized in that, Also includes: A dielectric layer is located on the first side, the dielectric layer is located on the gallium nitride layer and covers the modulated gallium nitride layer, and the first conductive plug and the second conductive plug are located within the dielectric layer.
7. The semiconductor structure as described in claim 1, characterized in that, The materials of the first barrier layer and the second barrier layer include aluminum gallium nitride.
8. The semiconductor structure as described in claim 1, characterized in that, Along the first direction, the width of the first barrier layer and the second barrier layer is greater than 25 nanometers.
9. The semiconductor structure as described in claim 1, characterized in that, The P-type ions include: magnesium ions, zinc ions, or fluoride ions.
10. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A gallium nitride layer is formed on the substrate, the gallium nitride layer having a first side and a second side opposite to each other, the substrate being located on the second side, and the gallium nitride layer comprising a plurality of cell regions arranged along a first direction and adjacent to each other; A first barrier layer and a second barrier layer are formed in each of the cell regions, and the first barrier layer and the second barrier layer penetrate the gallium nitride layer from the first side to the second side. A modulated gallium nitride layer is formed on each of the cell regions, the modulated gallium nitride layer is located on the first side, the modulated gallium nitride layer is doped with p-type ions, and the modulated gallium nitride layer is located on the gallium nitride layer between the first barrier layer and the second barrier layer; A plurality of gate electrodes are formed, the gate electrodes being located on the first side, and the gate electrodes being electrically connected to the modulated gallium nitride layer on the corresponding cell region; A plurality of source electrodes are formed, wherein the source electrodes are located on the first side, and the gate electrodes are located between adjacent source electrodes, wherein the source electrode on one side of the gate electrode is electrically connected to the gallium nitride layer on the side of the first barrier layer away from the second barrier layer, and the source electrode on the other side of the gate electrode is electrically connected to the gallium nitride layer on the side of the second barrier layer away from the first barrier layer. After forming the gate electrode and the source electrode, the substrate is removed; A metal layer is formed on the surface of the gallium nitride layer located on the second side; A drain electrode is formed, the drain electrode is located on the second side, the metal layer is located between the gallium nitride layer and the drain electrode, and the drain electrode is electrically connected to the metal layer to form a plurality of cell units arranged along the first direction and adjacent to each other.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the first barrier layer and the second barrier layer includes: forming a first barrier trench and a second barrier trench that are separated from each other in the cell region, the first barrier trench and the second barrier trench penetrating the gallium nitride layer from the first side to the second side; forming a barrier material layer in the first barrier trench and the second barrier trench and on the surface of the gallium nitride layer on the first side; and planarizing the barrier material layer until the surface of the gallium nitride layer on the first side is exposed, thereby forming the first barrier layer and the second barrier layer.
12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the modulated gallium nitride layer includes: forming a modulated gallium nitride material layer on the surface of the gallium nitride layer located on the first side; performing a patterned etching process on the modulated gallium nitride material layer to form the modulated gallium nitride layer on the surface of each of the cell regions.
13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The gate electrode and the source electrode are formed simultaneously.
14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The adjacent cell units share the source electrode.
15. The method for forming a semiconductor structure as described in claim 10, characterized in that, The metal layer covers the surface of all the cell units where the gallium nitride layer is located on the second side.
16. The method for forming a semiconductor structure as described in claim 10, characterized in that, All the aforementioned cell units share one drain electrode.
17. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming the gate electrode and the source electrode, the method further includes: forming a first conductive plug, wherein the gate electrode is electrically connected to the modulated gallium nitride layer through the first conductive plug; and forming a second conductive plug, wherein the source electrode is electrically connected to the gallium nitride layer through the second conductive plug.
18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Before forming the gate electrode and the source electrode, the method further includes: forming a dielectric layer located on the first side, the dielectric layer being located on the gallium nitride layer and covering the modulated gallium nitride layer, and the first conductive plug and the second conductive plug being located within the dielectric layer.
Citation Information
Patent Citations
Back gate full-controlled AlGaN / GaN heterojunction enhanced power HEMT device and preparation method thereof
CN112768508A
Double-channel vertical super-junction GaN HEMT (High Electron Mobility Transistor) and preparation method
CN117012819A