Method of manufacturing display device

Abstract

A method of manufacturing a display device includes forming a bank in a display area on a substrate in a third direction, the substrate extending in a first direction and a second direction intersecting the first direction, the third direction intersecting the first direction and the second direction, the bank having an opening; forming a dam member on the substrate in a third direction in the display area, the dam member disposed along an edge of the display area; aligning the light emitting element and the opening provided on the surface of the carrier substrate to face each other; moving the carrier substrate towards the substrate and disposing the light emitting element at least partially in the opening; and separating the carrier substrate from the light emitting element.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0081329, filed on June 21, 2024, and Korean Patent Application No. 10-2024-0089061, filed on July 5, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to display devices and methods of manufacturing the display device. More specifically, this disclosure relates to display devices with improved reliability and methods of manufacturing the display device. Background Technology

[0004] The importance of display devices has increased with the development of multimedia. Therefore, the use of display devices such as liquid crystal displays, organic light-emitting diode (OLED) displays, and inorganic light-emitting diode (LED) displays is also increasing. In particular, research is actively underway on microLEDs, which can achieve higher brightness and faster response times compared to traditional LEDs.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background technology of the inventive concept, and therefore may contain information that does not form prior art known to those skilled in the art. Summary of the Invention

[0006] Embodiments of this disclosure provide a display device with improved reliability and a method for manufacturing the display device. For example, the display device can improve the reliability of the bonding process of the light-emitting element by providing a dam member on the substrate having a height greater than the height of the light-emitting element.

[0007] Embodiments of this disclosure provide a display device including a display area and a non-display area surrounding the display area, and the display device includes: a substrate extending in a first direction and a second direction intersecting the first direction; and a display element layer disposed on the substrate in a third direction intersecting the first and second directions, wherein the display element layer includes a dam disposed on the substrate in the display area and having an opening; light-emitting elements, each of which overlaps with the opening and is at least partially disposed in the opening; and a dam member disposed along the edge of the display area, wherein each of the light-emitting elements has a first height in the third direction, and the dam member has a second height in the third direction greater than the first height.

[0008] The embankment can have a third height in a third direction, and the third height can be less than the second height.

[0009] The display element layer can have a fourth height in the third direction, and the fourth height can be less than the second height.

[0010] The first height can be a distance between the substrate and an upper surface of the light emitting element, and the second height can be a distance between the substrate and the end portion of the dam member.

[0011] The display element layer can further include anode electrodes respectively overlapping the openings, and the light emitting elements can be disposed on the anode electrodes.

[0012] The display apparatus can further include a bonding member disposed between the light emitting elements and the anode electrodes, wherein the bonding member can include a Sn-Ag-Cu (SAC) alloy.

[0013] The display element layer can further include outer coating layers respectively disposed in the openings, and the light emitting elements can be partially embedded in the outer coating layers.

[0014] The dam can have a third height in the third direction, and the third height can be substantially equal to the second height.

[0015] The first portion of the dam can have a third height in the third direction, the second portion of the dam can have a fifth height in the third direction, the third height can be greater than the fifth height, and the third height can be substantially equal to the second height.

[0016] Another embodiment of the disclosure provides a method of manufacturing a display apparatus, including: forming a dam in a display area on a substrate in a third direction, the substrate extending in a first direction and a second direction intersecting the first direction, the third direction intersecting the first direction and the second direction, the dam having an opening; forming a dam member on the substrate in the third direction in the display area, the dam member being disposed along an edge of the display area; aligning light emitting elements disposed on a surface of a carrier substrate and the opening to face each other; moving the carrier substrate toward the substrate, and disposing the light emitting elements at least partially in the opening; and separating the carrier substrate from the light emitting elements.

[0017] Each of the light emitting elements can have a first height in the third direction, and the dam member can have a second height in the third direction greater than the first height.

[0018] The dam can have a third height in the third direction, and the third height can be less than the second height.

[0019] The dam can have a third height in the third direction, and the third height can be substantially equal to the second height.

[0020] The first part of the dike may have a third height in the direction of the third party, and the second part of the dike may have a fifth height in the direction of the third party. The third height may be greater than the fifth height, and the third height may be substantially equal to the second height.

[0021] Placing the light-emitting element at least partially in the opening may also include applying heat or pressure to another surface of the carrier substrate opposite to the first surface.

[0022] The carrier substrate may include an adhesive layer disposed on one surface of the carrier substrate, and the adhesive layer may be disposed between the carrier substrate and the light-emitting element, and may expand due to heat.

[0023] Expansion of the adhesive layer can be contained within a portion of the adhesive layer by dam components.

[0024] Another embodiment of this disclosure provides a method for manufacturing a display device, comprising: forming a dam in a display region on a substrate in a third direction, the substrate extending in a first direction and a second direction intersecting the first direction, the third direction intersecting the first and second directions, the dam having an opening; forming a dam member on a surface of a carrier substrate on which a light-emitting element is disposed, the dam member being configured to correspond to an edge of the display region on the substrate; aligning the light-emitting element and the opening on the carrier substrate to face each other; moving the carrier substrate toward the substrate to at least partially dispose the light-emitting element in the opening; and separating the carrier substrate from the light-emitting element.

[0025] When separating the carrier substrate from the light-emitting element, the dam component can be separated from the substrate along with the carrier substrate.

[0026] Each of the light-emitting elements may have a first length in a third direction, and the dam member may have a second length in a third direction that is longer than the first length. Attached Figure Description

[0027] Figure 1 A schematic block diagram of a display device according to an embodiment is shown.

[0028] Figure 2 An embodiment is shown. Figure 1 A schematic block diagram of one of the sub-pixels.

[0029] Figure 3 An embodiment is shown. Figure 1 A schematic top view of the display panel.

[0030] Figure 4 An embodiment is shown. Figure 3 A schematic cross-sectional view of the display panel.

[0031] Figure 5 An embodiment according to another embodiment is shown. Figure 3 schematic cross-sectional view of a display panel according to an embodiment.

[0032] Figure 6 schematic cross-sectional view taken along line I-I' of Figure 3

[0033] Figure 7 schematic top view of one of the pixels of Figure 3

[0034] Figure 8 schematic cross-sectional view taken along line A-A' of Figure 7

[0035] Figure 9 schematic cross-sectional view taken along line B-B' of Figure 7

[0036] Figure 10 schematic flowchart of a method of manufacturing a display apparatus according to an embodiment of the disclosure.

[0037] Figures 11 to 15 schematically illustrates a method of manufacturing a display apparatus of Figure 10

[0038] Figure 16 schematic flowchart of a method of manufacturing a display apparatus according to another embodiment of the disclosure.

[0039] Figures 17 to 22 schematically illustrates a method of manufacturing a display apparatus of Figure 16

[0040] Figure 23 schematic top view of a display panel according to another embodiment. Figure 1

[0041] Figure 24 schematic cross-sectional view taken along line II-II' of Figure 23

[0042] Figure 25 schematic top view of one of the pixels of Figure 23

[0043] Figure 26 schematic cross-sectional view taken along line C-C' of Figure 25

[0044] Figures 27 to 31 schematically illustrates a method of manufacturing a display apparatus according to another embodiment of the disclosure.

[0045] ​​​​​​​​​​ Figure 32 a schematic cross-sectional view taken along Figure 23 line II-II' of FIG. 1.

[0046] Figure 33 a schematic block diagram of a display system according to an embodiment is shown.

[0047] Figures 34 to 37 a schematic perspective view of an application example of the display system of Figure 33 FIG. 1. DETAILED DESCRIPTION

[0048] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following description is intended to provide a sufficient disclosure to enable one of ordinary skill in the art to understand the present invention and is not intended to limit any other disclosure in order to obscure the scope of the present invention. Furthermore, the inventive concept can be implemented in different forms and is not limited to the embodiments set forth herein. The embodiments described herein are provided for the purpose of describing the technical concept of the present invention in sufficient detail to enable those skilled in the art to easily practice the present invention.

[0049] Throughout the specification, in the case where an element is described as being "connected" to another element, it not only includes "directly connected" but also includes "indirectly connected" with another device therebetween. The terms used herein are used to describe specific embodiments for the purpose of describing the present invention and are not intended to limit the scope of the present invention. Throughout the specification, unless explicitly described to the contrary, the words "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. For the purpose of the present disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as any one of X, Y and Z, or any combination of two or more of X, Y and Z, such as, for example, XYZ, XY, YZ and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Although the terms first, second, etc. can be used herein to describe various constituent elements, the constituent elements should not be limited by these terms. The terms are used to distinguish one constituent element from another. Therefore, a first constituent element discussed below could be termed a second constituent element without departing from the teachings of the present disclosure.

[0051] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation and / or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0052] Various implementations are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized implementations. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the example implementations described herein are not to be construed as being limited to the particular shapes of regions as illustrated and are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the example implementations.

[0053] Figure 1 A schematic block diagram of a display device according to an implementation is shown.

[0054] Reference Figure 1 The display device DD can include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0055] The display panel DP can include sub-pixels SP. The sub-pixels SP can be electrically connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP can be electrically connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0056] The sub-pixels SP can generate light of two or more colors. For example, the sub-pixels SP can generate light of colors such as red, green, blue, cyan, magenta, yellow, etc., respectively.

[0057] Two or more of the sub-pixels SP can constitute one pixel PXL. For example, the pixel PXL can include three sub-pixels SP as shown in FIG. 1A. Figure 1 The pixel PXL can emit light of various colors and various brightnesses according to a combination of light emitted from the sub-pixels SP included therein.

[0058] The gate driver 120 can be electrically connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. The gate control signal GCS can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0059] The gate driver 120 can be disposed on one side of the display panel DP. However, embodiments are not limited thereto. For example, the gate driver 120 can be divided into two or more physically and / or logically separated drivers, and the drivers can be disposed on one side of the display panel DP and on another side of the display panel DP opposite the one side. As described above, according to embodiments, the gate driver 120 can be disposed around the display panel DP in various forms.

[0060] The data driver 130 can be electrically connected to the sub-pixels SP arranged in a column direction through the first to n-th data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. The data control signal DCS can include a source start signal, a source shift clock signal, a source output enable signal, and the like.

[0061] The data driver 130 can receive voltages from the voltage generator 140. The data driver 130 can apply data signals having gray scale voltages corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using the received voltages. In a case in which a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, data signals corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Accordingly, the sub-pixels SP can generate light corresponding to the data signals, and the display panel DP can display an image (or a plurality of images).

[0062] In other embodiments, the gate driver 120 and the data driver 130 can include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0063] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can generate a plurality of voltages and provide the generated voltages to components of the display apparatus DD, such as the gate driver 120, the data driver 130, and the controller 150. The voltage generator 140 can generate the plurality of voltages by receiving an input voltage from the outside of the display apparatus DD and adjusting the received voltage.

[0064] The voltage generator 140 can generate a first power voltage and a second power voltage. The generated first power voltage and second power voltage can be provided to the sub-pixels SP through the power lines PL. In other embodiments, at least one of the first power voltage and the second power voltage can be provided from the outside of the display apparatus DD.

[0065] The voltage generator 140 can provide various voltages and / or signals. For example, the voltage generator 140 can provide one or more initialization voltages applied to the sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of the transistors and / or light emitting elements of the sub-pixels SP, a predetermined reference voltage can be applied to the first to nth data lines DL1 to DLn, and the voltage generator 140 can generate the reference voltage to transmit it to the data driver 130. For example, during a display operation for displaying an image on the display panel DP, a common pixel control signal can be applied to the sub-pixels SP, and the voltage generator 140 can generate the pixel control signal. The voltage generator 140 can provide the pixel control signal to the sub-pixels SP through the pixel control line PXCL. Figure 1 It is shown that the pixel control line PXCL is electrically connected between the voltage generator 140 and the display panel DP, but embodiments are not limited thereto. For example, the pixel control line PXCL can be electrically connected between the gate driver 120 and the display panel DP. The pixel control signal can be transmitted from the voltage generator 140 to the pixel control line PXCL through the gate driver 120.

[0066] The controller 150 can control various operations of the display apparatus DD. The controller 150 can receive input image data IMG and a control signal CTRL corresponding thereto from the outside. The controller 150 can provide the gate control signal GCS, the data control signal DCS, and the voltage control signal VCS in response to the control signal CTRL.

[0067] The controller 150 can convert the input image data IMG to be suitable for the display apparatus DD or the display panel DP to output image data DATA. The controller 150 can output the image data DATA by aligning the input image data IMG to be suitable for the sub-pixels SP of a row unit.

[0068] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 can be mounted on one integrated circuit. As Figure 1As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component separate from the driver integrated circuit (DIC).

[0069] Figure 2 An embodiment is shown. Figure 1 A schematic block diagram of one of the sub-pixels. Figure 2 In Figure 1 Among the sub-pixels SP, sub-pixels SPij set in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) are shown as an example.

[0070] refer to Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0071] The light-emitting element (LD) can be electrically connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN can be electrically connected to... Figure 1 One of the power lines PL in the circuit is used to receive the first power voltage. The second power voltage node VSSN can be electrically connected to... Figure 1 The first power line (PL) is another power line in the circuit to receive a second power voltage. The first power voltage may have a higher voltage level than the second power voltage.

[0072] The light-emitting element (LD) can be electrically connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be electrically connected to the first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be electrically connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be electrically connected to a second power voltage node VSSN. The light-emitting element LD can emit light according to the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0073] The sub-pixel circuit SPC can be electrically connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm and Figure 1a jthdata line DLj of the first data line DL1 to the nthdata line DLnof the display panel DP. The sub-pixel circuit SPC can control the light emitting element LD to emit light in accordance with a data signal received through the jthdata line DLj in response to a gate signal received through the ithgate line GLi. The sub-pixel circuit SPC can further be connected to a pixel control line PXCL of the display panel DP. The sub-pixel circuit SPC can further control the light emitting element LD in response to a pixel control signal received through the pixel control line PXCL. Figure 1

[0074] For these operations, the sub-pixel circuit SPC can include circuit elements, e.g., transistors and one or more capacitors.

[0075] The transistors of the sub-pixel circuit SPC can include P-type transistors and / or N-type transistors. The transistors of the sub-pixel circuit SPC can include metal oxide semiconductor field effect transistors (MOSFETs). The transistors of the sub-pixel circuit SPC can include amorphous silicon semiconductors, single crystalline silicon semiconductors, polycrystalline silicon semiconductors, and oxide semiconductors.

[0076] Figure 3 A schematic top view of a display panel according to an embodiment is shown. Figure 1

[0077] Referring to Figure 3 , the display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be provided around the display area DA.

[0078] The display panel DP can include sub-pixels SP in the display area DA. The sub-pixels SP can be arranged in a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP can be arranged in a matrix format in the first direction DR1 and the second direction DR2. As another example, the sub-pixels SP can be arranged in a zigzag form in the first direction DR1 and the second direction DR2. In other embodiments, the arrangement of the sub-pixels SP can vary. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0079] Two or more of the plurality of sub-pixels SP can constitute one pixel PXL. Figure 3 A pixel PXL is shown to include three sub-pixels SP1 to SP3, but embodiments are not limited thereto. For example, the pixel PXL can include two sub-pixels SP. Hereinafter, for better understanding and ease of description, the pixel PXL can include a first sub-pixel SP1 to a third sub-pixel SP3.

[0080] ​​Each of the first to third sub-pixels SP1 to SP3 can generate one of various colors such as red, green, blue, cyan, magenta, and yellow. Hereinafter, for clear and brief description, the first sub-pixel SP1 can generate red light, the second sub-pixel SP2 can generate green light, and the third sub-pixel SP3 can generate blue light.

[0081] Each of the first to third sub-pixels SP1 to SP3 can include at least one light emitting element to generate light. The light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of the same color. For example, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate blue light. In other embodiments, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate light of different colors. For example, the light emitting elements of the first to third sub-pixels SP1 to SP3 can generate red, green, and blue light, respectively.

[0082] As the display panel DP, a self-emission display panel such as an LED display panel using a micro- or nano-scale light emitting diode as a light emitting element and an organic light emitting display panel using an organic light emitting diode as a light emitting element can be used.

[0083] The display panel DP can include a dam member DAM in the display area DA. The dam member DAM can be disposed at an edge of the display area DA. The dam member DAM can be disposed in a closed loop at the edge of the display area DA. For example, in a case where the display panel DP is disposed in a rectangular shape having a pair of short sides and a pair of long sides, the dam member DAM can be disposed in a closed loop at the edge of the display area DA by extending in the first direction DR1 along the short side and extending in the second direction DR2 along the long side at the edge of the display area DA.

[0084] The constituent elements for controlling the sub-pixels SP can be disposed in the non-display area NDA. The conductive lines electrically connected to the sub-pixels SP (for example, the first to m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power lines PL, and the pixel control lines PXCL shown in FIG. 1) can be disposed in the non-display area NDA. Figure 1 The first to m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power lines PL, and the pixel control lines PXCL shown in FIG. 1 can be disposed in the non-display area NDA.

[0085] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, and the controller 150 in FIG. 1 can be disposed in the non-display area NDA of the display panel DP. The gate driver 120 can be disposed in the non-display area NDA. The data driver 130, the voltage generator 140, and the controller 150 can be implemented as a separate printed circuit board (PCB) from the display panel DP. Figure 1The driver integrated circuit DIC can be electrically connected to the conductive lines provided in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as one integrated circuit separate from the display panel DP together with the data driver 130, the voltage generator 140, and the controller 150.

[0086] The display area DA can have various shapes. The display area DA can have a closed loop shape including straight and / or curved sides. For example, the display area DA can have a shape such as a polygonal shape, a circular shape, a semi-circular shape, and an elliptical shape.

[0087] The display panel DP can have a flat display surface. In other embodiments, the display panel DP can have an at least partially rounded display surface. The display panel DP can be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB of the display panel DP can include a material having flexible properties.

[0088] Figure 4 A schematic cross-sectional view of a display panel according to an embodiment is shown. Figure 3 A schematic cross-sectional view of a display panel according to an embodiment is shown.

[0089] Referring to FIG. 1, Figure 4 The display panel DP can include a substrate SUB and a pixel circuit layer PCL, a display element layer DPL, and a light function layer LFL stacked in this order on the substrate SUB in a third direction DR3 intersecting the first direction DR1 and the second direction DR2.

[0090] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB can include a glass substrate. As another example, the substrate SUB can include a polyimide (PI) substrate. As yet another example, the substrate SUB can include a silicon wafer substrate formed using a semiconductor process.

[0091] The substrate SUB can be made of a flexible material to be bendable or foldable, and can have a single-layer structure or a multi-layer structure. For example, the flexible material can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, embodiments are not limited thereto.

[0092] The pixel circuit layer PCL can be provided on the substrate SUB. The pixel circuit layer PCL can include insulating layers and semiconductor patterns and conductive patterns provided between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as circuit elements, conductive lines, etc.

[0093] The circuit elements of the pixel circuit layer PCL can include Figure 3 a sub-pixel circuit SPC (see Figure 2 ) for each of the sub-pixels SP. For example, the circuit elements of the pixel circuit layer PCL can be provided as transistors and one or more capacitors of the sub-pixel circuit SPC.

[0094] The conductive lines of the pixel circuit layer PCL can include conductive lines electrically connected to the sub-pixels SP. The conductive lines of the pixel circuit layer PCL can include various signal lines and / or voltage lines required for driving the display element layer DPL.

[0095] The display element layer DPL can be provided on the pixel circuit layer PCL. The display element layer DPL can include light emitting elements of the sub-pixels SP.

[0096] The light functional layer LFL can be provided on the display element layer DPL. The light functional layer LFL can include a light conversion pattern having color conversion particles and / or scattering particles. For example, the color conversion particles can include quantum dots. The quantum dots can change the wavelength (or color) of light emitted from the display element layer DPL. The light functional layer LFL can further include a light scattering pattern having scattering particles. The light conversion pattern and the light scattering pattern can be omitted.

[0097] The light functional layer LFL can further include a color filter layer including a color filter. The color filter can selectively transmit light of a specific wavelength (or a specific color). The color filter layer can be omitted.

[0098] A window for protecting an exposed surface (or an upper surface) of the display panel DP can be provided on the light functional layer LFL. The window can protect the display panel DP from external impact (or force). The window can be coupled to the light functional layer LFL by an optically transparent adhesive (bonding) member. The window can have a multi-layer structure selected from a glass substrate, a plastic film, and a plastic substrate. The multi-layer structure can be formed by a continuous process or an adhesive process using an adhesive layer. All or a part of the window can be flexible.

[0099] Figure 5 A schematic cross-sectional view of a display panel according to another embodiment is illustrated. Figure 3

[0100] Referring to Figure 5 , the display panel DP' can include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, an input sensing layer ISL, and a light functional layer LFL. Figure 5 The substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL of the display panel DP' are respectively the same as those of the display panel DP of Figure 4 ​The substrate SUB, the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL described are similarly configured. Hereinafter, redundant descriptions thereof will be omitted.

[0101] The input sensing layer ISL can detect a user input on an upper surface (or display surface) of the display panel DP'. The input sensing layer ISL can include components suitable for sensing an external object such as a user's hand or a pen. For example, the input sensing layer ISL can include a touch electrode.

[0102] Figure 6 A schematic cross-sectional view taken along a line I-I' of Figure 3 is shown.

[0103] Referring to Figure 3 and Figure 6 , the pixel circuit layer PCL, the display element layer DPL, and the light functional layer LFL can be sequentially disposed on the substrate SUB in the third direction DR3. The display element layer DPL can include an insulating layer INSL, a light emitting element LD, a first bank BNK1, and a dam member (or dam structure) DAM. The insulating layer INSL can include an overcoat layer OCL and a third passivation layer PSV3.

[0104] The first bank BNK1 can be disposed in the display area DA on the substrate SUB (or the pixel circuit layer PCL). The first bank BNK1 can have a first opening OP1 corresponding to a light emitting area EMA (see Figure 9 ) of the sub-pixel SP in the third direction DR3. For example, the first bank BNK1 can surround the light emitting element LD disposed in the sub-pixel SP, and can have the first opening OP1 corresponding to the light emitting area EMA (see Figure 9 ) of the corresponding light emitting element LD.

[0105] The light emitting element LD can be disposed in the display area DA on the substrate SUB (or the pixel circuit layer PCL). The light emitting element LD can be arranged in the first direction DR1 and / or the second direction DR2. The light emitting elements LD can each overlap the first openings OP1 spaced apart from each other. The light emitting elements LD can be at least partially disposed in the first openings OP1. For example, the first light emitting element LD1, the second light emitting element LD2, the second light emitting element LD3, …, the p-2th light emitting element LDp-2, the p-1th light emitting element LDp-1, and the pth light emitting element LDp can respectively overlap the 1_1th opening OP1_1, the 1_2th opening OP1_2, the 1_3th opening OP1_3, …, the 1_P-2th opening OP1_P-2, the 1_P-1th opening OP1_P-1, and the 1_Pth opening OP1_P. The first light emitting element LD1 to the pth light emitting element LDp can be at least partially disposed in the 1_1th opening OP1_1 to the 1_Pth opening OP1_P, respectively.

[0106] The dam member DAM can be provided in the display region DA on the substrate SUB (or the pixel circuit layer PCL). The dam member DAM can be provided along the edge of the display region DA. The dam member DAM can be provided so as to surround the display region DA in which the light emitting elements LD are provided, in a plan view. For example, in a case where the first to p-th light emitting elements LD1 to LDp are arranged in the first direction DR1, the dam member DAM can be provided in a direction opposite to the first direction DR1 from the first light emitting element LD1. The dam member DAM can be provided in the first direction DR1 from the p-th light emitting element LDp. The dam member DAM can be provided outside the light emitting elements LD in the first direction DR1 and in the direction opposite to the first direction DR1. Further, although not illustrated in FIG. 1, in a case where the light emitting elements LD are arranged in the second direction DR2, the dam member DAM can be provided outside the light emitting elements LD in the second direction DR2 and in the direction opposite to the second direction DR2. Figure 6

[0107] The dam member DAM can be formed integrally with the first bank BNK1, but is not limited thereto, and the dam member DAM can be formed separately from the first bank BNK1.

[0108] Each of the light emitting elements LD can have a first height H1 in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The first height H1 can be a distance between the substrate SUB (or the pixel circuit layer PCL) and an upper surface LTS of the light emitting element LD opposite to the substrate SUB in the third direction DR3. The dam member DAM can have a second height H2 greater than the first height H1 in the third direction DR3. The second height H2 can be a distance between the substrate SUB (or the pixel circuit layer PCL) and an end portion EPT of the dam member DAM opposite to the substrate SUB in the third direction DR3. For example, the dam member DAM can be provided on the pixel circuit layer PCL so as to protrude further than the light emitting element LD in the third direction DR3.

[0109] The first bank BNK1 can be provided on the pixel circuit layer PCL, and can have a third height H3 smaller than the second height H2 of the dam member DAM in the third direction DR3. The third height H3 can be a distance between the substrate SUB (or the pixel circuit layer PCL) and an upper surface BTS of the first bank BNK1 opposite to the substrate SUB in the third direction DR3. Since the first bank BNK1 has the third height H3 smaller than the first height H1 of the light emitting element LD, the light emitting element LD can protrude further than the first bank BNK1 in the third direction DR3.

[0110] ​The display element layer DPL can have a fourth height H4 in the third direction DR3 that is smaller than the second height H2 of the dam member DAM. For example, the fourth height H4 can be smaller than the first height H1 in the third direction DR3, but larger than the third height H3. Thus, unlike the first bank BNK1, the dam member DAM can protrude from the display element layer DPL to the light function layer LFL.

[0111] In other embodiments, the dam member DAM can be provided to protrude in the direction opposite to the substrate SUB along the edge of the display area DA. For example, the dam member DAM can be provided on the same layer as the first bank BNK1 to protrude in the third direction DR3 than the light emitting element LD.

[0112] Figure 7 A schematic top view of one of the pixels PXL according to an embodiment is shown. Figure 3

[0113] Reference is made to Figure 7 The pixel PXL can include the first to third sub-pixels SP1 to SP3. The first to third sub-pixels SP1 to SP3 can be arranged in the first direction DR1. However, the arrangement of the pixel PXL is not limited thereto and can be variously changed in other embodiments. For example, the first to third sub-pixels SP1 to SP3 can be arranged in a zigzag pattern (or shape).

[0114] The first to third anode electrodes AE1 to AE3 can be respectively provided in the first to third sub-pixels SP1 to SP3. The first anode electrode AE1 can be provided as an anode electrode AE (see Figure 2 ) of a sub-pixel circuit SPC (see Figure 2 ) electrically connected to the first sub-pixel SP1. The second anode electrode AE2 can be provided as an anode electrode AE of the sub-pixel circuit SPC electrically connected to the second sub-pixel SP2. The third anode electrode AE3 can be provided as an anode electrode AE of the sub-pixel circuit SPC electrically connected to the third sub-pixel SP3.

[0115] The cathode electrode CE can be spaced apart from the first to third anode electrodes AE1 to AE3. The cathode electrode CE can be provided at the same height as the first to third anode electrodes AE1 to AE3. The cathode electrode CE can be spaced apart from the first to third anode electrodes AE1 to AE3 in the second direction DR2. The cathode electrode CE can extend in the first direction DR1 and serve as a common electrode for the pixel PXL and other pixels adjacent to the pixel PXL. Although not shown, the cathode electrode CE not only extends in the first direction DR1 but also in the second direction DR2 and can serve as a common electrode for Figure 3 ​The common electrode can be provided in all of the subpixels SP. The cathode electrode CE can have various shapes.

[0116] The first to third light emitting elements LD1 to LD3 can be provided on the first to third anode electrodes AE1 to AE3 and the cathode electrode CE. The first light emitting element LD1 can be electrically connected to the first anode electrode AE1 and the cathode electrode CE. The first light emitting element LD1 can be provided as a light emitting element LD electrically connected to the subpixel circuit SPC of the first subpixel SP1 (see Figure 2 ). The second light emitting element LD2 can be electrically connected to the second anode electrode AE2 and the cathode electrode CE. The second light emitting element LD2 can be provided as a light emitting element LD electrically connected to the subpixel circuit SPC of the second subpixel SP2. The third light emitting element LD3 can be electrically connected to the third anode electrode AE3 and the cathode electrode CE. The third light emitting element LD3 can be provided as a light emitting element LD electrically connected to the subpixel circuit SPC of the third subpixel SP3.

[0117] The first to third light emitting elements LD1 to LD3 can be inorganic light emitting diodes including an inorganic light emitting material. However, embodiments are not limited thereto, and for example, organic light emitting diodes can be used.

[0118] Figure 8 A schematic cross-sectional view taken along a line A-A' of Figure 7 is shown.

[0119] Referring to Figure 7 and Figure 8 , the pixel circuit layer PCL, the display element layer DPL, and the light function layer LFL can be sequentially provided on the substrate SUB in the third direction DR3.

[0120] The pixel circuit layer PCL can include insulating layers, semiconductor patterns, and conductive patterns stacked on the substrate SUB. The insulating layers can include the buffer layer BFL, one or more interlayer insulating layers ILD, and one or more passivation layers PSV1 and PSV2. The semiconductor patterns and the conductive patterns can be provided between the insulating layers. The conductive patterns can include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0121] As described with reference to Figure 2 , the subpixel circuit SPC of each of the first to third subpixels SP1 to SP3 can include transistors and one or more capacitors. The semiconductor patterns and the conductive patterns of the pixel circuit layer PCL can be used as the transistors and the capacitors of the subpixel circuit SPC. The conductive patterns of the pixel circuit layer PCL can also be used as a wire, for example, Figure 1The first to m-th gate lines GL1 to GLm, the first to n-th data lines DL1 to DLn, the power line PL, and the pixel control line PXCL in the pixel circuit layer PCL.

[0122] A buffer layer BFL can be provided on the substrate SUB. The buffer layer BFL can prevent impurities from diffusing into circuit elements and conductive lines included in the pixel circuit layer PCL. The buffer layer BFL can include an inorganic insulating layer including an inorganic material. The buffer layer BFL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and a metal oxide such as aluminum oxide (AlO x ). The buffer layer BFL can be provided as a single layer or multiple layers. In the case where the buffer layer BFL is provided as multiple layers, the corresponding layers can be made of the same material or different materials.

[0123] One or more barrier layers can be provided between the substrate SUB and the buffer layer BFL. Each of the barrier layers can include polyimide.

[0124] A transistor T_SP1 can be provided on the buffer layer BFL. The transistor T_SP1 can be one of the transistors of the sub-pixel circuit SPC included in the first sub-pixel SP1. For example, the transistor T_SP1 can be understood as a transistor electrically connected to the first anode electrode AE1 among the transistors of the sub-pixel circuit SPC.

[0125] The transistor T_SP1 can include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 can be one of a source electrode and a drain electrode, and the second terminal ET2 can be the other of the source electrode and the drain electrode. For example, the first terminal ET1 can be the source electrode, and the second terminal ET2 can be the drain electrode.

[0126] The semiconductor pattern SCP can be provided on the buffer layer BFL. The semiconductor pattern SCP can include a first contact region in contact with the first terminal ET1 and a second contact region in contact with the second terminal ET2. A region between the first contact region and the second contact region can be a channel region. The channel region can overlap the gate electrode GE of the transistor T_SP1. The channel region can be a semiconductor pattern that is not doped with impurities, and can be an intrinsic semiconductor. The first contact region and the second contact region can be semiconductor patterns doped with impurities. As the impurities, for example, a p-type impurity can be used, but embodiments are not limited thereto.

[0127] The semiconductor pattern SCP can include one of various types of semiconductors, for example, one of an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polysilicon semiconductor, a low-temperature polysilicon semiconductor, and an oxide semiconductor.

[0128] An interlayer insulating layer ILD can be disposed on the semiconductor pattern SCP in sequence. The interlayer insulating layer ILD can be an inorganic insulating layer including an inorganic material. For example, each of the interlayer insulating layers ILD can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and a metal oxide such as aluminum oxide (AlO x ). However, the interlayer insulating layer ILD is not limited thereto. For example, one of the interlayer insulating layers ILD can include an organic insulating layer including an organic material.

[0129] The interlayer insulating layer ILD can electrically separate the conductive patterns and / or the semiconductor patterns disposed between the interlayer insulating layers ILD from each other. For example, the interlayer insulating layer ILD can include a gate insulating layer GI disposed on the semiconductor pattern SCP. The gate insulating layer GI can be disposed between the semiconductor pattern SCP and the gate electrode GE such that the gate electrode GE is spaced apart from the semiconductor pattern SCP. The gate insulating layer GI can be entirely disposed on the semiconductor pattern SCP and the buffer layer BFL to cover the semiconductor pattern SCP and the buffer layer BFL. As the number of layers required for forming the conductive patterns and / or the semiconductor patterns increases, the number of the interlayer insulating layers ILD can increase.

[0130] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap the channel region of the semiconductor pattern SCP. The gate electrode GE can be provided as a single layer including at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). The gate electrode GE can be provided as a multi-layer including at least one of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag) as a low-resistance material.

[0131] The first terminal ET1 and the second terminal ET2 can be disposed on the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 can contact the semiconductor pattern SCP through a contact hole penetrating the interlayer insulating layer ILD. The first terminal ET1 and the second terminal ET2 can contact a first contact region and a second contact region of the semiconductor pattern SCP, respectively. Each of the first terminal ET1 and the second terminal ET2 can include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0132] Although the first terminal ET1 and the second terminal ET2 are illustrated as separate electrodes electrically connected to the semiconductor pattern SCP, embodiments are not limited thereto. The first terminal ET1 can be a first contact region adjacent to one side of a channel region of the semiconductor pattern SCP, and the second terminal ET2 can be a second contact region adjacent to the other side of the channel region thereof. The first terminal ET1 can be electrically connected to the light emitting element LD through a connection member such as a bridge electrode provided on at least one of the interlayer insulating layers ILD.

[0133] The transistor T_SP1 can be a low-temperature polysilicon transistor. However, embodiments are not limited thereto. For example, the transistor T_SP1 can be an oxide semiconductor transistor. The sub-pixel circuit SPC (see FIG. 1) of the first sub-pixel SP1 can include different types of transistors. For example, the transistor T_SP1 can be a low-temperature polysilicon transistor, and another transistor of the first sub-pixel SP1 can be an oxide semiconductor transistor. The oxide semiconductor of the corresponding oxide semiconductor transistor can be provided on one of the interlayer insulating layers ILD, instead of the insulating layer of the semiconductor pattern SCP on which the transistor T_SP1 is provided thereon. Figure 2 )can include different types of transistors. For example, the transistor T_SP1 can be a low-temperature polysilicon transistor, and another transistor of the first sub-pixel SP1 can be an oxide semiconductor transistor. The sub-pixel circuit SPC (see

[0134] A case in which the transistor T_SP1 is a transistor having a top gate structure has been described as an example, but embodiments are not limited thereto. For example, the transistor T_SP1 can be a transistor having a bottom gate structure. The structure of the transistor T_SP1 can be variously changed.

[0135] At least some of various wirings of the display panel DP and / or the display device DD can also be provided on the interlayer insulating layers ILD.

[0136] The first passivation layer PSV1 can be provided on the interlayer insulating layers ILD and the first terminal ET1 and the second terminal ET2. The passivation layer can also be referred to as a protection layer or a via layer. The first passivation layer PSV1 can protect components provided thereunder, and can provide a flat upper surface.

[0137] The connection pattern CP can be provided on the first passivation layer PSV1. The connection pattern CP can penetrate the first passivation layer PSV1 to be electrically connected to the first terminal ET1 of the transistor T_SP1. The connection pattern CP can include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0138] At least some of various wirings of the display panel DP and / or the display device DD can also be provided on the first passivation layer PSV1.

[0139] A second passivation layer PSV2 can be provided on the connection pattern CP and the first passivation layer PSV1. The second passivation layer PSV2 can protect components provided thereunder, and can provide a flat upper surface.

[0140] Each of the first passivation layer PSV1 and the second passivation layer PSV2 can include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer can include at least one of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and a metal oxide such as aluminum oxide (AlO x ). The organic insulating layer can include at least one of, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0141] The first passivation layer PSV1 and the second passivation layer PSV2 can include the same material as one of the interlayer insulating layers ILD, but embodiments are not limited thereto. Each of the first passivation layer PSV1 and the second passivation layer PSV2 can be provided as a single layer, but can also be provided as multiple layers.

[0142] A display element layer DPL can be provided on the second passivation layer PSV2. The display element layer DPL can include a first anode electrode AE1, a cathode electrode CE, a first bank BNK1, a first reflective electrode RFE1 and a second reflective electrode RFE2, a first light emitting element LD1, an overcoat layer OCL, a third passivation layer PSV3, and a capping layer CPL.

[0143] The first anode electrode AE1 and the cathode electrode CE can be provided on the pixel circuit layer PCL.

[0144] The first anode electrode AE1 can be electrically connected to the connection pattern CP through a contact hole that penetrates the second passivation layer PSV2. For example, the first anode electrode AE1 can be electrically connected to the transistor T_SP1.

[0145] The cathode electrode CE can be spaced apart from the first anode electrode AE1 in the first direction DR1. The cathode electrode CE can be electrically connected to Figure 2 a second power voltage node VSSN. Accordingly, a second power voltage applied to the second power voltage node VSSN can be transmitted to the cathode electrode CE.

[0146] The first bank BNK1 can be disposed on the first anode electrode AE1 and the cathode electrode CE. The first bank BNK1 can have a first opening OP1 exposing a portion of the first anode electrode AE1 and the cathode electrode CE. The first light emitting element LD1 can be disposed in the first opening OP1 of the first bank BNK1. The first bank BNK1 can be provided as a pixel defining film defining a region in which the first light emitting element LD1 is disposed.

[0147] The first bank BNK1 can include a light blocking material, thereby preventing light mixing between adjacent sub-pixels SP (see Figure 1 The first bank BNK1 can include an organic material. For example, the first bank BNK1 can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

[0148] The first reflective electrode RFE1 can be disposed on the exposed portion of the first anode electrode AE1 and a side surface of the first bank BNK1 adjacent to the first anode electrode AE1. The second reflective electrode RFE2 can be disposed on the exposed portion of the cathode electrode CE and a side surface of the first bank BNK1 adjacent to the cathode electrode CE. The first reflective electrode RFE1 and the second reflective electrode RFE2 can include a conductive material suitable for reflecting light. Accordingly, light emitting efficiency of the first light emitting element LD1 can be improved. The first reflective electrode RFE1 and the second reflective electrode RFE2 can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, embodiments are not limited thereto.

[0149] The first light emitting element LD1 can be electrically connected to the first anode electrode AE1 through the first reflective electrode RFE1. The first light emitting element LD1 can be electrically connected to the cathode electrode CE through the second reflective electrode RFE2. The first light emitting element LD1 can be bonded to and coupled in parallel to the first reflective electrode RFE1 and the second reflective electrode RFE2.

[0150] The first light emitting element LD1 can include a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an auxiliary layer 15. The first light emitting element LD1 can include a light emitting stack in which the second semiconductor layer 13, the active layer 12, the first semiconductor layer 11, and the auxiliary layer 15 are sequentially stacked in a third direction DR3.

[0151] The first light emitting element LD1 can include a first bonding electrode BDE1 and a second bonding electrode BDE2 facing in the same direction (e.g., a direction opposite to the third direction DR3). The first bonding electrode BDE1 can be electrically connected to the second semiconductor layer 13. The second bonding electrode BDE2 can be electrically connected to the first semiconductor layer 11 exposed by etching the second semiconductor layer 13 and the active layer 12. The first light emitting element LD1 can be a flip chip type light emitting element.

[0152] The first semiconductor layer 11 can provide electrons to the active layer 12. For example, the first semiconductor layer 11 can include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and can be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), or the like. However, the material included in the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 can be made of various materials. For example, the first semiconductor layer 11 can include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). In other embodiments, the first semiconductor layer 11 can form an n-type semiconductor layer together with the auxiliary layer 15.

[0153] The active layer 12 can be disposed on the first semiconductor layer 11, and electrons and holes are recombined in the active layer 12. When the electrons and holes are recombined in the active layer 12, the electrons and holes can move to a low energy level, and thus, light having a wavelength corresponding to the low energy level can be generated. The active layer 12 can have a single quantum well structure or a multiple quantum well structure. In the case where the active layer 12 is formed as a multiple quantum well structure, a unit including a barrier layer, a strain enhancement layer, and a well layer can be repeatedly stacked to form the active layer 12. However, embodiments of the active layer 12 are not limited thereto.

[0154] The second semiconductor layer 13 can be provided on the active layer 12 and provide holes into the active layer 12. The second semiconductor layer 13 can include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 can include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 can include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and can be a p-type semiconductor layer doped with a second conductive dopant (or a p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material included in the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 can be formed of various materials. For example, the second semiconductor layer 13 can include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or a p-type dopant).

[0155] The auxiliary layer 15 can include a gallium nitride (GaN) semiconductor material not doped with an impurity, and can form an n-type semiconductor layer together with the first semiconductor layer 11.

[0156] The first bonding electrode BDE1 can be electrically connected to the second semiconductor layer 13. The second bonding electrode BDE2 can be electrically connected to the first semiconductor layer 11. The first bonding electrode BDE1 and the second bonding electrode BDE2 can include a eutectic metal.

[0157] The first light emitting element LD1 can further include an insulating film 16 covering an outer circumferential surface of the light emitting stack (or structure). The insulating film 16 can prevent a short circuit that can occur in a case where the active layer 12 contacts other conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 16 can include a transparent insulating material. The insulating film 16 can expose lower surfaces of the first bonding electrode BDE1 and the second bonding electrode BDE2.

[0158] The first coupling member CMB1 can be disposed between the first light emitting element LD1 and the first anode electrode AE1. The second coupling member CMB2 can be disposed between the first light emitting element LD1 and the cathode electrode CE. The first coupling member CMB1 and the second coupling member CMB2 can be disposed on one surface of the light emitting stack facing the substrate SUB. The first coupling member CMB1 and the second coupling member CMB2 can be disposed on one surface of the first bonding electrode BDE1 and the second bonding electrode BDE2. The first coupling member CMB1 can be disposed between the first bonding electrode BDE1 and the first anode electrode AE1. The second coupling member CMB2 can be disposed between the second bonding electrode BDE2 and the cathode electrode CE.

[0159] The first and second coupling members CMB1 and CMB2 can be joined to the first and second reflective electrodes RFE1 and RFE2. The first and second coupling members CMB1 and CMB2 and the first and second reflective electrodes RFE1 and RFE2 can be joined by applying heat to an area in contact with each other. In an area in which the first and second coupling members CMB1 and CMB2 are in contact with the first and second reflective electrodes RFE1 and RFE2, the first and second coupling members CMB1 and CMB2 and the first and second reflective electrodes RFE1 and RFE2 can be joined to each other by forming an alloy.

[0160] The first and second coupling members CMB1 and CMB2 can include an Sn-Ag-Cu (SAC) alloy. However, this is an example, and the first and second coupling members CMB1 and CMB2 can include various known metallic materials and / or an alloy of at least two or more metallic materials selected therefrom.

[0161] A lower surface of the first bonding electrode BDE1 can be in contact with the first reflective electrode RFE1. Accordingly, the first bonding electrode BDE1 can be electrically connected to the first anode electrode AE1 through the first reflective electrode RFE1. A lower surface of the second bonding electrode BDE2 can be in contact with the second reflective electrode RFE2. Accordingly, the second bonding electrode BDE2 can be electrically connected to the cathode electrode CE through the second reflective electrode RFE2.

[0162] An overcoat layer OCL can be disposed in the first opening OP1 in which the first and second reflective electrodes RFE1 and RFE2 and the first light emitting element LD1 are disposed. The overcoat layer OCL can fixedly join the first light emitting element LD1 to the first and second reflective electrodes RFE1 and RFE2 so that the first light emitting element LD1 does not move. The overcoat layer OCL can protect components disposed thereunder from foreign substances such as dust and moisture. For example, the overcoat layer OCL can include at least one of an inorganic insulating film and an organic insulating film. For example, the overcoat layer OCL can include an epoxy resin, but embodiments are not limited thereto.

[0163] A third passivation layer PSV3 can be disposed on the first bank BNK1 and the overcoat layer OCL. The third passivation layer PSV3 can protect components disposed thereunder and can provide a flat upper surface. The third passivation layer PSV3 can include the same material as one of the first and second passivation layers PSV1 and PSV2, but embodiments are not limited thereto.

[0164] The third passivation layer PSV3 can not be provided on the upper surface LTS of the first light emitting element LD1. The first light emitting element LD1 can protrude into the light functional layer LFL. The first light emitting element LD1 can be at least partially provided in the second opening OP2 of the second bank BNK2. For example, the height of the upper surface LTS of the first light emitting element LD1 from the substrate SUB can be higher than the lowermost end RBE of the reflective layer RFL. Thus, light emitted from the first light emitting element LD1 can be provided to the light functional layer LFL at a relatively high proportion.

[0165] The cap layer CPL can be provided on the third passivation layer PSV3. The cap layer CPL can protect components, such as the first light emitting element LD1, under the cap layer CPL from external moisture and humidity. The cap layer CPL can not be provided on the upper surface of the first light emitting element LD1. In other embodiments, the cap layer CPL can completely cover the first light emitting element LD1 and the third passivation layer PSV3. The cap layer CPL can include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and a metal oxide such as aluminum oxide (AlO x ). However, the material of the cap layer CPL is not limited thereto.

[0166] The pixel circuit layer PCL and the display element layer DPL of the first sub-pixel SP1 have been described above. In a range not otherwise described herein, Figure 6 Each of the second sub-pixel SP2 and the third sub-pixel SP3 can be configured similarly to the first sub-pixel SP1.

[0167] The light functional layer LFL can be provided on the cap layer CPL. The light functional layer LFL can include the second bank BNK2, the reflective layer RFL, the fourth passivation layer PSV4, the first light conversion pattern CCP1, the low refractive layer LRL, and the color filter layer CFL.

[0168] The second bank BNK2 can be provided on the cap layer CPL. The second bank BNK2 can overlap the first bank BNK1 in the third direction DR3. The second bank BNK2 can have a second opening OP2 overlapping the first opening OP1. For example, in a plan view, the diameter of the second opening OP2 can be greater than the diameter of the first opening OP1.

[0169] The second bank BNK2 can include a light blocking material to prevent adjacent sub-pixels SP (see Figure 1The second bank BNK2 can include an organic material. For example, the second bank BNK2 can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

[0170] The reflective layer RFL can be disposed on a side surface of the second bank BNK2 adjacent to the second opening OP2. The reflective layer RFL can reflect incident light, thereby improving the efficiency of the outgoing light. The reflective layer RFL can include a material suitable for reflecting light. The reflective layer RFL can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, embodiments are not limited thereto.

[0171] The fourth passivation layer PSV4 can be disposed in the second opening OP2 on the capping layer CPL. The fourth passivation layer PSV4 can protect components disposed thereunder and can provide a flat upper surface. The fourth passivation layer PSV4 can include the same material as one of the first passivation layer PSV1 to the third passivation layer PSV3, but embodiments are not limited thereto.

[0172] The first light conversion pattern CCP1 can be disposed in the second opening OP2 on the fourth passivation layer PSV4.

[0173] The first light conversion pattern CCP1 can include color conversion particles and / or scattering particles. The color conversion particles can convert incident light into light of a different color by changing the wavelength of the incident light. The color conversion particles can scatter incident light. The color conversion particles can be quantum dots. However, embodiments are not limited thereto. The scattering particles can scatter incident light.

[0174] The first sub-pixel SP1 can be a red sub-pixel. In the case where the first light emitting element LD1 emits blue light, the first light conversion pattern CCP1 can include first color conversion particles QD1 to convert the blue light into red light. In the case where the first light emitting element LD1 emits red light, the first light conversion pattern CCP1 can include scattering particles. The particles included in the first light conversion pattern CCP1 can vary variously according to the first light emitting element LD1.

[0175] The low-refractive layer LRL can be disposed on the second bank BNK2, the reflection layer RFL, and the first light conversion pattern CCP1. The low-refractive layer LRL can have a lower refractive index than the first light conversion pattern CCP1. The low-refractive layer LRL can refract or totally reflect the corresponding light according to an incident angle of the light. For example, the low-refractive layer LRL can provide the light that has passed through the first light conversion pattern CCP1 back to the first light conversion pattern CCP1. Accordingly, the light conversion efficiency of the first light conversion pattern CCP1 can be improved.

[0176] The color filter layer CFL can be disposed on the low-refractive layer LRL. The color filter layer CFL can include a first color filter CF1 and a light blocking pattern LBP. The first color filter CF1 can overlap the first light conversion pattern CCP1 in the third direction DR3. The first color filter CF1 can selectively transmit light in a desired wavelength range. In a case where the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 can include a red color filter. The light blocking pattern LBP can include at least one of various types of light blocking materials.

[0177] Figure 9 A schematic cross-sectional view taken along line B-B' of Figure 7 is shown.

[0178] Referring to Figure 7 and Figure 9 , the pixel circuit layer PCL, the display element layer DPL, and the light function layer LFL can be sequentially disposed on the substrate SUB.

[0179] Figure 9 The pixel circuit layer PCL and the display element layer DPL of FIG. 1A can be configured similarly to those described with reference to Figure 8 . In the pixel circuit layer PCL, sub-pixel circuits SPC corresponding to the first to third sub-pixels SP1 to SP3 can be provided (see FIG. 2A). In the display element layer DPL, first to third light emitting elements LD1 to LD3 corresponding to the first to third sub-pixels SP1 to SP3, respectively, can be provided. The first to third light emitting elements LD1 to LD3 can overlap the first opening OP1 of the first bank BNK1. The first light emitting element LD1 can be electrically connected between the cathode electrode CE (see FIG. 2A) and a transistor T_SP1 (see FIG. 2A) included in the sub-pixel circuit SPC (see FIG. 2A) of the first sub-pixel SP1. The second light emitting element LD2 can be electrically connected between the cathode electrode CE and a transistor T_SP2 (see FIG. 2A) included in the sub-pixel circuit SPC (see FIG. 2A) of the second sub-pixel SP2. The third light emitting element LD3 can be electrically connected between the cathode electrode CE and a transistor T_SP3 (see FIG. 2A) included in the sub-pixel circuit SPC (see FIG. 2A) of the third sub-pixel SP3. Figure 2 Figure 8 Figure 2 Figure 8 Figure 2 ​​​​The third light emitting element LD3 can be electrically connected between the transistor included in the third sub-pixel circuit SPC (see Figure 2 ) and the transistor included in the third sub-pixel circuit SPC (see

[0180] The light functional layer LFL can be provided on the display element layer DPL. Figure 9 The light functional layer LFL of the display element layer DPL can be configured similarly to the light functional layer LFL described with reference to Figure 8 The light functional layer LFL of the display element layer DPL can be configured similarly to the light functional layer LFL described with reference to

[0181] The second bank BNK2 has the second opening OP2. The light emitting area EMA and the non-light emitting area NEMA for the first to third sub-pixels SP1 to SP3 are defined by the second bank BNK2. The area overlapping with the second bank BNK2 can correspond to the non-light emitting area NEMA. The area overlapping with the second opening OP2 of the second bank BNK2 can correspond to the light emitting area EMA of the first to third sub-pixels SP1 to SP3.

[0182] The fourth passivation layer PSV4 can be provided on the capping layer CPL in the second opening OP2. On the fourth passivation layer PSV4, the first and second color conversion patterns CCP1 and CCP2 and the light scattering pattern LSP can be provided in the second opening OP2.

[0183] The first to third light emitting elements LD1 to LD3 can emit blue light. The first color conversion pattern CCP1 can include first color conversion particles QD1 to convert the blue light into red light. The second color conversion pattern CCP2 can include second color conversion particles QD2 to convert the blue light into green light. The light scattering pattern LSP can include scattering particles SCT to scatter the blue light so as to improve light output efficiency. Accordingly, the first to third sub-pixels SP1 to SP3 can be provided as red, green, and blue sub-pixels, respectively. At least one of the first and second color conversion patterns CCP1 and CCP2 and the light scattering pattern LSP can further include color conversion particles to convert the blue light into white light.

[0184] The first to third light emitting elements LD1 to LD3 can emit red, green, and blue light, respectively. For example, each of the first and second color conversion patterns CCP1 and CCP2 and the light scattering pattern LSP can include scattering particles SCT. As described above, the particles included in the first and second color conversion patterns CCP1 and CCP2 and the light scattering pattern LSP can vary according to the first to third light emitting elements LD1 to LD3.

[0185] The first light conversion pattern CCP1 and the second light conversion pattern CCP2 and the light scattering pattern LSP can be omitted.

[0186] The low-refractive layer LRL can be disposed on the second bank BNK2, the reflection layer RFL, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP. The low-refractive layer LRL can have a lower refractive index than the first light conversion pattern CCP1 and the second light conversion pattern CCP2 and the light scattering pattern LSP. The low-refractive layer LRL can be omitted in a region corresponding to the third sub-pixel SP3.

[0187] The color filter layer CFL can be disposed on the low-refractive layer LRL. The color filter layer CFL can include the first to third color filters CF1 to CF3 and a light-blocking pattern LBP.

[0188] Each of the first to third color filters CF1 to CF3 can selectively transmit light in a desired wavelength range. In the case where the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 can include a red color filter. In the case where the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 can include a green color filter. In the case where the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 can include a blue color filter. The first to third color filters CF1 to CF3 can have a higher refractive index than the low-refractive layer LRL. However, embodiments are not limited thereto, and the first to third color filters CF1 to CF3 can have a refractive index lower than or equal to the refractive index of the low-refractive layer LRL.

[0189] The light-blocking pattern LBP can be disposed between the first to third color filters CF1 to CF3 and spaced apart from each other in the first direction DR1. The light-emitting area EMA and the non-light-emitting area NEMA for the first to third sub-pixels SP1 to SP3 can be defined by the light-blocking pattern LBP. An area overlapping the light-blocking pattern LBP can correspond to the non-light-emitting area NEMA. An area not overlapping the light-blocking pattern LBP can correspond to the light-emitting area EMA.

[0190] Light-blocking patterns (LBPs) can include at least one of various types of light-blocking materials. Each of the light-blocking patterns (LBPs) can be provided as a multilayer in which at least two of the first color filters (CF1) to the third color filters (CF3) overlap. For example, each of the light-blocking patterns (LBPs) can be formed by overlapping the first color filters (CF1) to the third color filters (CF3). In another example, the light-blocking pattern between the first color filters (CF1) and the second color filters (CF2) in the light-blocking pattern (LBP) can be formed as a multilayer in which the first color filters (CF1) and the second color filters (CF2) overlap, and the light-blocking pattern between the second color filters (CF2) and the third color filters (CF3) in the light-blocking pattern (LBP) can be formed as a multilayer in which the second color filters (CF2) and the third color filters (CF3) overlap. The light-blocking pattern between the first color filters (CF1) and the third color filters (CF3) of adjacent pixels can be formed as a multilayer in which the first color filters (CF1) and the third color filters (CF3) overlap. Each of the first color filters (CF1) to the third color filters (CF3) can extend to the non-emitting region (NEMA) to form the light-blocking pattern (LBP).

[0191] Figure 10 A schematic flowchart of a method for manufacturing a display device according to an embodiment is shown.

[0192] refer to Figure 10 The method of manufacturing a display device DD according to the embodiment may include: forming a dam with an opening on a display area of ​​a substrate (S100); forming a dam member (or structure) disposed along the edge of the display area on the display area of ​​the substrate (S110); aligning the light-emitting element of the carrier substrate and the opening of the substrate to face each other (S120); moving the carrier substrate toward the substrate to at least partially dispose the light-emitting element in the opening (S130); and separating the carrier substrate from the light-emitting element (S140).

[0193] Figures 11 to 15 schematically shown Figure 10 Methods for manufacturing display devices.

[0194] Figure 11 It shows Figure 10 Schematic cross-sectional views in S100 and S110. In the following text, Figures 11 to 15 Each line I-I' in the middle is used to connect with Figure 3 The cutting plane line at the same position as line I-I' in the middle.

[0195] In the following text, reference will be made to Figures 11 to 15 Description of manufacturing reference Figure 6 The method described for a display device. Figures 11 to 15 The description has already referenced Figure 6 The description of the content can be omitted.

[0196] The pixel circuit layer PCL on the substrate SUB can be formed based on a conventional process for manufacturing a semiconductor device. For example, a conductive layer or an insulating layer included in the pixel circuit layer PCL can be formed by a photolithography process. In other examples, a conductive layer or an insulating layer included in the pixel circuit layer PCL can be etched by various methods (wet etching, dry etching, etc.), and can be deposited by various methods (sputtering, chemical vapor deposition, etc.). However, embodiments are not limited thereto.

[0197] Referring to Figure 3 , Figure 10 and Figure 11 , in S100, a first bank BNK1 can be formed on the substrate SUB (or the pixel circuit layer PCL).

[0198] The first bank BNK1 can be formed by applying an organic material including a light-blocking material on the pixel circuit layer PCL, and then patterning it using a mask. The first bank BNK1 can be formed in the display area DA on the substrate SUB in the third direction DR3, the substrate SUB extending in the first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first bank BNK1 can have a third height H3 in the third direction DR3.

[0199] The first bank BNK1 can protrude in the third direction DR3, and can be formed to have a first opening OP1. An overcoat layer OCL can be provided in the first opening OP1 of the first bank BNK1. Thereafter, light-emitting elements LD (see Figure 12 ) can be respectively provided in the first opening OP1 on the overcoat layer OCL. Accordingly, the first opening OP1 of the first bank BNK1 can correspond to a light-emitting area EMA (see Figure 9 ).

[0200] In S110, a dam member DAM can be formed on the substrate SUB (or the pixel circuit layer PCL).

[0201] The dam member (or structure) DAM can be formed by patterning the pixel circuit layer PCL using a mask. The dam member DAM can be formed in the display area DA in the third direction DR3, and can be provided along an edge of the display area DA. For example, the dam member DAM can have a second height H2 greater than the third height H3 in the third direction DR3.

[0202] Although Figure 11The first bank BNK1 and the dam member DAM are shown to be formed sequentially, but the present disclosure is not limited thereto. For example, the first bank BNK1 and the dam member DAM are formed in the same process, but they can be formed to have different heights. For example, the first bank BNK1 and the dam member DAM can be formed to have different heights by a patterning process using a multi-halftone mask. The multi-halftone mask has slits formed in partial regions so that the amount of light transmission can vary depending on the region. Due to the difference in the amount of light transmission, the degree of etching can vary for each region. However, embodiments are not limited thereto.

[0203] The heights H2 and H3 of the first bank BNK1 and the dam member DAM can be changed by adjusting the amount of light transmission using a mask. For example, the first bank BNK1 can be formed to have a relatively low height by increasing the amount of light transmission. By reducing the amount of light transmission, the dam member DAM can be formed to have a relatively high height. By reducing the amount of light transmission to the edge region of the display area DA using a mask, a relatively high dam member DAM than the first bank BNK1 can be provided.

[0204] Figure 12 The schematic cross-sectional view in S120 is shown. Figure 10

[0205] Referring to Figure 3 , Figure 10 and Figure 12 , before S120, a light emitting element LD can be formed on the carrier substrate C_SUB or one surface SS1 of the carrier substrate C_SUB. The method of forming the light emitting element LD on the carrier substrate C_SUB or one surface SS1 of the carrier substrate C_SUB is not limited. For example, various known semiconductor manufacturing methods can be applied.

[0206] The carrier substrate C_SUB can be a substrate for forming the light emitting element LD. For example, the light emitting element LD can be formed by growing on a semiconductor substrate such as a silicon wafer. For example, the light emitting element LD can be configured similarly to the first light emitting element LD1 described with reference to Figure 8 .

[0207] Thereafter, the light emitting element LD can be transferred onto the overcoat layer OCL (or the anode electrode) on the substrate SUB by an imprint method using an elastic polymer material as a transfer substrate. Accordingly, the carrier substrate C_SUB can include an adhesive layer ADL on one surface SS1 of the carrier substrate C_SUB. The adhesive layer ADL can be disposed between the carrier substrate C_SUB and the light emitting element LD. For example, the adhesive layer ADL can include polydimethylsiloxane (PDMS), but is not limited thereto.

[0208] ​In S120, the carrier substrate C SUB and the substrate SUB can be aligned with each other. By moving the carrier substrate C SUB in the first direction DR1 and / or the second direction DR2, the light emitting elements LD on the carrier substrate C SUB and the first openings OP1 on the substrate SUB can be aligned to face each other in the third direction DR3. The carrier substrate C SUB can be aligned such that the light emitting elements LD are disposed on the overcoat layer OCL on the substrate SUB.

[0209] Figure 13 A schematic cross-sectional view in S130 is shown. Figure 10

[0210] Referring to Figure 3 , Figure 10 and Figure 13 , in S130, by moving the carrier substrate C SUB toward the substrate SUB, the light emitting elements LD can be at least partially disposed in the first openings OP1. The carrier substrate C SUB can be moved toward the substrate SUB in a direction opposite to the third direction DR3, and thus, the light emitting elements LD can be partially embedded in the overcoat layer OCL disposed in each of the first openings OP1. However, this is an example, and the disclosure is not limited thereto. For example, the overcoat layer OCL is only partially disposed in a region adjacent to a lower portion of the light emitting element LD, so that the light emitting element LD can not be partially embedded in the overcoat layer OCL.

[0211] Thereafter, heat or pressure can be applied to another surface SS2 of the carrier substrate C SUB opposite to one surface SS1. For example, heat and pressure can be applied by irradiating a laser LS. Thus, the light emitting elements LD on the carrier substrate C SUB can be joined to the anode electrodes AE (see Figure 2 ) on the substrate SUB. This can be performed by applying heat and pressure to a region in which the light emitting elements LD and the anode electrodes AE (see Figure 2 ) contact each other at a certain temperature. The light emitting elements LD and the anode electrodes AE (see Figure 2 ) can be joined by a joining member including a Sn-Ag-Cu (SAC) alloy in a region in which the light emitting elements LD and the anode electrodes AE (see Figure 2 ) contact each other.

[0212] The adhesive layer ADL disposed between the carrier substrate C SUB and the light emitting elements LD can expand according to heat and pressure. Since the joining member is melted by heat, the light emitting elements LD cannot be fixed to the substrate SUB, and can move radially as the adhesive layer ADL expands. In the case where the light emitting elements LD unexpectedly move, the light emitting elements LD and the substrate SUB (or the anode electrodes AE (see Figure 2 ​) will be misaligned. Thus, the electrical connection between the light emitting elements LD and the substrate SUB (or the anode electrodes AE (see Figure 2 ) can become unstable, and the display quality of the display device can be relatively low.

[0213] The dam member DAM can protrude towards the carrier substrate C SUB along the edge of the display area DA. For example, the dam member DAM can protrude in the third direction DR3 by a second length L2 that is larger than the sum of the first length LI of the light emitting elements LD and the third length L3 of the first bank BNK1. Thus, the dam member DAM can block or at least reduce the expansion of the adhesive layer ADL according to heat and pressure by penetrating the adhesive layer ADL on the carrier substrate C SUB during the bonding process, thereby suppressing or preventing unintended movement of the light emitting elements LD.

[0214] Figure 14 A schematic cross-sectional view in S140 of Figure 10 is shown.

[0215] With reference to Figure 3 , Figure 10 and Figure 14 , in S140, the carrier substrate C SUB can be separated from the light emitting elements LD. By moving the carrier substrate C SUB in a direction away from the substrate SUB, the carrier substrate C SUB can be separated from the light emitting elements LD. The bonding between the light emitting elements LD and the anode electrodes AE (see Figure 2 ) can be maintained. The adhesion between the light emitting elements LD and the overcoat layer OCL can be maintained. For example, in S130, the light emitting elements LD can maintain their substantially same positions at which they are attached to the overcoat layer OCL.

[0216] The bonding force between the adhesive layer ADL (see Figure 12 ) and the light emitting elements LD can be weaker than the bonding force between the light emitting elements LD and the overcoat layer OCL. Thus, the carrier substrate C SUB is separated from the light emitting elements LD, but the adhesion between the light emitting elements LD and the overcoat layer OCL can be maintained.

[0217] Figure 15 A schematic cross-sectional view after S140 of Figure 10 is shown.

[0218] With reference to Figure 3 , Figure 9 , Figure 10 and Figure 15Following S140, a light functional layer LFL can be further formed on the display element layer DPL, which includes the light-emitting element LD. For example, a third passivation layer PSV3 and a capping layer CPL can be further formed. A display panel DP, including a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, and a light functional layer LFL, can be formed. Since the dam member DAM is not separated from the substrate SUB along with the carrier substrate C_SUB, the display element layer DPL can include an outer coating OCL, a third passivation layer PSV3, a light-emitting element LD, a first dam BNK1, and a dam member DAM.

[0219] Figure 16 A schematic flowchart of a method for manufacturing a display device according to another embodiment of the present disclosure is shown.

[0220] refer to Figure 16 A method for manufacturing a display device DD according to another embodiment may include: forming a dam with an opening on a display area of ​​a substrate (S100'); forming a dam member corresponding to the edge of the display area on a surface of a carrier substrate on which a light-emitting element is disposed (S110'); aligning the light-emitting element of the carrier substrate and the opening of the substrate so that they face each other (S120'); moving the carrier substrate toward the substrate to at least partially dispose the light-emitting element in the opening (S130'); and separating the carrier substrate from the light-emitting element (S140').

[0221] Figures 17 to 22 The manufacturing process is illustrated schematically. Figure 16 Methods for displaying devices.

[0222] Figure 17 It shows Figure 16 A schematic cross-sectional view of S100'. In the following text, Figures 17 to 22 Each line I-I' in the diagram is understood to be used with... Figure 3 The cutting plane line at the same position as line I-I' in the middle.

[0223] In the following text, reference will be made to Figures 17 to 22 Description Reference Figure 6 A method for manufacturing a display device is described. Figures 17 to 22 The description has already referenced Figure 6 The description of the content can be omitted.

[0224] The pixel circuit layer (PCL) on the substrate SUB can be formed using conventional processes for manufacturing semiconductor devices. For example, the conductive or insulating layer included in the pixel circuit layer PCL can be formed using a photolithography process. Alternatively, the conductive or insulating layer included in the pixel circuit layer PCL can be etched using various methods (wet etching, dry etching, etc.) and deposited using various methods (sputtering, chemical vapor deposition, etc.). However, the implementation is not limited to these methods.

[0225] refer to Figure 3 , Figure 16 and Figure 17 In S100', a first dam BNK1 can be formed on the substrate SUB (or pixel circuit layer PCL). The method for forming the first dam BNK1 with a first opening OP1 on the display area DA of the substrate SUB (or pixel circuit layer PCL) can be the same as the referenced method. Figure 11 The configurations described are similar. Redundant descriptions will be omitted below. However, it is possible to form the dam structure DAM (see [reference]) without using the substrate SUB (or pixel circuit layer PCL). Figure 6 ).

[0226] Figure 18 It shows Figure 16 A schematic cross-sectional view of S110'.

[0227] refer to Figure 3 , Figure 16 and Figure 18 In S110', a dam member DAM' can be formed on a carrier substrate C_SUB' or a surface SS1 of the carrier substrate C_SUB'.

[0228] The dam member DAM' can be formed as an adhesive layer ADL extending through one surface SS1 of the carrier substrate C_SUB'. For example, the dam member DAM' can be formed separately and then attached to the adhesive layer ADL. However, it is not limited to this. For example, the dam member DAM' can be formed directly on one surface SS1 of the carrier substrate C_SUB'. The adhesive layer ADL may not need to be inserted between the dam member DAM' and the carrier substrate C_SUB'.

[0229] A dam member DAM' can be formed from one surface SS1 of the carrier substrate C_SUB' in a direction opposite to the third direction DR3 toward the substrate SUB. The dam member DAM' can be configured to correspond to the edge of the display area DA on the substrate SUB. For example, the dam member DAM' can have a second length L2 on the third direction DR3 that is longer than the first length L1 of the light-emitting element LD. Therefore, the dam member DAM' attached to the carrier substrate C_SUB' can protrude further from the light-emitting element LD in a direction opposite to the third direction DR3.

[0230] Therefore, the dam component DAM' can block the expansion of the adhesive layer ADL due to heat and pressure by penetrating the carrier substrate C_SUB' during the bonding process, and can suppress or prevent the unintended movement of the light-emitting element LD.

[0231] refer to Figure 3 , Figure 16 and Figure 18 A light-emitting element (LD) can be formed on one surface SS1 of the carrier substrate C_SUB'. The method for forming the carrier substrate C_SUB' and the light-emitting element LD on the carrier substrate C_SUB' can be compared with the reference... Figure 12 The similar configurations described below will be omitted from the following text.

[0232] Figure 19 It shows Figure 16 A sectional view of S120'.

[0233] refer to Figure 3 , Figure 16 and Figure 19 In S120', the carrier substrate C_SUB' and the substrate SUB can be aligned with each other. The method of aligning the light-emitting element of the carrier substrate and the opening of the substrate so that they face each other can be used with reference. Figure 12 The similar configurations described below will be omitted from the following text.

[0234] Figure 20 It shows Figure 16 A sectional view of S130'.

[0235] refer to Figure 3 , Figure 16 and Figure 20 In S130', by moving the carrier substrate C_SUB' toward the substrate SUB, the light-emitting element LD can be at least partially disposed in the first opening OP1. Thereafter, heat or pressure can be applied to the other surface SS2 of the carrier substrate C_SUB' opposite one surface SS1. The step of at least partially disposing the light-emitting element LD in the first opening OP1 and applying heat or pressure can be referenced. Figure 13 The similar configurations described below will be omitted from the following text.

[0236] The dam member DAM' may protrude from one surface SS1 of the carrier substrate C_SUB' toward the substrate SUB along the edge of the display area DA. For example, the dam member DAM' may protrude a second length L2 on the third direction DR3 (see...). Figure 18 The second length L2 is greater than the first length L1 of the light-emitting element LD (see...). Figure 18The sum of the length L3 of the first dike BNK1 and the length L3 of the third dike.

[0237] Figure 21 It shows Figure 16 A schematic cross-sectional view of S140'.

[0238] refer to Figure 3 , Figure 16 and Figure 21 In S140', the carrier substrate C_SUB' can be separated from the light-emitting element LD by moving the carrier substrate C_SUB' in a direction away from the substrate SUB. The method for separating the carrier substrate C_SUB' from the light-emitting element LD can be the same as described in the reference. Figure 14 The configurations described are similar. Redundant descriptions will be omitted below. However, the dam component DAM' can be separated from the substrate SUB along with the carrier substrate C_SUB'. For example, the light-emitting element LD remains attached to the outer coating OCL on the substrate SUB, but the dam component DAM' can be separated from the substrate SUB.

[0239] Figure 22 It shows in Figure 16 The sectional view after S140'.

[0240] refer to Figure 3 , Figure 9 , Figure 16 and Figure 22 Following S140', a light functional layer LFL can be further formed on the display element layer DPL, which includes the light-emitting element LD. A display panel DP, including a substrate SUB, a pixel circuit layer PCL, a display element layer DPL', and a light functional layer LFL, can be formed. Since the dam member DAM' is separated from the substrate SUB along with the carrier substrate C_SUB', the display element layer DPL' can include an outer coating OCL, a third passivation layer PSV3, a light-emitting element LD, and a first dam BNK1, and may not include the dam member DAM'.

[0241] Figure 23 An embodiment according to another embodiment is shown. Figure 1 A schematic top view of the display panel.

[0242] refer to Figure 23 The display panel DP' may include a substrate SUB, a display area DA, a non-display area NDA, pixels PXL, sub-pixels SP, and dam components DAM. The substrate SUB, display area DA, non-display area NDA, pixels PXL, sub-pixels SP, and dam components DAM may be referenced. Figure 3 The similar configurations described below will be omitted from the following text.

[0243] The display panel DP' may include a first embankment BNK1' having substantially the same height as the dam component DAM. The area where the first embankment BNK1' is located may be a non-luminous area NEMA (see [link to relevant documentation]). Figure 26 The first dam BNK1' can be configured to surround each of the sub-pixels SP in the plan view. The first dam BNK1' can be configured in the region surrounded by the dam member DAM to be spaced apart from each other on the first direction DR1 and the second direction DR2 intersecting the first direction DR1.

[0244] A first dam BNK1' having substantially the same height as the dam component DAM can be positioned between sub-pixels SP. For example, the first dam BNK1' can be positioned between the first sub-pixel SP1 and the second sub-pixel SP2, and can extend in the second direction DR2. The first dam BNK1' can also be positioned between the first sub-pixel SP1 and the fourth sub-pixel SP4, and can extend in the first direction DR1.

[0245] Figure 24 It shows along Figure 23 A schematic cross-sectional view taken from line II-II'.

[0246] refer to Figure 23 and Figure 24 The pixel circuit layer PCL, the display element layer DPL'', and the optical functional layer LFL can be sequentially disposed on the substrate SUB on the third-party DR3. The display element layer DPL'' may include a light-emitting element LD, a first dam BNK1, and a dam member DAM. The substrate SUB, pixel circuit layer PCL, optical functional layer LFL, light-emitting element LD, and dam member DAM can be connected to a reference... Figure 6 The similar configurations described below will be omitted from the following text.

[0247] The first embankment BNK1' can be disposed on the substrate SUB (or pixel circuit layer PCL) in the display area DA, and protrude toward the light functional layer LFL on the third-direction DR3. The first embankment BNK1' can have a light-emitting area EMA corresponding to the sub-pixel SP (see [link to relevant documentation]). Figure 26 The first opening OP1' corresponds to the first opening OP1'. For example, the first embankment BNK1' may surround the light-emitting element LD disposed in the sub-pixel SP, and may have a light-emitting area EMA corresponding to the light-emitting element LD (see [link to relevant documentation]). Figure 26 The first opening OP1' corresponding to )

[0248] The dam component DAM can be integrally formed with the first dike BNK1', but is not limited thereto, and the dam component DAM can also be formed separately from the first dike BNK1'.

[0249] The dam member DAM may have a second height H2 on a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The second height H2 may be the distance between the substrate SUB (or pixel circuit layer PCL) and the end point EPT of the dam member DAM. The first dam BNK1' may have a third height H3' on the third direction DR3 that is substantially equal to the second height H2. The third height H3' may be the distance between the substrate SUB (or pixel circuit layer PCL) and the upper surface BTS' of the dam member DAM. The dam member DAM and the first dam BNK1' may be disposed on the pixel circuit layer PCL, configured to protrude further than the light-emitting element LD on the third direction DR3.

[0250] The display element layer DPL'' can have a fourth height H4 on the third-direction DR3 that is smaller than the second height H2 of the dam component DAM and the third height H3' of the first embankment BNK1'. Therefore, the dam component DAM and the first embankment BNK1' can protrude from the display element layer DPL to the optical function layer LFL.

[0251] The dam component DAM and the first dam BNK1' can be configured to protrude in the opposite direction to the substrate SUB between the edge of the display area DA and the sub-pixel SP.

[0252] Figure 25 An embodiment is shown. Figure 23 A schematic top view of one of the pixels.

[0253] refer to Figure 23 and Figure 25 Pixel PXL' may include first sub-pixels SP1' to third sub-pixels SP3'. First sub-pixels SP1' to third sub-pixels SP3' may include first anode electrodes AE1 to third anode electrodes AE3, cathode electrode CE, first light-emitting elements LD1 to third light-emitting elements LD3, and a first embankment BNK1'. The first anode electrodes AE1 to third anode electrodes AE3, cathode electrode CE, and first light-emitting elements LD1 to third light-emitting elements LD3 may be related to a reference... Figure 7 The similar configurations described below will be omitted from the following text.

[0254] The first embankment BNK1' can be configured to surround the first sub-pixel SP1' to the third sub-pixel SP3'. The first embankment BNK1' can be formed between the first sub-pixel SP1' and the third sub-pixel SP3' to define the light-emitting area EMA (see [link to documentation]). Figure 26 For example, the area where the first embankment BNK1' is located can be a non-luminescent area NEMA (see [reference]). Figure 26 ).

[0255] The first embankment BNK1' may surround the first light-emitting element LD1 to the third light-emitting element LD3 in the plan view. The first embankment BNK1' may not overlap with the first light-emitting element LD1 to the third light-emitting element LD3.

[0256] The first dam BNK1' may be disposed on the first anode electrode AE1 to the third anode electrode AE3 and the cathode electrode CE. The first dam BNK1' may overlap with at least some of the first anode electrode AE1 to the third anode electrode AE3. The first dam BNK1' may overlap with at least a portion of the cathode electrode CE.

[0257] Figure 26 It shows along Figure 25 A schematic cross-sectional view taken by line C-C'.

[0258] refer to Figure 25 and Figure 26 The pixel circuit layer PCL, the display element layer DPL', and the optical functional layer LFL' can be sequentially disposed on the substrate SUB. The pixel circuit layer PCL can be connected to a reference... Figure 8 The similar configurations described.

[0259] The display element layer DPL' may include a first light-emitting element LD1 to a third light-emitting element LD3, an outer coating OCL, a third passivation layer PSV3, a first diaphragm BNK1', and a capping layer CPL'. The first light-emitting element LD1 to the third light-emitting element LD3, the outer coating OCL, and the third passivation layer PSV3 may be compatible with a reference layer. Figure 8 and Figure 9 The similar configurations described.

[0260] The optical functional layer LFL' may include a fourth passivation layer PSV4, a reflective layer RFL, a first light conversion pattern CCP1 and a second light conversion pattern CCP2, a light scattering pattern LSP, a low refractive index layer LRL, a color filter layer CFL, first color filters CF1 to third color filters CF3, and a light blocking pattern LBP. The fourth passivation layer PSV4, the reflective layer RFL, the first light conversion pattern CCP1 and the second light conversion pattern CCP2, the light scattering pattern LSP, the low refractive index layer LRL, the color filter layer CF1, first color filters CF1 to third color filters CF3, and the light blocking pattern LBP can be compared with a reference... Figure 8 and Figure 9 The similar configurations described below will be omitted from the following text.

[0261] The first dike BNK1' can be connected to the dam component DAM on the third-direction DR3 (see...). Figure 24The first dam BNK1' has substantially equal height. It can be disposed on the pixel circuit layer PCL and can be disposed on at least some of the display element layer DPL' and the light function layer LFL'. Therefore, the first dam BNK1' can have an opening of the display element layer DPL' and an opening of the light function layer LFL' connected to its first opening OP1'.

[0262] The capping layer CPL' may be disposed on the first dam BNK1'. The capping layer CPL' may be disposed on the upper surface of the first dam BNK1'. In addition to covering the light-emitting elements LD1 to LD3, the capping layer CPL' may completely cover the first dam BNK1' and the third passivation layer PSV3. In other embodiments, the capping layer CPL' may not be disposed on the upper surface of the first dam BNK1'.

[0263] A fourth passivation layer PSV4 can be disposed on the capping layer CPL' within the first embankment BNK1'. On the fourth passivation layer PSV4, a first light conversion pattern CCP1, a second light conversion pattern CCP2, and a light scattering pattern LSP can be disposed within the first opening OP1'. On the capping layer CPL', a reflective layer RFL can be disposed on the side surface of the first embankment BNK1' adjacent to the first opening OP1'.

[0264] The first dam BNK1' can be disposed on the substrate SUB (or pixel circuit layer PCL) to protrude at least a portion of the optical functional layer LFL' on the third-direction DR3. The first dam BNK1' is not removed but utilized in subsequent processes, thereby improving manufacturing efficiency. For example, the first dam BNK1' can be used as a capping layer CPL (see...). Figure 9 The second dike BNK2 on ) (see Figure 9 ), to prevent adjacent sub-pixels from SP (see Figure 1 The light mixing between ).

[0265] Figures 27 to 31 A method for manufacturing a display device according to another embodiment of the present disclosure is illustrated schematically.

[0266] In the following text, Figures 27 to 31 Each of the lines II-II' in the middle is used to connect with Figure 23 The cutting plane line at the same position as line II-II' in the middle.

[0267] In the following text, reference will be made to Figures 27 to 31 Description Reference Figure 24 A method for manufacturing a display device is described. Figures 27 to 31 The description has already referenced Figure 24 The description of the content can be omitted.

[0268] refer to Figure 23 and Figure 27 A dam member (or structure) DAM and a first dam BNK1' can be formed on the substrate SUB (or pixel circuit layer PCL). The method for forming the dam member DAM and the first dam BNK1' on the display area DA of the substrate SUB (or pixel circuit layer PCL) can be compared with the reference... Figure 11 The similar configurations described below will be omitted from the following text.

[0269] The dam component DAM and the first dike BNK1' can have substantially equal heights. The dam component DAM and the first dike BNK1' can be formed in the same process to have the same height. For example, the dam component DAM can have a second length L2 in the third direction DR3, and the first dike BNK1' can have a fifth length L5 in the third direction DR3 that is substantially equal to the second length L2. In other embodiments, depending on the location where the first dike BNK1' is set, the first dike BNK1' can have a height portion different from the height of the dam component DAM. This will be referred to later. Figure 32 Describe it.

[0270] refer to Figure 23 and Figure 28 A light-emitting element (LD) can be formed on a carrier substrate C_SUB or on one surface SS1 of the carrier substrate C_SUB. The method for forming the carrier substrate C_SUB and the light-emitting element LD on one surface SS1 of the carrier substrate C_SUB can be compared with the reference method. Figure 12 The similar configurations described below will be omitted from the following text.

[0271] The carrier substrate C_SUB and the substrate SUB can be aligned with each other. The light-emitting element LD on the carrier substrate C_SUB and the first opening OP1' on the substrate SUB can be aligned so that they face each other. The carrier substrate C_SUB can be aligned such that the light-emitting element LD is disposed on the outer coating OCL on the substrate SUB. The method for aligning the carrier substrate C_SUB and the substrate SUB can be referenced. Figure 12 The similar configurations described below will be omitted from the following text.

[0272] refer to Figure 23 and Figure 29 By moving the carrier substrate C_SUB toward the substrate SUB, the light-emitting element LD can be at least partially disposed in the first opening OP1'. Thereafter, heat or pressure can be applied to the other surface SS2 of the carrier substrate C_SUB opposite to one surface SS1. The steps of at least partially disposing the light-emitting element LD on the carrier substrate C_SUB in the first opening OP1' and applying heat or pressure can be referenced. Figure 13The similar configurations described below will be omitted from the following text.

[0273] The dam component DAM and the first dam BNK1' may protrude toward the carrier substrate C_SUB. The dam component DAM may be disposed along the edge of the display area DA, and the first dam BNK1' may be disposed between the light-emitting elements LD. For example, the dam component DAM and the first dam BNK1' may protrude from the light-emitting elements LD on a third-direction DR3 to penetrate the adhesive layer ADL on the carrier substrate C_SUB. For example, similar to the dam component DAM, the first dam BNK1' penetrating the adhesive layer ADL on the carrier substrate C_SUB may be disposed between the light-emitting elements LD.

[0274] refer to Figure 23 and Figure 30 By moving the carrier substrate C_SUB in a direction away from the substrate SUB, the carrier substrate C_SUB can be separated from the light-emitting element LD. The method for separating the carrier substrate C_SUB from the light-emitting element LD can be referenced. Figure 14 The configurations described are similar. Redundant descriptions will be omitted below. The light-emitting element (LD) can retain the outer coating (OCL) attached to the substrate (SUB), and the dam member (DAM) and the first dam (BNK1') can also be retained without separating from the substrate (SUB).

[0275] refer to Figure 23 , Figure 24 and Figure 31 A light functional layer LFL can be further formed on the display element layer DPL'', which includes the light-emitting element LD. A display panel DP including a substrate SUB, a pixel circuit layer PCL, a display element layer DPL'', and a light functional layer LFL can be formed. The dam member DAM and the first dam BNK1' can be disposed on the pixel circuit layer PCL and can have a height that penetrates at least a portion of the light functional layer LFL.

[0276] Figure 32 It shows along Figure 23 The sectional view taken from line II-II'.

[0277] refer to Figure 23 and Figure 32 The pixel circuit layer PCL, display element layer DPL''', and optical functional layer LFL can be sequentially disposed on the substrate SUB on the third-direction DR3. The display element layer DPL''' may include a light-emitting element LD, a first dam BNK1'', and a dam member DAM. The substrate SUB, pixel circuit layer PCL, optical functional layer LFL, light-emitting element LD, and dam member DAM can be connected to a reference... Figure 6 The similar configurations described below will be omitted from the following text.

[0278] The first embankment BNK1'' may include a first portion BNK1_1 and a second portion BNK1_2. For example, when the first light-emitting elements LD1 to p-th light-emitting elements LDp are arranged in the first direction DR1, a portion of the first portion BNK1_1 of the first embankment BNK1'' may be arranged in the direction opposite to the first direction DR1 of the first light-emitting element LD1. A portion of the second portion BNK1_2 of the first embankment BNK1'' may be arranged in the first direction DR1 of the first light-emitting element LD1. A portion of the second portion BNK1_2 of the first embankment BNK1'' may be arranged between the first light-emitting element LD1 and the second light-emitting element LD2. Figure 32 The diagram shows the first part BNK1_1 and the second part BNK1_2 alternately arranged in the first direction DR1, but this disclosure is not limited thereto. For example, the first part BNK1_1 and the second part BNK1_2 can be randomly arranged.

[0279] The first part BNK1_1 may have a third height H3 on the third-direction DR3. The third height H3 of the first part BNK1_1 may be substantially equal to the second height H2 of the dam member DAM. The third height H3 may be the distance between the substrate SUB (or pixel circuit layer PCL) and the upper surface BTS1' of the first part BNK1_1. The second part BNK1_2 may have a fifth height H5 on the third-direction DR3, which is smaller than the third height H3. The fifth height H5 may be the distance between the substrate SUB (or pixel circuit layer PCL) and the upper surface BTS2 of the second part BNK1_2.

[0280] The first portion BNK1_1 of the first dike BNK1'' can have a substantially equal height to the dam component DAM, and the second portion BNK1_2 of the first dike BNK1'' can have a height smaller than the height of the dam component DAM. For example, depending on the location where the first dike BNK1'' is set, the first dike BNK1'' can have a different height than the height portion of the dam component DAM. For example, depending on the location using a patterning process employing a multi-half-tone mask, the first dike BNK1'' can be formed to have different heights.

[0281] The heights H3 and H5 of the first dam BNK1'' can be changed by adjusting the amount of light transmitted through a mask. For example, a second part BNK1_2 with a relatively low height in the first dam BNK1'' can be formed by increasing the amount of light transmitted. A first part BNK1_1 with a relatively high height in the first dam BNK1'' can be formed by decreasing the amount of light transmitted.

[0282] Figure 33 A schematic block diagram of a display system according to an embodiment is shown.

[0283] refer to Figure 33 The display system 1000 may include a processor 1100 and a display device 1200.

[0284] Processor 1100 can perform various tasks and calculations. Processor 1100 may include application processors, graphics processors, microprocessors, central processing units (CPUs), etc. Processor 1100 can be electrically connected to other components of display system 1000 via a bus system and enable them to step.

[0285] Processor 1100 can transmit input image data IMG and control signal CTRL to display device 1200. Display device 1200 can display an image based on the input image data IMG and control signal CTRL. Display device 1200 can be connected to a reference... Figure 1 The described display device DD is similarly configured. Input image data IMG and control signal CTRL can be provided respectively as... Figure 1 The input image data is IMG and the control signal is CTRL.

[0286] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, automatic displays, smart glasses, portable multimedia layers (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display devices (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0287] Figures 34 to 37 It shows Figure 33 A schematic 3D diagram illustrating an application example of the display system.

[0288] refer to Figure 34 , Figure 33 The display system 1000 can be applied to a smartwatch 2000, which includes a display section 2100 and a strip section 2200.

[0289] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 may have a structure in which the strap portion 2200 is mounted on the user's wrist. Here, the display system 1000 and / or display device 1200 may be applied to the display portion 2100, so that image data including time information can be provided to the user.

[0290] refer to Figure 35 , Figure 33The display system 1000 can be applied to the automotive display system 3000. Here, the automotive display system 3000 may include a computing system disposed inside and / or outside the vehicle to provide image data.

[0291] For example, the display system 1000 and / or display device 1200 may be applied to at least one of the infotainment panel 3100, instrument panel 3200, passenger display 3300, head-up display 3400, side mirror display 3500 and rear seat display 3600 provided in the vehicle.

[0292] refer to Figure 36 , Figure 33 The display system 1000 can be applied to the smart glasses 4000. The smart glasses 4000 can be a wearable electronic device that can be worn on a user's head. For example, the smart glasses 4000 can be a wearable device for augmented reality.

[0293] The smart glasses 4000 may include a frame 4100 and a lens portion 4200. The frame 4100 may include a housing 4110 for holding the lens portion 4200 and a leg portion 4120 for the user to wear. The leg portion 4120 may be hinged to the housing 4110 to fold or unfold relative to the housing 4110.

[0294] The battery, touchpad, microphone, and camera can be embedded in frame 4100. The projector that outputs light and the processor that controls the light signals can also be embedded in frame 4100.

[0295] The lens portion 4200 may include optical components that transmit or reflect light. For example, the lens portion 4200 may include glass, transparent synthetic resin, etc.

[0296] To enable the user's eyes to recognize visual information, the lens portion 4200 can reflect an image caused by light signals transmitted from the projector of the frame 4100 via its rear surface (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as time and date displayed on the lens portion 4200. The projector and / or lens portion 4200 can be a type of display device. The display device 1200 can be applied to the projector and / or lens portion 4200.

[0297] refer to Figure 37 , Figure 33 The display system 1000 can be applied to head-mounted display devices 5000.

[0298] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality or mixed reality.

[0299] The head-mounted display device 5000 may include a headband 5100 and a display device retaining housing 5200. The headband 5100 may be electrically connected to the display device retaining housing 5200. The headband 5100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 5000 to a user's head. The horizontal strap may wrap around the side portion of the user's head, and the vertical strap may wrap around the upper portion of the user's head. However, the implementation is not limited to this. For example, the headband 5100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0300] Display device housing 5200 can accommodate display system 1000 and / or display device 1200.

[0301] In a display device according to an embodiment of the present disclosure, a dam member is provided on a substrate as an adhesive layer penetrating the carrier substrate, such that expansion of the adhesive layer (ADL) due to heat and pressure during the bonding process of the light-emitting element can be blocked or at least reduced. By suppressing unintended movement of the light-emitting element caused by the expansion of the adhesive layer, misalignment of the light-emitting element can be prevented. Therefore, the display device according to an embodiment of the present disclosure can improve display quality by improving the electrical connection reliability of the light-emitting element.

[0302] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from the description. Therefore, the inventive concept is not limited to these embodiments, but rather to the broader scope of the claims and various apparent modifications and equivalent arrangements.

[0303] According to embodiments of this disclosure, a display device with improved reliability and a method for manufacturing the display device are provided.

[0304] The effects of the embodiments disclosed herein are not limited to those described above, and many more effects are included in this specification.

Claims

1. A method for manufacturing a display device, comprising: A dam is formed on a substrate in a display area in a third direction, the substrate extending in a first direction and a second direction intersecting the first direction, the third direction intersecting the first direction and the second direction, the dam having an opening; A dam member is formed on the substrate in the display area, facing the third direction, and the dam member is disposed along the edge of the display area; The light-emitting element and the opening disposed on the surface of the carrier substrate are aligned so that they face each other; The carrier substrate is moved toward the substrate, and the light-emitting element is at least partially disposed in the opening; as well as Separate the carrier substrate from the light-emitting element.

2. The method for manufacturing a display device according to claim 1, wherein, Each of the light-emitting elements has a first height in the third direction, and The dam component has a second height in the third direction that is greater than the first height.

3. The method for manufacturing a display device according to claim 2, wherein, The embankment has a third height in the third direction, and The third height is smaller than the second height.

4. The method for manufacturing a display device according to claim 2, wherein, The embankment has a third height in the third direction, and The third height is equal to the second height.

5. The method for manufacturing a display device according to claim 2, wherein, The first part of the dike has a third height in the direction of the third party. The second part of the dike has a fifth height in the third direction. The third height is greater than the fifth height, and The third height is equal to the second height.

6. The method for manufacturing a display device according to claim 1, wherein, Arranging the light-emitting element at least partially in the opening includes applying heat or pressure to another surface of the carrier substrate opposite to the surface of the carrier substrate.

7. The method for manufacturing a display device according to claim 6, wherein, The carrier substrate includes an adhesive layer disposed on the surface of the carrier substrate. The adhesive layer is disposed between the carrier substrate and the light-emitting element, and expands under the heat or pressure. The expansion of the adhesive layer is blocked by the dam member within a portion of the adhesive layer.

8. A method for manufacturing a display device, comprising: A dam is formed on a substrate in a display area in a third direction, the substrate extending in a first direction and a second direction intersecting the first direction, the third direction intersecting the first direction and the second direction, the dam having an opening; A dam member is formed on the surface of a carrier substrate on which a light-emitting element is disposed, the dam member being configured to correspond to the edge of the display area on the substrate; Align the light-emitting element and the opening on the carrier substrate so that they face each other; The carrier substrate is moved toward the substrate to at least partially assemble the light-emitting element in the opening; as well as Separate the carrier substrate from the light-emitting element.

9. The method of manufacturing a display device according to claim 8, wherein, When the carrier substrate is separated from the light-emitting element, the dam component is separated from the substrate together with the carrier substrate.

10. The method of manufacturing a display device according to claim 8, wherein, Each of the light-emitting elements has a first length in the third direction, and The dam component has a second length that is longer than the first length in the third direction.

Images