Stacked battery and method of manufacturing the same and photovoltaic module

Abstract

The embodiment of the present application relates to the photovoltaic field, and provides a laminated cell, a preparation method thereof and a photovoltaic module, the laminated cell comprises a first electrode, an electron transport layer, an absorption layer, a hole transport layer, a passivation laminated layer, a silicon bottom layer and a second electrode which are sequentially stacked; wherein the passivation laminated layer comprises a doped ZnOS layer, a doped polysilicon layer and a SiO2 layer which are sequentially stacked, the doping types of the doped ZnOS layer and the doped polysilicon layer are different, and the doped ZnOS layer is located between the hole transport layer and the doped polysilicon layer. In the present application, the doped ZnOS layer is introduced above the doped polysilicon layer, which helps to solve the problem of the parasitic absorption limitation of ITO, and the doped ZnOS layer has high light transmittance and low contact resistance, which helps to reduce the series resistance, improve the current density, and further helps to improve the fill factor and open circuit voltage of the cell.

Description

Technical Field

[0001] This application relates to the field of photovoltaics, and in particular to a tandem solar cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Developing renewable new energy sources to replace traditional fossil fuels is of great significance. Solar energy is inexhaustible. Generating electricity from a continuous source of solar energy is the best way to replace fossil fuels. Currently, the most efficient and stable solar cells are silicon solar cells, with a photoelectric conversion efficiency reaching up to 25%. From the first monocrystalline silicon solar cell in 1954 to today, solar cells have used many semiconductor materials, including silicon, inorganic compound semiconductors, organic semiconductors, and even some metals. Silicon is abundant, being the second most abundant element on Earth (approximately 27%) after oxygen. Furthermore, silicon is stable, non-toxic, and has a mature manufacturing process, making it the primary material for the research, development, production, and application of solar cells. Monocrystalline silicon solar cells feature an inverted pyramid texture, a double-layer anti-reflective coating, and a back-reflection structure, giving them excellent light-trapping performance. The use of an oxide layer to passivate both the front and back sides increases the minority carrier lifetime. Moreover, point contact replaces the original fully covered aluminum alloy back contact, resulting in a conversion efficiency of up to 24.7%, close to the theoretical value.

[0003] In recent years, many researchers have used tandem cells with other types of cells to break through the theoretical maximum efficiency of silicon solar cells, such as silicon-perovskite tandem cells, silicon-dye tandem cells, and silicon-polymer tandem cells. The highest efficiency reported so far for silicon-perovskite tandem cells is 25.2%. However, the fabrication process of tandem cells is complex and their stability is poor. The cells involved in the tandem process inevitably reduce the efficiency of the original silicon solar cell, resulting in only a limited increase in the maximum efficiency. Summary of the Invention

[0004] This application provides a tandem battery, its preparation method, and a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the tandem battery.

[0005] To achieve the above objectives, according to one aspect of the present invention, a stacked battery is provided, comprising a first electrode, an electron transport layer, an absorption layer, a hole transport layer, a passivation stack, a silicon substrate, and a second electrode stacked sequentially; wherein the passivation stack comprises a doped ZnOS layer, a doped polycrystalline silicon layer, and a SiO2 layer stacked sequentially, and the doping types of the doped ZnOS layer and the doped polycrystalline silicon layer are different, with the doped ZnOS layer located between the hole transport layer and the doped polycrystalline silicon layer.

[0006] Furthermore, the resistivity of the passivation stack is 3~20 Ω·cm.

[0007] Furthermore, the thickness of the passivation stack is 26.5~132nm.

[0008] Furthermore, the thickness of the ZnOS-doped layer is 15-30 nm; the thickness of the polysilicon-doped layer is 10-100 nm; and the thickness of the SiO2 layer is 1.5-2 nm.

[0009] Furthermore, the doping concentration in the doped polysilicon layer is 2 × 10⁻⁶. 18 ~2×10 19 cm -3 .

[0010] Furthermore, the doping concentration in the ZnOS layer is 8 × 10⁻⁶. 19 ~2×10 21 cm -3 .

[0011] Furthermore, the molar ratio of oxygen to sulfur in the doped ZnOS layer is (1~2):(1~2).

[0012] Furthermore, the absorption layer comprises a stacked ABX3 layer and a CsPbI3 quantum dot layer, with the CsPbI3 quantum dot layer located close to the electron transport layer. Here, A is selected from any one or more of Cs, CH(NH2)2, and CH3NH3, B is Pb, and X is selected from any one or more of Cl, Br, and I.

[0013] Furthermore, the tandem solar cell also includes an anti-reflective layer disposed on the side away from the first electrode of the electron transport layer.

[0014] Furthermore, the thickness of the anti-reflective layer is 100~120nm.

[0015] Furthermore, the anti-reflective layer is made of MgF2.

[0016] According to another aspect of the present invention, a method for fabricating a tandem battery is provided. The tandem battery is the aforementioned tandem battery. The method includes: step S1, depositing a second electrode material on one side of a silicon wafer to form a second electrode, introducing oxygen while simultaneously depositing silicon to form a SiO2 layer, then introducing a first doping source to form a doped amorphous silicon layer on the side of the SiO2 layer away from the silicon wafer, then performing a first annealing treatment to form a doped polycrystalline silicon layer, depositing ZnO, a second doping source, and ZnS by magnetron sputtering, and then performing a second annealing treatment to form a doped ZnOS layer, wherein the first doping source and the second doping source are of different types; step S2, depositing a hole transport material on the side of the doped ZnOS layer away from the doped polycrystalline silicon layer to form a hole transport layer; step S3, depositing an absorber material on the side of the hole transport layer away from the doped ZnOS layer to form an absorber layer; step S4, depositing an electron transport material on the side of the absorber layer away from the hole transport layer to form an electron transport layer; step S5, depositing a first electrode material on the side of the electron transport layer away from the absorber layer to form a first electrode, thereby obtaining a tandem battery.

[0017] Furthermore, the temperature of the first annealing treatment is 700~900℃; the time of the first annealing treatment is 1~40min.

[0018] Furthermore, the magnetron sputtering pressure is 0.3~0.5 Pa; the magnetron sputtering power is 150~300 W; the magnetron sputtering deposition rate is 2~5 nm / s; and / or, the temperature of the second annealing treatment is 350~450 °C; and the time of the second annealing treatment is 10~30 min.

[0019] According to another aspect of the present invention, a photovoltaic module is provided, comprising a cell string, an encapsulating film and a cover plate, wherein the cell string is formed by connecting a plurality of the aforementioned stacked cells or stacked cells prepared by the aforementioned method of preparing stacked cells.

[0020] The technical solution provided in this application has at least the following advantages:

[0021] In this application, the introduction of a doped ZnOS layer between the hole transport layer and the doped polycrystalline silicon layer helps to overcome the parasitic absorption limitation of ITO. Furthermore, the doped ZnOS layer exhibits high transmittance and low contact resistance, which helps reduce series resistance and increase current density, thereby improving the fill factor and open-circuit voltage of the battery. The synergistic effect among the doped ZnOS layer, the doped polycrystalline silicon layer, and the SiO2 layer, and the control of different doping types between the doped ZnOS layer and the doped polycrystalline silicon layer, helps to optimize the interfacial contact of the heterojunction, reduce carrier recombination losses, and enhance the mechanical strength and chemical stability of the entire tandem battery system. Therefore, the tandem battery of this application exhibits high photoelectric conversion efficiency. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the structure of a first type of stacked battery according to an embodiment of this application is shown;

[0024] Figure 2 A schematic diagram of a second type of stacked battery provided according to an embodiment of this application is shown.

[0025] The above figures include the following reference numerals:

[0026] 10. Anti-reflection layer; 20. First electrode; 30. Conductive layer; 40. Electron transport layer; 41. SnO2 layer; 42. C60 layer; 50. Absorption layer; 51. CsPbI3 quantum dot layer; 52. ABX3 layer; 60. Hole transport layer; 70. Passivation stack; 71. Doped ZnOS layer; 72. Doped polysilicon layer; 73. SiO2 layer; 81. n-type polysilicon layer; 82. First SiO2 layer. x Layer; 90, silicon bottom layer; 101, second SiO x Layer; 102, p-type polycrystalline silicon layer; 110, passivation layer; 120, second electrode. Detailed Implementation

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the embodiments.

[0028] Terminology explanation: FA is short for CH(NH2)2, and MA is short for CH3NH3.

[0029] As analyzed in the background section of this application, the existing technology of tandem solar cells has the problem of low photoelectric conversion efficiency. In order to solve this problem, this application provides a tandem solar cell, a method for its fabrication, and a photovoltaic module.

[0030] In a typical embodiment of this application, a stacked battery is provided, such as Figure 1As shown, the tandem battery includes a first electrode 20, an electron transport layer 40, an absorption layer 50, a hole transport layer 60, a passivation layer 70, a silicon substrate 90, and a second electrode 120 stacked sequentially. The passivation layer 70 includes a doped ZnOS layer 71, a doped polycrystalline silicon layer 72, and a SiO2 layer 73 stacked sequentially. The doping types of the doped ZnOS layer 71 and the doped polycrystalline silicon layer 72 are different, and the doped ZnOS layer 71 is located between the hole transport layer 60 and the doped polycrystalline silicon layer 72.

[0031] In this application, the introduction of a doped ZnOS layer between the hole transport layer and the doped polycrystalline silicon layer helps to overcome the parasitic absorption limitation of ITO. Furthermore, the doped ZnOS layer exhibits high transmittance and low contact resistance, which helps reduce series resistance and increase current density, thereby improving the fill factor and open-circuit voltage of the battery. The synergistic effect among the doped ZnOS layer, the doped polycrystalline silicon layer, and the SiO2 layer, and the control of different doping types between the doped ZnOS layer and the doped polycrystalline silicon layer, helps to optimize the interfacial contact of the heterojunction, reduce carrier recombination losses, and enhance the mechanical strength and chemical stability of the entire tandem battery system. Therefore, the tandem battery of this application exhibits high photoelectric conversion efficiency.

[0032] In some embodiments of this application, the stacked battery further includes an emitter layer located on the back side of the silicon substrate 90.

[0033] In some embodiments of this application, the stacked battery includes, from top to bottom, a first electrode 20, an electron transport layer 40, an absorption layer 50, a hole transport layer 60, a passivation stack 70, a silicon substrate 90, and a second electrode 120, stacked sequentially. The passivation stack 70 includes, from top to bottom, a doped ZnOS layer 71, a doped polycrystalline silicon layer 72, and a SiO2 layer 73, stacked sequentially. The doping types of the doped ZnOS layer 71 and the doped polycrystalline silicon layer 72 are different, and the doped ZnOS layer 71 is located between the hole transport layer 60 and the doped polycrystalline silicon layer 72.

[0034] In some embodiments of this application, the resistivity of the passivation stack 70 is 3~20 Ω·cm; the thickness of the passivation stack 70 is 26.5~132 nm.

[0035] Controlling the resistivity of the passivation stack within the aforementioned range helps reduce series resistance, lower energy consumption, and improve the overall efficiency of the battery. Controlling the thickness of the passivation stack within the aforementioned range helps maintain low resistance while effectively guiding photons into the absorption layer.

[0036] In some embodiments of this application, the thickness of the doped ZnOS layer 71 is 15~30nm; the thickness of the doped polysilicon layer 72 is 10~100nm; and the thickness of the SiO2 layer 73 is 1.5~2nm.

[0037] Controlling the thickness of the ZnOS-doped layer within the aforementioned range helps maintain high electrical conductivity while improving light transmittance. Controlling the thickness of the polycrystalline silicon-doped layer within the aforementioned range helps improve charge separation and transport capabilities while reducing resistance, thereby contributing to higher fill factor and open-circuit voltage. Controlling the thickness of the SiO2 layer within the aforementioned range helps reduce interface state density and non-radiative recombination, thus improving the battery's electrical performance.

[0038] To further optimize charge transport and separation and improve light utilization, in some embodiments of this application, the thickness ratio of the doped ZnOS layer, the doped polysilicon layer and the SiO2 layer is 15:(10~50):(1.5~1.7).

[0039] In some embodiments of this application, the doping concentration in the doped polysilicon layer 72 is 2 × 10⁻⁶. 18 ~2×10 19 cm -3 .

[0040] Controlling the doping concentration in the doped polysilicon layer within the above range helps to optimize the conductivity.

[0041] In some embodiments of this application, the doping concentration in the ZnOS layer 71 is 8 × 10⁻⁶. 19 ~2×10 21 cm -3 .

[0042] Controlling the doping concentration in the ZnOS layer within the above range helps to balance the high transparency and conductivity of the ZnOS layer.

[0043] In some embodiments of this application, the molar ratio of oxygen to sulfur in the doped ZnOS layer 71 is (1~2):(1~2).

[0044] Controlling the molar ratio of oxygen to sulfur in the doped ZnOS layer within the above range helps to optimize the electronic structure of the material and improve its electrical conductivity and optical transparency.

[0045] In some embodiments of this application, the doping source in the doped polysilicon layer is a p-doping source, which is at least one of the Group III elements, such as boron, aluminum, gallium, etc.; and / or, the doping source in the doped ZnOS layer is an n-doping source, which is at least one of the Group V elements, such as phosphorus, arsenic, antimony, bismuth, etc.

[0046] p-doped polycrystalline silicon layers effectively enhance hole mobility and reduce defect states, thereby improving charge transport efficiency. n-doped ZnOS layers help improve the electronic conductivity of ZnOS layers, promote rapid electron collection and transport, reduce charge recombination losses within the battery, and improve battery efficiency.

[0047] In some embodiments of this application, the absorption layer 50 includes a stacked ABX3 layer 52 and a CsPbI3 quantum dot layer 51, with the CsPbI3 quantum dot layer 51 located close to the electron transport layer 40. In this layer, A is selected from any one or more of Cs, CH(NH2)2 and CH3NH3, B is Pb, and X is selected from any one or more of Cl, Br and I.

[0048] Due to their size and surface effects, CsPbI3 quantum dots exhibit excellent absorption capabilities for short-wave ultraviolet to near-infrared light. When located above the ABX3 layer, they can first absorb most of the short-wavelength light, and then allow the ABX3 layer to absorb the remaining spectrum, especially the longer wavelengths. This creates complementary absorption, covering a wide range of the solar spectrum and helping to improve overall light absorption efficiency and photoelectric conversion efficiency.

[0049] In some embodiments of this application, the particle size of the CsPbI3 is 7~9 nm.

[0050] In some embodiments of this application, the band gap of the ABX3 layer is 1.62~1.8eV; and / or, the thickness of the ABX3 layer is 300~2000nm; and / or, the thickness of the CsPbI3 quantum dot layer is 30~50nm.

[0051] Controlling the band gap of the ABX3 layer within the aforementioned range helps absorb the higher-energy portions of the solar spectrum. Controlling the thickness of the CsPbI3 quantum dot layer within the aforementioned range helps improve the absorption of short-wavelength light, especially in the ultraviolet region, which helps to broaden the light absorption range and improve the overall photoelectric conversion efficiency. Controlling the thickness of the ABX3 layer within the aforementioned range helps to improve photon absorption efficiency and reduce charge recombination, thereby contributing to an increase in open-circuit voltage and fill factor.

[0052] In order to further optimize light absorption, reduce light reflection and transmission loss, and improve photoelectric conversion efficiency, in some embodiments of this application, the thickness ratio of the above-mentioned ABX3 layer to the CsPbI3 quantum dot layer is 300:(30~40).

[0053] In some embodiments of this application, such as Figure 2As shown, the above-mentioned tandem battery further includes an anti-reflection layer 10, which is disposed on the side away from the first electrode 20 of the electron transport layer 40; and / or, the tandem battery further includes a conductive layer 30, which is disposed between the first electrode and the electron transport layer; and / or, the tandem battery further includes an n-type polycrystalline silicon layer 81 and a first SiO2 layer disposed between the silicon underlayer and the passivation layer. x Layer 82, first SiO x Layer 82 is located close to the silicon substrate; and / or, the tandem cell further includes a second SiO2 layer disposed sequentially between the silicon substrate and the second electrode. x Layer 101, p-type polysilicon layer 102 and passivation layer 110, and second SiO x Layer 101 is close to the bottom silicon layer.

[0054] An anti-reflective layer is disposed on the first electrode side, away from the electron transport layer, which helps reduce light reflection from the battery surface, increases the amount of sunlight incident, and thus improves light absorption efficiency. The conductive layer helps enhance charge collection and transport efficiency. The n-type polycrystalline silicon layer 81 and the first SiO2 layer... x Layer 82 is disposed between the silicon underlayer and the passivation stack, which helps to reduce the defect state density on the silicon substrate surface and improve interface quality. Second SiO x The arrangement of layer 101, p-type polycrystalline silicon layer 102 and passivation layer helps to reduce interfacial recombination on both sides of the silicon substrate and improve the overall performance of the cell.

[0055] In order to further improve the photoelectric conversion efficiency, in some embodiments of this application, the thickness of the anti-reflection layer 10 is 100~120nm; and / or, the material of the anti-reflection layer 10 is MgF2.

[0056] In some embodiments of this application, the thickness of the conductive layer is 10-100 nm; and / or, the material of the conductive layer is selected from any one or more of indium tin oxide, zinc-doped indium oxide, tungsten-doped indium oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and boron-doped zinc oxide; and / or, the n-type polycrystalline silicon layer 81 and the first SiO x The total thickness of layer 82 is 61.5~100 nm; and / or, the second SiO x The total thickness of layer 101 and p-type polysilicon layer 102 is 61.5~100 nm; and / or, the thickness of the passivation layer is 80~100 nm; and / or, the material of the passivation layer is selected from Al2O3 and / or SiN. x .

[0057] In some embodiments of this application, the thickness of the first electrode is 100-200 nm; and / or, the material of the first electrode can be silver, copper, aluminum, gold, platinum, etc.; and / or, the thickness of the electron transport layer is 40-50 nm; and / or, the material of the electron transport layer is selected from SnO2 and / or C60; and / or, the thickness of the hole transport layer is 5-20 nm; and / or, the material of the hole transport layer is NiO. x ; and / or, the thickness of the silicon substrate is 180~200μm; and / or, the material of the silicon substrate is selected from n-type CzSi; and / or, the thickness of the second electrode is 20~30μm; and / or, the material of the second electrode can be silver paste, silver-aluminum paste, copper paste, etc.

[0058] Controlling the thickness and material type of the first electrode within the aforementioned ranges facilitates current collection and transmission, reducing efficiency losses caused by series resistance. Controlling the thickness and material type of the electron transport layer within the aforementioned ranges helps improve electron transport and reduce the probability of recombination during transport. Controlling the thickness and material type of the hole transport layer within the aforementioned ranges helps reduce non-radiative recombination at the interface, improving the stability and efficiency of the battery. Controlling the thickness and material type of the silicon substrate within the aforementioned ranges helps improve the lifetime of photogenerated carriers and reduce recombination losses within the substrate, thereby enhancing the overall photoelectric conversion efficiency. Controlling the thickness and material type of the second electrode within the aforementioned ranges helps enhance the mechanical stability of the battery structure.

[0059] In some embodiments of this application, the electron transport layer 40 includes a stacked SnO2 layer 41 and a C60 layer 42, with the SnO2 layer located above the C60 layer, and the thickness ratio of the SnO2 layer to the C60 layer being 1:(1~2).

[0060] SnO2 is a metal oxide with excellent electron transport properties and high electron affinity. It can effectively collect and transport electrons generated by the absorption layer, reducing the energy barrier during electron transport and improving electron transport efficiency. The C60 layer provides a stable electron transport platform, reducing nonradiative recombination of electrons during transport and increasing electron lifetime and transport distance. Controlling the thickness ratio of the SnO2 layer to the C60 layer within the aforementioned range helps to enhance their synergistic effect, further improving electron transport efficiency.

[0061] In another typical embodiment of this application, a method for fabricating the aforementioned tandem solar cell is provided. This method includes: Step S1, depositing a second electrode material on one side of a silicon wafer to form a second electrode, introducing oxygen while simultaneously depositing silicon to form a SiO2 layer, then introducing a first doping source to form a doped amorphous silicon layer on the side of the SiO2 layer away from the silicon wafer, followed by a first annealing treatment to form a doped polycrystalline silicon layer, depositing ZnO, a second doping source, and ZnS using magnetron sputtering, and then performing a second annealing treatment to form a doped ZnOS layer, wherein the first and second doping sources are of different types; Step S2, depositing a hole transport material on the side of the doped ZnOS layer away from the doped polycrystalline silicon layer to form a hole transport layer; Step S3, depositing an absorber material on the side of the hole transport layer away from the doped ZnOS layer to form an absorber layer; Step S4, depositing an electron transport material on the side of the absorber layer away from the hole transport layer to form an electron transport layer; Step S5, depositing a first electrode material on the side of the electron transport layer away from the absorber layer to form a first electrode, thus obtaining the tandem solar cell.

[0062] In step S1, the formation of the passivation stack helps improve charge transfer while reducing parasitic absorption limitations. In step S2, the formation of the hole transport layer helps improve charge separation and transport efficiency. In step S3, the formation of the absorption layer helps enhance the light absorption capability of the battery. In step S4, the formation of the electron transport layer helps reduce non-radiative recombination and improve the open-circuit voltage and fill factor of the battery.

[0063] The silicon in step S1 can be α-Si.

[0064] In some embodiments of this application, the temperature of the first annealing treatment is 700~900℃; the time of the first annealing treatment is 1~40min.

[0065] Controlling the temperature and time of the first annealing treatment within the above range helps to promote the crystallization transformation of silicon. This transformation process helps to improve the electrical conductivity of the material, reduce the resistance, enhance the charge transport capacity, help reduce the defect state density on the silicon substrate surface, improve the interface quality, thereby reducing nonradiative recombination of charges and enhancing the stability of the cell.

[0066] To improve the uniformity and density of the ZnOS doped layer formation, thereby further improving the photoelectric conversion efficiency, in some embodiments of this application, the magnetron sputtering pressure is 0.3~0.5 Pa; the magnetron sputtering power is 150~300 W; the magnetron sputtering deposition rate is 2~5 nm / s; and / or, the temperature of the second annealing treatment is 350~450 °C; and the time of the second annealing treatment is 10~30 min.

[0067] In some embodiments of this application, step S5 includes: step S51, depositing conductive layer material on the side of the electron transport layer away from the absorption layer to form a conductive layer; step S52, depositing first electrode material on the side of the conductive layer away from the electron transport layer to form a first electrode; and step S53, depositing antireflective material on the side of the first electrode away from the conductive layer to form an antireflective layer, thereby obtaining a stacked battery.

[0068] The formation of a conductive layer helps reduce energy loss during charge transport and improves the fill factor of the battery. The formation of an anti-reflective layer helps reduce the reflection of incident light on the battery surface, increases the amount of light incident, and thus improves light absorption efficiency and photoelectric conversion efficiency.

[0069] In another typical embodiment of this application, a photovoltaic module is provided, including a battery string, an encapsulating film and a cover plate, wherein the battery string is formed by connecting multiple of the aforementioned stacked cells or stacked cells prepared by the aforementioned method of preparing stacked cells.

[0070] Since the cell strings in the above-mentioned photovoltaic module are connected by the tandem cells of this application or the tandem cells prepared by the method of this application, the photovoltaic module has a high photoelectric conversion efficiency.

[0071] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0072] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0073] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0074] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0075] Example 1

[0076] Both sides of a silicon wafer (n-type CzSi, 180 μm thick) were polished, followed by RCA (a cleaning method proposed by American Wireless) cleaning to remove metallic impurities. Then, double-sided texturing was performed using a sodium hydroxide aqueous solution with 10% isopropanol as an additive. The texturing temperature was 80°C, resulting in a pyramidal textured surface with a thickness of 1.2 μm, yielding the silicon underlayer. The silicon wafer was placed in an 800°C dry oxygen environment to form SiO2 layers with a thickness of 1.5 nm on both sides. At a temperature of 620°C and a pressure of 300 mTorr, amorphous silicon layers were deposited on the SiO2 layers on both sides using low-pressure chemical vapor deposition (LPCVD), with a thickness of 60 nm on both sides. In a POCl3 atmosphere at 880°C, one side of the amorphous silicon layer was doped to form n-type CzSi. + -Si layer, in BCl3 atmosphere, at 950℃, doping of the amorphous silicon layer on the other side to form p + -Si layer, and finally annealed in hydrogen at 750°C for 30 min to form the first SiO layer on one side of the silicon wafer. x Layer 82 and n-type polycrystalline silicon layer 81, first SiO x The total thickness of layer 82 and n-type polysilicon layer 81 is 61.5 nm, and a second SiO is formed on the other side of the silicon wafer. x Layer 101 and p-type polycrystalline silicon layer 102, second SiO x The total thickness of layer 101 and p-type polysilicon layer 102 is 61.5 nm. α-Si deposition is performed during oxygen introduction to form a 1.5 nm thick SiO2 layer 73 on the n-type polysilicon layer 81. A 10 nm thick boron-doped α-Si layer (doping concentration of 2 × 10⁻⁶) is then deposited on the SiO2 layer using plasma-enhanced chemical vapor deposition. 19 cm -3 Then anneal at 700℃ for 1 min to form p + - A 10nm thick polycrystalline silicon layer, i.e., a doped polycrystalline silicon layer 72, was deposited using magnetron sputtering (working pressure 0.3Pa, power 150W, deposition rate 2nm / s) to deposit ZnO, phosphorus, and ZnS onto the p-type silicon substrate. + - An n-type layer with a thickness of 15nm is formed on the polycrystalline silicon layer. + -ZnOS layer (doping concentration of 2×10⁻⁶)21 cm -3 The molar ratio of oxygen to sulfur is 1:1, i.e., a ZnOS-doped layer 71 is formed. Then, it is annealed at 350℃ under nitrogen for 10 min. The SiO2 layer 73, the polycrystalline silicon-doped layer 72, and the ZnOS-doped layer 71 constitute a passivation stack 70 with a resistivity of 3 Ω·cm. NiO is then sputtered (oxygen partial pressure 10%). x Nanoparticles (average particle size 3 nm, x = 1~1.2) are deposited on n + A hole transport layer 60 with a thickness of 20 nm is formed on the ZnOS layer. Cs 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 3. The precursor solution was spin-coated (4000 rpm) onto the hole transport layer, quenched with chlorobenzene as an antisolvent, and then annealed at 100°C for 30 min to form a Cs layer with a thickness of 300 nm. 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 ABX3 layers (band gap 1.68 eV), i.e., ABX3 layers 52, with CsPbI3 solution (concentration 10 mg / mL, solvent n-hexane, CsPbI3 particle size 8 nm) sprayed onto CsPbI3. 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08The CsPbI3 quantum dot layer 51 with a thickness of 30 nm is formed by drying the ABX3 layer 52 and the CsPbI3 quantum dot layer 51. The ABX3 layer 52 and the CsPbI3 quantum dot layer 51 constitute the absorption layer 50. The C60 layer 42 with a thickness of 20 nm is formed on the CsPbI3 quantum dot layer by thermal evaporation of C60. The SnO2 layer 41 with a thickness of 20 nm is formed on the C60 layer by atomic deposition (at a temperature of 100 °C). The C60 layer 42 and the SnO2 layer 41 constitute the electron transport layer 40. The conductive layer 30 with a thickness of 80 nm is formed on the SnO2 layer by sputtering indium tin oxide. The first electrode 20 with a thickness of 100 nm is formed on the conductive layer by thermal evaporation of silver. The anti-reflection layer 10 with a thickness of 100 nm is formed on the first electrode by evaporation of MgF2. A 10 nm thick Al2O3 layer was deposited on a p-type polycrystalline silicon layer 102 using atomic layer deposition (trimethylaluminum as the precursor, temperature 150℃, and a deposition thickness of 0.12 nm per cycle). A 70 nm thick SiN layer was then formed on the surface of the Al2O3 layer using plasma-enhanced chemical vapor deposition (SiH4 to NH3 volume ratio 1:3, RF power 300 W). x (x is 1.5~1.8), and finally a passivation layer 110 with a thickness of 80 nm is formed on the surface of the p-type polycrystalline silicon layer 102. Silver paste (linewidth 15 μm, thickness 20 μm) is screen-printed on the surface of the passivation layer 110, and sintering is performed in a chain furnace under N2 atmosphere at a peak temperature of 800 °C to form the second electrode 120, resulting in a tandem solar cell with the structure shown below. Figure 2 As shown.

[0077] Example 2

[0078] The difference from Example 1 is that n + The thickness of the ZnOS layer is 15 nm, p + - The polycrystalline silicon layer has a thickness of 50 nm, the SiO2 layer 73 has a thickness of 1.7 nm, and the resistivity of the passivation stack is 5 Ω·cm, thus obtaining a stacked cell.

[0079] Example 3

[0080] The difference from Example 1 is that n + The thickness of the ZnOS layer is 15 nm, p + - The polycrystalline silicon layer has a thickness of 100 nm, the SiO2 layer 73 has a thickness of 1.5 nm, and the resistivity of the passivation stack is 8 Ω·cm, thus obtaining a stacked cell.

[0081] Example 4

[0082] The difference from Example 1 is that n + The thickness of the ZnOS layer is 30 nm, p +- The thickness of the polycrystalline silicon layer is 10 nm, the thickness of the SiO2 layer 73 is 2 nm, and the resistivity of the passivation stack is 10 Ω·cm, thus obtaining the stacked cell.

[0083] Example 5

[0084] The difference from Example 1 is that n + The thickness of the ZnOS layer is 40 nm, p + - The thickness of the polycrystalline silicon layer is 5nm, the thickness of the SiO2 layer 73 is 2.5nm, and the resistivity of the passivation stack is 20Ω·cm, finally obtaining the stacked cell.

[0085] Example 6

[0086] The difference from Example 1 is that p in the passivation stack + - The boron doping concentration in the polycrystalline silicon layer is 2×10⁻⁶. 18 cm -3 n + The phosphorus doping concentration in the ZnOS layer is 8 × 10⁻⁶. 19 cm -3 Ultimately, a stacked battery is obtained.

[0087] Example 7

[0088] The difference from Example 1 is that p in the passivation stack + - The boron doping concentration in the polycrystalline silicon layer is 1.5 × 10⁻⁶. 18 cm -3 n + The phosphorus doping concentration in the ZnOS layer is 2.5 × 10⁻⁶. 21 cm -3 Ultimately, a stacked battery is obtained.

[0089] Example 8

[0090] The difference from Example 1 is that n + - The molar ratio of oxygen to sulfur in the ZnOS layer is 1:2, resulting in a tandem battery.

[0091] Example 9

[0092] The difference from Example 1 is that n + - The molar ratio of oxygen to sulfur in the ZnOS layer is 1:3, resulting in a tandem battery.

[0093] Example 10

[0094] The difference from Example 1 is that Cs is used. 0.05 MA 0.95 Pb(I 0.92 Br 0.08)3 (band gap of 1.62 eV) replaces Cs 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 )3, finally obtaining the stacked battery.

[0095] Example 11

[0096] The difference from Example 1 is that Cs is used. 0.05 (FA 0.82 MA 0.18 ) 0.95 Pb(I 0.92 Br 0.08 )3 (band gap of 1.5 eV) replace Cs 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 )3, finally obtaining the stacked battery.

[0097] Example 12

[0098] The difference from Example 1 is that the particle size of CsPbI3 is 100nm, and a stacked battery is finally obtained.

[0099] Example 13

[0100] The difference from Example 1 is that Cs 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 The thickness of the three layers is 300 nm, and the thickness of the CsPbI3 quantum dot layer is 40 nm, thus obtaining a stacked battery.

[0101] Example 14

[0102] The difference from Example 1 is that Cs 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 The thickness of the three layers is 2000 nm, and the thickness of the CsPbI3 quantum dot layer is 30 nm, thus obtaining a stacked battery.

[0103] Example 15

[0104] The difference from Example 1 is that both sides of the silicon wafer (n-type CzSi, 200 μm thick) were polished, followed by RCA (a cleaning method proposed by American Wireless) cleaning to remove metal impurities. Then, double-sided texturing was performed using a sodium hydroxide aqueous solution with 10% isopropanol as an additive. The texturing temperature was 80°C, resulting in a pyramidal textured surface with a thickness of 1.2 μm. The silicon wafer was placed in an 800°C dry oxygen environment to form SiO2 layers with a thickness of 1.5 nm on both sides. Amorphous silicon layers were deposited on the SiO2 layers on both sides using low-pressure chemical vapor deposition at 620°C and 300 mTorr. The thickness of the amorphous silicon layers on both sides was 90 nm. One side of the amorphous silicon layer was doped in a POCl3 atmosphere at 880°C to form n-type CzSi. + -Si layer, in BCl3 atmosphere, at 950℃, doping of the amorphous silicon layer on the other side to form p + -Si layer, and finally annealed in hydrogen at 750°C for 30 min to form the first SiO layer on one side of the silicon wafer. x Layer 82 and n-type polycrystalline silicon layer 81, first SiO x The total thickness of layer 82 and n-type polysilicon layer 81 is 91.5 nm, and a second SiO is formed on the other side of the silicon wafer. x Layer 101 and p-type polycrystalline silicon layer 102, second SiO x The total thickness of layer 101 and p-type polysilicon layer 102 is 91.5 nm. α-Si deposition is performed during oxygen introduction to form a 1.5 nm thick SiO2 layer on the n-type polysilicon layer 81. A 10 nm thick boron-doped α-Si layer (doping concentration of 2 × 10⁻⁶) is then deposited on the SiO2 layer using plasma-enhanced chemical vapor deposition. 19 cm -3 Then anneal at 700℃ for 1 min to form p + - A polycrystalline silicon layer (10 nm thick) was deposited on p-type silicon using magnetron sputtering (working pressure 0.3 Pa, power 150 W, deposition rate 2 nm / s) to deposit ZnO, phosphorus, and ZnS. + - An n-type layer with a thickness of 15nm is formed on the polycrystalline silicon layer. + -ZnOS layer (doping concentration of 2×10⁻⁶) 21 cm -3 The molar ratio of oxygen to sulfur was 1:1, and then annealed at 350℃ under nitrogen for 10 min to obtain a passivated stack with a resistivity of 3 Ω·cm. NiO was then sputtered (oxygen partial pressure 10%). x Nanoparticles (average particle size 3 nm) are deposited on n + A hole transport layer with a thickness of 5 nm is formed on the ZnOS layer. Cs 0.05 (FA 0.92 MA0.08 ) 0.95 Pb(I 0.92 Br 0.08 3. The precursor solution was spin-coated (4000 rpm) onto the hole transport layer, quenched with chlorobenzene as an antisolvent, and then annealed at 100°C for 30 min to form a Cs layer with a thickness of 300 nm. 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 Three layers (band gap 1.68 eV) were formed by spraying a CsPbI3 solution (concentration 10 mg / mL, solvent n-hexane, CsPbI3 particle size 8 nm) onto a CsPbI3 substrate. 0.05 (FA 0.92 MA 0.08 ) 0.95 Pb(I 0.92 Br 0.08 The CsPbI3 quantum dot layer is then dried to form a 30 nm thick CsPbI3 quantum dot layer. A 25 nm thick C60 layer is formed on the CsPbI3 quantum dot layer by thermal evaporation. A 25 nm thick SnO2 layer is formed on the C60 layer by atomic deposition (at a temperature of 100 °C). A 10 nm thick conductive layer is formed on the SnO2 layer by sputtering indium tin oxide. A 200 nm thick first electrode is formed on the conductive layer by thermal evaporation of silver. A 120 nm thick anti-reflection layer is formed on the first electrode by evaporation of MgF2. A 10 nm thick Al2O3 layer was deposited on a p-type polycrystalline silicon layer 102 using atomic layer deposition (trimethylaluminum as the precursor, temperature 150℃, and a deposition thickness of 0.12 nm per cycle). A 90 nm thick SiN layer was then formed on the surface of the Al2O3 layer using plasma-enhanced chemical vapor deposition (SiH4 to NH3 volume ratio 1:3, RF power 300 W). x (x is 1.5~1.8), and finally a passivation layer with a thickness of 100nm is formed on the surface of the p-type polycrystalline silicon layer 102. Silver paste (linewidth of 15μm and thickness of 30μm) is screen-printed on the surface of the passivation layer, and sintering is carried out in a chain furnace at a peak temperature of 800℃ under N2 atmosphere to form a second electrode, thus obtaining a tandem cell.

[0105] Comparative Example 1

[0106] The difference from Example 1 is that an ITO layer is used to replace n. + -ZnOS layer, finally to obtain stacked battery.

[0107] Comparative Example 2

[0108] The difference from Example 1 is that the addition of phosphorus is omitted, forming a ZnOS layer, and finally obtaining a stacked battery.

[0109] Comparative Example 3

[0110] The difference from Example 1 is that the addition of ZnS is omitted, resulting in n + -ZnO layer, finally to obtain stacked battery.

[0111] Performance testing

[0112] Resistivity testing of the passivation stack: A four-point probe method is used. During testing, the two outer probes inject a known current into the sample, while the two inner probes measure the resulting voltage drop. The sheet resistance of the passivation stack is calculated using Ohm's law, and the resistivity is then calculated using the formula.

[0113] Thickness testing of each layer: ellipsometry was used for measurement.

[0114] The doping concentration was measured using an electrochemical capacitance-voltage tester, and the result was calculated using the average value.

[0115] Test method for photoelectric conversion efficiency of tandem solar cells: 25℃, one atmosphere, under standard simulated sunlight (AM1.5G, 100 milliwatts per square centimeter (mW / cm²)). 2 Under irradiation, the battery performance was tested to obtain the IV curve (volt-ampere characteristic curve). Based on the IV curve and the data fed back by the testing equipment (four-channel digital source meter, Keithley 2450), the short-circuit current density Jsc (unit: milliampere / cm²) can be obtained. 2 )), Open circuit voltage Voc (unit: volts (V)).

[0116] The fill factor FF of the battery can be calculated using the formula FF = Jsc × Voc / (Jmpp × Vmpp), in percentage. The photoelectric conversion efficiency PCE of the battery can be calculated using the formula PCE = Jsc × Voc × FF / Pw, in percentage; Pw represents the input power, in milliwatts (mW).

[0117] The tandem solar cells prepared in the above embodiments and comparative examples were tested for photoelectric conversion efficiency, open-circuit voltage, short-circuit current density and fill factor, respectively. The test results are shown in Table 1.

[0118] Table 1

[0119]

[0120] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0121] In this application, the introduction of a doped ZnOS layer between the hole transport layer and the doped polycrystalline silicon layer helps to overcome the parasitic absorption limitation of ITO. Furthermore, the doped ZnOS layer exhibits high transmittance and low contact resistance, which helps reduce series resistance and increase current density, thereby improving the fill factor and open-circuit voltage of the battery. The synergistic effect among the doped ZnOS layer, the doped polycrystalline silicon layer, and the SiO2 layer, and the control of different doping types between the doped ZnOS layer and the doped polycrystalline silicon layer, helps to optimize the interfacial contact of the heterojunction, reduce carrier recombination losses, and enhance the mechanical strength and chemical stability of the entire tandem battery system. Therefore, the tandem battery of this application exhibits high photoelectric conversion efficiency.

[0122] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A stacked battery, characterized in that, The tandem battery includes a first electrode (20), an electron transport layer (40), an absorption layer (50), a hole transport layer (60), a passivation layer (70), a silicon substrate (90), and a second electrode (120) stacked sequentially; wherein, the passivation layer (70) includes a doped ZnOS layer (71), a doped polycrystalline silicon layer (72), and a SiO2 layer (73) stacked sequentially, and the doped ZnOS layer (71) and the doped polycrystalline silicon layer (72) have different doping types, and the doped ZnOS layer (71) is located between the hole transport layer (60) and the doped polycrystalline silicon layer (72).

2. The stacked battery according to claim 1, characterized in that, The resistivity of the passivation stack (70) is 3~20 Ω·cm.

3. The stacked battery according to claim 1, characterized in that, The thickness of the passivation stack (70) is 26.5~132nm.

4. The stacked battery according to claim 1, characterized in that, The thickness of the doped ZnOS layer (71) is 15~30nm; the thickness of the doped polycrystalline silicon layer (72) is 10~100nm; and the thickness of the SiO2 layer (73) is 1.5~2nm.

5. The stacked battery according to any one of claims 1 to 4, characterized in that, The doping concentration in the doped polycrystalline silicon layer (72) is 2×10⁻⁶. 18 ~2×10 19 cm -3 .

6. The stacked battery according to any one of claims 1 to 4, characterized in that, The doping concentration in the doped ZnOS layer (71) is 8 × 10⁻⁶. 19 ~2×10 21 cm -3 .

7. The stacked battery according to any one of claims 1 to 4, characterized in that, The molar ratio of oxygen to sulfur in the doped ZnOS layer (71) is (1~2):(1~2).

8. The stacked battery according to any one of claims 1 to 4, characterized in that, The absorption layer (50) includes a stacked ABX3 layer (52) and a CsPbI3 quantum dot layer (51), and the CsPbI3 quantum dot layer (51) is close to the electron transport layer (40), wherein A is selected from any one or more of Cs, CH(NH2)2 and CH3NH3, B is Pb, and X is selected from any one or more of Cl, Br and I.

9. The stacked battery according to any one of claims 1 to 4, characterized in that, The stacked battery also includes an anti-reflective layer (10) disposed on the side of the first electrode (20) away from the electron transport layer (40).

10. The stacked battery according to claim 9, characterized in that, The thickness of the anti-reflective layer (10) is 100~120nm.

11. The stacked battery according to claim 9, characterized in that, The anti-reflective layer (10) is made of MgF2.

12. A method for preparing a stacked battery, wherein the stacked battery is the stacked battery according to any one of claims 1 to 11, characterized in that, The preparation method includes: Step S1: Deposit the second electrode material on one side of the silicon wafer to form the second electrode. Introduce oxygen and deposit silicon to form a SiO2 layer. Then, introduce the first doping source to form a doped amorphous silicon layer on the side of the SiO2 layer away from the silicon wafer. Then, perform a first annealing process to form a doped polycrystalline silicon layer. Deposit ZnO, the second doping source and ZnS by magnetron sputtering. Then, perform a second annealing process to form a doped ZnOS layer. The first doping source and the second doping source are of different types. Step S2: Deposit hole transport material on the side of the doped ZnOS layer away from the doped polysilicon layer to form a hole transport layer; Step S3: Deposit the absorber material on the side of the hole transport layer away from the doped ZnOS layer to form an absorber layer; Step S4: Deposit electron transport material on the side of the absorption layer away from the hole transport layer to form an electron transport layer; Step S5: Deposit the first electrode material on the side of the electron transport layer away from the absorption layer to form the first electrode, thereby obtaining the stacked battery.

13. The method for preparing a stacked battery according to claim 12, characterized in that, The temperature of the first annealing treatment is 700~900℃; the time of the first annealing treatment is 1~40min.

14. The method for preparing a stacked battery according to claim 12 or 13, characterized in that, The magnetron sputtering pressure is 0.3~0.5 Pa; the magnetron sputtering power is 150~300 W; the magnetron sputtering deposition rate is 2~5 nm / s; and / or, the temperature of the second annealing treatment is 350~450 °C; and the time of the second annealing treatment is 10~30 min.

15. A photovoltaic module, comprising a battery string, an encapsulating film, and a cover plate, characterized in that, The battery string is formed by connecting multiple stacked batteries prepared by the method of any one of claims 1 to 11 or any one of claims 12 to 14.

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