Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. A display device according to an embodiment may include: a first substrate defining a display area and a non-display area; the display component is arranged on the first substrate and is used for displaying an image; the second substrate is arranged on the display assembly; the filling layer is arranged between the first substrate and the second substrate; and a sealing member located at edge portions of the first substrate and the second substrate and coupling the first substrate and the second substrate. The packing layer may include a first packing layer and a second packing layer each including a different material. The second packing layer may be spaced apart from the sealing member with an empty space therebetween.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0081268 filed on June 21, 2024, and Korean Patent Application No. 10-2024-0084259 filed on June 27, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, a method of manufacturing a display device, and an electronic device including a display device. Background Technology

[0004] In recent years, with the increasing interest in information display, research and development of display devices has been ongoing. Summary of the Invention

[0005] The purpose of this disclosure is to provide a display device with improved reliability and a method for manufacturing the display device.

[0006] The display device according to the embodiments may include: a first substrate defining a display area and a non-display area; a display component disposed on the first substrate and displaying an image; a second substrate disposed on the display component; a filler layer disposed between the first substrate and the second substrate; and a sealing member located at the edge portions of the first substrate and the second substrate and connecting the first substrate and the second substrate. The filler layer may include a first filler layer and a second filler layer each comprising different materials. The second filler layer may be spaced apart from the sealing member, having an empty space therebetween.

[0007] In an embodiment, each of the first filler layer and the second filler layer may comprise a thermosetting resin or a UV-curable resin formed from a filler material, a catalyst, and a crosslinking compound.

[0008] In this embodiment, the filler material may include silicon (Si), the catalyst may include platinum (Pt), and the crosslinking compound may contain Si-H groups.

[0009] In an embodiment, the crosslinking compound of the second filler layer may have a content greater than or equal to about 70% of the crosslinking compound of the first filler layer.

[0010] In one embodiment, the filling material of the second filling layer may have a content greater than or equal to about 70% of the filling material of the first filling layer.

[0011] In an embodiment, the catalyst in the second filling layer may have a content greater than or equal to about 70% of the catalyst in the first filling layer.

[0012] In this embodiment, the second substrate may be a glass substrate.

[0013] In this implementation, the empty space may be a vacuum or may be filled with gas.

[0014] In an embodiment, the display component may include: a pixel circuit layer disposed on a first substrate; a light-emitting element layer including a light-emitting element comprising a first electrode disposed on the pixel circuit layer, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer; and a thin film encapsulation layer disposed between the light-emitting element layer and the fill layer.

[0015] The display device according to an embodiment may include: a first substrate defining a display area and a non-display area; a display component disposed on the first substrate and displaying an image; a second substrate disposed on the display component; a filler layer disposed between the first substrate and the second substrate; and a sealing member located at the edge portions of the first substrate and the second substrate and connecting the first substrate and the second substrate. The filler layer may include a first filler layer and a second filler layer formed from respective filler materials, catalysts, and crosslinking compounds. The first filler layer and the second filler layer may include materials different from each other. The crosslinking compound of the second filler layer may have a content greater than or equal to about 70% of the crosslinking compound of the first filler layer.

[0016] In one embodiment, the second filling layer may be spaced apart from the sealing member, with an empty space between them.

[0017] In this embodiment, the first substrate and the second substrate may be glass substrates.

[0018] The display device according to the above embodiments can be manufactured by the following method, which includes: preparing a first mother substrate defining a display area and a non-display area; forming a display assembly on the surface of the first mother substrate; applying a sealing member along an edge to the surface of the first mother substrate; applying a filler layer to the surface of a second mother substrate; joining (e.g., bonding) the surfaces of the first mother substrate and the second mother substrate; and separating the first mother substrate and the second mother substrate in units of display units. The filler layer may include a first filler layer and a second filler layer, each comprising different materials. The second filler layer may be spaced apart from the sealing member, having empty spaces therebetween.

[0019] In an embodiment, each of the first filler layer and the second filler layer may comprise a thermosetting resin or an ultraviolet (UV) curable resin formed from a filler material, a catalyst, and a crosslinking compound.

[0020] In this embodiment, the filler material may include silicon (Si), the catalyst may include platinum (Pt), and the crosslinking compound may contain Si-H groups.

[0021] In an embodiment, the crosslinking compound of the second filler layer may have a content greater than or equal to about 70% of the crosslinking compound of the first filler layer.

[0022] In one embodiment, when a filling layer is applied to the surface of a second mother substrate, the second filling layer may be applied to the surface of the second mother substrate that overlaps with a region within approximately 500 μm of the display area from the boundary between the display area and the non-display area toward the display area.

[0023] In one embodiment, the connection between the surfaces of the first mother substrate and the second mother substrate may include irradiating a sealing member with a laser beam.

[0024] In one embodiment, the method may further include curing the filler layer after irradiating the sealing member with a laser beam.

[0025] In one embodiment, the filler layer can be applied to the surface of the second mother substrate using a spray dispenser.

[0026] An electronic device according to an embodiment may include: a processor configured to provide input image data to a display device; and a display device configured to display an image based on the input image data. The display device includes: a first substrate defining a display area and a non-display area; a display assembly disposed on the first substrate and displaying an image; a second substrate disposed on the display assembly; a filler layer disposed between the first substrate and the second substrate; and a sealing member located at the edge portions of the first substrate and the second substrate and connecting the first substrate and the second substrate. The filler layer includes a first filler layer and a second filler layer each comprising different materials. The second filler layer is spaced apart from the sealing member, having an empty space therebetween.

[0027] According to embodiments of the display device, a filler layer may be disposed between a first substrate (or display substrate) and a second substrate (or encapsulation substrate). The filler layer may include: a first filler layer located in a first region of the second substrate overlapping the display region of the first substrate; and a second filler layer adjacent to the first filler layer, comprising a material different from that of the first filler layer. This arrangement can reduce or prevent defects (such as tearing of the outer portion of the display panel) caused by spreadability deviations of the filler layer components in the central and outer portions of the display region, thereby improving the reliability of the display device.

[0028] The effects of the implementation are not limited to the examples provided, and encompass a wider range of effects as described in this specification. Attached Figure Description

[0029] Figure 1 A schematic perspective view illustrating a display device according to an embodiment.

[0030] Figure 2A schematic cross-sectional view illustrating the display panel according to an embodiment.

[0031] Figure 3 To explain Figure 1 A schematic cross-sectional view of the display panel.

[0032] Figure 4 To explain Figure 2 A schematic diagram illustrating the implementation of the sub-pixel.

[0033] Figure 5 To explain Figure 2 A schematic planar diagram of pixels.

[0034] Figure 6 For along Figure 5 A schematic cross-sectional view taken from line II-II'.

[0035] Figure 7 For along Figure 2 A schematic cross-sectional view taken from line I-I'.

[0036] Figure 8 A schematic block diagram illustrating a method for manufacturing a display device according to an embodiment.

[0037] Figures 9 to 19 A schematic diagram illustrating the process steps of a method for manufacturing a display device according to an embodiment.

[0038] Figure 20 A schematic block diagram illustrating an electronic device according to an embodiment.

[0039] Figure 21 To explain Figure 20 A schematic diagram illustrating an example of an electronic device implemented as a smartphone.

[0040] Figure 22 To explain Figure 20 A schematic diagram illustrating an example of an electronic device implemented as a tablet computer. Detailed Implementation

[0041] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The various embodiments are not necessarily exclusive, nor are they intended to limit the present disclosure. For example, specific shapes, configurations, and characteristics of embodiments may be used or implemented in another embodiment.

[0042] In the accompanying drawings, the dimensions (e.g., thickness), scale, and dimensions of the elements may be enlarged for ease of description and clarity. The same reference numerals and / or reference characters refer to the same elements throughout.

[0043] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0044] The terms “comprises,” “comprising,” “includes,” and / or “including,” “has,” “have,” and / or “having,” and their variations thereof, shall be used in this discussion.

[0045] When used in a document, it indicates the presence of described features, integers, steps, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0046] The phrase "in a plan view" refers to an object viewed from above, and the phrase "in a schematic cross-sectional view" refers to a cross-section of an object cut perpendicularly from the side. Therefore, the expression "in a plan view" as used herein can mean in a third-direction DR3 (see...). Figure 1 The phrase "in a schematic cross-sectional view" refers to viewing the object from the side at the first DR1 (see diagram). Figure 1 ) Direction or second direction DR2 (see Figure 1 ) Observe the cross section of a vertically cut object

[0047] Face. Third direction DR3 (see Figure 1 It can also be referred to as the "thickness direction".

[0048] Furthermore, throughout the specification, the term “on” the target element will be understood to mean located above or below the target element, and will not necessarily be understood to mean located “on the upper side” based on a direction opposite to the direction of gravity.

[0049] When an element (such as a layer, section, or portion) is referred to as being "on" another element or layer, "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly attached to" another element or layer, no intermediary element or layer is present. For this purpose, the term "connection" may refer to a physical connection and / or an electrical connection, with or without an intermediary element.

[0050] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” or “on” are used herein to describe the relationship between one element or component and another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, in the case where the device illustrated in the drawings is flipped, the device located “below” or “under” another device may be placed “on top” of the other device. Accordingly, the interpretative term “below” can include both “down” and “up” positions. The device may also be oriented in other directions, and therefore spatial relative terms may be interpreted differently depending on the orientation.

[0051] As used herein, the singular forms “a”, “an”, and “the” are intended to also include the plural forms unless the context clearly indicates otherwise.

[0052] As used herein, the terms “about” or “approximately” include stated values ​​and mean within an acceptable range of deviations from a particular value, determined by consideration of the measurements discussed and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system) by a person skilled in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0053] In the specification and claims, the term "and / or" is intended, for the purposes of its meaning and interpretation, to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a connecting or separating sense and are to be understood as equivalent to "and / or".

[0054] In the specification and claims, the phrase "at least one of..." is intended, for the purposes of its meaning and interpretation, to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0055] Unless otherwise specified or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in commonly used dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0056] In the following, embodiments of the present disclosure, as well as other details required for a person skilled in the art to readily understand the present disclosure, will be explained in detail with reference to the accompanying drawings.

[0057] Figure 1 A schematic perspective view illustrating a display device DD according to an embodiment. Figure 1 For convenience, the structure of the display device DD is briefly explained with the display area DA in which the image is displayed as the center, including, for example, the display panel DP provided in the display device DD.

[0058] refer to Figure 1 A display device DD can display images. A display device DD can refer to any electronic device that provides a display surface. For example, a display device DD can include, but is not limited to, televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, mobile phones, smartphones, tablet computers, electronic watches, smartwatches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and camcorders.

[0059] Display devices DD can be flat panel displays, flexible displays, curved displays, foldable displays, bendable displays, or rollable displays. Display devices DD can also be used in transparent display devices, head-mounted display devices, wearable display devices, etc.

[0060] The display device DD may include a display panel DP that provides a display surface. Examples of the display panel DP may include, but are not limited to, inorganic light-emitting display panels, organic light-emitting diode display panels, quantum dot light-emitting display panels, plasma display panels, and field emission display panels. The following describes an embodiment in which an organic light-emitting diode display panel is used as an example of a display panel DP, but this disclosure is not limited thereto, and the same technical concept can be applied to other display panels in which it is applicable.

[0061] The shape of the display device DD can vary. For example, the display device DD can have different shapes, such as rectangles, squares (including squares with rounded corners (or vertices), other polygons, and circles. The shape of the display area DA of the display device DD can correspond to the overall shape of the display device DD. Figure 1 In the diagram, the display device DD and the display area DA are represented as rectangles.

[0062] The display device DD may include a display area DA and a non-display area NDA. The display area DA may refer to the area in which an image is displayed, and the non-display area NDA may refer to the area in which no image is displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may be referred to as a passive area. The display area DA may be located at the center of the display device DD, but is not limited to this arrangement.

[0063] The display area DA may be an area in which subpixels SP (or pixels) are provided. Subpixels SP may include at least one light-emitting element. For example, the light-emitting element may include a light-emitting layer (e.g., an organic light-emitting layer). The portion emitting light from the light-emitting element may be defined as the light-emitting area. The display device DD may display an image in the display area DA by driving the subpixels SP in response to image data.

[0064] The non-display area NDA can be a region located near the display area DA. In implementations, the non-display area NDA can refer to the remaining area on the display panel DP other than the display area DA. For example, the non-display area NDA may include wiring areas, pad areas, and dummy areas.

[0065] exist Figure 1 The accompanying drawings show a first direction DR1, a second direction DR2, and a third direction DR3. The directions indicated by DR1, DR2, and DR3 are relative concepts and may correspond to different directions. In this specification, DR1 and DR2 may be orthogonal to each other, and DR3 may be the normal direction of the plane defined by DR1 and DR2, but is not limited thereto.

[0066] The thickness direction of the display device DD may be parallel to a third direction DR3, which is the normal direction of the plane defined by the first direction DR1 and the second direction DR2. In this specification, the upper surface (or top surface) and lower surface (or bottom surface) of the components forming the display device DD may be defined based on the third direction DR3.

[0067] Figure 2 A schematic cross-sectional view of the display panel DP according to an embodiment is provided, and Figure 3 To explain Figure 1A schematic cross-sectional view of the display panel DP.

[0068] refer to Figures 1 to 3 According to the embodiments, the display panel DP (or display device DD) may include a first substrate SUB1, a display element layer DPL, a second substrate SUB2, a filler layer 100, and a sealing member SM. The sealing member SM can bond the first substrate SUB1 and the second substrate SUB2. Each of the first substrate SUB1 and the second substrate SUB2 may include a display area DA and a non-display area NDA.

[0069] The first substrate SUB1 can be used as the substrate of the display panel DP. The first substrate SUB1 can be made of a rigid material. For example, the first substrate SUB1 may include glass, but is not limited to this material. In an embodiment, the first substrate SUB1 may include quartz.

[0070] The display element layer DPL can be disposed on the surface of the first substrate SUB1 on the third-direction DR3 (hereinafter referred to as the "upper surface").

[0071] The display element layer (DPL) (or display assembly) can display an image, thereby defining the display area DA of the display panel DP. For example, the area on the first substrate SUB1 where the display element layer DPL is disposed can be the display area DA, and the area where the display element layer DPL is not disposed can be the non-display area NDA. The display element layer DPL may overlap with the display area DA on the third direction DR3, and may not overlap with the non-display area NDA on the third direction DR3.

[0072] The display element layer (DPL) may include elements and circuitry for displaying images, such as pixel circuitry (e.g., switching elements) and light-emitting elements electrically connected to the pixel circuitry. The pixel circuitry and light-emitting elements may form sub-pixels (SPs).

[0073] The display panel DP may include subpixels SP. Subpixels SP may be disposed in the display area DA on the first substrate SUB1. Subpixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of subpixels SP is not limited to this example. For example, subpixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, subpixels SP may be arranged in a pentile pattern. Arrangement. The first direction DR1 can correspond to the row direction, and the second direction DR2 can correspond to the column direction. Two or more sub-pixels SP from multiple sub-pixels SP can form a single pixel PXL.

[0074] The pad PD can be disposed in the non-display area NDA on the first substrate SUB1. The pad PD can be electrically connected to the sub-pixel SP via wiring. The pad PD can connect the display panel DP and other components of the display device DD.

[0075] The second substrate SUB2 may be disposed on the display element layer DPL. The second substrate SUB2 may serve as an encapsulation substrate to protect the display element layer DPL. The second substrate SUB2 may face the first substrate SUB1. The second substrate SUB2 may be a rigid glass substrate. The second substrate SUB2 may have a refractive index that is substantially constant in the visible wavelength range.

[0076] In the non-display area NDA, a sealing member SM may be disposed between the first substrate SUB1 and the second substrate SUB2. The sealing member SM may be disposed along the edges of the first substrate SUB1 and the second substrate SUB2 in the non-display area NDA to surround the display area DA in a plan view. The first substrate SUB1 and the second substrate SUB2 may be connected by the sealing member SM. In embodiments, the sealing member SM may be made of inorganic or organic materials. For example, the sealing member SM may include, but is not limited to, inorganic materials (such as glass frit) or organic materials (such as epoxy resin).

[0077] In the display area DA, a filler layer 100 may be disposed between the first substrate SUB1 and the second substrate SUB2. The filler layer 100 may act as a buffer against external pressures applied to the display panel DP, but is not limited to this function. The filler layer 100 may maintain the gap between the first substrate SUB1 and the second substrate SUB2. The filler layer 100 extends into the non-display area NDA between the first substrate SUB1 and the second substrate SUB2, and may be spaced apart from the sealing member SM, creating an empty space between the filler layer 100 and the sealing member SM. This empty space, not occupied by liquid or solid material, may be vacuum, filled with air, or filled with other gases, but is not limited to these.

[0078] The filler layer 100 may include a material capable of transmitting light. For example, the filler layer 100 may include an organic material, such as a silicone resin or an epoxy acrylic resin. The filler layer 100 may include a material suitable for refractive index matching. In an embodiment, the filler layer 100 may include a first filler layer 110 and a second filler layer 120. The first filler layer 110 and the second filler layer 120 may include different materials. The filler layer 100 will be described in detail later.

[0079] Figure 4 To explain Figure 2 A schematic diagram illustrating the implementation of the sub-pixel SP. Figure 4 Explanation Figure 2Subpixels SPij are arranged in rows i (where i is greater than or equal to 1 and less than or equal to m) and columns j (where j is greater than or equal to 1 and less than or equal to n) of subpixels SP.

[0080] refer to Figure 2 and Figure 4 Each subpixel SPij may include a subpixel circuit SPC and a light-emitting element LD.

[0081] The light-emitting element (LD) can be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN can transmit a first power supply voltage, and the second power supply voltage node VSSN can transmit a second power supply voltage. The first power supply voltage can have a relatively high voltage level, and the second power supply voltage can have a lower voltage level than the first power supply voltage.

[0082] The anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0083] The sub-pixel circuit (SPC) can be electrically connected to signal lines. For example, the SPC can be electrically connected to the i-th gate line GLi, the i-th light-emitting control line ELi, and the j-th data line DLj. The SPC can control the light-emitting element (LD) based on signals received through these signal lines.

[0084] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In some embodiments, such as Figure 4 As shown, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to the gate signal received through the respective sub-gate line.

[0085] The sub-pixel circuit SPC can operate in response to a light emission control signal received via the i-th light emission control line ELi. In some embodiments, the i-th light emission control line ELi may include one or more sub-light emission control lines. When the i-th light emission control line ELi includes two or more sub-light emission control lines, the sub-pixel circuit SPC can operate in response to a light emission control signal received via the respective sub-light emission control line.

[0086] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN according to the stored voltage, in response to a light emission control signal received via the i-th light emission control line ELi. Accordingly, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0087] Figure 5 To explain Figure 2 A schematic plan view of the pixel PXL.

[0088] refer to Figure 2 and Figure 5 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that can be arranged in the first direction DR1.

[0089] The first sub-pixel SP1 may include a first light-emitting region EMA1 and a non-light-emitting region NEA surrounding the first light-emitting region EMA1. The second sub-pixel SP2 may include a second light-emitting region EMA2 and a non-light-emitting region NEA surrounding the second light-emitting region EMA2. The third sub-pixel SP3 may include a third light-emitting region EMA3 and a non-light-emitting region NEA surrounding the third light-emitting region EMA3.

[0090] The first light-emitting region EMA1 can be a region in which light is emitted from the light-emitting layer corresponding to the first sub-pixel SP1. The second light-emitting region EMA2 can be a region in which light is emitted from the light-emitting layer corresponding to the second sub-pixel SP2. The third light-emitting region EMA3 can be a region in which light is emitted from the light-emitting layer corresponding to the third sub-pixel SP3. Each light-emitting region can be understood as an opening in the pixel-defining layer corresponding to each of the first sub-pixel SP1 to the third sub-pixel SP3 (see...). Figure 6 (OP in the text).

[0091] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have substantially the same area, but are not limited to this configuration. In some embodiments, the second sub-pixel SP2 may have an area larger than that of the first sub-pixel SP1, and the third sub-pixel SP3 may have an area larger than that of the second sub-pixel SP2.

[0092] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have polygonal shapes. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have rectangular or hexagonal shapes, but are not limited to these shapes. In some embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have circular or semi-elliptical shapes, etc.

[0093] Figure 5 The arrangement of the first sub-pixels SP1 to the third sub-pixels SP3 shown is illustrative, and the implementation is not limited to this example. Each pixel PXL may include two or more sub-pixels SP, and the sub-pixels SP may be arranged in various ways. Each of the sub-pixels SP may have various shapes, and each of the light-emitting regions of the sub-pixels SP may also have various shapes.

[0094] Figure 6 For along Figure 5 A schematic cross-sectional view taken from line II-II'.

[0095] exist Figure 6 For ease of explanation, the cross-sectional structure (or stacking structure) of the display device DD is briefly explained with the pixel PXL included in the display device DD as the center. The thickness direction of each of the first substrate SUB1 and the second substrate SUB2 is indicated by the third direction DR3.

[0096] refer to Figure 5 and Figure 6 The display device DD may include components disposed in the display area (see...). Figure 2 At least one pixel PXL in the display area DA (see "DA"). Pixel PXL can provide space in the display area DA (see "DA"). Figure 2 )middle.

[0097] Pixel PXL may include at least one sub-pixel SP. For example, pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. In some embodiments, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel, but is not limited thereto. Hereinafter, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are collectively referred to as a sub-pixel SP and / or multiple sub-pixels SP.

[0098] Each of the first sub-pixels SP1 to the third sub-pixels SP3 may include a first substrate SUB1, a display element layer DPL, and a second substrate SUB2. A fill layer 100 may be disposed between the first substrate SUB1 and the second substrate SUB2.

[0099] The first substrate SUB1 may include a transparent insulating material and be capable of transmitting light. The first substrate SUB1 may be a rigid substrate.

[0100] The display element layer (DPL) (or display assembly) may be disposed on the upper surface of the first substrate SUB1. The display element layer DPL may include a pixel circuit layer (PCL), a light-emitting element layer (LDL), and a thin-film encapsulation layer (TFE). The pixel circuit layer (PCL) and the light-emitting element layer (LDL) may be disposed overlapping each other on the upper surface of the first substrate SUB1.

[0101] At least one insulating layer may be disposed in the pixel circuit layer PCL. As an example, the insulating layer may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a via layer VIA, which are sequentially stacked along the third direction DR3 on the upper surface of the first substrate SUB1. The insulating layer disposed in the pixel circuit layer PCL is not limited to the above embodiment, and other insulating layers may be added, or some insulating layers may be omitted.

[0102] The buffer layer BFL can be completely disposed on the first substrate SUB1. The buffer layer BFL prevents impurities from diffusing into circuit elements (or forming sub-pixel circuits) (see...). Figure 4 The buffer layer BFL can be an inorganic insulating film comprising inorganic materials. The buffer layer BFL may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following. The buffer layer BFL may be provided as a single layer or as a multilayer comprising two or more layers. When the buffer layer BFL is provided as a multilayer, each layer may comprise the same material or different materials. Depending on the substrate material and process conditions, the buffer layer BFL may be omitted.

[0103] The gate insulating layer GI may be entirely disposed on the buffer layer BFL. The gate insulating layer GI and the buffer layer BFL may comprise the same material, or may comprise one or more suitable (or selected) materials mentioned as constituent materials of the buffer layer BFL. For example, the gate insulating layer GI may be an inorganic insulating film comprising inorganic materials.

[0104] The interlayer insulating layer (ILD) may be entirely provided and / or formed on the gate insulating layer (GI). The interlayer insulating layer (ILD) and the buffer layer (BFL) may comprise the same material, or may comprise one or more suitable (or selected) materials mentioned as constituent materials of the buffer layer (BFL).

[0105] The via layer (VIA) may be entirely provided and / or formed on the interlayer insulating layer (ILD). The via layer (VIA) may be an inorganic insulating film comprising inorganic materials or an organic insulating film comprising organic materials. The inorganic insulating film may include, for example, silicon oxide (SiO₂). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO x At least one of the following: organic insulating film. The organic insulating film may include, for example, at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In some embodiments, the through-hole layer VIA may be an organic insulating film comprising organic materials.

[0106] The via layer (VIA) may be partially open to include vias. These vias may be connection holes for electrically connecting the sub-pixel circuitry (SPC) of each sub-pixel (SP) to the light-emitting element (LD).

[0107] The circuit elements (or the circuits forming the sub-pixel circuits) of each of the first sub-pixel SP1 to the third sub-pixel SP3 are shown in [reference]. Figure 4 The driving elements (e.g., transistors) of the "SPC" in the image can be disposed in the pixel circuit layer PCL. For example, transistor T_SP1 of the first sub-pixel SP1, transistor T_SP2 of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be disposed in the pixel circuit layer PCL. Transistor T_SP1 of the first sub-pixel SP1 can be one of the transistors included in the sub-pixel circuit SPC of the first sub-pixel SP1, transistor T_SP2 of the second sub-pixel SP2 can be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 6 In order to provide a clear and concise explanation, only one transistor of each sub-pixel SP is shown, while the rest of the circuit elements are omitted.

[0108] The transistor T_SP1 of the first sub-pixel SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and a second terminal EL2.

[0109] The gate electrode GE may be disposed on the gate insulating layer GI and covered by the interlayer insulating layer ILD. For example, the gate electrode GE may be a gate conductive layer disposed between the gate insulating layer GI and the interlayer insulating layer ILD. The gate electrode GE may overlap with a portion of the semiconductor pattern SCP. For example, the gate electrode GE may overlap with the active pattern of the semiconductor pattern SCP.

[0110] A semiconductor pattern SCP can be provided and / or formed on a buffer layer BFL. The semiconductor pattern SCP can be a semiconductor layer including polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The semiconductor pattern SCP may include an active pattern, a first contact region, and a second contact region. The active pattern, the first contact region, and the second contact region may include semiconductor layers doped or undoped. For example, the first and second contact regions may include doped semiconductor layers, while the active pattern may include undoped semiconductor layers. The active pattern may be a region doped at a lower concentration than the first and second contact regions. Accordingly, the conductivity of the first and second contact regions may be greater than the conductivity of the active pattern. The first and second contact regions can be used as the source / drain region (or source electrode / drain electrode) of the transistor T_SP1 of the first sub-pixel SP1.

[0111] The active pattern of the semiconductor pattern SCP is the region that overlaps with the gate electrode GE and can be used as a channel region. A first contact region of the semiconductor pattern SCP can be connected to one end of the active pattern and electrically connected to a first terminal EL1. A second contact region of the semiconductor pattern SCP can be connected to the other end of the active pattern and electrically connected to a second terminal EL2.

[0112] A first terminal EL1 may be provided and / or formed on an interlayer insulating layer ILD. For example, the first terminal EL1 may include a source-drain conductive layer formed between the interlayer insulating layer ILD and the via layer VIA. The first terminal EL1 may contact a first contact area of ​​the semiconductor pattern SCP through a contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0113] The second terminal EL2 may be provided and / or formed on the interlayer insulating layer ILD and may be spaced apart from the first terminal EL1. The second terminal EL2 may include a source-drain conductive layer formed between the interlayer insulating layer ILD and the via layer VIA. The second terminal EL2 may contact a second contact area of ​​the semiconductor pattern SCP through another contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0114] According to the implementation method, the lower metal pattern BML can be disposed below the transistor T_SP1 of the first sub-pixel SP1.

[0115] The lower metal pattern BML can be a conductive layer located between the first substrate SUB1 and the buffer layer BFL. According to an embodiment, the lower metal pattern BML can be electrically connected to the transistor T_SP1 of the first sub-pixel SP1 to increase the driving range of the voltage supplied to the gate electrode GE.

[0116] Since the gate electrode GE, the first terminal EL1, and the second terminal EL2 are electrically connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be provided as one of the transistors in the sub-pixel circuit SPC that forms the first sub-pixel SP1.

[0117] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be substantially the same as the transistor T_SP1 of the first sub-pixel SP1.

[0118] As described above, the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0119] A light-emitting element layer (LDL) may be disposed on a pixel circuit layer (PCL). The LDL may include a light-emitting element (LD) and a pixel definition layer (PDL). The LD may include a lower electrode, a light-emitting layer, and a upper electrode (UE). A light-emitting element (LD) may be provided in each of the first sub-pixels SP1 to SP3. The LD provided in the first sub-pixel SP1 may be a first light-emitting element (LD1), the LD provided in the second sub-pixel SP2 may be a second light-emitting element (LD2), and the LD provided in the third sub-pixel SP3 may be a third light-emitting element (LD3).

[0120] The first lower electrode LE1 can be disposed on the pixel circuit layer PCL (or via layer VIA) of the first sub-pixel SP1, the second lower electrode LE2 can be disposed on the pixel circuit layer PCL (or via layer VIA) of the second sub-pixel SP2, and the third lower electrode LE3 can be disposed on the pixel circuit layer PCL (or via layer VIA) of the third sub-pixel SP3. Each of the first lower electrode LE1 to the third lower electrode LE3 can be electrically connected to a circuit element disposed in the pixel circuit layer PCL through a via through the via layer VIA. For example, the first lower electrode LE1 can be electrically connected to the transistor T_SP1 of the first sub-pixel SP1 through the first via VIH1 through the via layer VIA, the second lower electrode LE2 can be electrically connected to the transistor T_SP2 of the second sub-pixel SP2 through the second via VIH2 through the via layer VIA, and the third lower electrode LE3 can be electrically connected to the transistor T_SP3 of the third sub-pixel SP3 through the third via VIH3 through the via layer VIA.

[0121] In some embodiments, the first lower electrode LE1, the second lower electrode LE2, and the third lower electrode LE3 may be anode electrodes. When viewed from a third party towards DR3, each of the first lower electrode LE1 to the third lower electrode LE3 may have the same... Figure 5The first light-emitting regions EMA1 to the third light-emitting regions EMA3 have similar shapes. For example, when viewed from a third party to DR3, the first lower electrode LE1 may have a shape similar to that of the first light-emitting region EMA1, the second lower electrode LE2 may have a shape similar to that of the second light-emitting region EMA2, and the third lower electrode LE3 may have a shape similar to that of the third light-emitting region EMA3, but is not limited to these shapes.

[0122] Each of the first lower electrode LE1 to the third lower electrode LE3 may be electrically connected to the corresponding sub-pixel circuit SPC and receive a drive current. Each of the first lower electrode LE1 to the third lower electrode LE3 may include, but is not limited to, an opaque conductive material capable of reflecting light. In some embodiments, the first lower electrode LE1 to the third lower electrode LE3 may include a transparent conductive material.

[0123] A pixel defining layer (PDL) may be located on first lower electrodes LE1 to third lower electrodes LE3. The PDL may include an opening OP that exposes a portion of the first lower electrode LE1, a portion of the second lower electrode LE2, and a portion of the third lower electrode LE3, respectively. The PDL may be a structure that defines (or divides) the light-emitting region of each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the PDL may define a first light-emitting region EMA1 of the first sub-pixel SP1, a second light-emitting region EMA2 of the second sub-pixel SP2, and a third light-emitting region EMA3 of the third sub-pixel SP3.

[0124] The pixel defining layer (PDL) may include an organic insulating film containing organic materials. These organic materials may include acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, etc. In some embodiments, the pixel defining layer (PDL) may include a light-absorbing material, or a light-absorbing agent may be applied to the pixel defining layer (PDL) to absorb light from the outside. For example, the pixel defining layer (PDL) may include a carbon-based black pigment. However, embodiments are not limited to this.

[0125] A first light-emitting layer EML1 may be disposed on a first lower electrode LE1 exposed by an opening OP of a pixel-defining layer PDL, a second light-emitting layer EML2 may be disposed on a second lower electrode LE2 exposed by another opening OP of the pixel-defining layer PDL, and a third light-emitting layer EML3 may be disposed on a third lower electrode LE3 exposed by yet another opening OP of the pixel-defining layer PDL. Each of the first light-emitting layers EML1 to the third light-emitting layers EML3 may have a multilayer structure, which includes a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0126] The first emissive layer EML1 to the third emissive layer EML3 may include at least one luminescent material that emits light of different colors corresponding to the sub-pixel SP. For example, the first emissive layer EML1 may include at least one luminescent material that emits red light, the second emissive layer EML2 may include at least one luminescent material that emits green light, and the third emissive layer EML3 may include at least one luminescent material that emits blue light. However, the implementation is not limited to this, and in some implementations, each of the first emissive layer EML1 to the third emissive layer EML3 may emit white light as a whole by stacking multiple luminescent materials capable of producing different colors of light (such as red, green, and blue light). A color filter may be further disposed on each of the first emissive layer EML1 to the third emissive layer EML3. The color filter may include at least one of the following color filters: a red color filter, a green color filter, and a blue color filter.

[0127] The upper electrode UE can be disposed on the first light-emitting layer EML1 to the third light-emitting layer EML3 and the pixel defining layer PDL. In some embodiments, the upper electrode UE can be a cathode electrode. The upper electrode UE can be a common layer provided in the first sub-pixel SP1 to the third sub-pixel SP3. The upper electrode UE can be provided in the form of a plate throughout the entire display area DA. In some embodiments, the upper electrode UE can be used as a half-mirror, which partially transmits and partially reflects light emitted from the respective light-emitting layer.

[0128] The upper electrode UE can be a thin metal layer with sufficient thickness to transmit light emitted from the corresponding light-emitting layer. The upper electrode UE can be formed of a metallic material or a transparent conductive material having a relatively thin thickness. In some embodiments, the upper electrode UE may include at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In another embodiment, the upper electrode UE may include at least one of magnesium and silver. However, the material of the upper electrode UE is not limited to these examples.

[0129] The portion of the upper electrode UE overlapping with the first lower electrode LE1, the first light-emitting layer EML1, and the first lower electrode LE1 can form a first light-emitting element LD1. The first lower electrode LE1 can be the first electrode of the first light-emitting element LD1, and the upper electrode UE can be the second electrode of the first light-emitting element LD1. The portion of the upper electrode UE overlapping with the second lower electrode LE2, the second light-emitting layer EML2, and the second lower electrode LE2 can form a second light-emitting element LD2. The second lower electrode LE2 can be the first electrode of the second light-emitting element LD2, and the upper electrode UE can be the second electrode of the second light-emitting element LD2. The portion of the upper electrode UE overlapping with the third lower electrode LE3, the third light-emitting layer EML3, and the third lower electrode LE3 can form a third light-emitting element LD3. The third lower electrode LE3 can be the first electrode of the third light-emitting element LD3, and the upper electrode UE can be the second electrode of the third light-emitting element LD3.

[0130] A thin-film encapsulation layer (TFE) may be disposed on the upper electrode (UE). The TFE may cover the light-emitting element layer (LDL). The TFE prevents oxygen and / or moisture from penetrating into the LDL. In some embodiments, the TFE may comprise a structure in which one or more inorganic films and one or more organic films are alternately stacked. For example, the inorganic films may include silicon nitride, silicon oxide, or silicon oxynitride. The organic films may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, or benzocyclobutene resin. However, the materials in the organic and inorganic films of the TFE are not limited to these examples.

[0131] The second substrate SUB2 may be disposed on the display element layer DPL including the above configuration. The second substrate SUB2 may face the first substrate SUB1 on the third-party DR3. The second substrate SUB2 may serve as a packaging substrate protecting the display element layer DPL.

[0132] The filler layer 100 may be disposed in the display area DA between the display element layer DPL on the first substrate SUB1 and the second substrate SUB2. For example, the first filler layer 110 may be disposed in the display area DA between the first substrate SUB1 and the second substrate SUB2. The first filler layer 110 may maintain the gap between the first substrate SUB1 and the second substrate SUB2.

[0133] Figure 7 For along Figure 2 A schematic cross-sectional view taken from line I-I'.

[0134] To avoid about Figure 7 The redundant explanations in the implementation methods are only explained in relation to the implementation methods mentioned above.

[0135] refer to Figure 2 and Figure 7 The display panel DP (or display device DD) may include a first substrate SUB1 and a second substrate SUB2 bonded together by a sealing member SM. A display element layer DPL may be disposed on the upper surface of the first substrate SUB1. The display element layer DPL may include a pixel circuit layer PCL, a light-emitting element layer LDL, and a thin-film encapsulation layer TFE.

[0136] The filler layer 100 may be disposed between the display element layer DPL on the first substrate SUB1 and the second substrate SUB2. The filler layer 100 may be formed by inkjet printing, spin coating, slot coating, jet dispensing or screen printing, but the embodiments are not limited to these.

[0137] The filler layer 100 may be formed on the surface of the second substrate SUB2 (e.g., the surface of the display element layer DPL facing the first substrate SUB1) and may be located between the display element layer DPL and the second substrate SUB2 in the process of connecting the second substrate SUB2 to the first substrate SUB1.

[0138] A filler layer 100 may be disposed on a first substrate SUB1 and may cover the display element layer DPL. The filler layer 100 may contact the upper surface of the first substrate SUB1 and may contact the upper and side surfaces of the display element layer DPL. The filler layer 100 may contact the surface (e.g., the "lower surface") of the second substrate SUB2. An empty space may exist between the filler layer 100 and the sealing member SM. To prevent the filler layer 100 from being affected by the laser during the curing stage of the sealing member SM, the filler layer 100 and the sealing member SM may be spaced apart from each other.

[0139] The filler layer 100 reduces the empty space or air layer between the first substrate SUB1 and the second substrate SUB2, while preventing voids, thereby enabling a clear image to be displayed. The filler layer 100 may be formed of a material that ensures ease of application and transparency. The filler layer 100 may include a silicone-containing polymer resin. For example, the silicone-containing polymer resin may include, but is not limited to, at least one of silicone-containing acrylate resins, silicone-containing epoxy resins, silicone-containing vinyl resins, and silicone-containing phenyl resins.

[0140] In some embodiments, the filler layer 100 may include a first filler layer 110 and a second filler layer 120. The first filler layer 110 may be disposed in the middle portion of the display area DA of the first substrate SUB1 and the second substrate SUB2, while the second filler layer 120 may be disposed in the outer portion of the display area DA of the first substrate SUB1 and the second substrate SUB2 and in the non-display area NDA adjacent to the outer portion. The edge ED of the second filler layer 120 may be located at a selected interval d from the boundary BD between the display area DA and the non-display area NDA toward the display area DA. The interval d may refer to the distance between the boundary BD and the edge ED of the second filler layer 120, which may be about 500 μm, but is not limited thereto. For example, the second filler layer 120 may be located between the first substrate SUB1 and the second substrate SUB2, extending from the non-display area NDA into the outer portion of the display area DA adjacent to the non-display area NDA. The second filler layer 120 may be spaced apart from the sealing member SM in the non-display area NDA.

[0141] The first filler layer 110 and the second filler layer 120 may comprise different materials. To prevent haze due to mixing, the first filler layer 110 and the second filler layer 120 may comprise similar components. For example, the first filler layer 110 and the second filler layer 120 may comprise a silicone-containing thermosetting resin or a UV-curable resin.

[0142] In some embodiments, each of the first filler layer 110 and the second filler layer 120 may comprise a filler material, a catalyst, and a crosslinking compound. For example, the filler material may comprise silicon (Si), the catalyst may comprise platinum (Pt), and the crosslinking compound may contain Si-H groups, but is not limited thereto. Here, the platinum catalyst may act as an initiator for curing during the manufacturing process of the display device DD.

[0143] The contents of the components included in the first filler layer 110 and the second filler layer 120 may differ from each other. For example, the content of the crosslinking compound included in each of the first filler layer 110 and the second filler layer 120 may vary. For example, the first filler layer 110 and the second filler layer 120 may include the same filler material content, and the first filler layer 110 and the second filler layer 120 may also include the same catalyst content. For example, the content of the crosslinking compound included in the second filler layer 120 may be greater than or equal to about 70% of the content of the crosslinking compound included in the first filler layer 110.

[0144] As another example, the contents of both the filler material and the crosslinking compound included in each of the first filler layer 110 and the second filler layer 120 may differ. For example, the contents of the filler material included in the first filler layer 110 and the second filler layer 120 may differ from each other, and the contents of the crosslinking compound included in the first filler layer 110 and the second filler layer 120 may differ from each other, while the contents of the catalyst included in the first filler layer 110 and the second filler layer 120 may be the same. For example, the contents of the filler material included in the second filler layer 120 may be greater than or equal to about 70% of the contents of the filler material included in the first filler layer 110, and the contents of the crosslinking compound included in the second filler layer 120 may be greater than or equal to about 70% of the contents of the crosslinking compound included in the first filler layer 110.

[0145] As another example, the contents of the filler material, catalyst, and crosslinking compound included in the first filler layer 110 and the second filler layer 120 may all be different. For example, the contents of the filler material included in the first filler layer 110 and the filler material included in the second filler layer 120 may be different from each other, and the contents of the catalyst included in the first filler layer 110 and the crosslinking compound included in the second filler layer 120 may be different from each other. For example, the contents of the filler material included in the second filler layer 120 may be greater than or equal to about 70% of the contents of the filler material included in the first filler layer 110, the contents of the catalyst included in the second filler layer 120 may be greater than or equal to about 70% of the contents of the catalyst included in the first filler layer 110, and the contents of the crosslinking compound included in the second filler layer 120 may be greater than or equal to about 70% of the contents of the crosslinking compound included in the first filler layer 110. In this article, the percentage of filler material content, catalyst content, and crosslinking compound content refers to "wt%".

[0146] Table 1

[0147]

[0148] Table 1 shows the ratio of material in the filler layer 100 applied to the outer portion of the display area DA to material in the filler layer 100 applied to the middle portion of the display area DA in the comparative examples and embodiments (shown in Table 1 as "Outer Portion / Middle Portion Ratio"). A comparative example may refer to a case where the same material is applied to both the middle and outer portions of the display area DA. In contrast, an embodiment may refer to a case where different materials are applied to the middle and outer portions of the display area DA. As shown in Table 1 above, in the case of the comparative example, it can be seen that there is a significant difference in the content of filler material between the middle and outer portions of the display area DA, and a relatively large amount of crosslinking compound is included in the filler layer 100 in the outer portion of the display area DA. However, in the case of the embodiment, the content of filler material is the same in both the middle and outer portions of the display area DA to prevent excessive crosslinking compound from being included in the filler layer 100 in the outer portion of the display area DA.

[0149] As described above, the content of the crosslinking compound in the second filler layer 120 may differ from the content of the crosslinking compound in the first filler layer 110. In the process of joining the first substrate SUB1 and the second substrate SUB2, taking into account the difference in material spreadability of the filler layer 100 between the central portion of the display area DA and the outer portion of the display area DA (or the area of ​​the display area DA adjacent to the non-display area NDA), the content of the crosslinking compound in the second filler layer 120 is set (or intended) to be lower than the content of the crosslinking compound in the first filler layer 110.

[0150] If a filler layer 100 comprising the same material (or comprising one type of material) is disposed in both the middle and outer portions of the display region DA between the first substrate SUB1 and the second substrate SUB2, the components forming the filler layer 100 (such as filler material, catalyst, and crosslinking compound) may have different spreadability during the process of joining the first substrate SUB1 and the second substrate SUB2. This may result in a difference in composition between the filler layer 100 extending to the middle portion of the display region DA and the filler layer 100 extending to the outer portion of the display region DA and the adjacent non-display region NDA. For example, compared to the filler layer 100 extending to the middle portion of the display region DA, the filler layer 100 extending to the outer portion of the display region DA and the adjacent non-display region NDA may contain less filler material and catalyst, while the amount of crosslinking compound may remain unchanged. Therefore, the filler layer 100 extending to the outer portion of the display region DA (or located in the outer portion of the display region DA) may include a relatively large amount of crosslinking compound than the filler layer 100 extending to the middle portion of the display region DA. The first substrate SUB1 and the second substrate SUB2 may not be properly connected in the outer portion of the display area DA and the adjacent non-display area NDA, causing the second substrate SUB2 to detach, and thus the sub-pixels located in the outer portion of the display area DA (see...) Figure 6 Tearing black spot defects may occur in the “SP” section.

[0151] Accordingly, in the above embodiments, non-bonding of the first substrate SUB1 and the second substrate SUB2 in the outer portion of the display area DA can be reduced or minimized. This can be achieved by preventing the filler layer 100 extending to the outer portion of the display area DA from including a relatively large amount of crosslinking compound compared to the filler layer 100 extending to the middle portion of the display area DA. By providing a second filler layer 120 with a lower content of crosslinking compound between the first substrate SUB1 and the second substrate SUB2 in the region corresponding to the outer portion of the display area DA, and providing a first filler layer 110 with a higher content of crosslinking compound in the region corresponding to the middle portion of the display area DA, the bonding process between the first substrate SUB1 and the second substrate SUB2 can be improved.

[0152] The following describes a method for manufacturing a display device DD according to an embodiment.

[0153] Figure 8 A schematic block diagram illustrating a method for manufacturing a display device according to an embodiment, and Figures 9 to 19 A schematic diagram illustrating the process steps of this method. Figure 9 To explain the use of Figure 8 A schematic plan view of the first mother substrate M1 in the first step S100. Figure 10To explain the use of Figure 8 A schematic plan view of the first mother substrate M1 in the second step S200. Figure 11 To explain the use of Figure 8 A schematic plan view of the second mother substrate M2 in the third step S300. Figure 12 To illustrate applying fill layer 100 to the source Figure 11 A schematic perspective view of the display unit DPC on the second mother substrate M2. Figure 13A To explain from Figure 11 A schematic plan view of the display unit DPC on the second mother substrate M2. Figure 13B and Figure 13C To explain from Figure 13A A schematic plan view of a modified example of the first fill layer 110 and the second fill layer 120. Figures 14 to 16 To explain Figure 8 A schematic diagram of the fourth step S400. Figure 17 For along Figure 14 Explanation of the intercept of line III-III' Figure 8 The fifth step, S500, is shown in a schematic cross-sectional view. Figure 18 and Figure 19 To explain Figure 8 A schematic diagram of the sixth step S600.

[0154] exist Figures 8 to 19 In the embodiments shown, the manufacturing steps of the display device DD are described as being performed one after another. However, it should be understood that, assuming the overall concept of this disclosure remains unchanged, some steps shown as being performed consecutively may be performed simultaneously, the order of each step may be changed, some steps may be omitted, or additional steps may be included between existing steps.

[0155] about Figures 8 to 19 For ease of explanation, redundant descriptions will be omitted.

[0156] refer to Figure 8 and Figure 9 Prepare a first mother substrate M1, and form a display element layer DPL on the upper surface 10 of the first mother substrate M1 (S100 - Step 1). The display element layer DPL is as shown in the reference. Figure 6 and Figure 7 As stated above, and because various display element layers (DPLs) can be used, a description of the specific manufacturing method is omitted.

[0157] The first mother substrate M1 is a substrate used to simultaneously manufacture multiple display units (DPCs) for ease of process, and can also be used as a display device (see...). Figure 1The first substrate SUB1 (hereinafter referred to as "DD") may include at least one unit region. The unit region corresponds to a separate display unit DPC (or a separate display device DD), and the separate display unit DPC may be formed in each unit region.

[0158] In some embodiments, each of the plurality of display units DPCs can be individually separated and can serve as a display device DD. After the plurality of display units DPCs are formed simultaneously on the first mother substrate M1, these display units DPCs can be separated by a cutting process or the like. The display units DPCs can be arranged in a matrix form on the upper surface 10 of the first mother substrate M1, in which rows (or rows of display units) extend in the first direction DR1 and columns (or columns of display units) extend in the second direction DR2.

[0159] Each of the multiple display units (DPCs) may include a display area DA in which a display element layer (DPL) is disposed and a non-display area NDA surrounding the display area DA.

[0160] refer to Figure 8 and Figure 10 A sealing member SM is applied along the edge of the upper surface 10 of the first mother substrate M1 (S200 - step 2).

[0161] In the accompanying drawings, the sealing member SM is shown as being formed on the upper surface 10 of the first mother substrate M1, but is not limited thereto. According to an embodiment, the sealing member SM may be formed on a second mother substrate (see...). Figure 11 The surface of “M2” in the text (see Figure 11 (20) in the middle.

[0162] refer to Figure 8 , Figure 11 , Figure 12 and Figure 13C Prepare a second mother substrate M2, and apply a first filling layer 110 and a second filling layer 120 to the surface 20 of the prepared second mother substrate M2 (S300 - step 3).

[0163] The second mother substrate M2 is a packaging substrate connected to the first mother substrate M1 to form a plurality of display units DPC, and can be used as the second substrate SUB2 of the display device DD. The second mother substrate M2 may include at least one unit region corresponding to a unit region of the first mother substrate M1. Each unit region may include a first region A1 and a second region A2. The first region A1 may correspond to the display region DA of the first mother substrate M1 (see...). Figure 1 And the second region A2 may correspond to the non-display region NDA of the second mother substrate M2 (see...). Figure 1 ).

[0164] The first filler layer 110 can be applied to the central portion of the first region A1 of the second mother substrate M2, while the second filler layer 120 can be applied to the outer portion of the first region A1 adjacent to the second region A2 of the second mother substrate M2. For example, the uncured filler layer 100 can be applied to the first region A1 on the surface 20 of the second mother substrate M2 using the nozzle NZ of a spray dispenser. The nozzle NZ may include a first nozzle NZ1 for applying the material of the first filler layer 110 and a second nozzle NZ2 for applying the material of the second filler layer 120. The first filler layer 110 and the second filler layer 120 may include different materials.

[0165] refer to Figure 13A The outer portion of the first region A1 of the second mother substrate M2, on which the second filler layer 120 is applied, may be from the first region A1 (or the display region DA (see...) Figure 1 )) and the second area A2 (or non-display area NDA (see Figure 1 The boundary BD between the two regions is a region within a selectable interval d in the middle portion of the first region A1. The interval d can be approximately 500 μm, but is not limited to this.

[0166] exist Figure 13A In the diagram, the second filler layer 120 is shown as applied to the left and right sides of the outer portion of the first region A1 of the second mother substrate M2, but is not limited thereto. In some embodiments, such as Figure 13B As shown, the second filler layer 120 can be applied to the entire outer portion (e.g., left, right, upper and lower sides) of the first region A1 of the second mother substrate M2.

[0167] In the above embodiment, it is described that the first filler layer 110 is applied to the middle portion of the first region A1 of the second mother substrate M2, and the second filler layer 120 is applied to the outer portion of the first region A1 of the second mother substrate M2, but the embodiment is not limited thereto. In other embodiments, such as Figure 13C As shown, a second filler layer 120 can be applied to the middle portion of the first region A1 of the second mother substrate M2, and a first filler layer 110 can be applied to the outer portion of the first region A1 of the second mother substrate M2.

[0168] refer to Figure 8 , Figure 14 , Figure 15 and Figure 16 Connect the first mother substrate M1 and the second mother substrate M2 (S400 - Step 4).

[0169] A first mother substrate M1 may be provided such that its upper surface 10 faces the surface 20 of a second mother substrate M2. By moving the first mother substrate M1 toward the second mother substrate M2, the first mother substrate M1 and the second mother substrate M2 can be connected via a sealing member SM. In some embodiments, the second mother substrate M2 may be provided such that its surface 20 faces the upper surface 10 of the first mother substrate M1.

[0170] In the process of connecting the first mother substrate M1 and the second mother substrate M2, the uncured filler layer 100 can be pressed into close contact by the first mother substrate M1 and / or the display element layer DPL formed on the first mother substrate M1. Accordingly, the uncured filler layer 100 can extend from the first region A1 toward the second region A2. The extension of the filler layer 100 in the direction of the sealing member SM can be controlled by adjusting the application time and speed of the filler layer 100, so as to ensure that the filler layer 100 remains separated from the sealing member SM.

[0171] Subsequently, the connected first mother substrate M1 and second mother substrate M2 can be flipped up and down so that the first mother substrate M1 is at the bottom.

[0172] The laser beam L can be used to irradiate the sealing member SM to partially melt it, allowing the first mother substrate M1 and the second mother substrate M2 to be fully connected. When the laser beam L irradiates the sealing member SM, the filler layer 100 remains separated from and does not contact the sealing member SM. Therefore, the filler layer 100 is not affected by heat energy from the laser beam L or from the sealing member SM itself.

[0173] refer to Figure 8 and Figure 17 The curable filler layer 100 (S500 - step 5) can be cured.

[0174] The curing process of filler layer 100 can be carried out by heat curing, UV curing, or a combination of heat curing and UV curing.

[0175] refer to Figure 8 , Figure 18 and Figure 19 By irradiating a laser beam along the patterned cutting lines CUL on the first mother substrate M1 and the second mother substrate M2, the first mother substrate M1 and the second mother substrate M2 can be separated in units of display units DPC (S600 - step 6).

[0176] Each display unit (DPC) can realize a display device (DD) including a first substrate (SUB1) containing a display element layer (DPL) and a second substrate (SUB2) disposed on the first substrate (SUB1). The display device (DD) can be connected to a reference. Figures 1 to 3 The display device described is the same as DD.

[0177] Following the above processes, a scribing process can be performed to smooth the edges of the individual display units (DPCs) (or display devices (DDs)). The scribing process may involve gently polishing the sharp edges using a laser beam or a grinding wheel (W) from a grinding machine.

[0178] After the scribing process, a chemical strengthening process can be performed on the first substrate SUB1 and the second substrate SUB2 of each display unit DPC. Before the chemical strengthening process, a cleaning process can also be performed to remove any foreign matter from the surfaces of the first substrate SUB1 and the second substrate SUB2.

[0179] Separate display units (DPCs) can be used in various electronic devices, such as TVs, smartphones, and wearable devices. For example, these DPCs can be used in devices that implement virtual reality (VR) or augmented reality (AR).

[0180] Figure 20 A schematic block diagram illustrating the electronic device 1000 according to an embodiment. Figure 21 To explain Figure 20 A schematic diagram illustrating an example of an electronic device 1000 implemented as a smartphone. Figure 22 To explain Figure 20 A schematic diagram illustrating an example of an electronic device 1000 implemented as a tablet computer.

[0181] refer to Figures 20 to 22 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an I / O device (input / output device) 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device DD. The electronic device 1000 may further include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as Figure 21 As explained herein, the electronic device 1000 can be implemented as a smartphone. In an implementation, such as... Figure 22 As explained herein, electronic device 1000 can be implemented as a tablet computer. However, the foregoing examples are illustrative, and electronic device 1000 is not necessarily limited to the foregoing examples. For example, electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, or head-mounted display device, etc.

[0182] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may be a microprocessor, a central processing unit, or an application processor, etc. Processor 1010 can be connected to other components via address buses, control buses, and data buses, etc. In embodiments, processor 1010 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0183] The memory device 1020 may store data required to perform the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices (such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nanofloating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) devices, and ferroelectric random access memory (FRAM) devices) and / or volatile memory devices (such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, mobile DRAM devices, etc.).

[0184] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), or CD-ROMs, etc.

[0185] I / O device 1040 may include input devices (such as a keyboard, keypad, touchpad, touch screen, and mouse) and output devices (such as a speaker and printer). In some embodiments, display device 1060 may be included in I / O device 1040.

[0186] The power supply 1050 provides the power required to operate the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0187] Display device 1060 can display images corresponding to visual information of electronic device 1000. Here, display device 1060 may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting display device, but is not necessarily limited to these. Display device 1060 can be connected to other components via a bus or other communication link.

[0188] Embodiments have been disclosed herein, and although terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the claims.

Claims

1. A display device, comprising: The first substrate defines a display area and a non-display area; A display component is disposed on the first substrate and displays an image; A second substrate is disposed on the display assembly; A filler layer is disposed between the first substrate and the second substrate; as well as A sealing member, located at the edge portions of the first substrate and the second substrate, and connecting the first substrate and the second substrate, is characterized in that... The filling layer includes a first filling layer and a second filling layer, each comprising different materials, and The second filling layer is spaced apart from the sealing member, with an empty space between them.

2. The display device according to claim 1, characterized in that, Each of the first filler layer and the second filler layer comprises a thermosetting resin or a UV-curable resin formed from a filler material, a catalyst, and a crosslinking compound.

3. The display device according to claim 2, characterized in that, The filler material includes silicon. The catalyst includes platinum, and The crosslinked compound contains Si-H groups.

4. The display device according to claim 3, characterized in that, The crosslinking compound of the second filler layer has a content of greater than or equal to 70% of the crosslinking compound of the first filler layer.

5. The display device according to claim 3, characterized in that, The filling material of the second filling layer has a content of greater than or equal to 70% of the filling material of the first filling layer.

6. The display device according to claim 3, characterized in that, The catalyst in the second filling layer has a content of 70% or more of the catalyst in the first filling layer.

7. The display device according to claim 1, characterized in that, The second substrate is a glass substrate.

8. The display device according to claim 1, characterized in that, The empty space is either a vacuum or filled with gas.

9. A display device, comprising: The first substrate defines a display area and a non-display area; A display component is disposed on the first substrate and displays an image; A second substrate is disposed on the display assembly; A filler layer is disposed between the first substrate and the second substrate; as well as A sealing member, located at the edge portions of the first substrate and the second substrate, and connecting the first substrate and the second substrate, is characterized in that... The filling layer comprises a first filling layer and a second filling layer formed by various free filler materials, catalysts, and crosslinking compounds. The first filler layer and the second filler layer comprise different materials from each other, and The crosslinking compound of the second filler layer has a content of greater than or equal to 70% of the crosslinking compound of the first filler layer.

10. An electronic device comprising: A processor configured to provide input image data to a display device; and The display device is configured to display an image based on the input image. The display device is characterized in that it is a display device according to any one of claims 1 to 9.

Images