Fault detection methods, control devices and fault detection equipment

Abstract

This application proposes a fault detection method, control device, and fault detection equipment, relating to the field of fault detection technology. The fault detection method includes: acquiring attribute information of a computing board to be tested; displaying at least one computing board model rendering corresponding to the attribute information; establishing a mapping relationship between the computing board model rendering and the parameters of the computing board to be tested; and, in response to a detection operation on the computing board to be tested, acquiring the current operating status of the computing board to be tested and mapping its parameters to the computing board model rendering, so as to display the operating status of each computing chip of the computing board to be tested on the display interface of the fault detection equipment. This application can significantly improve fault detection efficiency, achieve intuitive and visual location of fault points, reduce subjective errors in manual inspection, and improve the accuracy and timeliness of maintenance work.

Description

Technical Field

[0001] This application relates to the field of fault detection technology, and in particular to a fault detection method, control device and fault detection equipment. Background Technology

[0002] In the maintenance practice of blockchain servers, the maintenance process is highly dependent on manual operation. Maintenance personnel need to use special tools to manually inspect the computing boards with dense electronic components and complex structures, and check the fault points one by one. The inspection process is time-consuming and lacks positioning accuracy. Summary of the Invention

[0003] The main objective of this invention is to provide a fault detection method that aims to improve fault detection efficiency and enhance the accuracy and timeliness of maintenance work.

[0004] To achieve the above objectives, the present invention provides a fault detection method applied to a fault detection device, wherein the fault detection device is communicatively connected to the computing board to be detected, and the fault detection method includes:

[0005] Obtain the attribute information of the computing board to be tested;

[0006] Display at least one rendering of a computing board model corresponding to the attribute information; there is a mapping relationship between the rendering of the computing board model and the parameters of the computing board to be tested;

[0007] In response to the detection operation on the computing board to be tested, the current operating status of the computing board to be tested is obtained, and the parameters are mapped with the computing board model effect diagram so as to display the operating status of each computing chip of the computing board to be tested on the display interface of the fault detection device.

[0008] Optionally, displaying at least one rendering of a computing board model corresponding to the attribute information includes:

[0009] The model and hardware configuration of the computing board to be tested are determined based on the attribute information.

[0010] Determine the target computing board model in the preset computing board model library that matches the model and the hardware configuration;

[0011] The target computing board model is retrieved and rendered to generate a corresponding computing board model rendering, which includes the layout position and functional partition identifiers of each computing chip.

[0012] Optionally, after retrieving the target computing board model and rendering the corresponding computing board model effect diagram, the method further includes:

[0013] In response to the test operation on the computing board to be tested, a confirmation operation for the rendering of the computing board model is displayed on the display interface to determine whether the target computing board model is consistent with the computing board to be tested;

[0014] If the match is confirmed, the target computing board model is determined to be the matching model of the computing board to be tested, and the corresponding testing process is carried out.

[0015] If an inconsistency is confirmed, a new target computing board model is selected for matching until a model that is completely consistent with the computing board to be tested is found, and the corresponding testing process is carried out.

[0016] Optionally, the display interface has a first side, a second side, a third side, and a fourth side, with the first side and the third side being arranged opposite to each other, and the second side and the fourth side being arranged opposite to each other; the computing board model rendering includes a computing board, a first test parameter block, a test control block, and a second test parameter block;

[0017] The step of retrieving the target computing board model and rendering the corresponding computing board model image includes:

[0018] Obtain the actual size information of the computing board and the interface size information of the display interface;

[0019] Calculate the ratio between the first long side in the actual size information and the second long side in the interface size information;

[0020] Adjust the actual size information according to the ratio to generate the corresponding computing board layout size information, and arrange the computing board between the second, third and fourth sides of the display interface according to the computing board layout size information;

[0021] The test control block is positioned at the center of the first side, and the first test parameter block, the test control block, and the second test parameter block are distributed at intervals along the first side; wherein, the first test parameter block is used to adjust the power supply parameters of the computing board under test, and the second test parameter block is used to determine the operating status of the computing board.

[0022] Optionally, the fault detection method further includes:

[0023] Obtain the location and encoding information of each computing chip in the computing board;

[0024] The simulated computing chip in the computing board model diagram is divided into multiple adjacent chip blocks according to a preset interval row. The multiple adjacent chip blocks include a start number block, a middle number block and an end number block.

[0025] Select the chip block closest to the side as the starting numbered block;

[0026] Based on the location information and the encoding information, the code is sequentially encoded along the starting number block, the intermediate number block, and the ending number block according to a preset encoding path;

[0027] The encoded rendering of the computing board model is displayed on the display interface.

[0028] Optionally, the step of obtaining the current operating status of the computing power board under test in response to the detection operation specifically includes:

[0029] Obtain the computing power parameter range, preset electrical data range, and preset temperature data of the computing chip corresponding to the attribute information;

[0030] In response to the detection operation on the computing power board to be tested, a first detection data packet is sent to the computing power board to be tested, and the computing power parameter value, first electrical data and current temperature value of each computing power chip returned by the computing power board to be tested are monitored.

[0031] Each computing power parameter value is compared with the computing power parameter range to confirm the first state information;

[0032] Each of the first electrical data points is compared with the preset electrical data range to confirm the second state information;

[0033] Each current temperature value is compared with the preset temperature data to confirm the third state information;

[0034] The operating state is determined based on the first state information, the second state information, and the third state information, and the operating state includes normal operation or abnormal operation.

[0035] Optionally, after determining the operating state based on the first state information, the second state information, and the third state information, the method further includes:

[0036] If an abnormal operation of a computing chip is detected in the computing board to be tested, the location information, encoding information and current computing power value of the abnormally operating chip are obtained.

[0037] Based on the location information and the encoding information, the abnormal chip is identified as the simulated computing chip corresponding to the computing board model rendering.

[0038] The current computing power value is set after the encoding of the analog computing power chip and displayed on the display interface.

[0039] Optionally, obtaining the attribute information of the computing board to be tested includes:

[0040] In response to the selection operation for the computing board to be tested, the power supply parameters, number of computing chips and computing chip layout information corresponding to the model of the computing board to be tested are determined;

[0041] The power supply parameters, the number of computing chips, and the arrangement information of the computing chips are determined as the attribute information;

[0042] The computing board to be tested further includes at least one of a temperature sensing chip or a storage chip; the fault detection method further includes:

[0043] Send detection data to the temperature sensing chip and / or the storage chip, and monitor the status data returned by the temperature sensing chip and / or the storage chip;

[0044] In the event of abnormal status data, the first position of the temperature sensing chip and / or the storage chip in the computing board model rendering is obtained;

[0045] The analog temperature sensor chip and / or analog storage chip at the first position are controlled to display the corresponding alarm information.

[0046] In addition, to achieve the above objectives, the present invention also provides a control device, the control device comprising: a memory, a processor, and a fault detection program stored in the memory and executable on the processor, the fault detection program being configured to implement the fault detection method as described above.

[0047] Furthermore, to achieve the above objectives, the present invention also provides a fault detection device, characterized in that it comprises:

[0048] The display interface is used to display the rendering of the computing board model and the operating status of each computing chip on the computing board to be tested.

[0049] An interface circuit, wherein the interface circuit is used for communicative connection with the computing board under test; and

[0050] As described above, the control device is electrically connected to the display interface and the interface circuit respectively. The control device is used to acquire the attribute information of the computing board to be tested, and control the display interface to display at least one computing board model rendering corresponding to the attribute information.

[0051] The control device is also used to respond to the detection operation of the computing power board to be tested, obtain the current operating status of the computing power board to be tested, perform parameter mapping with the computing power board model effect diagram, and control the display interface to display the operating status of each computing power chip of the computing power board to be tested.

[0052] The fault detection method of this invention is applied to a fault detection device. This method acquires the attribute information of the computing board to be tested, then displays at least one computing board model rendering corresponding to the attribute information. There is a mapping relationship between the computing board model rendering and the parameters of the computing board to be tested. Finally, in response to the detection operation on the computing board to be tested, the current operating status of the computing board is acquired and mapped to the parameters of the computing board model rendering, so as to display the operating status of each computing chip of the computing board to be tested on the display interface of the fault detection device. Thus, by dynamically combining the computing board attribute information with the model rendering, a visual mapping of operating parameters and physical layout is achieved, which can significantly improve fault detection efficiency, achieve intuitive visual location of fault points, reduce subjective errors in manual inspection, and improve the accuracy and timeliness of maintenance work. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a schematic flowchart of a fault detection method according to an embodiment of the present invention;

[0056] Figure 2 for Figure 1 A flowchart illustrating step S200 in the process;

[0057] Figure 3 for Figure 2 A flowchart illustrating step S230 in the process;

[0058] Figure 4 This is a schematic flowchart of a fault detection method according to another embodiment of the present invention;

[0059] Figure 5 This is a schematic flowchart of a fault detection method according to another embodiment of the present invention;

[0060] Figure 6 for Figure 1 A flowchart illustrating step S300 in the process;

[0061] Figure 7This is a schematic flowchart of a fault detection method according to another embodiment of the present invention;

[0062] Figure 8 for Figure 1 A flowchart illustrating step S100 in the process;

[0063] Figure 9 This is a schematic flowchart of a fault detection method according to another embodiment of the present invention;

[0064] Figure 10 This is a rendering of the computing board model when the computing board under test is running normally.

[0065] Figure 11 This is a diagram showing the effect of the computing board model when the computing board is malfunctioning.

[0066] Figure 12 This is a schematic diagram of the display interface structure;

[0067] Figure 13 This is a schematic diagram of the structure of a fault detection device according to an embodiment of the present invention;

[0068] Figure 14 for Figure 13 A schematic diagram of the back structure.

[0069] Explanation of icon numbers:

[0070] 10 - Display interface; 11 - First side; 12 - Second side; 13 - Third side; 14 - Fourth side; 20 - Interface circuit; 30 - Control device.

[0071] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0072] In blockchain server repair practice, equipment from brands such as Antminer, Whatsminer, and Avalon encompasses multiple components including power supplies, computing boards, and the entire machine, making the repair process highly dependent on manual operation. Repair personnel must use specialized tools to manually inspect the densely packed and complex computing boards, systematically checking for faults. Technicians struggle to quickly identify circuit link status and fault location distribution, resulting in time-consuming and inaccurate inspection processes. Especially with high-density integrated components like computing boards, manual methods are easily influenced by subjective factors, leading to low repair efficiency and continuously rising labor costs.

[0073] Blockchain servers encompass various types, including large-scale computing servers and distributed storage servers. During operation, these servers are highly susceptible to various malfunctions due to prolonged high-load operation, environmental factors, or hardware aging. Traditional fault detection methods are not only inefficient but also often fail to accurately identify some well-hidden faults, thus affecting normal server operation and causing unnecessary losses to enterprises. Therefore, developing an efficient and accurate fault detection method and equipment is crucial for improving the operational stability of blockchain servers and reducing maintenance costs.

[0074] The main solution of this application embodiment is: by obtaining the attribute information of the computing board to be tested, and then displaying at least one computing board model effect diagram corresponding to the attribute information, wherein there is a mapping relationship between the computing board model effect diagram and the parameters of the computing board to be tested, and finally, in response to the detection operation of the computing board to be tested, the current running status of the computing board to be tested is obtained and the parameters are mapped with the computing board model effect diagram, so as to display the running status of each computing chip of the computing board to be tested on the display interface of the fault detection device.

[0075] In this embodiment, for ease of description, the following description will focus on the control device as the executing entity.

[0076] This application provides a solution that dynamically combines computing board attribute information with model renderings to achieve a visual mapping of operating parameters and physical layout. This can significantly improve fault detection efficiency, enable intuitive visual location of fault points, reduce subjective errors in manual inspection, and enhance the accuracy and timeliness of maintenance work.

[0077] Therefore, the present invention proposes a fault detection method; it is understood that the fault detection device is equipped with a control device for storing and executing the following method. The control device can be implemented by a main controller, such as MCU (Microcontroller Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), SOC (System On Chip), etc.

[0078] Reference Figure 1 , Figures 10 to 14 In one embodiment of the present invention, the fault detection method is applied to a fault detection device, which is communicatively connected to the computing board to be detected. The fault detection method includes steps S100-S300, wherein:

[0079] S100: Obtain the attribute information of the computing board to be tested;

[0080] S200. Display at least one computing board model rendering corresponding to the attribute information; there is a mapping relationship between the computing board model rendering and the parameters of the computing board to be tested;

[0081] S300: In response to the detection operation of the computing power board to be tested, the current operating status of the computing power board to be tested is obtained, and the parameters are mapped with the computing power board model effect diagram, so as to display the operating status of each computing power chip of the computing power board to be tested on the display interface 10 of the fault detection device.

[0082] The attribute information of the computing board includes its model, specifications, production batch, number and layout of computing chips, basic performance parameters of each chip, interface type and quantity, and heat dissipation configuration parameters. The computing board model rendering is a virtual image simulating the style and attributes of the computing board under test, obtained by pre-drawing or calling a network model based on the computing board's attribute information. These images can intuitively demonstrate the expected operating effect of the computing board under different parameter configurations. The mapping relationship between the computing board model rendering and the parameters of the computing board under test can be pre-established, for example, mapping computing power values ​​to chip values ​​in the model rendering, and voltage values ​​to power module display values ​​in the model rendering. This mapping relationship allows users to quickly understand the various parameters of the computing board under test and their corresponding operating status by observing the model rendering.

[0083] The detection operation can be manually triggered by the operator or automatically triggered by the fault detection equipment based on preset conditions. Once triggered, the fault detection equipment first sends a detection data packet to the computing board under test to quickly obtain its current operating status data. This data includes, but is not limited to, real-time computing power values, voltage values, and temperature values ​​of each computing chip. Parameter mapping refers to comparing and associating the acquired current operating status data of the computing board under test with corresponding parameters in a pre-stored model rendering of the computing board. Through this parameter mapping, the fault detection equipment can accurately represent the actual operating status of the computing board under test. For example, it can map the real-time acquired computing power values ​​of the computing chips to the corresponding chip's numerical display area in the model rendering, and map voltage values ​​to the power module's display area. The fault detection equipment can intuitively and clearly display the operating status of each computing chip on the computing board under test on its display interface 10, including normal operation, abnormal operation and other statuses, and present them on the display interface 10 in an intuitive way, thereby helping operators to quickly and accurately determine whether the computing board has a fault and the specific location and type of the fault.

[0084] For each computing chip, based on its real-time computing power, voltage, and temperature data, the corresponding location and parameter display area are located in the computing board model diagram. The actual data is then filled in, allowing operators to clearly see the operating status of each computing chip, including whether it is working properly and whether there are any abnormal parameters. This presentation method greatly improves the efficiency and accuracy of fault detection, making it easier for operators to quickly locate the problem.

[0085] In practical applications, obtaining the attribute information of the computing board under test can be understood as the process of extracting its physical characteristics and configuration information. For example, this can be achieved by reading the firmware information, hardware identifiers, or configuration files of the computing board, or by manually inputting relevant information, primarily to achieve accurate identification of the computing board under test. When displaying at least one computing board model rendering corresponding to the attribute information, the rendering can be generated by calling a preset model library and filtering matching models. For example, the corresponding entry in the model library can be retrieved based on the model number and hardware configuration, and the relevant model data can be loaded. The purpose is to ensure that the rendering accurately reflects the actual structural layout of the computing board. Furthermore, the mapping relationship between the computing board model rendering and the parameters of the computing board under test can be achieved through predefined rule tables or algorithms. For example, binding the operating status data with specific areas in the rendering can achieve a visual presentation of the parameters. In response to the testing operation of the computing board under test, obtaining the current operating status can be achieved by sending test commands and receiving returned data. For example, sending diagnostic signals to the computing board and parsing its feedback information aims to monitor the working status of the computing chip in real time.

[0086] The innovation of this application lies in its construction of a dynamic mapping mechanism between attribute information and computing board model renderings, which enables the visualization of the fault detection process, thereby solving the problem of low fault location efficiency in manual maintenance. Specifically, the fault detection equipment establishes a communication connection with the computing board under test, providing a foundation for real-time data interaction; by acquiring attribute information and determining the corresponding model rendering, model matching errors caused by structural differences between different computing board models are avoided; and by mapping operational status data with model renderings, abnormal states can be directly and intuitively displayed on the rendering, significantly improving the efficiency of fault location.

[0087] The working principle of this embodiment is as follows: The fault detection device establishes a communication connection with the computing board under test, providing a physical basis for real-time data interaction and ensuring the continuity of the detection process and the reliability of the data. The key input is the acquisition of the attribute information of the computing board under test, which includes core parameters such as model and hardware configuration. This information is used to accurately identify the physical characteristics of the computing board and avoid model matching errors caused by structural differences between different models of computing boards. When displaying at least one computing board model rendering corresponding to the attribute information, the matching model is selected based on the attribute information, ensuring that the rendering accurately reflects the chip layout and functional partitions of the actual computing board. This method of dynamically generating renderings based on attribute information ensures the consistency between the visual interface and the physical device, allowing users to intuitively understand the device structure without relying on experience. Furthermore, there is a mapping relationship between the computing board model rendering and the actual parameters, transforming abstract operating parameters into visual interface elements, solving the pain point of scattered and difficult-to-connect parameters in traditional maintenance. In response to the testing operation of the computing power board under test, the current operating status is obtained and mapped with parameters of the computing power board model diagram. This process accurately locates the operating status data to the corresponding position of each computing power chip according to the predefined structure of the model diagram, so that abnormal states can be directly highlighted on the diagram. Thus, users can quickly identify faulty chips by observing the interface, avoiding the tedious process of manual point-by-point testing, significantly improving the intuitiveness and efficiency of fault location. The entire technical solution, through the technical chain of attribute information-driven model matching and operating status mapping to the visualization interface, transforms the invisible circuit state into visible graphical information, fundamentally optimizing the fault diagnosis process and effectively solving the problem of low fault location efficiency caused by the lack of fault detection visualization functions in blockchain server maintenance.

[0088] The fault detection method of this embodiment is applied to a fault detection device. This method acquires the attribute information of the computing board to be tested, then displays at least one computing board model rendering corresponding to the attribute information. There is a mapping relationship between the computing board model rendering and the parameters of the computing board to be tested. Finally, in response to the detection operation of the computing board to be tested, the current operating status of the computing board is acquired and mapped to the parameters of the computing board model rendering. This allows the operating status of each computing chip of the computing board to be tested to be displayed on the display interface 10 of the fault detection device. Thus, by dynamically combining the computing board attribute information with the model rendering, a visual mapping of operating parameters and physical layout is achieved, which can significantly improve fault detection efficiency, enable intuitive visual location of fault points, reduce subjective errors in manual inspection, and improve the accuracy and timeliness of maintenance work.

[0089] Optionally, refer to Figure 2 Another embodiment of the present invention provides a fault detection method based on the above. Figure 1The illustrated embodiment displays at least one rendering of a computing board model corresponding to the attribute information, including steps S210-S230, wherein:

[0090] S210. Determine the model and hardware configuration of the computing board to be tested based on the attribute information;

[0091] S220. Determine the target computing board model in the preset computing board model library that matches the model and the hardware configuration;

[0092] S230. Retrieve the target computing board model and render the corresponding computing board model rendering. The model rendering includes the layout position and functional partition identifier of each computing chip.

[0093] The attribute information refers to the set of technical parameters that uniquely identify the computing board under test, which can be implemented using methods such as device serial number, hardware specification table, or factory configuration list. Model and hardware configuration refer to the specific product category and technical specification combination of the computing board under test, which can be extracted by parsing key fields in the attribute information. The preset computing board model library is a database storing various standardized computing board model data, which can be implemented using relational databases, NoSQL databases, or file systems, aiming to provide diverse model selections to adapt to different devices under test. The target computing board model is a standardized model that perfectly matches the computing board under test, determined through a dual verification mechanism of model and hardware configuration, aiming to ensure the uniqueness and accuracy of model selection. The computing board model rendering is a visual interface generated based on the target computing board model, which can be implemented using 3D modeling, vector drawing, or image rendering techniques, aiming to intuitively display the physical layout and functional partitions of the computing chip.

[0094] This solution first parses the attribute information of the computing board to be tested, converting it into corresponding model and hardware configuration parameters. This process effectively avoids potential ambiguity or redundancy in the original attribute information, enabling subsequent model matching to be based on precise parameters. Next, a dual verification matching is performed in a pre-set computing board model library. Through a joint screening mechanism of model and hardware configuration, the possibility of multiple corresponding models is eliminated, ensuring that only a uniquely suitable actual device model is selected. Subsequently, a high-fidelity visualization interface is generated based on the selected target computing board model. By clearly identifying the layout and functional partitions of each computing chip, it provides an intuitive spatial reference for subsequent operational status mapping. The entire process forms a closed-loop matching mechanism from attribute information input to visualization output, significantly improving the accuracy and efficiency of fault detection.

[0095] Furthermore, this solution is closely integrated with the fundamental steps of obtaining the attribute information of the computing board under test, transforming the raw attribute information into precise model and hardware configuration parameters. Moreover, the generated computing board model not only includes the layout of each computing chip but also clearly identifies functional partitions, providing a clear visual reference for parameter mapping during response testing operations, thereby significantly reducing the risk of misjudgment in fault location.

[0096] Optionally, refer to Figure 3 Another embodiment of the present invention provides a fault detection method, based on the above. Figure 2 The embodiment shown includes steps S240-S260 after retrieving the target computing board model and rendering the corresponding computing board model effect diagram, wherein:

[0097] S240. In response to the test operation on the computing board to be tested, a confirmation operation on the display interface 10 is displayed for the rendering of the computing board model to determine whether the target computing board model is consistent with the computing board to be tested.

[0098] S250. If the match is confirmed, the target computing board model is determined to be the matching model of the computing board to be tested, and the corresponding testing process is carried out.

[0099] S260. If inconsistency is confirmed, select a new target computing board model for matching until a model that is completely consistent with the computing board to be tested is found, and then proceed with the corresponding testing process.

[0100] The test operation refers to the user's interactive actions triggered by the display interface 10 to verify the accuracy of model matching. This can be achieved through clicking a confirmation button, sliding selection, or voice commands, aiming to provide a natural interactive node to ensure the timeliness of model verification. The display interface 10 refers to the area in the fault detection equipment used to present visual information. It can be an LCD screen, a touch screen, or other display device with graphical display capabilities, aiming to provide users with an intuitive model comparison environment. The target computing board model refers to a candidate model selected from a preset computing board model library that matches the attribute information of the computing board to be tested. It can be generated through database queries, algorithm matching, or manual annotation.

[0101] This solution effectively addresses the technical flaw of automatically matched models potentially deviating from actual hardware by constructing a user-interventional model verification closed loop, ensuring the accuracy of the baseline model for fault detection. After retrieving and rendering the target computing board model, the control device 30 triggers a confirmation mechanism at the critical moment when the user initiates the test operation. This design utilizes the natural interaction nodes between the user and the system, avoiding invalid operations caused by model errors. The confirmation operation provided by the display interface 10 is based on the rendered visual model, enabling users to quickly identify model differences based on the physical characteristics of the actual computing board, compensating for the limitations of digital description of attribute information. Through the user's confirmation operation, the system's matching results are corrected directly based on their experience with the hardware entity, solving the matching inaccuracy problem when attribute information is incomplete or the model library does not cover special models. When a match is confirmed, the control device 30 identifies the target computing board model as the matching model and advances the testing process, ensuring that subsequent parameter mapping and status display are strictly based on the verified model. When a mismatch is confirmed, the user is required to select a new target computing board model on the display interface 10. After selecting the target computing board model, the display interface 10 displays the effect diagram of the computing board model corresponding to the target computing board model and confirms with the user again. If a mismatch still occurs, the user needs to continue to select a new model on the display interface 10. If a match is found, the testing process begins. This dynamic adjustment mechanism handles the initial matching failure through a cyclical verification process and continuously optimizes the model selection using user feedback until a perfectly matching target computing board model is found, thereby fundamentally avoiding misjudgments caused by model deviation.

[0102] Furthermore, this embodiment, combined with the techniques for acquiring the attribute information of the computing board to be tested and displaying the rendering of the computing board model, forms a complete fault detection process. Through preliminary matching of attribute information and secondary verification with user confirmation, the accuracy of model selection is significantly improved, enabling a better overall improvement in fault location efficiency and maintenance efficiency.

[0103] Optionally, refer to Figure 4 , Figures 10 to 12 Another embodiment of the present invention provides a fault detection method, based on the above. Figure 2 In the embodiment shown, the display interface 10 has a first side 11, a second side 12, a third side 13, and a fourth side 14 that are adjacent to each other. The first side 11 and the third side 13 are arranged opposite to each other, and the second side 12 and the fourth side 14 are arranged opposite to each other. The computing board model rendering includes a computing board, a first test parameter block, a test control block, and a second test parameter block.

[0104] The step of retrieving the target computing board model and rendering the corresponding computing board model image includes steps S231-S234, wherein:

[0105] S231. Obtain the actual size information of the computing board and the interface size information of the display interface 10;

[0106] S232. Calculate the ratio between the first long side in the actual size information and the second long side in the interface size information;

[0107] S233. Adjust the actual size information according to the ratio to generate the corresponding computing board layout size information, and arrange the computing board between the second side 12, the third side 13 and the fourth side 14 of the display interface 10 according to the computing board layout size information.

[0108] S234. The test control block is placed at the center of the first side 11, and the first test parameter block, the test control block, and the second test parameter block are distributed at intervals along the first side 11; wherein, the first test parameter block is used to adjust the power supply parameters of the computing board to be tested, and the second test parameter block is used to determine the operating status of the computing board.

[0109] The display interface 10 refers to the visual window on the fault detection device used to present the rendering of the computing board model and related operation areas, which can be implemented through an LCD screen or a touch screen. The first side 11, second side 12, third side 13, and fourth side 14 define the boundaries of the display interface 10, providing a clear spatial division basis for interface elements through their adjacent and relative arrangement. In this embodiment, the first side 11 refers to the bottom of the display interface 10, and the second side 12, third side 13, and fourth side 14 are then arranged counterclockwise.

[0110] The computing power module refers to the visualized area simulating the physical structure of the computing power board under test, which can be rendered and displayed as a two-dimensional planar diagram or a three-dimensional stereoscopic diagram. The first test parameter block is a functional module for adjusting power supply parameters, which can be implemented through sliders, virtual buttons, input boxes, or drop-down menus. The test control block is an operation module that centrally manages the testing process, which can implement start, pause, and stop control functions through button groups or virtual buttons. The second test parameter block is a functional module for monitoring the operating status of the computing power board, which can provide status feedback through data buttons, data boxes, real-time data curves, status lights, or text boxes.

[0111] In practical applications, obtaining the actual size information of the computing board and the interface size information of the display interface 10 is to ensure the accuracy of model rendering. This can be achieved through sensor measurement or querying a preset database. Calculating the ratio between the first long side in the actual size information and the second long side in the interface size information is to achieve proportional scaling. The purpose is to maintain the geometric accuracy of the chip layout and prevent visual distortion caused by scaling from affecting the efficiency of fault point identification.

[0112] This solution effectively addresses the issues of display adaptation and operational efficiency of the computing board model on screens of different sizes by defining a structured layout and scaling rendering mechanism for the display interface 10. The display interface 10 uses a frame with four adjacent sides set relatively to each other, providing a stable foundation for element positioning, avoiding visual confusion caused by arbitrary layouts, and enabling users to quickly establish a spatial understanding of the interface. The computing board model rendering is divided into functional areas: a computing power block, a test parameter block, and a control block, clearly distinguishing between model display and operational interaction, reducing the burden on users to switch attention during fault detection. Obtaining the actual size information of the computing board and the size information of the display interface 10, and rendering based on real physical parameters ensures the reliability of subsequent scaling calculations and avoids model distortion due to missing size information.

[0113] This embodiment calculates the ratio between the first long side of the actual size and the second long side of the interface size, and then achieves proportional scaling through long side alignment. This maintains the geometric accuracy of the chip layout and prevents deformation during scaling that could affect fault point identification. The computing board layout size information is generated according to the ratio, and the computing board is placed between the second side 12, the third side 13, and the fourth side 14 of the display interface 10. This maximizes the model display space using the three-sided area, while retaining the first side 11 as an operation area, optimizing the interface space allocation and making the computing chip layout clearly visible. The test control block is placed at the center of the first side 11, and the test parameter block and control block are distributed at intervals along the first side 11, concentrating key operation elements for quick one-handed access. The first test parameter block is specifically for adjusting power supply parameters, and the second test parameter block is used to determine the operating status. With clear functional division, users can complete parameter adjustments and status confirmation without switching interfaces, significantly improving the smoothness of fault detection and location efficiency. Based on this, the technical solution proposed above for obtaining the attribute information of the computing board to be tested and displaying the corresponding model effect diagram is combined to optimize the visualization effect and operation convenience in the fault detection process, thereby effectively improving the overall maintenance efficiency.

[0114] Optionally, refer to Figure 5 as well as Figure 10 In another embodiment of the present invention, a fault detection method is provided, based on the above. Figure 1 The embodiment shown further includes steps S400-S800, wherein:

[0115] S400: Obtain the location and encoding information of each computing chip in the computing board;

[0116] S500. Divide the simulated computing chip in the computing board model rendering into multiple adjacent chip blocks according to a preset interval row. The multiple adjacent chip blocks include a start number block, a middle number block and an end number block.

[0117] S600. Select a chip block near the side as the starting numbered block;

[0118] S700. Based on the location information and the encoding information, sequentially encode along the starting number block, the intermediate number block to the ending number block according to the preset encoding path;

[0119] S800, Display the encoded rendering of the computing board model to the display interface 10.

[0120] Location information refers to the specific coordinate data of the computing chip on the computing board, which can be implemented using a two-dimensional or three-dimensional coordinate system. Its purpose is to provide precise spatial positioning for subsequent coding. Coding information can be understood as a sequence of numbers or characters used to uniquely identify each computing chip. This can be achieved through hardware firmware reading or software algorithm generation, ensuring the uniqueness and traceability of each chip's identity. Preset interval row division refers to grouping the simulated computing chips according to a fixed number of rows based on the physical layout of the chips. This can be achieved using algorithms based on row-column arrangement rules or manually selected through the backend, aiming to reduce the complexity of dense chip layouts and facilitate quick identification and management by operators. Preset coding path refers to the trajectory planning for coding chip blocks according to a specific direction and sequence. It can use a polygonal, serpentine, or circular path design, aiming to ensure that the coding sequence is consistent with the chip's physical layout logic, thereby improving the intuitiveness and efficiency of fault location.

[0121] This solution effectively addresses the core problem of difficult fault location in densely packed chip layouts by constructing a block-based coding system. First, it acquires the location and coding information of each computing chip in the computing board. This step establishes a precise mapping relationship based on actual hardware layout data, ensuring that subsequent coding strictly corresponds to the coordinates and identification of the physical chip. This avoids the risk of misalignment caused by manual input and provides a reliable data foundation for visual positioning. Next, the simulated computing chips are divided into multiple adjacent chip blocks according to preset intervals, such as four rows per block, five rows per block, etc. This division method follows the common row-column layout pattern of computing boards, organizing the disordered chip group into logically clear unit groups, significantly reducing layout complexity and enabling operators to perform hierarchical management by block, rather than identifying chips one by one. Figure 10 As shown, the chip block closest to the side is selected as the starting numbering block. The edge of the display interface 10 is fully utilized as a visual anchor point, ensuring the encoding starting point aligns with the human eye's natural scanning habit from the boundary to the center, significantly reducing the cognitive load of initial positioning. Based on the location and encoding information, the blocks are sequentially encoded along a preset encoding path. A zigzag path design ensures the encoding direction is consistent with the chip's physical layout logic. This path planning based on actual location information gives the encoding sequence spatial continuity, allowing operators to quickly infer the positions of adjacent chips based on path patterns without needing to memorize individual chip numbers. Finally, the encoded model is displayed on the display interface 10, integrating the block-based encoding with the operating status in real time. This allows faulty chips to be instantly identified through their encoded positions, enabling precise fault location and efficient handling in complex layouts.

[0122] Based on this, this embodiment combines a block-based coding system with a computing board model diagram, which not only improves the efficiency of fault location but also enhances the operator's intuitive understanding of complex layouts, thereby significantly improving overall maintenance efficiency.

[0123] Optionally, refer to Figure 6 Another embodiment of the present invention provides a fault detection method based on the above. Figure 5 In the illustrated embodiment, in response to the detection operation on the computing power board to be tested, the current operating state of the computing power board to be tested is obtained, specifically in steps S310-S360, wherein:

[0124] S310. Obtain the computing power parameter range, preset electrical data range, and preset temperature data of the computing power chip corresponding to the attribute information;

[0125] S320. In response to the detection operation on the computing power board to be tested, a first detection data packet is sent to the computing power board to be tested, and the computing power parameter value, first electrical data and current temperature value of each computing power chip returned by the computing power board to be tested are monitored.

[0126] S330. Compare each of the computing power parameter values ​​with the computing power parameter range to confirm the first state information;

[0127] S340. Compare each of the first electrical data with the preset electrical data range to confirm the second state information;

[0128] S350. Compare each of the current temperature values ​​with the preset temperature data to confirm the third state information;

[0129] S360. Determine the operating state based on the first state information, the second state information, and the third state information. The operating state includes normal operation or abnormal operation.

[0130] The computing power parameter range refers to the performance index range that matches the specific model and configuration of the computing power board under test. This range can be dynamically adjusted to ensure that the testing standards are consistent with the actual equipment requirements. The preset electrical data range can be understood as the threshold range covering key electrical parameters such as power supply voltage, LDO signals (e.g., LDO_1.8V, LDO_0.8V), TX signals, and RX signals. This range can be achieved through experimental calibration or extraction from equipment specifications, aiming to comprehensively cover core aspects such as power supply stability and communication link integrity. The preset temperature data refers to the safe temperature range set based on the chip design specifications. This range can be obtained through thermal simulation analysis or historical data statistics, aiming to prevent hardware damage caused by overheating.

[0131] Among them, the computing power parameter value refers to the actual computing power displayed by the computing chip when processing the first detection data packet, which can intuitively reflect the chip's current performance. The first electrical data can be understood as the real-time measurement values ​​of key electrical parameters such as the power supply voltage, LDO signals (such as LDO_1.8V, LDO_0.8V), TX signal, and RX signal of the computing chip during the process of receiving and processing the first detection data packet. These data are crucial for evaluating the stability of the chip's electrical performance. The current temperature value refers to the temperature reading monitored in real time by the computing chip during operation, which is directly related to the chip's thermal management status and long-term reliability.

[0132] The first status information is derived by comparing the computing power parameter values ​​with the computing power parameter range, indicating whether the computing power chip is in a normal performance state. The first electrical data covers several key electrical parameters of the computing power chip during power supply and communication, which are crucial for evaluating the chip's electrical stability. The second status information is generated based on the comparison between the first electrical data and a preset electrical data range, used to determine if there are any electrical abnormalities in the chip. The current temperature value reflects the real-time temperature status of the computing power chip during operation, which is important for monitoring the chip's thermal management effectiveness. The third status information is derived by comparing the current temperature value with preset temperature data, indicating whether the chip's temperature is within a safe range. By combining the first, second, and third status information, the operating status of the computing power board under test can be comprehensively evaluated, thereby determining whether it is operating normally or abnormally. If any one of the first, second, or third status information of any chip is abnormal, it can be detected in a timely manner, significantly improving maintenance efficiency and accuracy.

[0133] When confirming the first state information, the control device 30 meticulously compares each computing power parameter value with a preset computing power parameter range. If all parameter values ​​fall within this range, it is determined to be in a normal state; otherwise, it is marked as abnormal. Similarly, when confirming the second state information, the control device 30 compares each first electrical data value with a preset electrical data range one by one. If all electrical data values ​​are within this range, it is determined to be in a normal state; if any data exceeds the range, it is marked as abnormal. Likewise, when confirming the third state information, the control device 30 compares each current temperature value with preset temperature data. If the temperature value is within the safe range, it is determined to be in a normal state; if the temperature exceeds the safe range, it is marked as abnormal. Finally, the control device 30 integrates the first, second, and third state information to determine the overall operating status of the computing power board under test. If all state information shows normal operation, the computing power board is determined to be operating normally; if any abnormal state information exists, the computing power board is determined to be operating abnormally.

[0134] In practical applications, the first detection data packet refers to a specific set of instructions used to trigger the response of the computing board under test and collect its operating status. It can be implemented using standardized protocols or custom formats, aiming to proactively acquire fine-grained operational information for each computing chip. The first status information can be understood as a performance evaluation result generated by comparing computing parameter values ​​with their ranges, clearly distinguishing whether computing performance is abnormal. The second status information refers to an electrical health assessment result generated based on comparing the first electrical data with a preset electrical data range, independently identifying power supply or communication faults. The third status information is a temperature risk assessment result generated by comparing the current temperature value with preset temperature data, focusing on identifying potential overheating problems.

[0135] This embodiment achieves refined identification of computing power anomalies, electrical anomalies, and temperature anomalies by decomposing the operational status detection process from multiple dimensions. First, it dynamically acquires the range of computing power parameters, preset electrical data range, and preset temperature data based on attribute information, ensuring a high degree of matching between the detection standards and the specific model and configuration of the computing power board under test, avoiding the risk of misjudgment that may arise from general parameter ranges. Then, by sending a first detection data packet and monitoring the returned computing power parameter values, first electrical data, and current temperature value, fine-grained acquisition of the operational status of each computing power chip is achieved. During this process, the monitoring of the first electrical data covers the power supply voltage, LDO signal, and TX / RX communication signal, effectively capturing potential fault signals related to power supply stability and communication link integrity. Next, by comparing the computing power parameter values, first electrical data, and current temperature value respectively, first status information, second status information, and third status information are generated, thereby independently identifying computing power performance anomalies, electrical faults, and temperature risks. Ultimately, the operating status is determined by combining the three status information. Through multi-dimensional cross-validation, the fault types are clearly distinguished. For example, when only computing power is abnormal, a performance problem is indicated. When electrical and temperature are abnormal at the same time, it points to a compound fault, which significantly improves the accuracy of fault location and the reliability of maintenance decisions.

[0136] Furthermore, this embodiment maps the operating status to the model rendering, which not only intuitively presents the operating status of each computing chip, but also allows for rapid location of faulty chips by combining location and encoding information, thereby significantly improving maintenance efficiency. This multi-level, multi-dimensional detection mechanism solves the problem of insufficient fault location accuracy caused by a lack of refined comparison, providing strong support for the efficient maintenance of equipment such as blockchain servers.

[0137] Optionally, refer to Figure 7 and Figure 11 Another embodiment of the present invention provides a fault detection method, based on the above. Figure 6The embodiment shown, after determining the operating state based on the first state information, the second state information, and the third state information, further includes steps S370-S390, wherein:

[0138] S370. If it is detected that a computing chip in the computing board to be tested is operating abnormally, obtain the location information, encoding information and current computing power value of the abnormally operating chip;

[0139] S380. Based on the location information and the encoding information, determine the abnormal chip as the simulated computing chip corresponding to the computing board model rendering.

[0140] S390. The current computing power value is set after the encoding of the analog computing power chip and displayed on the display interface 10.

[0141] Location information refers to the specific coordinates of the malfunctioning chip in physical space, which can be implemented using a two-dimensional or three-dimensional coordinate system. Its purpose is to provide basic data support for subsequent precise mapping. Encoding information can be understood as a unique identifier or tag for each computing chip. It can be generated through a preset encoding path (such as a polyline or serpentine pattern) to simplify the location process in complex layouts. The current computing power value refers to the actual computing power output of the malfunctioning chip at the time of the fault. It can be obtained by monitoring the data returned by the interface circuit 20 in real time, reflecting the specific severity of the fault.

[0142] Here, placing the current computing power value after the encoding of the analog computing power chip means, for example... Figure 11 As shown, please refer to chips numbered 141 and 142. 141 is a normally operating computing chip, and 142 is an abnormal computing chip. Computing chip 141 only has a number, while computing chip 142 has a computing power value of 71 in addition to the number 142. In this embodiment, the two are separated by a colon ":". In practice, symbols such as commas and semicolons ";" can be used to separate them to distinguish the computing chip number and the current computing power value.

[0143] In the event of an abnormal operation of a computing chip detected in the computing board under test, the control device 30 first captures key details of the abnormal chip, including its location information, encoding information, and current computing power value. This data acquisition ensures that maintenance personnel can quickly pinpoint the fault location, avoiding the limitations of relying solely on status judgments without obtaining real-time fault parameters. Subsequently, through the preset encoding path in the computing board model rendering, the coordinates of the physical chip are precisely associated with blocks in the virtual model. The introduction of encoding information significantly improves the location efficiency, overcoming the difficulty of finding the chip due to its density in traditional methods. Finally, the current computing power value is directly superimposed and displayed after the encoding of the simulated computing chip, allowing maintenance personnel to clearly observe the specific value of the abnormal chip on the display interface 10 without switching interfaces or consulting additional documents, thus effectively shortening the maintenance cycle.

[0144] Furthermore, this embodiment, by integrating real-time data from malfunctioning chips with a visualization model, not only solves the core problem of unintuitive fault location but also significantly improves the intuitiveness and response speed of fault diagnosis. This design makes the repair process more efficient, especially in equipment with dense electronic components and complex structures, enabling rapid and accurate location of fault points, thereby greatly reducing labor costs and time consumption.

[0145] Optionally, refer to Figure 8 Another embodiment of the present invention provides a fault detection method, based on the above. Figures 1 to 7 as well as Figures 10 to 12 In any of the embodiments shown, obtaining the attribute information of the computing board to be tested includes steps S110-S120, wherein:

[0146] S110. In response to the selection operation for the computing board to be tested, determine the power supply parameters, number of computing chips and computing chip layout information corresponding to the model of the computing board to be tested.

[0147] S120. The power supply parameters, the number of computing chips, and the arrangement information of computing chips are determined as the attribute information.

[0148] Among them, attribute information refers to a set of structured data related to the computing board to be tested. It can be implemented using power supply parameters, the number of computing chips, and the arrangement of computing chips. The purpose is to ensure that the system can accurately call the computing board model and complete the state mapping based on this data.

[0149] The selection of the computing board to be tested can be done manually, such as through a selection box or drop-down menu in the user interface, or automatically by scanning the identification code on the computing board and automatically associating it with the corresponding model. Power supply parameters cover key indicators such as voltage, current, and power. These parameters directly determine the power supply control of the computing board and are the basis for evaluating electrical performance in subsequent testing. The number of computing chips clarifies the scale of the core computing unit of the computing board to be tested, providing a quantitative benchmark for generating computing parameter ranges and comparisons. The computing chip layout information describes the physical distribution of the chips on the computing board, including row and column spacing and arrangement direction. This information is crucial for constructing the model rendering and implementing block-based encoding. During the determination of attribute information, the control device 30 first receives the selection command issued by the user or system, and then retrieves the corresponding power supply parameters, number of computing chips, and layout information from the preset database based on the model identifier in the command. If the database does not directly store complete attribute information for a certain model, the control device 30 can also dynamically obtain it by parsing the equipment specification or calling the online data interface, ensuring the accuracy and timeliness of the attribute information.

[0150] Based on power supply parameters, the control device 30 can dynamically generate a preset electrical data range that matches the computing board under test, avoiding misjudgments caused by parameter mismatch. The number of computing chips directly determines the range of computing parameters and the scale of the first detection data packet, ensuring that each chip is effectively covered. The computing chip layout information is used to construct a 3D model rendering. By mapping the coordinates of the physical chips to the virtual model, visual positioning and intuitive presentation of fault points are achieved. In addition, attribute information provides key basis for subsequent maintenance decisions, such as assessing the maintenance difficulty based on chip layout density, or recommending suitable maintenance tools and safety measures based on power supply parameters.

[0151] This embodiment systematically acquires the attribute information of the computing power board under test, which not only improves the standardization of the testing process but also significantly enhances the accuracy of fault location. This design allows the testing method to adapt to computing power boards of different models and configurations, solving the compatibility problems caused by fixed parameters in traditional methods, and providing a reliable guarantee for the efficient maintenance of complex equipment such as blockchain servers.

[0152] Reference Figures 9 to 11 In another embodiment of the present invention, a fault detection method is provided, based on the above. Figures 1 to 7 as well as Figures 10 to 12 In any of the embodiments shown, the computing board to be tested further includes at least one of a temperature sensing chip or a memory chip; the fault detection method further includes steps S900-S1100, wherein:

[0153] S900: Send detection data to the temperature sensing chip and / or the storage chip, and monitor the status data returned by the temperature sensing chip and / or the storage chip;

[0154] S1000: In the event of abnormal status data, obtain the first position of the temperature sensing chip and / or the storage chip in the computing board model rendering.

[0155] S1100: Control the analog temperature sensing chip and / or analog storage chip at the first position to display the corresponding alarm information.

[0156] Among them, temperature sensing chips or storage chips refer to key components outside of computing chips in the computing board. They can be independent hardware modules or functional units integrated into the computing board, with the aim of expanding the detection range to cover the operating status of all components. In practical applications, detection data refers to the instructions or signals used to trigger temperature sensing chips or storage chips to provide feedback on their operating status. These can be sent through a preset communication protocol to proactively acquire the status information of these components. In addition, alarm information can be understood as a visual fault indication mechanism, specifically in the form of a chip image turning red and / or a fault code popping up, with the aim of enabling maintenance personnel to quickly identify abnormal components.

[0157] In this embodiment, by responding to the selection operation of the computing board to be tested, the power supply parameters, number of computing chips, and arrangement information of the corresponding model are automatically associated, avoiding the tediousness and potential errors of manual input, thereby ensuring the accuracy and reliability of attribute information. Based on this, the control device 30 uses this attribute information to accurately call the computing board model and actively monitors the returned status data by sending detection data to the temperature sensing chip and storage chip, compensating for the deficiency of only focusing on the computing chip. When the status data is abnormal, the control device 30 obtains the first position of the temperature sensing chip or storage chip in the computing board model rendering, accurately mapping the fault point to the spatial coordinates of the visualized model, thereby achieving intuitive fault location. Finally, by controlling the simulated temperature sensing chip or simulated storage chip at the first position to display alarm information, the intuitiveness and efficiency of fault diagnosis are significantly improved. This embodiment not only solves the problem of incomplete fault location caused by the lack of detection of temperature sensing chips and storage chips, but also optimizes the fault identification experience of maintenance personnel through a visualized alarm mechanism, thereby significantly improving overall maintenance efficiency.

[0158] The present invention also proposes a control device 30, the control device 30 comprising: a memory, a processor, and a fault detection program stored in the memory and executable on the processor, the fault detection program being configured to implement the fault detection method as described above.

[0159] In practical applications, the control device 30 establishes a communication connection with the computing board under test, providing a foundation for real-time data interaction. Acquiring the attribute information of the computing board under test, including core parameters such as model and hardware configuration, serves as a key input. Its function is to accurately identify the physical characteristics of the computing board and avoid model matching errors caused by structural differences between different computing board models. When displaying at least one computing board model rendering corresponding to the attribute information, the matching model is selected based on the attribute information, ensuring that the rendering accurately reflects the chip layout and functional partitions of the actual computing board. This method of dynamically generating renderings based on attribute information ensures consistency between the visual interface and the physical device, allowing users to intuitively understand the device structure without relying on experience.

[0160] In response to the testing operation of the computing power board under test, the current operating status is obtained and mapped with parameters of the computing power board model diagram. This process accurately locates the operating status data to the corresponding position of each computing power chip according to the predefined structure of the computing power board model diagram, so that abnormal states can be directly highlighted on the diagram. Thus, users can quickly identify faulty chips by observing the interface, avoiding the tedious process of manual point-by-point testing, significantly improving the intuitiveness and efficiency of fault location. The entire technical solution, through the technical chain of attribute information-driven model matching and operating status mapping to the visualization interface, transforms the invisible circuit state into visible graphical information, fundamentally optimizing the fault diagnosis process, and effectively solving the problem of low fault location efficiency caused by the lack of fault detection visualization functions in blockchain mining machine repair.

[0161] It is worth noting that since the control device 30 of the present invention is based on the above-described fault detection method, the embodiments of the control device 30 of the present invention include all the technical solutions of all embodiments of the above-described fault detection method, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0162] Reference Figure 13 and Figure 14 The present invention also proposes a fault detection device, which includes a display interface 10, an interface circuit 20, and a control device 30 as described in the above embodiment, wherein:

[0163] The display interface 10 is used to display the rendering of the computing board model and the operating status of each computing chip of the computing board under test; the interface circuit 20 is used to communicate with the computing board under test; the control device 30 is electrically connected to the display interface 10 and the interface circuit 20 respectively, and the control device 30 is used to acquire the attribute information of the computing board under test and control the display interface 10 to display at least one rendering of the computing board model corresponding to the attribute information; the control device 30 is also used to acquire the current operating status of the computing board under test in response to the detection operation of the computing board under test, perform parameter mapping with the rendering of the computing board model, and control the display interface 10 to display the operating status of each computing chip of the computing board under test.

[0164] The display interface 10 can be a high-resolution screen that clearly and accurately displays the rendering of the computing board model and the operating status of each computing chip, ensuring that users can intuitively observe the real-time status of each chip. The interface circuit 20 adopts a high-speed and stable communication protocol to ensure fast and accurate data transmission with the computing board under test, avoiding data delays or errors caused by communication problems. The control device 30 integrates a high-performance processor and a dedicated algorithm module, which can efficiently process the acquired attribute information and operating status data, realize rapid parameter mapping and status display control, thereby improving the response speed and detection accuracy of the entire fault detection equipment.

[0165] In practical applications, the fault detection device in this embodiment acquires the attribute information of the computing board under test, which can be understood as the process of extracting its physical characteristics and configuration information from the computing board under test. For example, this can be achieved by reading the firmware information, hardware identifiers, or configuration files of the computing board, or by manually inputting relevant information. The purpose is to achieve accurate identification of the computing board under test. When displaying at least one computing board model rendering corresponding to the attribute information, the rendering can be generated by calling a preset model library and filtering matching models. For example, the corresponding entries in the model library can be retrieved according to the model and hardware configuration, and the relevant model data can be loaded. The purpose is to ensure that the rendering can truly reflect the structural layout of the actual computing board. The mapping relationship between the computing board model rendering and the parameters of the computing board under test can be achieved through a predefined rule table or algorithm. For example, the running status data can be bound to a specific area in the rendering to achieve a visual presentation of the parameters. In response to the detection operation of the computing board under test, the current running status can be obtained by sending test commands and receiving return data. For example, a diagnostic signal can be sent to the computing board and its feedback information can be parsed. The purpose is to monitor the working status of the computing chip in real time.

[0166] The core innovation of this embodiment lies in the integrated combination of the display interface 10, interface circuit 20, and control device 30, along with the introduction of a mechanism for dynamically generating computing board model renderings based on attribute information. This solves the inefficiency problem caused by the lack of intuitive feedback in traditional manual maintenance. Specifically, the display interface 10 can present the computing board model renderings and operating status in real time, allowing maintenance personnel to directly observe fault locations without having to inspect each board individually. The interface circuit 20 ensures reliable communication between the device and the computing board under test, providing a foundation for data interaction. The control device 30 generates matching model renderings based on attribute information and associates operating status data with specific chip locations in the model through parameter mapping, such as highlighting abnormal chips, significantly shortening fault diagnosis time and improving maintenance efficiency and accuracy.

[0167] The innovation of this embodiment lies in its ability to visualize the fault detection process by constructing a dynamic mapping mechanism between attribute information and the computing board model rendering, thereby solving the problem of low fault location efficiency in manual maintenance. Specifically, the fault detection device establishes a communication connection with the computing board under test, providing a foundation for real-time data interaction; by acquiring attribute information and generating corresponding model renderings, model matching errors caused by structural differences between different computing board models are avoided; and by mapping the operating status data with the model renderings, abnormal states can be directly and intuitively displayed on the renderings, significantly improving the efficiency of fault location.

[0168] In this embodiment, the fault detection device establishes a communication connection with the computing board under test, providing a physical basis for real-time data interaction. Acquiring the attribute information of the computing board under test serves as a key input. This attribute information includes core parameters such as model and hardware configuration, which accurately identifies the physical characteristics of the computing board, avoiding model matching errors caused by structural differences between different computing board models, and laying a data foundation for subsequent visualization. Furthermore, when displaying at least one computing board model rendering corresponding to the attribute information, the matching model is selected based on the attribute information, ensuring that the rendering accurately reflects the chip layout and functional partitions of the actual computing board. This method of dynamically generating renderings based on attribute information ensures consistency between the visualization interface and the physical device, allowing users to intuitively understand the device structure without relying on experience. A mapping relationship exists between the computing board model rendering and actual parameters, transforming abstract operating parameters into visual interface elements, solving the pain point of scattered and difficult-to-connect parameters in traditional maintenance. In response to the testing operation of the computing power board under test, the current operating status is obtained and mapped with parameters of the computing power board model diagram. This process accurately locates the operating status data to the corresponding position of each computing power chip according to the predefined structure of the model diagram, so that abnormal states can be directly highlighted on the diagram. Thus, users can quickly identify faulty chips by observing the interface, avoiding the tedious process of manual point-by-point testing, significantly improving the intuitiveness and efficiency of fault location. The entire technical solution, through the technical chain of attribute information-driven model matching and operating status mapping to the visualization interface, transforms the invisible circuit state into visible graphical information, fundamentally optimizing the fault diagnosis process and effectively solving the problem of low fault location efficiency caused by the lack of fault detection visualization functions in blockchain server maintenance.

[0169] It is worth noting that since the fault detection device of the present invention is based on the control device 30 described above, the embodiments of the fault detection device of the present invention include all the technical solutions of all embodiments of the control device 30 described above, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0170] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A fault detection method, applied to fault detection equipment, characterized in that, The fault detection device is communicatively connected to the computing board under test, and the fault detection method includes: Obtain the attribute information of the computing board to be tested; Display at least one rendering of a computing board model corresponding to the attribute information; there is a mapping relationship between the rendering of the computing board model and the parameters of the computing board to be tested; In response to the detection operation of the computing board to be tested, the current operating status of the computing board to be tested is obtained and the parameters are mapped with the computing board model effect diagram so as to display the operating status of each computing chip of the computing board to be tested on the display interface of the fault detection device. The fault detection method further includes: Obtain the location and encoding information of each computing chip in the computing board; The simulated computing chip in the computing board model diagram is divided into multiple adjacent chip blocks according to a preset interval row. The multiple adjacent chip blocks include a start number block, a middle number block and an end number block. Select the chip block closest to the side as the starting numbered block; Based on the location information and the encoding information, the code is sequentially encoded along the starting number block, the intermediate number block, and the ending number block according to a preset encoding path; The encoded rendering of the computing board model is displayed on the display interface.

2. The fault detection method as described in claim 1, characterized in that, The display of at least one computing board model rendering corresponding to the attribute information includes: The model and hardware configuration of the computing board to be tested are determined based on the attribute information. Determine the target computing board model in the preset computing board model library that matches the model and the hardware configuration; The target computing board model is retrieved and rendered to generate a corresponding computing board model rendering, which includes the layout position and functional partition identifiers of each computing chip.

3. The fault detection method as described in claim 2, characterized in that, The display interface has a first side, a second side, a third side, and a fourth side, which are adjacent to each other. The first side and the third side are arranged opposite to each other, and the second side and the fourth side are arranged opposite to each other. The computing board model rendering includes a computing board, a first test parameter block, a test control block, and a second test parameter block. The step of retrieving the target computing board model and rendering the corresponding computing board model image includes: Obtain the actual size information of the computing board and the interface size information of the display interface; Calculate the ratio between the first long side in the actual size information and the second long side in the interface size information; Adjust the actual size information according to the ratio to generate the corresponding computing board layout size information, and arrange the computing board between the second, third and fourth sides of the display interface according to the computing board layout size information; The test control block is positioned at the center of the first side, and the first test parameter block, the test control block, and the second test parameter block are distributed at intervals along the first side; wherein, the first test parameter block is used to adjust the power supply parameters of the computing board under test, and the second test parameter block is used to determine the operating status of the computing board.

4. The fault detection method as described in claim 2, characterized in that, After retrieving the target computing board model and rendering the corresponding computing board model effect image, the process further includes: In response to the test operation on the computing board to be tested, a confirmation operation for the rendering of the computing board model is displayed on the display interface to determine whether the target computing board model is consistent with the computing board to be tested; If the match is confirmed, the target computing board model is determined to be the matching model of the computing board to be tested, and the corresponding testing process is carried out. If an inconsistency is confirmed, a new target computing board model is selected for matching until a model that is completely consistent with the computing board to be tested is found, and the corresponding testing process is carried out.

5. The fault detection method as described in claim 1, characterized in that, The step of obtaining the current operating status of the computing power board under test in response to the detection operation is as follows: Obtain the computing power parameter range, preset electrical data range, and preset temperature data of the computing chip corresponding to the attribute information; In response to the detection operation on the computing power board to be tested, a first detection data packet is sent to the computing power board to be tested, and the computing power parameter value, first electrical data and current temperature value of each computing power chip returned by the computing power board to be tested are monitored. Each computing power parameter value is compared with the computing power parameter range to confirm the first state information; Each of the first electrical data points is compared with the preset electrical data range to confirm the second state information; Each current temperature value is compared with the preset temperature data to confirm the third state information; The operating state is determined based on the first state information, the second state information, and the third state information, and the operating state includes normal operation or abnormal operation.

6. The fault detection method as described in claim 5, characterized in that, After determining the operating state based on the first state information, the second state information, and the third state information, the method further includes: If an abnormal operation of a computing chip is detected in the computing board to be tested, the location information, encoding information and current computing power value of the abnormally operating chip are obtained. Based on the location information and the encoding information, the abnormal chip is identified as the simulated computing chip corresponding to the computing board model rendering. The current computing power value is set after the encoding of the analog computing power chip and displayed on the display interface.

7. The fault detection method according to any one of claims 1 to 6, characterized in that, The step of obtaining the attribute information of the computing board to be tested includes: In response to the selection operation for the computing board to be tested, the power supply parameters, number of computing chips and computing chip layout information corresponding to the model of the computing board to be tested are determined; The power supply parameters, the number of computing chips, and the arrangement information of the computing chips are determined as the attribute information; The computing board to be tested further includes at least one of a temperature sensing chip or a storage chip; the fault detection method further includes: Send detection data to the temperature sensing chip and / or the storage chip, and monitor the status data returned by the temperature sensing chip and / or the storage chip; In the event of abnormal status data, the first position of the temperature sensing chip and / or the storage chip in the computing board model rendering is obtained; The analog temperature sensor chip and / or analog storage chip at the first position are controlled to display the corresponding alarm information.

8. A control device, characterized in that, The control device includes: a memory, a processor, and a fault detection program stored in the memory and executable on the processor, the fault detection program being configured to implement the fault detection method as described in any one of claims 1 to 7.

9. A fault detection device, characterized in that, include: The display interface is used to display the rendering of the computing board model and the operating status of each computing chip on the computing board to be tested. An interface circuit, wherein the interface circuit is used for communicative connection with the computing board under test; and The control device as described in claim 8 is electrically connected to the display interface and the interface circuit respectively. The control device is used to acquire the attribute information of the computing board to be tested and control the display interface to display at least one computing board model rendering corresponding to the attribute information. The control device is also used to respond to the detection operation of the computing power board to be tested, obtain the current operating status of the computing power board to be tested, perform parameter mapping with the computing power board model effect diagram, and control the display interface to display the operating status of each computing power chip of the computing power board to be tested.

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