Reset control method and device for universal graphics processor, and chip

Abstract

The invention provides a reset control method and device for a universal graphics processor and a chip, and relates to the technical field of integrated circuits. The method takes over a reset control right by a reset management unit, and comprises the following steps: receiving a global reset signal for triggering reset initialization of a functional module of the universal graphics processor; dividing the function modules into a plurality of reset groups according to at least one grouping strategy in a power domain, a clock domain and a reset domain of the universal graphics processor; generating a group of reset control signals with different time sequences based on the reset group; and applying corresponding reset control signals to each reset group in sequence according to different time sequences. Through a staged and grouped reset control strategy, the transient current impact at the moment of reset is effectively inhibited, the problem of functional abnormality caused by power supply voltage drop in the reset process of the general graphic processor is solved, and the reliability of a chip and the integrity of a power supply are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a reset control method, device, and chip for a general-purpose graphics processor. Background Technology

[0002] In the design of current high-performance computing chips, such as general-purpose computing on graphics processing units (GPGPUs), it is necessary to initialize various functional units and register modules in the chip to improve reset response speed and avoid metastability problems caused by reset signal and clock competition.

[0003] Currently, a global reset strategy based on asynchronous setting and synchronous release is commonly used for initialization. However, as the integration scale of GPGPU continues to expand, it typically contains thousands of parallel computing units and is divided into multiple voltage and clock domains. If a global reset method is still used, multiple parallel modules within the chip will simultaneously end their reset state and start running at the moment of reset release, causing a sharp increase in power consumption in a very short time and generating a huge transient current surge, which in turn causes a significant voltage drop in the power network. In particular, when clock modules such as phase-locked loops are reset, causing a sudden change in clock frequency, the current fluctuation will be further aggravated.

[0004] Therefore, using a global reset method can cause power integrity issues during the reset process in high-performance GPGPUs. Summary of the Invention

[0005] This invention provides a reset control method, device, and chip for a general-purpose graphics processor, which solves the power integrity problem caused by transient current surges resulting from multiple functional modules simultaneously de-resetting during the reset process of a general-purpose graphics processor.

[0006] To address the aforementioned technical problems, this invention proposes an architecture where a reset management unit takes over system reset control. Its core lies in replacing the traditional global synchronous reset mechanism with a phased, grouped reset control strategy to optimize power integrity.

[0007] This invention provides a reset control method for a general-purpose graphics processor. The main contents of the method include: after receiving a global reset signal, the reset management unit does not immediately reset all functional modules. Instead, it first divides the numerous functional modules into multiple reset groups according to at least one strategy among the power domain, clock domain, and reset domain, based on the physical and logical structure of the chip. Subsequently, the reset management unit generates a set of reset control signals that are staggered in timing and applies their corresponding reset signals to each reset group in a preset order, thereby realizing a phased reset operation that disperses the concentrated high current impact.

[0008] According to the reset control method for a general graphics processor provided by the present invention, the following specific principles are mainly followed when performing grouping operations: First, functional modules in different power domains are physically isolated into different groups; Second, even within the same power domain, if functional modules are clocked by different phase-locked loops, they are also divided into different groups; Third, logically, a single phase-locked loop and its driven downstream functional modules are regarded as an associated group for unified management.

[0009] According to a reset control method for a general graphics processor provided by the present invention, for the aforementioned associated group containing a phase-locked loop, the reset operation of the phase-locked loop point is arranged after all associated functional modules to alleviate the current superposition effect.

[0010] According to the reset control method for a general-purpose graphics processor provided by the present invention, when a large functional module group driven by a single phase-locked loop is found to be too large, a secondary grouping mechanism is introduced to avoid significant current surges within the group. That is, the large group is decomposed into several smaller subgroups (N>1), and under this divide-and-conquer structure, the timing principle of the final reset of the phase-locked loop is followed.

[0011] According to the reset control method of a general graphics processor provided by the present invention, it also supports logical grouping based on reset control requirements, namely reset domains: for modules that are in the same physical domain (such as the same power domain or clock domain) but require different reset timing, they can be further divided into different logical reset domains, thereby achieving more refined timing control.

[0012] According to the reset control method for a general graphics processor provided by the present invention, the core variable for implementing staged reset is the reset delay time of each group. The delay time is designed as a flexibly configurable parameter, which provides a basis for subsequent system-level optimization.

[0013] According to the reset control method for a general-purpose graphics processor provided by the present invention, the aforementioned configurable delay parameters are stored in a dedicated register integrated within the reset management unit, which ensures fast and stable loading and retrieval of the delay configuration.

[0014] According to the reset control method for a general-purpose graphics processor provided by the present invention, during the chip design stage, the initial values ​​of each group delay parameter are determined based on the results of accurate power integrity simulation analysis and combined with the design experience of past successful projects, ensuring that the solution has high reliability before the first tape-out.

[0015] According to the reset control method of a general graphics processor provided by the present invention, after the chip is running normally, the delay value in the register can be dynamically rewritten by software instructions; when the system triggers the reset process again, the reset management unit will automatically use these updated optimized parameters to generate a reset sequence.

[0016] According to the reset control method of a general graphics processor provided by the present invention, the power supply voltage drop data of the chip is collected by testing the chip under actual typical reset scenarios, and a better delay time configuration is determined based on the analysis results.

[0017] According to the reset control method of a general graphics processor provided by the present invention, when the reset management unit recognizes a cold reset signal from outside the chip, it will take over and perform the above-mentioned phased reset process in groups on all downstream defined functional modules.

[0018] According to a reset control method for a general graphics processor provided by the present invention, before formally issuing a reset control signal to a group containing a phase-locked loop, the clock output of the phase-locked loop is switched from its normal high-frequency mode to a stable free-running mode, so as to avoid unpredictable system behavior due to clock loss during the reset process.

[0019] This invention provides a reset control device for a general-purpose graphics processor, comprising: a receiving unit for receiving a global reset signal, which is a trigger signal for resetting and initializing a functional module of the general-purpose graphics processor; a partitioning unit for partitioning the functional module into multiple reset groups according to at least one grouping strategy of the power domain, clock domain, and reset domain of the general-purpose graphics processor; a generating unit for generating a set of reset control signals with different timing sequences based on the multiple reset groups; and a control unit for sequentially applying the corresponding reset control signals to the multiple reset groups according to the different timing sequences.

[0020] The present invention provides a reset control device for a general-purpose graphics processor, comprising: a reset management unit, wherein the reset management unit is configured to perform a reset control method for a general-purpose graphics processor as described above.

[0021] This invention provides a general-purpose graphics processor chip that integrates a reset control device for the aforementioned general-purpose graphics processor.

[0022] The present invention provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it performs operations for configuring the registers in the reset control device of the general-purpose graphics processor, and writes the delay time configuration parameters of each reset group to the register of the reset management unit.

[0023] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements a reset control method for a general-purpose graphics processor as described above.

[0024] The reset control method, device, and chip for general-purpose graphics processors provided by this invention solve the problem of transient current surges faced by GPGPUs under traditional global reset by having a reset management unit take over the system reset control and adopting a phased and grouped reset strategy. The active control mechanism effectively disperses and smooths the concentrated huge current peaks on the time axis, thereby suppressing the voltage drop phenomenon of the power network and improving the power integrity during the reset process.

[0025] Specifically, the power domain and clock domain partitioning strategy, combined with the final reset timing design of the phase-locked loop, achieves dynamic load balancing for each power domain, effectively avoiding the risk of overload in local voltage domains. At the same time, it isolates the reset current of the phase-locked loop from the digital logic, and with the help of a clock mode switching mechanism, it ensures the clock stability of the reset process. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart illustrating a reset control method for a general-purpose graphics processor provided by the present invention.

[0028] Figure 2 This is a schematic diagram of the architecture of the reset grouping strategy provided by the present invention.

[0029] Figure 3 This is a schematic diagram of the structure of a reset control device for a general-purpose graphics processor provided by the present invention.

[0030] Figure 4 This is a schematic diagram of the structure of another general-purpose graphics processor reset control device provided by the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0032] In high-performance computing chips, some basic and general circuit design and control methods have been widely adopted. In terms of digital circuit reset design, asynchronous reset and synchronous release are mature and widely used circuit design techniques.

[0033] Asynchronous reset and synchronous release techniques are typically implemented using a reset synchronizer circuit. Its basic structure includes an asynchronous reset flip-flop and subsequent synchronization logic. When the reset signal is asynchronously active, the circuit immediately enters the reset state; when the reset is canceled, the release operation is synchronized with the clock signal edge. This effectively avoids metastability issues that may arise from the reset signal release timing being too close to the clock edge, ensuring the determinism of the circuit exiting the reset state.

[0034] At the physical design level of very large-scale chips (such as GPGPUs and high-performance central processing units (CPUs), multi-power domain and multi-clock domain designs have become essential architectures for managing chip power consumption and performance. Multi-power domain technology allows different functional modules or blocks to be placed under different supply voltages, achieving energy efficiency optimization through dynamic voltage and frequency adjustment strategies. Multi-clock domain technology allows different parts of the chip to be driven by independent clock sources to match their respective performance requirements and reduce the dynamic power consumption of the clock network. The division of power domains and clock domains is the foundation for modular power management and clock management.

[0035] However, it should be noted that although the aforementioned technologies have solved fundamental problems such as reset metastability, power consumption and performance modular optimization, they have not been able to effectively address the system-level power integrity challenges caused by reset operations, especially when massively parallel modules exit reset simultaneously.

[0036] Therefore, how to build a control scheme that can coordinate the management of reset timing and power integrity based on existing general technologies is a technical problem in this field that has not yet been fully solved.

[0037] To address the aforementioned problems, this invention provides a reset control method, apparatus, and chip for a general-purpose graphics processor. It should be noted that this embodiment is described using reset control of a very large-scale GPGPU as an example; however, it is also applicable to other chips, such as very large-scale CPUs / field-programmable gate arrays (FPGAs).

[0038] It should also be noted that, in this invention, "ultra-large scale" refers to a quantitative description of the integration and power consumption characteristics of high-performance computing chips such as GPGPUs. Specifically, it refers to a chip possessing at least one of the following characteristics: Transistor integration level: The total number of transistors integrated into the chip is no less than 5 billion.

[0039] Number of computing cores: The chip contains no less than 1,000 parallel processing cores (such as CUDA Core, Stream Processor, etc.).

[0040] Power consumption level: The chip's peak power consumption under typical workloads is no less than 150 watts.

[0041] Power domain complexity: The number of independently controllable power domains inside the chip is no less than 5.

[0042] The reset control scheme provided by this invention exhibits increasingly significant optimization effects as chip size, core count, and power consumption levels increase. When chips reach the aforementioned ultra-large scale standards, the transient current problem caused by traditional global reset strategies becomes extremely prominent. At this point, the power integrity improvement effect brought about by the grouped and phased reset method of this invention is most pronounced.

[0043] Figure 1 This is a flowchart illustrating a reset control method for a general-purpose graphics processor provided by the present invention. The method is applied to a reset management unit, which takes over the reset control.

[0044] like Figure 1 As shown, the method includes the following steps: S101, Receive global reset signal.

[0045] In this embodiment of the invention, the global reset signal is a trigger signal that initiates the reset initialization of the functional modules of the general-purpose graphics processor. This signal is typically a low-level active signal lasting at least 1000 reference clock cycles, with a voltage level consistent with the chip's input / output (I / O) voltage domain, such as 1.8V.

[0046] For example, the global reset signal can be a power-on reset signal issued by the power management chip, or a soft reset signal triggered by the system software by writing to a specific configuration register.

[0047] In the specific circuit implementation, the reset management unit includes a global reset detection module, which employs a two-stage synchronizer structure to avoid metastability. The first-stage flip-flop is powered by a normally open power supply domain that is always available to the chip, ensuring reliable detection of the reset signal under any power supply condition.

[0048] Specifically, taking the chip power-on scenario as an example, once the chip power supply is stable, the power management unit sends a low-level pulse lasting at least 1 microsecond to the reset management unit of the general-purpose graphics processor as a global reset signal, marking the start of the entire chip reset process. Upon detecting a valid reset edge, the module generates an internal synchronous reset enable signal, initiating the subsequent state machine.

[0049] Optionally, the global reset signal includes a cold reset signal, a hot reset signal, a warm reset signal, and a cool reset signal.

[0050] In one alternative implementation, after receiving a cold reset signal, the reset management unit takes over the reset operation for all downstream reset groups.

[0051] For example, a cold reset signal is typically triggered by a hardware event, such as powering the entire system back on or pressing a physical reset button. Its goal is to restore the chip to a known, absolutely clean initial state.

[0052] Specifically, when the reset management unit recognizes the valid edge of the cold reset signal, its internal state machine first completes its own initialization, and then activates its reset sequence generation logic to prepare to perform a comprehensive, phased reset operation on all downstream defined functional modules in groups.

[0053] The initialization process of the state machine includes: clearing all internal counters and pointers; loading the group delay register group to its default value; and configuring the sequence control register to full group reset mode.

[0054] In another optional implementation, after receiving a hot reset signal / warm reset signal / cool reset signal, the reset management unit does not perform a reset, but instead generates different reset sequences based on the triggering conditions and applies them to the reset groups that need to be reset.

[0055] These three reset types are distinguished by specific fields written to the reset type configuration register via the system bus, with different types corresponding to different reset range mapping tables.

[0056] For example, a hot reset may be triggered by the operating system crash recovery process, which aims to quickly restore most computing functions without power interruption, but may retain the current state of some debug modules or caches.

[0057] Specifically, in such scenarios, the reset management unit maintains its current operating state and distinguishes the reset type by parsing the code on the reset control bus or reading the internal mode register.

[0058] For example, when a hot reset is detected, a pre-configured hot reset sequence is indexed from the registers. This sequence may only include resets of the compute core array and part of the memory controller, while skipping modules such as the management controller and performance counters.

[0059] Thus, by distinguishing reset types and matching different reset sequences, the present invention achieves an optimized balance between reset granularity and system recovery speed, enabling both thorough initialization and rapid partial recovery.

[0060] S102. Based on at least one grouping strategy of the power domain, clock domain and reset domain of the general graphics processor, the functional modules are divided into multiple reset groups.

[0061] In one alternative implementation, functional modules that supply power to different power domains can be divided into different reset groups.

[0062] For example, a general-purpose graphics processor chip may include a high-performance analog power domain A (VDDA) that powers the general-purpose computing core and a low-power analog power domain B (VDDB) that powers the input / output interface.

[0063] Specifically, all computing cores belonging to the VDDA power domain are divided into one or more reset groups, while input / output modules belonging to the VDDB power domain are strictly divided into independent reset groups. The reset management unit maintains an independent reset control state machine for each power domain, and the two state machines communicate and coordinate through asynchronous first-in-first-out (FIFO).

[0064] In another alternative implementation, functional modules that are powered by the same power domain but whose clocks are supplied by different phase-locked loops can be divided into different reset groups.

[0065] For example, within the VDDA power domain, two independent phase-locked loops (PLLs) are deployed. PLL0 serves the computing core array that requires high frequencies, while PLL1 serves the memory controller unit that is insensitive to clock jitter. Each PLL has different output frequency ranges and lock-time characteristics.

[0066] Specifically, although the functional modules share the same power supply VDDA, due to their different clock sources, the reset management unit divides the functional modules in different clock domains into independent reset groups and assigns them different reset delay times. For example, the memory controller group can be reset first to ensure the memory interface is stable, and then the computing core group can be reset after a certain period of time to smooth the total current demand.

[0067] In another alternative implementation, a single phase-locked loop and its driving functional modules can be grouped into the same reset group.

[0068] For example, a reset group may contain a PLL and all cores clocked by the PLL. The PLL drives a separate clock network with a specific topology, and all functional modules driven by this clock network are physically constrained within a contiguous region.

[0069] Specifically, the clock source and its timing load are bound together as a logic reset unit. The reset management unit communicates with the phase-locked loop (PLL) through a dedicated PLL control interface. In the reset sequence, the unit first configures the PLL parameters through this interface, and then simultaneously resets the PLL and its driving functional modules.

[0070] The following is combined Figure 2 The reset grouping strategy of the present invention will be described by way of example.

[0071] like Figure 2 As shown, when the system issues a reset request, the reset management unit, as the core control hub, establishes control connections with multiple downstream reset groups through a dedicated reset control bus.

[0072] For example, the reset group adopts a hierarchical architecture: firstly, a first-level physical division is performed based on the power domain, where group 0 and group 1 are located in the VDDA power domain, and group 2 is located in the VDDB power domain, so as to realize the isolation management of different power supply areas.

[0073] The timing relationship between group 0 and group 1 is determined by the "inter-group reset delay (T)". grp0_grp1 The parameter is defined as “)”, which characterizes the reset operation delay between group 0 and group 1.

[0074] Furthermore, within the VDDA power domain, a two-level division is performed based on the clock source: Group 0 is clocked by PLL0 and contains multiple computing cores (Core N). The reset timing of PLL0 and the computing cores within the group is determined by the "PLL-to-module reset delay (T)". PLL0 The "ip)" control is used to coordinate the reset release timing between PLL0 and its driver module (group 0).

[0075] For example, group 1 is clocked by phase-locked loop (PLL1) and also contains multiple computing cores (core N). The reset timing of PLL1 and the computing cores within the group is communicated via the "PLL-to-module reset delay (T)". PLL1 The "ip)" control is used to coordinate the reset release timing between PLL1 and its drive module (group 1).

[0076] For example, group 2 under the VDDB power domain is driven by PLL2 and contains its corresponding multiple computing cores (CoreN). The reset timing of PLL2 and the computing cores within the group is achieved through the "phase-locked loop to module reset delay (T)". PLL2 The "ip)" control is used to coordinate the reset release timing between PLL2 and its driver module (group 2).

[0077] In this embodiment of the invention, each reset group uses a single phase-locked loop and its driven functional module set as the basic building block, forming a three-level control architecture of power domain-clock domain-functional module.

[0078] Thus, this invention, through its hierarchical and multi-dimensional grouping strategy, lays a solid physical and logical foundation for subsequent refined, phased reset implementation.

[0079] In another alternative implementation, functional modules that require differentiated reset timing but belong to the same clock domain or power domain can be divided into different reset groups.

[0080] For example, even within the same PLL-driven group, there may be modules with different sensitivity to reset timing, such as a regular computing core and an arbitration logic responsible for task scheduling.

[0081] Specifically, based on the reset domain partitioning strategy, large groups can be further subdivided into multiple reset domains. The reset management unit can configure different delay times for these reset domains.

[0082] For example, the computing core can be reset first, and the arbitration logic can be reset after it stabilizes, thus avoiding erroneous scheduling decisions during initialization. This fine-grained control is achieved through a reset domain enable bitmap register, with each bit controlling the reset enable of a subgroup.

[0083] Thus, by introducing the concept of a reset domain, this invention achieves finer-grained timing control within the same physical group, further optimizing the stability and reliability of the reset process.

[0084] S103. Based on multiple reset groups, generate a set of reset control signals with different timing sequences.

[0085] Optionally, the different timing sequences of the reset control signals can be determined by the delay time corresponding to each reset group. The delay time is a configurable parameter.

[0086] For example, different delay times can be assigned to each reset group, and these time values ​​are different from each other. For instance, the delay time register is 32 bits wide, the time unit is a reference clock cycle, and the delay value of each group is stored in a specific register address.

[0087] Specifically, the reset management unit contains a programmable delay line or counter. After the global reset signal takes effect, the unit starts its internal timing. The timer is implemented using a 32-bit incrementing counter. When the counter value matches the delay register value of a certain group, the matching logic generates a pulse with a single clock cycle width. This pulse, after synchronization, drives the reset signal generator of the corresponding group.

[0088] Thus, by artificially introducing and controlling the delay time, the present invention successfully transforms the instantaneous current peak into a current waveform with a lower amplitude that extends along the time axis, fundamentally alleviating the power supply voltage drop.

[0089] In this embodiment of the invention, the reset management unit has a built-in register. This register is used to store the delay time of each reset group.

[0090] For example, the register can be a set of memory-mapped registers accessed via an advanced peripheral bus (APB) or a similar low-bandwidth bus.

[0091] Specifically, the software driver can configure the delay time of each group by writing to specific register addresses. When the state machine of the reset management unit executes the reset sequence, it reads values ​​from these registers as preset values ​​for the delay timers.

[0092] Thus, by storing delay parameters in registers, this invention transforms the control of reset timing from fixed hardware logic into a flexible, software-defined strategy.

[0093] In some embodiments, the initial value of the delay time may be determined based on power integrity simulation or historical design experience.

[0094] For example, during the design phase before chip tape-out, electronic design automation (EDA) tools can be used to perform transient simulation of the power network at the moment of reset.

[0095] Specifically, the optimal reset time interval for each group is determined through iterative simulation. For example, simulation results show that when the reset release time interval for two groups is set to a specific number of clock cycles, the maximum voltage drop can be reduced to a level that meets design requirements. Therefore, the optimized initial delay time value is programmed into the register of the reset management unit.

[0096] In this way, the scientific determination of the initial delay value ensures that the chip has reliable reset performance after the first tape-out, reducing design risks.

[0097] S104. Apply the corresponding reset control signals to multiple reset groups in sequence according to different timing sequences.

[0098] In some embodiments, the reset management unit activates the reset signal lines leading to each reset group sequentially according to the timing generated in S103.

[0099] For example, during a specific clock cycle after the arrival of the global reset signal, the reset management unit pulls down the dedicated reset signal line of each group, maintains a configurable effective pulse width, and then releases it.

[0100] The effective level of the reset control signal is low, and the reset signal line of each group uses a dedicated wiring layer to ensure signal integrity.

[0101] Specifically, taking two consecutive reset groups as an example, the reset signal of the first group is valid at time T0, and all functional modules within it enter the reset state. At time T0 + pulse width, the signal becomes invalid, and the module begins initialization. At this time, the second group is still in the reset state, and its current consumption is extremely low. The reset signal of the second group becomes valid only at time T1 (T1 > T0 + pulse width), thus differentiating its current surge from that of the first group.

[0102] In the reset control method for a general-purpose graphics processor provided in this invention embodiment, the reset process is transformed from coarse to fine by having the reset management unit take over the reset control. Specifically, after receiving the global reset signal, a dedicated unit uniformly schedules the process, breaking the traditional decentralized mode where each module responds to the reset independently. Through a grouping strategy based on physical characteristics such as power domain and clock domain, the large circuit system is divided into logically clear reset units, effectively identifying module combinations that may cause current conflicts. Then, based on the grouping, reset signals with different timing are generated to reasonably distribute concentrated current surges in the time dimension, making the power network load tend to be smoother. Finally, through the phased operation of applying reset signals in sequence, effective peak shifting of current is achieved, and voltage drops are suppressed. This allows the chip to maintain the coordinated initialization of each module during the reset process while ensuring the stable power supply of the power network, thus improving the reset reliability and power integrity of large-scale integrated circuits.

[0103] Optionally, for the reset group containing the phase-locked loop (PLL) mentioned above, the PLL can be placed in the last reset position in its group or related group.

[0104] Among them, the relevant grouping refers to all subgroups that have a driving relationship with the original phase-locked loop after secondary grouping due to excessive size.

[0105] For example, a modular partitioning strategy can be used when performing secondary partitioning on an original large group containing a phase-locked loop and multiple computing cores driven by it.

[0106] In practice, assuming the original group contains one PLL and 64 computing cores, when the secondary grouping condition is met, based on the functional coupling degree and power distribution characteristics, the 64 cores are divided into four subgroups (SubGroup0-SubGroup3), each containing 16 cores. The PLL is treated as the fifth group, forming a hierarchical reset topology.

[0107] Thus, by employing the unconventional timing strategy of final reset of the phase-locked loop, this invention effectively decouples the reset currents of analog and digital circuits at the circuit level, thereby improving power supply integrity.

[0108] Optionally, if the reset group includes a phase-locked loop (PLL), the clock of the PLL can be switched from high-frequency mode to free-running mode before applying a reset control signal to the reset group.

[0109] In this embodiment of the invention, high-frequency mode refers to the phase-locked loop being in a normal locked state, outputting a stable high-frequency clock signal; free-running mode refers to the phase-locked loop having its feedback loop opened or bypassed, outputting a low-frequency, unlocked reference clock signal freely generated by its internal voltage-controlled oscillator.

[0110] For example, the high-frequency mode typically outputs a stable clock of 2.0 GHz, while the free-running mode outputs a reference clock of approximately 500 MHz.

[0111] For example, before resetting the group in which the phase-locked loop is located, the reset management unit configures the mode control register of the phase-locked loop through the standard configuration interface, switching it from the normal high-frequency locked mode to the low-frequency free-running mode.

[0112] Specifically, this switching operation is completed according to a precise timing plan before the group's reset signal takes effect. In practice, 200 clock cycles before the target group's planned reset time, the reset management unit writes a switching command to the PLL mode register via the APB bus, then waits 100 cycles to ensure the mode switch is complete before performing the subsequent reset operation.

[0113] Thus, by introducing a preparatory step for clock mode switching, the present invention further improves the robustness and security of the reset process at the system level.

[0114] Furthermore, in the case of dividing a single phase-locked loop and its driving functional modules into the same reset group, if the size of the reset group meets the secondary grouping condition, the functional modules can be divided into N reset groups, and the phase-locked loop can be placed in the last reset group.

[0115] Where N is an integer greater than 1.

[0116] In this embodiment of the invention, the secondary grouping condition can be that the area of ​​the reset group exceeds a preset area. The preset area can be a manually set value that can be flexibly adjusted according to the actual scenario.

[0117] For example, the preset area can be a threshold value for the total area of ​​modules that may cause a critical voltage drop when a single group is reset, determined through power integrity simulation. In practical design, the preset area is usually set to 5 million gates, which corresponds to a chip area of ​​approximately 2.5 mm² in a 7nm process.

[0118] For example, taking a preset area of ​​5 million doors as an example. If the total area of ​​a functional module group driven by a phase-locked loop is calculated to be 8 million doors, which exceeds the preset area, then the secondary grouping condition is triggered.

[0119] Specifically, based on the physical layout and data path characteristics of the functional modules, and by analyzing the data dependencies between modules, the 8 million gate circuit can be divided into three subgroups: subgroup A (3 million gates), subgroup B (2.5 million gates), and subgroup C (2.5 million gates). The reset sequence is configured as follows: first, each subgroup is reset sequentially, and finally, the phase-locked loop is reset.

[0120] In actual reset, in order to optimize current distribution, the reset time interval of each subgroup can be set to 50 clock cycles, that is: T subgroup A=0, T subgroup B=50, T subgroup C=100, TPLL=150.

[0121] Furthermore, the size of each subgroup can be uniformly divided, or non-uniformly divided according to the functional characteristics of the modules to achieve optimal current distribution. In engineering practice, when dividing non-uniformly, modules with higher power density are concentrated in smaller groups to enable more precise reset timing control.

[0122] Thus, by performing secondary division of large-scale groups and maintaining the final reset principle of the phase-locked loop, the present invention achieves effective control of power integrity at the chip architecture level under extreme scale.

[0123] Optionally, the aforementioned registers can be dynamically updated during the storage delay time.

[0124] In some embodiments, the delay time in the register can be dynamically updated via software configuration during general-purpose graphics processor operation.

[0125] For example, after the system software is loaded, the software can write a new set of delay parameters to the register of the reset management unit according to the current power supply status or performance mode of the system.

[0126] Specifically, when the system detects that it is in a specific working scenario, the driver can adjust the reset delay time of all groups based on the initial value to further optimize the reset performance.

[0127] For example, in mobile scenarios with limited heat dissipation, the latency of all groups is increased by 30%. This configuration is written via the system bus and takes effect immediately upon the next global reset.

[0128] In this embodiment of the application, the delay time for each reset group to be updated can be determined based on the test results of the power supply voltage drop under typical reset scenarios.

[0129] For example, during the testing phase after the chip is returned to the die, automated test equipment is used to perform multiple reset operations, while the voltage ripple of each power domain is measured through on-chip monitoring circuitry.

[0130] Specifically, after the test data analysis reveals a voltage anomaly under a specific reset timing, the test algorithm automatically adjusts the delay time of the relevant groups and retests to verify the optimization effect.

[0131] The specific process is as follows: First, test the voltage drop under the initial delay configuration. If it exceeds the threshold (e.g., 75mV), increase the delay time by 50%. If it still exceeds the threshold after retesting, continue to increase it by 25%. Iterate in this way until the optimal value is found. The optimal value is determined as the delay time to be updated and can be stored in non-volatile memory for subsequent use.

[0132] Thus, by combining measured data with a dynamic optimization mechanism, the present invention enables the reset timing to adapt to specific chip properties and system environment, achieving personalized optimal configuration.

[0133] Furthermore, upon receiving a global reset signal again, a reset control signal is generated based on the updated delay time.

[0134] For example, after updating the delay time of the groups, when the system triggers a new global reset, the reset management unit will read the new delay value from the register to generate a reset control signal. The signal generation process is as follows: global reset signal is valid → reset management unit state machine is reset → read the updated value from the delay parameter register → start the counter → generate reset signals for each group sequentially according to the new delay time, forming a complete control closed loop.

[0135] Specifically, during the reset process, the internal counter of the reset management unit uses the updated delay time to control the reset timing of each group, thereby applying optimized timing and achieving better power integrity.

[0136] For example, the original latency of a certain group was 100 cycles, which was adjusted to 150 cycles after optimization. In the optimized reset process, the reset of this group will occur in the 150th cycle after the global reset begins, achieving performance optimization through timing adjustments.

[0137] Thus, through a closed-loop configuration and application mechanism, this invention enables the results of software optimization and testing to be reflected in actual operation, thereby continuously improving system reliability.

[0138] The reset control device for a general-purpose graphics processor provided by the present invention will be described below. The reset control device for a general-purpose graphics processor described below can be referred to in correspondence with the reset control method for a general-purpose graphics processor described above.

[0139] Figure 3 This is a schematic diagram of a reset control device for a general-purpose graphics processor provided in an embodiment of the present invention. The reset control device for the general-purpose graphics processor includes: a receiving unit 301, a dividing unit 302, a generating unit 303, and a control unit 304.

[0140] The system comprises: a receiving unit 301 for receiving a global reset signal, which is a trigger signal for resetting and initializing the functional modules of the general-purpose graphics processor; a partitioning unit 302 for partitioning the functional modules into multiple reset groups according to at least one grouping strategy of the power domain, clock domain, and reset domain of the general-purpose graphics processor; a generating unit 303 for generating a set of reset control signals with different timing sequences based on the multiple reset groups; and a control unit 304 for sequentially applying the corresponding reset control signals to the multiple reset groups according to different timing sequences.

[0141] In some embodiments, the division unit 302 is specifically used to: divide functional modules powered by different power domains into different reset groups; divide functional modules powered by the same power domain but clocked by different phase-locked loops into different reset groups; and divide a single phase-locked loop and its driven functional modules into the same reset group.

[0142] In some embodiments, for a reset group containing a phase-locked loop, the division unit 302 is further configured to place the phase-locked loop at the last reset position in its group or related group.

[0143] In some embodiments, when a single phase-locked loop and its driven functional modules are assigned to the same reset group, the division unit 302 is further configured to: divide the functional modules into N reset groups when the size of the reset group satisfies the secondary grouping condition, and place the phase-locked loop in the last reset group, where N is an integer greater than 1.

[0144] In some embodiments, the division unit 302 is further configured to divide functional modules that require differentiated reset timing and belong to the same clock domain or power domain into different reset groups.

[0145] In some embodiments, the reset control device for a general-purpose graphics processor provided in this invention further includes an update unit, which is configured to dynamically update the delay time in the register through software configuration during the operation of the general-purpose graphics processor; the generation unit 303 is further configured to generate a reset control signal based on the updated delay time when a global reset signal is received again.

[0146] In some embodiments, the above-mentioned updating unit is specifically used to determine the delay time to be updated for each reset group based on the test results of the power supply voltage drop under typical reset scenarios.

[0147] In some embodiments, when the reset group includes a phase-locked loop, the control unit 304 is further configured to switch the clock of the phase-locked loop from a high-frequency mode to a free-running mode before applying a reset control signal to the reset group.

[0148] In the reset control device for a general-purpose graphics processor provided by this invention, a dedicated unit uniformly schedules the global reset signal, breaking the traditional decentralized mode where each module responds to reset independently. Through a grouping strategy based on physical characteristics such as power domain and clock domain, the massive circuit system is divided into logically clear reset units, effectively identifying module combinations that may cause current conflicts. Then, based on the grouping, reset signals with different timing sequences are generated, reasonably dispersing concentrated current surges over time, thus smoothing the power network load. Finally, through a phased operation of sequentially applying reset signals, effective peak shifting of current is achieved, suppressing voltage drops. This ensures that the chip maintains coordinated initialization of each module during the reset process while guaranteeing stable power supply to the power network, improving the reset reliability and power integrity of large-scale integrated circuits.

[0149] Figure 4 This is a schematic diagram of another general-purpose graphics processor (GPU) reset control device provided in an embodiment of the present invention. The GPU reset control device 400 includes a reset management unit 401. The reset management unit 401 is configured to execute the GPU reset control method provided by the methods described above. This method includes: receiving a global reset signal, which is a trigger signal that triggers the reset initialization of a functional module of the GPU; dividing the functional module into multiple reset groups according to at least one grouping strategy of the GPU's power domain, clock domain, and reset domain; generating a set of reset control signals with different timing sequences based on the multiple reset groups; and sequentially applying the corresponding reset control signals to the multiple reset groups according to the different timing sequences.

[0150] On the other hand, the present invention also provides a general-purpose graphics processor chip. Integrating the above-mentioned... Figure 4 The reset control device for the general-purpose graphics processor is shown.

[0151] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the reset control method for a general-purpose graphics processor provided in the above embodiments. The method includes: receiving a global reset signal, which is a trigger signal that triggers the reset initialization of a functional module of the general-purpose graphics processor; dividing the functional module into multiple reset groups according to at least one grouping strategy of the power domain, clock domain, and reset domain of the general-purpose graphics processor; generating a set of reset control signals with different timings based on the multiple reset groups; and applying the corresponding reset control signals to the multiple reset groups sequentially according to the different timings.

[0152] In another aspect, the present invention also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the reset control method for a general-purpose graphics processor provided in the above embodiments. The method includes: receiving a global reset signal, which is a trigger signal for triggering the reset initialization of a functional module of the general-purpose graphics processor; dividing the functional module into multiple reset groups according to at least one grouping strategy of the power domain, clock domain, and reset domain of the general-purpose graphics processor; generating a set of reset control signals with different timing sequences based on the multiple reset groups; and sequentially applying the corresponding reset control signals to the multiple reset groups according to the different timing sequences. The computer-readable storage medium can be either a non-transitory computer-readable storage medium or a transient computer-readable storage medium, and is not specifically limited here.

[0153] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0154] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as read-only memory (ROM) / random-access memory (RAM), magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reset control method of a general-purpose graphic processor, characterized by, The reset management unit takes over the reset control right and performs the following steps: receiving a global reset signal, the global reset signal being a trigger signal triggering functional module reset initialization of the general-purpose graphics processor; grouping the functional modules according to at least one grouping strategy in power domain, clock domain and reset domain of the general-purpose graphics processor, and dividing the functional modules into a plurality of reset groups; generating a set of reset control signals with different timings based on the plurality of reset groups; applying the corresponding reset control signal to the plurality of reset groups in turn according to the different timings.

2. The reset control method of a general-purpose graphics processor according to claim 1, wherein, The grouping strategy includes at least one of the following: functional modules powered by different power domains are divided into different reset groups; functional modules powered by the same power domain but supplied with clocks by different phase-locked loops are divided into different reset groups; a single phase-locked loop and the functional modules driven by the phase-locked loop are divided into the same reset group.

3. The reset control method of a general-purpose graphics processor according to claim 2, wherein For a reset group containing a phase-locked loop, the phase-locked loop is placed in the last reset position in the group or the related group.

4. The reset control method of a general-purpose graphics processor according to claim 3, wherein For the case where a single phase-locked loop and the functional modules driven by the phase-locked loop are divided into the same reset group, if the size of the reset group meets the secondary grouping condition, the functional modules are divided into N reset groups, and the phase-locked loop is placed in the last reset group, N being an integer greater than 1.

5. The reset control method of a general-purpose graphics processor according to claim 1, wherein The grouping strategy based on the reset domain includes: functional modules belonging to the same clock domain or power domain and requiring differentiated reset timing are divided into different reset groups.

6. The reset control method of a general-purpose graphics processor according to claim 1, wherein The different timings are determined by the delay time corresponding to each reset group; the delay time is a configurable parameter.

7. The reset control method of a general-purpose graphics processor according to claim 6, wherein The reset management unit is built-in with a register for storing the delay time of each reset group.

8. The reset control method of a general-purpose graphics processor according to claim 7, wherein, The initial value of the delay time is determined based on power integrity simulation or historical design experience.

9. The reset control method of a general-purpose graphics processor according to claim 7, wherein, The method further includes: updating the delay time in the register dynamically through software configuration during operation of the general-purpose graphics processor; based on the updated delay time, generating the reset control signal when the global reset signal is received again.

10. The reset control method of a general-purpose graphics processor according to claim 9, wherein, The method further includes: based on the test results of power supply voltage drop in typical reset scenarios, determining the delay time to be updated for each reset group.

11. The reset control method of a general-purpose graphics processor according to claim 1, wherein, The global reset signal includes a cold reset signal, and the reset management unit takes over the reset operation of all downstream reset groups after receiving the cold reset signal.

12. The reset control method of a general-purpose graphics processor according to claim 2, wherein, The method further includes: in the case where the reset group contains the phase-locked loop, the clock of the phase-locked loop is switched from high-frequency mode to free-running mode before the reset control signal is applied to the reset group.

13. A reset control apparatus for a general-purpose graphics processor, comprising: It includes: a reset management unit configured to perform the method of any one of claims 1 to 12.

14. A general-purpose graphics processor chip, comprising: integrating the reset control device of claim 13.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements an operation for configuring the register in the reset control device of claim 13, the operation including: writing the delay time configuration parameter of each reset group to the register of the reset management unit.

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