Random number generation circuit, chip, and electronic device

Abstract

Embodiments of the present application provide a random number generation circuit, a chip and an electronic device. In the random number generation circuit, the output terminal of the last stage logic gate in at least two logic gates of each group of composite logic gates is connected to the first input terminal of the corresponding first latch unit; the second input terminal of the first latch unit is used to receive a first clock signal, and the output terminal of the first latch unit is used to connect the first input terminal of the corresponding second latch unit; the second input terminal of the second latch unit is used to receive a second clock signal, and the output terminal of the second latch unit is connected to the input terminal of the corresponding logic gate; the first input terminal of the sampling unit is used to receive a third clock signal, the second input terminal of the sampling unit is connected to the output terminal of the corresponding second latch unit, and the output terminal of the sampling unit is used to output a random number result. The present scheme can provide different types of random number results through the same random number generation circuit, improve the circuit multiplexing rate, and meet the random number demand of different application scenarios.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a random number generation circuit, chip, and electronic device. Background Technology

[0002] With the rapid development of information technology, information exchange is becoming increasingly frequent and close, making information security an increasingly important issue. Among these, security chips, as a core component of information security systems, play an irreplaceable role in ensuring the security of information transmission and storage. Based on their core security requirements, security chips must integrate secure and reliable random number sources to support critical security operations such as key generation and data encryption.

[0003] Related technologies provide pseudo-random number generators and true random number generators based on the generation mechanism and characteristics of random numbers. Pseudo-random number generators are used to generate random sequences with mathematical regularity, while true random number generators are used to generate unpredictable and non-repeatable random sequences. However, the aforementioned pseudo-random number generators and true random number generators can only provide a single type of random sequence and cannot meet the random number requirements of different application scenarios. Summary of the Invention

[0004] This application provides a random number generation circuit, chip, and electronic device that solves the problem that related technologies can only provide a single type of random sequence and cannot adapt to the random number requirements of different application scenarios. It can provide different types of random number results through the same random number generation circuit, improve circuit reuse rate, and meet the random number requirements of different application scenarios.

[0005] In a first aspect, embodiments of this application provide a random number generation circuit, which includes: at least one set of composite logic gates of the same number and corresponding one-to-one, at least one first latch unit and at least one second latch unit, and at least one sampling unit; Each group of the composite logic gates includes at least two cascaded logic gates, and the output of the last logic gate in the cascaded at least two logic gates is connected to the first input of the corresponding first latch unit. The second input terminal of the first latch unit is used to receive the first clock signal output by the control unit, and the output terminal of the first latch unit is used to connect to the first input terminal of the corresponding second latch unit. The second input terminal of the second latch unit is used to receive the second clock signal output by the control unit, and the output terminal of the second latch unit is connected to the input terminal of the corresponding logic gate; The first input terminal of the sampling unit is used to receive the third clock signal output by the control unit, the second input terminal of the sampling unit is connected to the output terminal of the corresponding second latch unit, and the output terminal of the sampling unit is used to output the random number result.

[0006] Optionally, the random number generation circuit further includes at least one inverting unit, wherein the at least one second latching unit includes an inverting connection group; The output of each second latch unit in the reverse connection group is connected to the input of the corresponding logic gate through the corresponding inverting unit.

[0007] Optionally, when the control unit is in pseudo-random number function state, the first clock signal and the second clock signal are pulse modulation signals of the same frequency, and there is a preset phase difference between the first clock signal and the second clock signal.

[0008] Optionally, when the control unit is in pseudo-random number function state, the third clock signal has the same frequency as the second clock signal.

[0009] Optionally, when the control unit is in the true random number function state, the first clock signal and the second clock signal are the same first preset level signal, which is used to enable the first latch unit and the second latch unit to be in the conducting state.

[0010] Optionally, when the control unit is in true random number function mode, the frequency of the third clock signal is less than the signal output frequency of the second latch unit.

[0011] Optionally, the at least two logic gates include one or more of the following: AND gate, OR gate, NOT gate, NAND gate, NOR gate, XNOR gate, and XOR gate.

[0012] Optionally, when the control unit is in a function reset state, the first clock signal and the second clock signal are the same second preset level signal, and the input terminals of the at least two logic gates are used to receive the initial input signal output by the control unit.

[0013] Secondly, embodiments of this application also provide a chip, including the random number generation circuit described in any embodiment of this application.

[0014] Thirdly, embodiments of this application also provide an electronic device, including the chip described in any embodiment of this application.

[0015] In this embodiment, the random number generation circuit includes at least one set of composite logic gates, at least one first latch unit, and at least one second latch unit, as well as at least one sampling unit. Each set of composite logic gates includes at least two cascaded logic gates, with the output of the last stage of the cascaded logic gates connected to the first input of the corresponding first latch unit. The second input of the first latch unit receives a first clock signal output by the control unit, and its output is connected to the first input of the corresponding second latch unit. The second input of the second latch unit receives a second clock signal output by the control unit, and its output is connected to the input of the corresponding logic gate. The first input of the sampling unit receives a third clock signal output by the control unit, its second input is connected to the output of the corresponding second latch unit, and its output is used to output a random number result. This solution can provide different types of random number results through the same random number generation circuit, improving circuit reuse and meeting the random number requirements of different application scenarios. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a random number generation circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of another random number generation circuit provided in an embodiment of this application; Figure 3 A schematic diagram of a random number generation circuit that provides an 8-bit random number result is provided in an embodiment of this application; Figure 4 A schematic diagram of the first clock signal and the second clock signal when the control unit provided in the embodiment of this application is in the pseudo-random number function state; Figure 5 This is a schematic diagram illustrating the generation of a true random number result provided in an embodiment of this application. Detailed Implementation

[0017] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the scope of the embodiments. Furthermore, it should be noted that, for ease of description, only the parts relevant to the embodiments of this application are shown in the accompanying drawings, not the entire structure.

[0018] In the description of this application, unless otherwise expressly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] Figure 1 This is a schematic diagram of a random number generation circuit provided in an embodiment of this application. Figure 1 As shown, the random number generation circuit includes at least one set of composite logic gates 101, at least one first latch unit 102 and at least one second latch unit 103, and at least one sampling unit 104, all of the same number and corresponding one-to-one.

[0021] In this system, the number of composite logic gates 101, first latch units 102, and second latch units 103 are equal and correspond one-to-one. The number of sampling units 104 can be determined according to the required number of random bits. Each sampling unit 104 can sample random numbers from an equal number of second latch units 103. A set of composite logic gates 101, a first latch unit 102, a second latch unit 103, and a sampling unit 104 can constitute an independent random bit generation channel. Each channel can independently generate one random bit in each cycle, so N channels can generate N bits of random numbers in parallel, greatly improving the random number generation rate.

[0022] Specifically, each group of composite logic gates 101 includes at least two cascaded logic gates 1011, which include one or more of the following: AND gate, OR gate, NOT gate, NAND gate, NOR gate, XNOR gate, and XOR gate. Each logic gate 1011 can be set with an initial signal value, and after the random number generation circuit runs, the signal values ​​output by each second latch unit 103 are fed back to the input terminal of the corresponding logic gate 1011 to continuously update the input signal value of each logic gate 1011.

[0023] In one embodiment, the at least two logic gates 1011 can be cascaded one by one. In another embodiment, the at least two logic gates 1011 can be first grouped and connected in parallel, and then the groups can be cascaded. The output of the last logic gate 1011 in the at least two logic gates 1011 is connected to the first input of the corresponding first latch unit 102, for outputting the logic calculation result to the first latch unit 102. The first latch unit 102 and the second latch unit 103 can be level-sensitive sequential logic units, specifically equipped with a first input, a second input, and an output. The first input can be used to receive input signal values, the second input can be used to receive clock signals, and the output can be used to output signal values. Specifically, when the first latch unit 102 or the second latch unit 103 receives a valid level signal, it can acquire and latch the signal value received at the first input. When the first latch unit 102 or the second latch unit 103 receives an invalid level signal, it can keep the previously latched signal value unchanged, resulting in a stable output. It should be noted that different types of latch units require different valid level signals, which can be high or low, and this application does not limit this. The sampling unit can be an edge-triggered sequential logic unit, such as a D flip-flop or a JK flip-flop, specifically configured with a first input terminal, a second input terminal, and an output terminal. Its first input terminal can be used to receive the input signal value, the second input terminal is used to receive the clock signal, and the output terminal is used to output the signal value. Taking a D flip-flop as an example, when the sampling unit receives the valid edge signal of the clock signal, it can sample and latch the signal value received at the first input terminal, thereby providing a stable random bit as a random number result.

[0024] The second input terminal of the first latch unit 102 is used to receive a first clock signal output by the control unit 201. This first clock signal can be used to control when the first latch unit 102 acquires the output signal value of its corresponding composite logic gate 101. Taking a high-level sensitive type as an example, if the first clock signal is a pulse-modulated signal, when the pulse-modulated signal is high, the first latch unit 102 can acquire the output signal value of its corresponding composite logic gate 101; when the pulse-modulated signal is low, the first latch unit 102 retains the acquired output signal value. If the first clock signal is a high-level signal, the output signal value of the first latch unit 102 changes with the input signal value, equivalent to a continuously conducting state. Furthermore, the output terminal of the first latch unit 102 is used to connect to the first input terminal of the corresponding second latch unit 103, and is used to output the input signal value received from its corresponding logic gate 1011 to the second latch unit 103. The second clock signal can be used to control when the second latch unit 103 acquires the output signal value of its corresponding composite logic gate 101. The specific processes by which different second clock signals control the second latch unit 103 can be found in the description of the first latch unit 102, and will not be repeated here. The output terminal of the second latch unit 103 is connected to the input terminal of the corresponding logic gate 1011, which allows the circuit to form a feedback loop. That is, the random output of the current cycle can be used as the input of the composite logic gate 101 in the next cycle, increasing the complexity of the random number result. Furthermore, the signal value acquired or latched by the second latch unit 103 can also be the source of input data for the sampling unit 104.

[0025] Specifically, the first input terminal of the sampling unit 104 is used to receive the third clock signal output by the control unit 201. This third clock signal can be used to control when the sampling unit 104 acquires the output signal value of its corresponding second latch unit 103. Furthermore, the third clock signal can be set to different frequencies to meet different functional requirements, such as simultaneous frequency sampling or low-frequency sampling of high-frequency signals. The second input terminal of the sampling unit 104 is connected to the output terminal of the corresponding second latch unit 103 and is used to receive the stable output signal value of the second latch unit 103. It should be noted that the number of sampling units 104 can be specifically determined according to the required number of random bits. At least one sampling unit 104 can sample random number results from an equal number of second latch units 103.

[0026] Figure 2 This is a schematic diagram of another random number generation circuit provided in an embodiment of this application. Figure 2As shown, the random number generation circuit also includes at least one inverting unit 105, and the number of at least one second latching unit 103 is multiple. These multiple second latching units 103 include an inverting connection group, specifically a subset of the multiple second latching units 103 pre-selected from the multiple second latching units 103. The output of each second latching unit 103 in the inverting connection group is connected to the input of the corresponding logic gate 1011 through the corresponding inverting unit 105. It should be noted that the inverting unit is used to invert the input signal value; for example, it converts an input of "0" to "1" and an input of "1" to "0". The output signal value of each second latching unit 103 in the inverting connection group is inverted by the inverting unit 105 before being fed back to the corresponding logic gate 1011. It should be noted that the logic gate corresponding to each inverting unit 105 can be one of the aforementioned cascaded at least two logic gates, specifically determined by a pre-set feedback loop, which is not limited in this application. Therefore, by adding an inverting unit, the combination of signal values ​​of the input logic gate 1011 can be made more diverse, thereby increasing the richness of random number results and enhancing randomness.

[0027] In practical implementation, the control unit is responsible for managing the functional state of the random number generation circuit. Specifically, it coordinates the timing of the entire random number generation process by managing the frequency and phase relationships of the first, second, and third clock signals. Specifically, the control unit can be configured with three functional states: a function reset state, a pseudo-random number function state, and a true random number function state.

[0028] In one embodiment, if the control unit is in a functional reset state, it means that the random number generation circuit needs to be initialized or reconfigured to prepare for subsequent random number generation. The first clock signal and the second clock signal can be set as valid level signals to reset the first latch unit and the second latch unit. Taking the first latch unit and the second latch unit as high-level sensitive as an example, the second preset level signal can be a low-level signal. The input terminals of at least two logic gates are used to receive the initial input signal output by the control unit, which can be the preset starting input data of each logic gate. Thus, the random number generation circuit can be automatically initialized to a preset known state, providing a reliable starting state for subsequent random number generation.

[0029] Figure 3 This is a schematic diagram of a random number generation circuit that provides an 8-bit random number result, as provided in an embodiment of this application. Figure 3As shown, the random number generation circuit includes 9 sets of composite logic gates 101, 9 first latch units 102, 9 second latch units 103, 8 sampling units 104, and 1 inverting unit 105. The first set of composite logic gates 101 consists of cascaded OR gates and XOR gates, while the remaining 8 sets of composite logic gates 101 consist of cascaded OR gates and XOR gates. The output signal values ​​QC = {Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0} of the inverting unit 105 and the 8 second latch units 103 are set. During the operation of the random number generation circuit, the inverting unit 105 and the 8 second latch units 103 will feed back their respective output signal values ​​to the input terminals of the corresponding logic gates. In the first group of compound logic gates 101, the two input signals of the OR gate are Q0 and Q8, and the output signal value of the OR gate is passed to the XOR gate, whose other input signal value is Q7. Therefore, the output of the first group of compound logic gates 101 is Q8 = (Q0...) Q8) Q7. The two input signals of the OR gate in the second group of compound logic gates 101 are Q8 and Q7, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q6. Therefore, the output of this group of compound logic gates 101 is Q7 = (Q8)Q7Q8 ... Q7) Q6. The two input signals of the OR gate in the third group of compound logic gates 101 are Q7 and Q6, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q5. Therefore, the output of this group of compound logic gates 101 is Q6 = (Q7)Q6Q7Q6 ... Q6) Q5. The two input signals of the OR gate in the fourth group of compound logic gates 101 are Q6 and Q5, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q4. Therefore, the output of this group of compound logic gates 101 is Q5 = (Q6)Q4Q5Q6 ... Q5) Q4. The two input signals of the OR gate in the fifth group of compound logic gates 101 are Q5 and Q4, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q3. Therefore, the output of this group of compound logic gates 101 is Q4 = (Q5)Q4Q5Q4 ... Q4) Q3. The two input signals of the OR gate in the sixth group of compound logic gates 101 are Q4 and Q3, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q2. Therefore, the output of this group of compound logic gates 101 is Q3 = (Q4)Q2Q3Q4 ...4Q3Q4Q3Q4Q3Q4Q4Q3Q4Q3Q4Q4Q3Q4Q3Q4Q4Q3Q4Q3Q4Q4Q3Q4Q4Q3Q4Q4Q3Q4 Q3) Q2. The two input signals of the OR gate in the 7th group of compound logic gates 101 are Q3 and Q2, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q1. Therefore, the output of the compound logic gate 101 is Q2 = (Q3)Q2Q3Q2 ...3Q2Q2Q3Q2Q3Q2Q2Q3Q2Q Q2) Q1. The two input signals of the OR gate in the 8th group of compound logic gates 101 are Q2 and Q1, and the output signal of the OR gate is passed to the XOR gate, whose other input signal is Q0. Therefore, the output of this group of compound logic gates 101 is Q1 = (Q2)Q1Q2 ...2Q1Q2Q1Q2Q2Q1Q2Q2Q1Q2Q2Q1Q2Q2Q1Q2Q2Q2Q1Q2Q2Q2Q1Q2Q2Q2Q2Q1Q2Q2Q2Q2Q3Q2Q2Q2Q3Q2Q2Q3Q2Q2Q3Q2Q2Q3Q2Q2Q3Q2Q2Q3Q2Q3 Q1) Q0. The two input signals of the OR gate in the 9th group of compound logic gates 101 are Q1 and Q0, and the output signal value of the OR gate is passed to the XOR gate. The other input signal value of the XOR gate is Q8. Therefore, the output of the compound logic gate 101 is Q0 = (Q1...) Q0) Q8.

[0030] In one embodiment, if the control unit is in pseudo-random number function mode, the first clock signal and the second clock signal are pulse-modulated signals of the same frequency, and there is a preset phase difference between the first clock signal and the second clock signal, which enables the first latch unit and the second latch unit to be in a cross-conduction state. Therefore, the first clock signal and the second clock signal are the same in frequency, but their effective edges on the time axis are not aligned; the effective edge of the second clock signal is delayed by a fixed time difference relative to the effective edge of the first clock signal. Taking the first latch unit and the second latch unit as examples where both are high-level sensitive, this preset phase difference ensures that the first clock signal and the second clock signal will not be simultaneously high, nor will rising and falling edges exist simultaneously. This prevents the unknown of simultaneous effective edges from triggering the simultaneous conduction of the first latch unit and the second latch unit, ensuring that the output signal value of the first latch unit is stable before being transmitted to the second latch unit, thereby achieving a cross-conduction state between the two latch units, ensuring reliable data transmission, and generating a deterministic pseudo-random number sequence. Figure 4 This is a schematic diagram of the first and second clock signals when the control unit provided in the embodiment of this application is in pseudo-random number function state. Figure 4As shown, the first clock signal and the second clock signal are periodic square wave signals, and there is a fixed phase difference between them. This ensures that neither the first clock signal nor the second clock signal will be simultaneously high, nor will the rising and falling edges exist simultaneously. Taking the first and second latch units as high-level sensitive as an example, when the first clock signal is high, the first latch unit receives and latches data, while the second clock signal is low, and the second latch unit is in a holding state. When the second clock signal is high, the second latch unit receives and latches data, while the first clock signal is low, and the first latch unit is in a holding state. Figure 3 Taking the random number generation circuit shown as an example, if the control unit is in the function reset state, QC is initialized to h100. Then, when the control unit is in the pseudo-random number function state, combined with the aforementioned... Figure 3 According to the logical calculation relationship provided in the corresponding embodiment, the sequence of the output signal values ​​QC of one inverting unit 105 and eight second latching units 103 is as follows: Therefore, under the premise of reproducibility and efficient computation, it provides statistical characteristics close to real random numbers, meeting the pseudo-random number requirements of practical application scenarios.

[0031] Optionally, if the control unit is in pseudo-random number function mode, the third clock signal is pre-configured to have the same frequency as the second clock signal. This can keep the sampling unit and the second latch unit in time synchronization, stably collect the data change results of the second latch unit in each cycle, and also help ensure that each output bit corresponds to a clear internal state, so that the generated pseudo-random sequence is completely reproducible.

[0032] In one embodiment, if the control unit is in a true random number generation state, the first clock signal and the second clock signal are the same first preset level signal, used to enable the first latch unit and the second latch unit to be in the conducting state. Taking the first latch unit and the second latch unit as high-level sensitive as an example, both the first clock signal and the second clock signal are high-level signals, and the outputs of the first latch unit and the second latch unit follow the inputs, which is equivalent to the conducting state. Since a set of composite logic gates, a first latch unit, a second latch unit, and a sampling unit can constitute an independent random bit generation channel, the feedback loop structure of different random bit generation channels is the same. However, due to the unavoidable and slight gate delay differences in semiconductor manufacturing processes, the delay deviation of each feedback loop is unpredictable. Figure 5 This is a schematic diagram illustrating the generation of truly random numbers, provided as an embodiment of this application. Figure 5 As shown, in Figure 3Based on the random number generation circuit shown, before the controller 201 enters the true random number function state, the output signal value QC of one inverting unit 105 and eight second latching units 103 is {Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0} = {0, 0, 0, 1, 1, 1, 0, 0, 0}. After the controller 201 enters the true random number function state, the first latching unit 102 and the second latching unit 103 are in the conducting state. The output signal value of the one inverting unit 105 and the eight second latching units 103 will be immediately fed back to the aforementioned composite logic gates for calculation and output, so that the input signal value of the one inverting unit 105 and the eight second latching units 103 changes to {0, 0, 1, 0, 0, 1, 1, 0, 0}. The dotted circle in the figure shows the part where the signal value changes. Therefore, the original output signal value is different from the current output signal value, and the corresponding output signal value will be changed immediately. As a result, the nine feedback loops enter high-frequency self-oscillation. Due to manufacturing process deviations and delay uncertainties introduced by temperature / voltage fluctuations, the delay of each feedback loop is different. It is impossible to accurately predict the output signal values ​​of the one inverting unit 105 and the eight second latching units 103 at a certain moment, thereby achieving the purpose of outputting true random numbers, improving the unpredictability of random numbers, and meeting the real machine number requirements of actual application scenarios.

[0033] Optionally, if the control unit is in true random number function mode, the frequency of the third clock signal is pre-configured to be lower than the signal output frequency of the second latch unit, so that the sampling unit uses the low frequency signal to collect the high frequency signal for sampling, and the quality of random numbers is better improved by taking advantage of the instability of timing asynchrony.

[0034] This application also provides a chip that includes the random number generation circuit provided in any of the above embodiments. It is understood that this embodiment does not specifically limit other components on the chip. This chip has the same functions and beneficial effects as the random number generation circuit provided in any of the above embodiments.

[0035] This application also provides an electronic device including the chip described above. The chip in the electronic device has the same functions and beneficial effects as the random number generation circuit provided in any of the above embodiments.

[0036] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0037] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A random number generation circuit, characterized in that, It includes composite logic gates, first latch units, second latch units, sampling units, and control units. The number of multiple composite logic gates, multiple first latch units, and multiple second latch units are the same and correspond one-to-one. The number of multiple sampling units corresponds one-to-one with a portion of the second latch units. Each group of the composite logic gates includes at least two cascaded logic gates, and the output of the last logic gate in the cascaded at least two logic gates is connected to the first input of the corresponding first latch unit. The second input terminal of the first latch unit is used to receive the first clock signal output by the control unit, and the output terminal of the first latch unit is connected to the first input terminal of the corresponding second latch unit. The second input terminal of the second latch unit is used to receive the second clock signal output by the control unit, and the output terminal of the second latch unit is connected to the input terminal of a corresponding logic gate; The first input terminal of the sampling unit is used to receive the third clock signal output by the control unit, the second input terminal of the sampling unit is connected to the output terminal of the corresponding second latch unit, and the output terminal of the sampling unit is used to output the random number result; Wherein, when the control unit is in pseudo-random number function state, the first clock signal and the second clock signal are pulse modulation signals of the same frequency, and there is a preset phase difference between the first clock signal and the second clock signal, which is used to enable the first latch unit and the second latch unit not to be in the conducting state at the same time. When the control unit is in the true random number function state, the first clock signal and the second clock signal are the same first preset level signal, which is used to enable the first latch unit and the second latch unit to be in the conducting state at the same time.

2. The random number generation circuit according to claim 1, characterized in that, The number of the second latch units is multiple, and some of the second latch units in the multiple second latch units form a reverse connection group, and each second latch unit in the reverse connection group corresponds to an inverting unit; The output of each second latch unit in the reverse connection group is connected to the input of the corresponding logic gate through the corresponding inverting unit.

3. The random number generation circuit according to claim 1, characterized in that, When the control unit is in pseudo-random number function mode, the third clock signal has the same frequency as the second clock signal.

4. The random number generation circuit according to claim 1, characterized in that, When the control unit is in true random number function mode, the frequency of the third clock signal is less than the signal output frequency of the second latch unit.

5. The random number generation circuit according to claim 1, characterized in that, The at least two logic gates include one or more of the following: AND gate, OR gate, NOT gate, NAND gate, NOR gate, XNOR gate, and XOR gate.

6. The random number generation circuit according to claim 1, characterized in that, When the control unit is in a function reset state, the first clock signal and the second clock signal are the same second preset level signal, and the input terminals of the at least two logic gates are used to receive the initial input signal output by the control unit.

7. A chip, characterized in that, Includes the random number generation circuit as described in any one of claims 1-6.

8. An electronic device, characterized in that, Includes the chip described in claim 7.

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