An instruction scheduling system and method
By employing a single-instruction-issue architecture with an instruction management module and a polling module, combined with a unified decoding and scalar processing module, the problems of compiler design complexity and code bloat are solved, achieving efficient parallelization of hardware resources and improved compatibility.
Patent Information
- Application Number
- CN202511758904.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2045-11-27
AI Technical Summary
Existing compilers are complex in design, have large code size, and poor compatibility. In particular, in very long instruction word architectures, compilers rely on extreme optimization, which leads to code bloat and compatibility issues.
The instruction management module uniformly receives the set of instructions to be executed, and the instruction polling module issues single instructions. The same set of instruction decoding and scalar processing modules are used for decoding and calculation, and the neural processing module is combined for parallel computing, thus avoiding parallel instruction stuffing and hardware resource conflicts.
It reduces compiler design complexity, decreases code size, improves the parallel utilization of hardware resources, realizes a software compiler that does not rely on extreme optimization, and enhances compatibility.
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Figure CN121209964B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of data processing, and particularly relates to an instruction scheduling system and an instruction scheduling method. BACKGROUND
[0002] The multi-issue technology of instructions is one of the core means for modern processors to improve performance, which significantly improves the instruction-level parallelism by issuing and executing multiple instructions in one clock cycle. At present, the multi-issue technology is mainly implemented by using a very long instruction word (VLIW) architecture. However, the compiler design is complex, and when there are insufficient parallel instructions, the compiler has to fill the instruction packet with no operation (NOP), which leads to an increase in code size. SUMMARY
[0003] The present application provides an instruction scheduling system to at least solve the problems of extremely complex compiler design, large code size and poor compatibility in the prior art.
[0004] The present application provides an instruction scheduling system, comprising:
[0005] An instruction management module configured to receive a plurality of sets of to-be-executed instructions corresponding to a plurality of code blocks respectively;
[0006] An instruction polling module configured to poll and select each to-be-executed instruction in each set of to-be-executed instructions;
[0007] An instruction decoding module configured to decode the to-be-executed instruction selected by polling to obtain a decoding result;
[0008] A scalar processing module configured to perform scalar calculation according to the decoding result to obtain a scalar calculation result;
[0009] A neural processing module configured to call the scalar calculation result from the scalar processing module and perform parallel calculation according to the scalar calculation result.
[0010] The present application also provides an instruction scheduling method, comprising:
[0011] Receiving a plurality of sets of to-be-executed instructions corresponding to a plurality of code blocks respectively;
[0012] Polling and selecting each to-be-executed instruction in each set of to-be-executed instructions;
[0013] Decoding the to-be-executed instruction selected by polling to obtain a decoding result;
[0014] Performing scalar calculation according to the decoding result to obtain a scalar calculation result, and performing parallel calculation according to the scalar calculation result.
[0015] Through the present application, since the instruction management module is used to uniformly receive the to-be-executed instruction set corresponding to each code block, the parallel instruction filling problem is avoided, and then the code bloating and compatibility problems are avoided. The instruction polling module is set to adopt single instruction emission, and the instructions are polled from different code blocks. The polling selected to-be-executed instructions are decoded by the same instruction decoding module, and scalar calculation is performed according to the decoding result by the same scalar processing module. The instruction decoding module and the scalar processing module required for subsequent processing of each to-be-executed instruction all use the same set of hardware resources. Compared with the traditional way of setting the instruction decoding module and the scalar processing module corresponding to each code block, the present application realizes the parallel execution of instructions of different code blocks with less hardware cost. The scalar calculation result is called from the scalar processing module by the neural processing module for parallel calculation, which realizes the full parallelization of different hardware resources and does not depend on the extremely optimized software compiler. Therefore, the technical problems of extremely complex compiler design and large code size can be solved, and the technical effect of not depending on the extremely optimized software compiler and greatly reducing the code size is achieved. BRIEF DESCRIPTION OF DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0017] Figure 1 The structural block diagram of an instruction scheduling system provided by the embodiments of the present application is shown in the figure.
[0018] Figure 2 The structural block diagram of another instruction scheduling system provided by the embodiments of the present application is shown in the figure.
[0019] Figure 3 The implementation flowchart of an instruction scheduling method provided by the embodiments of the present application is shown in the figure.
[0020] The marks in the drawings are as follows:
[0021] 1-instruction management module, 2-instruction polling module, 3-instruction decoding module, 4-scalar processing module, 5-neural processing module, 41-execution control unit, 42-scalar calculation unit, 43-general register, 51-data dimension conversion unit, 52-matrix multiplication unit, 53-vector calculation unit. DETAILED DESCRIPTION
[0022] The multi-issue technology of instructions is one of the core means for modern processors to improve performance, which significantly improves the instruction-level parallelism by issuing and executing multiple instructions in one clock cycle. The implementation methods mainly include superscalar and very long instruction word (VLIW).
[0023] VLIW is an architecture that simplifies processor design by transferring the complexity of parallelism mining from hardware to compiler. It has advantages in hardware complexity, power consumption and potential parallelism, but also faces serious challenges such as difficult compiler design, code bloating and poor compatibility.
[0024] Superscalar relies on complex hardware circuits for dynamic scheduling and belongs to dynamic multi-issue. Hardware dynamically determines and issues multiple independent instructions in each clock cycle, and hardware needs complex logic such as dynamic scheduling, dependency detection and out-of-order execution, which is complex.
[0025] Current neural processing units (NPUs) mostly choose VLIW architecture, and the core reason is that it can efficiently mine the instruction-level parallelism widely existing in neural network computing with lower hardware complexity and power consumption. However, there are still the following problems similar to modern processors.
[0026] First, the compiler design is extremely complex, and the performance of NPU highly depends on the optimization ability of the compiler. It is an extremely difficult task to develop a VLIW compiler that can fully mine parallelism and efficiently schedule instructions. Second, there are code bloating and compatibility problems. When there is not enough parallelizable instructions, the compiler has to fill the instruction packet with no-operations, resulting in an increase in code size. In addition, the code optimized for a specific VLIW width usually cannot run directly on processors with different VLIW widths, and the binary compatibility is poor.
[0027] Therefore, the instruction scheduling system provided by the present application does not rely on an extremely optimized software compiler, greatly reduces the code size and improves the compatibility.
[0028] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.
[0029] It should be noted that in the description of the present application, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent in such processes, methods, articles or devices. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.
[0030] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below in conjunction with the drawings and specific embodiments.
[0031] Referring to Figure 1 , Figure 1 The structure block diagram of an instruction scheduling system provided by the embodiment of the present application can include:
[0032] An instruction management module 1 is configured to receive a plurality of code blocks respectively corresponding to a plurality of sets of to-be-executed instructions;
[0033] An instruction polling module 2 is configured to poll and select each to-be-executed instruction in each set of to-be-executed instructions;
[0034] An instruction decoding module 3 is configured to decode the to-be-executed instruction selected by polling to obtain a decoding result;
[0035] A scalar processing module 4 is configured to perform scalar calculation according to the decoding result to obtain a scalar calculation result;
[0036] A neural processing module 5 is configured to call the scalar calculation result from the scalar processing module 4 and perform parallel calculation according to the scalar calculation result.
[0037] The instruction scheduling system provided by the embodiment of the present application can include an instruction management module 1, an instruction polling module 2, an instruction decoding module 3, a scalar processing module 4, and a neural processing module 5. The instruction management module 1 is used to uniformly receive the to-be-executed instruction sets corresponding to each code block respectively, and the instruction polling module 2 is used to poll and select each to-be-executed instruction in each to-be-executed instruction set. The instruction decoding module 3 is used to decode the to-be-executed instruction selected by polling, to obtain a decoding result. The scalar processing module 4 is used to perform scalar calculation according to the decoding result, to obtain a scalar calculation result. The neural processing module 5 is used to call the scalar calculation result from the scalar processing module 4, and perform parallel calculation according to the scalar calculation result. By adopting single instruction emission, but using a polling mode for different code blocks, that is, emitting one instruction for each code block, and alternately executing the instructions of each code block, the parallel working of the hardware resources corresponding to each code block is realized. By adopting the single instruction emission architecture, the same set of logic is used for the subsequent instruction decoding module 3 and the scalar processing module 4, avoiding the conflict of the general register 43 and the arbitration logic, and greatly reducing the hardware implementation area.
[0038] According to the present application, the to-be-executed instruction sets corresponding to each code block are uniformly received by the instruction management module, thereby avoiding the parallel instruction filling problem, and further avoiding the code expansion and compatibility problem. The instruction polling module is arranged to emit one instruction, and the instructions are polled from different code blocks. The same instruction decoding module is used to decode the to-be-executed instruction selected by polling, and the same scalar processing module is used to perform scalar calculation according to the decoding result. The instruction decoding module and the scalar processing module required for subsequent processing of each to-be-executed instruction all use the same set of hardware resources. Compared with the conventional mode of arranging the instruction decoding module and the scalar processing module corresponding to each code block, the present application realizes the parallel execution of the instructions of different code blocks at a lower hardware cost. The neural processing module is used to call the scalar calculation result from the scalar processing module for parallel calculation, to realize the full parallelization of different hardware resources, and to avoid the dependence on the extremely optimized software compiler. Therefore, the technical problem of extremely complex compiler design and large code size can be solved, and the technical effect of not depending on the extremely optimized software compiler and greatly reducing the code size is achieved.
[0039] In one specific embodiment of the present application, the scalar processing module 4 includes:
[0040] The execution control unit 41 is configured to generate a scalar calculation instruction according to the decoding result, and send the scalar calculation instruction to the scalar calculation unit 42.
[0041] The scalar calculation unit 42 is configured to perform scalar calculation according to the scalar calculation instruction, to obtain a scalar calculation result, and write the scalar calculation result into the general register 43.
[0042] General purpose register 43 is used to store the results of scalar calculations.
[0043] See Figure 2 , Figure 2 This is a structural block diagram of another instruction scheduling system provided in an embodiment of this application. The scalar processing module 4 may include an execution control unit 41, a scalar calculation unit 42, and a general-purpose register 43. The execution control unit 41 generates a scalar calculation instruction based on the decoding result and sends the instruction to the scalar calculation unit 42. The scalar calculation unit 42 performs scalar calculations based on the instructions, obtains the result, and writes it into the general-purpose register 43, which stores the result. By using a unified execution control unit 41, scalar calculation unit 42, and general-purpose register 43 for scalar calculations, conflicts and arbitration logic in the general-purpose register 43 are avoided, significantly reducing the hardware implementation area.
[0044] In one specific embodiment of this application, the scalar calculation unit 42 is specifically used to identify the instruction type of the scalar calculation instruction; when the identified instruction type is a synchronization signal set instruction, a synchronization signal set result is generated according to the synchronization signal set instruction; and the synchronization signal set result is determined as the scalar calculation result.
[0045] After receiving a scalar calculation instruction, the scalar calculation unit 42 identifies the instruction type. When the identified instruction type is a synchronization signal set instruction, it generates a synchronization signal set result based on the synchronization signal set instruction and determines the synchronization signal set result as the scalar calculation result. By responding promptly to the synchronization signal set instruction and generating the synchronization signal set result, the orderly execution of the instructions to be executed corresponding to each data block with data dependencies is ensured.
[0046] In one specific embodiment of this application, the scalar calculation unit 42 is further configured to perform address calculation according to the address calculation instruction when the identified instruction type is an address calculation instruction, and obtain the address calculation result; and determine the address calculation result as the scalar calculation result.
[0047] When the scalar computation unit 42 identifies the instruction type as an address computation instruction, it performs address computation according to the instruction, obtains the address computation result, and identifies the address computation result as the scalar computation result. By accurately recording the address computation result, the subsequent neural processing module 5 can easily perform subsequent parallel computations based on the recorded address computation result.
[0048] In one specific embodiment of this application, the scalar calculation unit 42 is specifically used to perform address calculation based on the address offset and instruction length in the address calculation instruction.
[0049] The address calculation instruction includes an address offset corresponding to the instruction and an instruction length. The scalar calculation unit 42 performs address calculation according to the address offset and the instruction length in the address calculation instruction when performing address calculation. The address calculation efficiency is improved, and the accuracy of the address calculation result is improved by performing address calculation according to the address offset and the instruction length.
[0050] In an embodiment of the present application, the neural processing module 5 is specifically configured to perform parallel execution on the instruction sets corresponding to the code blocks according to the scalar calculation results corresponding to the code blocks when there is no dependency between the code blocks.
[0051] When there is no dependency between the code blocks, the neural processing module 5 performs parallel execution on the instruction sets corresponding to the code blocks according to the scalar calculation results corresponding to the code blocks. By performing parallel execution on the instruction sets corresponding to the code blocks without dependency, full use of hardware resources is achieved, and the execution efficiency of the instruction sets is improved.
[0052] In an embodiment of the present application, the neural processing module 5 is specifically configured to perform parallel execution on the instruction sets corresponding to the code blocks according to the scalar calculation results corresponding to the code blocks according to a preset number of loops.
[0053] The neural processing module 5 performs parallel execution on the instruction sets corresponding to the code blocks according to the scalar calculation results corresponding to the code blocks according to a preset number of loops. By performing parallel execution on the instruction sets corresponding to the code blocks according to a preset number of loops, accurate execution of the instruction sets corresponding to the code blocks is ensured.
[0054] In an embodiment of the present application, the neural processing module 5 is specifically configured to perform sequential execution on the instruction sets corresponding to the code blocks according to the synchronization signal setting results in the scalar calculation results when the code blocks include code blocks with dependency between the code blocks.
[0055] When the code blocks include code blocks with dependency between the code blocks, the neural processing module 5 performs sequential execution on the instruction sets corresponding to the code blocks according to the synchronization signal setting results in the scalar calculation results. By using the synchronization signal setting results, a synchronization mechanism is achieved, and the use of a complex compiler is avoided, and the synchronization mechanism is implemented at a low hardware cost.
[0056] Neural processing module 5 is specifically used to obtain the instruction patterns of the instruction sets to be executed for each code block, and to determine whether each code block has a data dependency relationship with other code blocks based on the instruction patterns of the instruction sets to be executed for each code block. By setting instruction patterns in the instruction sets to be executed, fast and accurate identification of whether there are data dependencies between code blocks is achieved.
[0057] In one specific embodiment of this application, the neural processing module 5 includes a data dimension transformation unit 51, a matrix multiplication unit 52, and a vector calculation unit 53;
[0058] The data dimension transformation unit 51 is used to perform parallel data dimension transformation based on the scalar calculation results;
[0059] Matrix multiplication unit 52 is used to perform parallel matrix multiplication calculations based on scalar calculation results;
[0060] Vector computation unit 53 is used to perform parallel computation of activation functions based on scalar computation results.
[0061] like Figure 2 As shown, the neural processing module 5 may include a data dimension transformation unit 51, a matrix multiplication unit 52, and a vector computation unit 53. The data dimension transformation unit 51 performs parallel data dimension transformation based on the scalar computation results; the matrix multiplication unit 52 performs parallel matrix multiplication based on the scalar computation results; and the vector computation unit 53 performs parallel activation function computation based on the scalar computation results. By utilizing the data dimension transformation unit 51, matrix multiplication unit 52, and vector computation unit 53 to perform various calculations in parallel, the utilization of hardware resources and the efficiency of parallel computing are significantly improved.
[0062] Embodiments of this application also provide an instruction scheduling method.
[0063] See Figure 3 , Figure 3 The following is a flowchart illustrating the implementation of an instruction scheduling method provided in this application embodiment. The method may include the following steps.
[0064] S301: Receives the set of instructions to be executed corresponding to each code block.
[0065] S302: Poll and select each instruction to be executed from each set of instructions to be executed.
[0066] S303: Decode the instruction to be executed selected by polling to obtain the decoding result.
[0067] S304: Perform scalar computation based on the decoding result to obtain the scalar computation result, and then perform parallel computation based on the scalar computation result.
[0068] Through the present application, since the instruction management module is used to uniformly receive the to-be-executed instruction set corresponding to each code block, the parallel instruction filling problem is avoided, and then the code bloating and compatibility problems are avoided. The instruction polling module is arranged to adopt single instruction emission to poll instructions from different code blocks. The to-be-executed instruction selected by polling is decoded by the same instruction decoding module, and scalar calculation is performed according to the decoding result by the same scalar processing module, and the instruction decoding module and the scalar processing module required for subsequent processing of each to-be-executed instruction all use the same set of hardware resources. Compared with the conventional mode of arranging the instruction decoding module and the scalar processing module corresponding to each code block, the present application realizes the parallel execution of instructions of different code blocks with less hardware cost. The neural processing module retrieves the scalar calculation result from the scalar processing module for parallel calculation, realizes the full parallelization of different hardware resources, and does not depend on an extremely optimized software compiler. Therefore, the technical problems of extremely complex compiler design and large code size can be solved, and the technical effects of not depending on an extremely optimized software compiler and greatly reducing the code size are achieved.
[0069] In an embodiment of the present application, the scalar calculation according to the decoding result to obtain the scalar calculation result can include the following steps:
[0070] Step one: generate a scalar calculation instruction according to the decoding result, and send the scalar calculation instruction to a scalar calculation unit;
[0071] Step two: perform scalar calculation according to the scalar calculation instruction by using the scalar calculation unit to obtain the scalar calculation result, and write the scalar calculation result into a general register to store the scalar calculation result by using the general register.
[0072] In an embodiment of the present application, the scalar calculation according to the decoding result to obtain the scalar calculation result can include the following steps:
[0073] Step one: perform instruction category identification on the scalar calculation instruction by using the scalar calculation unit;
[0074] Step two: when the identified instruction category is a synchronization signal setting instruction, generate a synchronization signal setting result according to the synchronization signal setting instruction;
[0075] Step three: determine the synchronization signal setting result as the scalar calculation result.
[0076] In an embodiment of the present application, the method can further include the following steps:
[0077] Step one: when the identified instruction category is an address calculation instruction, perform address calculation according to the address calculation instruction to obtain an address calculation result;
[0078] Step two: determine the address calculation result as the scalar calculation result.
[0079] In an embodiment of the present application, performing parallel calculation according to the scalar calculation result can include the following steps:
[0080] Performing address calculation according to the address offset in the address calculation instruction and the instruction length.
[0081] In an embodiment of the present application, performing parallel calculation according to the scalar calculation result can include the following steps:
[0082] When there is no dependency between each code block, performing parallel execution of the instruction set corresponding to each code block according to the scalar calculation result corresponding to each code block.
[0083] In an embodiment of the present application, performing parallel calculation according to the scalar calculation result can include the following steps:
[0084] When there is a code block with dependency between each code block, for each code block with dependency, performing sequential execution of the instruction set corresponding to each code block according to the synchronization signal setting result in the scalar calculation result.
[0085] In an embodiment of the present application, performing parallel calculation according to the scalar calculation result can include the following steps:
[0086] Step one: performing data dimension parallel transformation according to the scalar calculation result by using a data dimension transformation unit;
[0087] Step two: performing matrix multiplication parallel calculation according to the scalar calculation result by using a matrix multiplication unit;
[0088] Step three: performing activation function parallel calculation according to the scalar calculation result by using a vector calculation unit.
[0089] Taking two code blocks as an example, code block P1 and code block P2, if there is no data dependency, the instruction set corresponding to each code block is independently executed.
[0090] As shown in Table 1, Table 1 is an instruction execution table of two code blocks without data dependency.
[0091] Table 1
[0092]
[0093] The pseudo code is as follows:
[0094]
[0095] The value in the parentheses above represents the execution order.
[0096] The code block P1 and the code block P2 are executed in parallel, and the two code blocks can correspond to different hardware modules in an artificial intelligence (AI) accelerator, such as a matrix multiplication, a vector calculation unit, to fully exert the hardware parallel computing power.
[0097] Taking two code block behaviors as an example, the code block P1 and the code block P2 have data dependency.
[0098] As shown in Table 2, Table 2 is an instruction execution table of two code blocks with data dependency.
[0099] Table 2
[0100]
[0101] The synchronization signals P1S and P2S of the code block P1 and the code block P2 are added, and the setting of 1 respectively represents that the P1 and the P2 complete one execution loop, and the pseudo code is as follows:
[0102]
[0103] The value in the parentheses above represents the execution order.
[0104] In the pseudo code above, the number of times of the loop of the code block P1 and the code block P2 is set to 1, that is, the two code blocks only work once, and the code block P2 can only work after the code block P1 finishes working.
[0105] When the Wait instruction is executed, taking (Wait P1S ==1) as an example, if the current P1S value is 0, the code block P2 does not execute the accumulation of the address value of the instruction, and jumps to the label 8 of the code block P1 to continue execution, and then jumps to 8-7-9-7-10-7-11-7-12-7-13-7-14-7-15-7-16-7-17-18-……-27.
[0106] The features of the embodiments of the instruction scheduling method can be referred to the related descriptions of the embodiments of the instruction scheduling system, which will not be repeated here.
[0107] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is set to execute the steps in any of the above instruction scheduling method embodiments when running.
[0108] In an example embodiment, the computer readable storage medium described above can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.
[0109] Embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program, when executed by a processor, implements the steps in any of the instruction scheduling method embodiments described above.
[0110] Embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps in any of the instruction scheduling method embodiments described above.
[0111] The skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
[0112] The above describes in detail the instruction scheduling system and the instruction scheduling method provided by the present application. The principles and implementation modes of the present application are described by applying specific examples in this paper, and the above description of the examples is only applicable to help understand the method and core idea of the present application. It should be pointed out that, for the ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the present application.
Claims
1. An instruction scheduling system, characterized by, The method comprises the following steps: receiving a plurality of code blocks respectively corresponding to a plurality of sets of to-be-executed instructions; polling and selecting each to-be-executed instruction in each set of to-be-executed instructions; decoding the polling and selected to-be-executed instruction to obtain a decoding result; performing scalar calculation according to the decoding result to obtain a scalar calculation result; fetching the scalar calculation result from the scalar processing module (4) and performing parallel calculation according to the scalar calculation result; The scalar processing module (4) comprises: an execution control unit (41) configured to generate a scalar calculation instruction according to the decoding result and send the scalar calculation instruction to a scalar calculation unit (42); the scalar calculation unit (42) is configured to perform scalar calculation according to the scalar calculation instruction to obtain the scalar calculation result and write the scalar calculation result into a general register (43); the general register (43) is configured to store the scalar calculation result; the scalar calculation unit (42) is specifically configured to identify the instruction category of the scalar calculation instruction; when the identified instruction category is a synchronization signal setting instruction, a synchronization signal setting result is generated according to the synchronization signal setting instruction; and the synchronization signal setting result is determined as the scalar calculation result; the scalar calculation unit (42) is further configured to, when the identified instruction category is an address calculation instruction, perform address calculation according to the address calculation instruction to obtain an address calculation result; and the address calculation result is determined as the scalar calculation result; the neural processing module (5) is specifically configured to, when there is no dependency relationship between the code blocks, perform parallel execution of the sets of to-be-executed instructions corresponding to the code blocks according to the scalar calculation results corresponding to the code blocks respectively; the neural processing module (5) is specifically configured to, when there is a code block with a dependency relationship between the code blocks, perform sequential execution of the sets of to-be-executed instructions corresponding to the code blocks with the dependency relationship according to the synchronization signal setting result in the scalar calculation result.
2. The instruction scheduling system of claim 1, wherein, The scalar calculation unit (42) is specifically configured to perform address calculation according to the address offset and the instruction length in the address calculation instruction.
3. The instruction scheduling system of claim 1, wherein, The neural processing module (5) is specifically configured to perform parallel execution of the sets of to-be-executed instructions corresponding to the code blocks according to the scalar calculation results corresponding to the code blocks according to a preset number of cycles.
4. The instruction scheduling system of claim 1, wherein, The neural processing module (5) comprises a data dimension transformation unit (51), a matrix multiplication unit (52), and a vector calculation unit (53); the data dimension transformation unit (51) is configured to perform data dimension parallel transformation according to the scalar calculation result; the matrix multiplication unit (52) is configured to perform matrix multiplication parallel calculation according to the scalar calculation result; the vector calculation unit (53) is configured to perform activation function parallel calculation according to the scalar calculation result.
5. An instruction scheduling method, characterized by, The method comprises the following steps: receiving a plurality of code blocks respectively corresponding to a plurality of sets of to-be-executed instructions; Polling and selecting each to-be-executed instruction in each to-be-executed instruction set; Decoding the polling and selected to-be-executed instruction to obtain a decoding result; Performing scalar calculation according to the decoding result to obtain a scalar calculation result, and performing parallel calculation according to the scalar calculation result; The scalar calculation according to the decoding result to obtain the scalar calculation result comprises: generating a scalar calculation instruction according to the decoding result, and sending the scalar calculation instruction to a scalar calculation unit; performing scalar calculation according to the scalar calculation instruction by using the scalar calculation unit to obtain the scalar calculation result, and writing the scalar calculation result into a general register to store the scalar calculation result by using the general register; The scalar calculation according to the scalar calculation instruction by using the scalar calculation unit to obtain the scalar calculation result comprises: performing instruction category identification on the scalar calculation instruction by using the scalar calculation unit; when the identified instruction category is a synchronization signal setting instruction, generating a synchronization signal setting result according to the synchronization signal setting instruction; determining the synchronization signal setting result as the scalar calculation result; The method further comprises: when the identified instruction category is an address calculation instruction, performing address calculation according to the address calculation instruction to obtain an address calculation result; determining the address calculation result as the scalar calculation result; The parallel calculation according to the scalar calculation result comprises: when there is no dependency relationship between each code block, performing parallel execution on each to-be-executed instruction set corresponding to each code block according to the scalar calculation result corresponding to each code block, respectively; The parallel calculation according to the scalar calculation result comprises: when there is a code block with a dependency relationship between each code block, for each code block with a dependency relationship, performing sequential execution on each to-be-executed instruction set corresponding to each code block according to the synchronization signal setting result in the scalar calculation result.
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