Chip interconnection processing method and chip

Abstract

The embodiment of the invention provides a chip interconnection processing method and a chip, and the method comprises the steps: arranging at least two controllers in a part or all of a plurality of chips, and enabling the at least two controllers to be connected with an internal bus; according to the invention, the plurality of chips are interconnected based on the PCIe bus through the at least two controllers of part of or all of the chips, the problem of contradiction between the interconnection demand of the plurality of chips and the system complexity and cost in the related technology can be solved, the interconnection access among the plurality of PCIe chips can be realized without using PCIe Switch, the hardware structure is simpler, and the cost is lower. And the cost is lower.

Description

Technical Field

[0001] This application relates to the field of chips, and more specifically, to a chip interconnection processing method and a chip. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) is a high-performance serial computer bus standard that can be used to connect peripheral devices (such as graphics processors, network adapters, and storage devices) as well as to interconnect internal subsystems of a chip. Devices / chips that support interconnection via the PCIe bus interface can be called PCIe devices / chips.

[0003] When only two PCIe chips in a system need to be interconnected, they can be directly connected via a PCIe link. One is the root complex (RC), and the other is the end point (EP). When a system requires interconnection between multiple (more than two) PCIe chips, a PCIe switch chip is needed. The chips that need to be interconnected are connected to a multi-port PCIe switch via PCIe links, enabling access between any two chips. Figure 2 As shown, one is RC, and the others are EP. However, the addition of the PCIeSwitch chip in the system means that all communication links between chips in the system must pass through the PCIe Switch. This not only significantly increases the complexity of system communication link management and hardware / software design, but also increases the chip's power consumption and cost. Furthermore, the number of ports on a single PCIe Switch chip is limited, and the interconnection network structure is usually constrained to star or tree topologies, resulting in low flexibility in the system interconnection structure. In addition, the PCIeSwitch needs to be integrated into a single board, meaning some boards require a PCIeSwitch chip while others do not, leading to insufficient symmetry in the interconnection of boards.

[0004] No solution has yet been proposed to address the conflict between the interconnection requirements of multiple chips and the system complexity and cost in related technologies. Summary of the Invention

[0005] This application provides a chip interconnection processing method and chip to at least solve the problem of the contradiction between the interconnection requirements of multiple chips and system complexity and cost in related technologies.

[0006] According to one embodiment of this application, a chip interconnect processing method is provided, applied to a chip, the method comprising:

[0007] At least two controllers are disposed within some or all of the chips in a plurality of chips, wherein the at least two controllers are connected to an internal bus;

[0008] The plurality of chips are interconnected via at least two controllers of some or all of the chips, based on a high-speed peripheral component interconnect PCIe bus.

[0009] According to another embodiment of this application, a chip is provided, the chip comprising: at least two controllers, the at least two controllers being connected to an internal bus, wherein...

[0010] The at least two controllers are used to interconnect with controllers of other chips based on the high-speed peripheral component interconnect PCIe bus.

[0011] According to yet another embodiment of this application, a computer program product is also provided, including computer program instructions, wherein the computer program instructions cause a computer to implement the steps in any of the above method embodiments.

[0012] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0013] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0014] In this embodiment, at least two controllers are provided inside some or all of the multiple chips, wherein the at least two controllers are connected to an internal bus; the multiple chips are interconnected through the at least two controllers of some or all of the chips based on the high-speed peripheral component interconnection PCIe bus, which can solve the problem of the contradiction between the interconnection requirements of multiple chips and the system complexity and cost in related technologies. It can realize the interconnection access between multiple PCIe chips without the need to use a PCIe switch, and the hardware structure is simpler and the cost is lower. Attached Figure Description

[0015] Figure 1 This is a hardware structure block diagram of a computer device for the chip interconnect processing method according to an embodiment of this application;

[0016] Figure 2 This is a flowchart of a chip interconnection processing method according to an embodiment of this application;

[0017] Figure 3 This is a flowchart of a chip interconnect processing method according to an optional embodiment of this application;

[0018] Figure 4 This is a schematic diagram illustrating the interconnection of multiple chips via a PCIe switch in related technologies;

[0019] Figure 5 This is a schematic diagram of the software configuration according to an embodiment of this application;

[0020] Figure 6 This is a schematic diagram of a chain topology according to an embodiment of this application;

[0021] Figure 7 This is a schematic diagram of a star topology according to an embodiment of this application;

[0022] Figure 8 This is a schematic diagram of a ring topology according to an embodiment of this application. Detailed Implementation

[0023] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0025] The methods and embodiments provided in this application can be executed in a computer device or similar computing device. Taking running on a computer device as an example, Figure 1 This is a hardware structure block diagram of a computer device for the chip interconnect processing method according to an embodiment of this application, such as... Figure 1 As shown, a computer device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor (MCU) or programmable logic device, etc.) and a memory 104 for storing data are also shown. The computer device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer device described above. For example, the computer device may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0026] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the chip interconnect processing method in this embodiment. The processor 102 executes various functional applications and single-board matching by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to computer devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0027] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer equipment. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0028] This embodiment provides a chip interconnect processing method for the aforementioned computer device. Figure 2 This is a flowchart of a chip interconnection processing method according to an embodiment of this application, such as... Figure 2 As shown, this process, applied to a chip, includes the following steps:

[0029] Step S202: At least two controllers are provided inside some or all of the chips of the multiple chips, and the at least two controllers are connected to an internal bus.

[0030] Step S204: Interconnect multiple chips via at least two controllers of some or all chips, based on the high-speed peripheral component interconnect PCIe bus.

[0031] Through the above steps S202 to S204, the contradiction between the interconnection requirements of multiple chips and the system complexity and cost in related technologies can be resolved. Interconnection access between multiple PCIe chips can be achieved without using a PCIe switch, resulting in a simpler hardware structure and lower cost.

[0032] In this embodiment, at least two controllers include existing controllers and newly added controllers. Step S204 specifically includes: determining the interconnection topology of multiple chips based on system requirements; and interconnecting the controllers of two chips to be connected among the multiple chips via a PCIe bus according to the interconnection topology. During the interconnection process, the two chips to be connected are connected through the controllers. The interconnection topology in this embodiment includes at least one of the following: chain topology, star topology, and ring topology. In a chain topology, the chips at both ends of the topology do not need new controllers; that is, the existing controllers are retained. The chips at both ends only need to be connected to adjacent chips. Chips in the middle of the topology each include two controllers, each connected to the controller of an adjacent chip. In a star topology, chips at the top endpoints do not need new controllers, and chips at other ends include at least two controllers. In a ring topology, each chip includes two controllers.

[0033] Figure 3 This is a flowchart of a chip interconnect processing method according to an optional embodiment of this application, such as... Figure 3 As shown, the method further includes:

[0034] Step S302: Determine the type of controller for each chip relative to the bus;

[0035] Step S304: Configure the internal bus address range for the controller of each chip;

[0036] Step S306: Perform cross-chip address routing based on the controller's type relative to the bus and the internal bus address range.

[0037] In one embodiment, step S306 may specifically include: for each chip, if the controller is a master device relative to the bus type, initiating a first address access request; if the controller is a slave device relative to the bus type, receiving the first address access request, the first address access request carrying an address to be accessed; if the address to be accessed is within the corresponding internal bus address range, accessing the internal component according to the address to be accessed; if the address to be accessed is outside the corresponding internal bus address range, sending the first address access request to the controller of the connected next-level chip based on the PCIe bus.

[0038] In another embodiment, step S306 may specifically include: for each chip, if the controller is a master device relative to the bus type, initiating a first address access request; if the controller is a slave device relative to the bus type, receiving the first address access request, the first address access request carrying an address to be accessed; if the address to be accessed is within the corresponding internal bus address range, accessing the internal component according to the address to be accessed; if the address to be accessed is outside the corresponding internal bus address range, converting the address to be accessed into an external PCIe address based on a pre-set mapping relationship between internal bus addresses and external PCIe addresses, and sending a second address access request to the controller of the next-level chip based on the PCIe bus, the second address access request carrying the converted external PCIe address.

[0039] Furthermore, in the controller's pre-configured inbound or outbound registers, the address to be accessed is converted into an external PCIe address based on the above mapping relationship.

[0040] In this embodiment of the application, step S302 may specifically include:

[0041] S3021, Determine the controller's access requirements;

[0042] S3022 determines the type of controller relative to the bus based on the controller's access requirements.

[0043] Furthermore, S3022 may specifically include: when the controller's access requirement is to access the internal space of other chips via the PCIe bus, setting the controller type to a master device, which indicates support for initiating access to the bus; when the controller's access requirement is to support other chips accessing their local space, setting the controller type to a slave device, which indicates support for responding to access from other master devices on the bus; when the controller's access requirement is to access the internal space of other chips via the PCIe bus and supports other chips accessing their local space, setting the controller type to both a master and a slave device, i.e., both a master and a slave device.

[0044] In one embodiment, the method further includes: setting a root component RC-side chip for the PCIe link between every two connected chips; monitoring and collecting the status of the PCIe link through the RC-side chip, and reporting the link status to the next-level chip, specifically according to a pre-determined reporting cycle set by the main control chip; if the main control chip does not receive the link status reported by the next-level chip within a pre-set timeout period, determining that the PCIe link with the next-level chip has failed, and reporting the link status of the failed PCIe link to the next-level chip.

[0045] Based on the original PCIe interface of the chip in this application embodiment, additional PCIe interfaces for interconnection with other chips are added. These interfaces are interconnected internally within the chip via an internal bus through a PCIe controller. Utilizing address routing on the internal bus, access from the original interface can be routed either to an internal module of the chip or to the interconnected PCIe interface, reaching another chip. When other chips in the system also employ similar interface expansion and internal bus address routing methods, multiple PCIe chips can be interconnected. Interconnection and access between multiple PCIe chips can be achieved without using a PCIe switch, resulting in a simpler hardware structure and lower cost. Furthermore, in interconnecting similar single-board systems, there is no need to embed a PCIe switch chip on a single board, leading to better symmetry in the single-board hardware structure. The interconnection structure between multiple PCIe chips in this invention is more flexible, allowing for various topologies such as chain, ring, and star topologies, and access latency can be reduced through ring-like topologies. Based on internal bus address routing, this invention can fully utilize the 64-bit address space for unified addressing, making it more user-friendly for upper-layer software applications. It effectively resolves the contradiction between the interconnection requirements of multiple PCIe chips and system complexity and cost.

[0046] In the hardware portion of this application embodiment, one or more additional PCIe controllers are located inside the chip for interconnection with other chips via the PCIe bus. Figure 4 This is a schematic diagram illustrating the interconnection of multiple chips via a PCIe switch in related technologies, such as... Figure 4 As shown, each chip only needs one PCIe controller. Compared to the interconnection method using a PCIe switch, removing the PCIe switch requires one or more additional PCIe controllers inside the chip. These controllers connect to internal buses (such as AMBAAXI bus, MicroBlaze bus, etc.) inside the chip and to other chips externally. After removing the PCIe switch, the interconnections between chips can form various topologies, including but not limited to the following: chain structure, where each chip except chip 1 and chip N needs an additional PCIe controller 2; star structure, where chip 2 needs N-2 additional PCIe controllers; ring structure, where chips 1-N each need an additional PCIe controller 2 to connect to other chips; where N is the number of chips to be interconnected.

[0047] The software portion of this application embodiment includes the following three modules: Figure 5 This is a schematic diagram of the software configuration according to an embodiment of this application, such as... Figure 5 As shown, it includes:

[0048] The internal bus address space configuration module of the chip: The internal PCIe controller can be either a master or a slave relative to the internal bus. If the PCIe controller needs to be used as a slave device on the bus, it needs its address range in the internal bus.

[0049] The PCIe controller address mapping configuration module configures the inbound and outbound registers of each chip's PCIe controller for inbound and outbound address mapping, completing the address translation between the chip's internal bus domain and the external PCIe bus domain.

[0050] Link Management Module: Used to manage link status, including bandwidth management, error detection, and reporting. First, the system master control chip is set as the management master; then, each RC and EP pair is managed independently as a standard point-to-point PCIe link (e.g., using standard PCIe Link Management Technology (LTM)); finally, the CPU of each chip reports to the CPU of the next-level RC via interrupts, until the report reaches the first chip. The first chip then presents the global link status to the user.

[0051] The multi-chip interconnection in this application embodiment may include the following steps:

[0052] Step 1: Determine the hardware interconnection relationships between chips. Based on system requirements, select a suitable chip interconnection topology, including but not limited to chain topology, star topology, ring topology, and combinations thereof. To meet the connectivity requirements, the corresponding chips need additional PCIe controllers and PCIe buses. Simultaneously, configure RC / EP relationships for each PCIe link according to system interconnection requirements.

[0053] Step 2: Determine the type of each PCIe controller within each chip relative to the internal bus. This can be master (the master device initiates access to the bus), slave (a slave device responds to access from other master devices on the bus), or both. If this chip needs to access the internal space of other chips via the PCIe bus, it needs to be configured as master type; if this chip supports other chips accessing its local space, it needs to be configured as slave type.

[0054] Step 3: Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip. For slave types, allocate a bus address space range for them. When a master inside the chip initiates an address access to the bus, if the address falls within the bus address range of the PCIe controller, then that PCIe controller will respond. For master types, it is not necessary to allocate an internal bus address range.

[0055] Step 4: Initialize the inbound / outbound address mapping configuration module, configure the inbound and outbound registers for each PCIe controller of each chip, and determine the mapping relationship between the chip's internal bus address space and the external PCIe address space.

[0056] Through steps 3 and 4, after the chips are interconnected via the PCIe bus, cross-chip address routing can be achieved by converting the internal bus address space of one or more chips to the PCIe bus domain address space, thus enabling the chips to access each other.

[0057] Step 5: Initialize the link management module. The main control chip is designated as the link management master. Then, the RC side of each PCIe link is responsible for completing the management initialization of its own link and starting to monitor the link status.

[0058] Step 6: Initiate Address Access. When a module within a chip (such as a CPU core) initiates an address access, the bus routes the access based on the address. If the address falls within the bus address range of the PCIe controller, the access is routed to the PCIe controller. After outbound address translation by the local PCIe controller, the address is converted into a PCIe bus address and sent to the PCIe bus. Upon reaching the peer chip, the peer chip receives the address and converts it to its own internal bus address via inbound address translation, then routes it via its own bus. If the address falls within the address range of a module within the chip, that module is accessed; if the address falls within the address range of another PCIe controller, the next PCI link is routed. This process is repeated, and different addresses are ultimately routed to different internal modules within the chip.

[0059] Step 7, Link Status Management Reporting. The main control chip is configured with a link reporting period T0 and a timeout period T1. The RC-side chip of each PCIe link is responsible for monitoring and collecting the status of this PCIe link and reporting it to the next higher level periodically according to the configured T0 time. If a link times out due to a fault, the fault status of this link needs to be reported in the report.

[0060] The embodiments of this application are described in detail below with examples.

[0061] Figure 6 This is a schematic diagram of a chain topology according to an embodiment of this application, such as... Figure 6 As shown, N is 4, meaning 4 chips are interconnected. Chip 1 needs to access the internal space of all other chips. Each chip's internal address space is 2GB, so unifying the addressing of the 4 chips requires 8GB of address space. The specific steps include the following:

[0062] 1. Determine the hardware interconnection relationships between the chips. Based on system requirements, select a suitable chain-like chip interconnection topology. To accommodate the interconnection, PCIe controller 2 needs to be added between chip 2 and chip 3. The chain-like connection relationship is as follows:

[0063] Chip 1 PCIe Controller 1 (RC) --- Chip 2 PCIe Controller 1 (EP);

[0064] Chip 2 PCIe Controller 2 (RC) --- Chip 3 PCIe Controller 1 (EP);

[0065] Chip 3 PCIe Controller 2 (RC) --- Chip 4 PCIe Controller 1 (EP);

[0066] 2. Determine the type of each PCIe controller relative to the bus within each chip. Since only chip 1 needs to access the internal space of other chips, the types of the PCIe controllers relative to the bus within each chip are as follows:

[0067] Chip 1 PCIe controller 1: s lave;

[0068] Chip 2 PCIe controller 1: master;

[0069] Chip 2 PCIe controller 2: s lave;

[0070] Chip 3PCIe controller 1: master;

[0071] Chip 3PCIe controller 2: s lave;

[0072] Chip 4 PCIe controller 1: master.

[0073] 3. Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip as follows:

[0074] Chip 1 PCIe Controller 1: 2G-8G;

[0075] Chip 2 PCIe controller 2: 2G-6G;

[0076] Chip 3PCIe controller 2: 2G-4G.

[0077] 4. Initialize the inbound / outbound address mapping configuration module to configure the inbound and outbound registers for each PCIe controller of each chip, and determine the mapping relationship between the chip's internal bus address space and the external PCIe address space.

[0078] RC side: no mapping, address pass-through; EP side: mapping, address translation.

[0079] Chip 1 PCIe controller 1: inbound / outbound remains unchanged;

[0080] Chip 2 PCIe controller 1: inboundaddr2->addr2-2G; outbound remains unchanged;

[0081] Chip 2 PCIe controller 2: inbound / outbound remains unchanged;

[0082] Chip 3PCIe controller 1: inbound addr3->addr3-2G; outbound remains unchanged;

[0083] Chip 3PCIe controller 2: inbound / outbound remains unchanged;

[0084] Chip 4 PCIe controller 1: inbound addr4->addr4-2G; outbound remains unchanged.

[0085] 5. Initialize the link management module. Determine chip 1 as the main control chip, and then the RC side of each PCIe link is responsible for completing the management initialization of this link and starting to monitor the status of this link.

[0086] 6. Initiate address access:

[0087] When the CPU of chip 1 initiates an address addr = 0G-2G, the bus routes to the internal module and accesses the internal address space of chip 1;

[0088] When the CPU of chip 1 initiates an access at address addr = 2G-4G, the bus routes to PCIe controller 1. After outbound address mapping, addr1 = addr and is sent to chip 2. Chip 2's PCIe controller 1 receives this access, and after inbound address mapping, addr2 = addr1-2G = addr-2G = 0G-2G, and is sent to chip 2's internal bus. Chip 2's internal bus then routes the access to its internal modules. When the CPU of chip 1 initiates an access at address addr = 2G-4G, it accesses chip 2's internal address space.

[0089] When the CPU of chip 1 initiates an address `addr = 4G-6G`, similarly, the address sent to the internal bus of chip 2 is `add2 = addr - 2G = 2G-4G`. The internal bus of chip 2 routes this address to PCIe controller 2. After address mapping between the outbound address of PCIe controller 2 and the inbound address of PCIe controller 1 of chip 3, the address sent to the internal bus of chip 3 is `add3 = addr2 - 2G = 0G-2G`, which is then routed to the internal module of this chip. When the CPU of chip 1 initiates an address `addr = 4G-6G`, it accesses the internal address space of chip 3.

[0090] When the CPU of chip 1 initiates an address `addr = 6G-8G`, similarly, the address sent to the internal bus of chip 3 is `add3 = addr - 4G = 2G-4G`. The internal bus of chip 3 routes this address to PCIe controller 2. After address mapping between the outbound address of PCIe controller 2 (chip 3) and the inbound address of PCIe controller 1 (chip 4), the address sent to the internal bus of chip 4 is `add4 = addr3 - 2G = 0G-2G`, which is then routed to the internal module of this chip. When the CPU of chip 1 initiates an address `addr = 6G-8G`, it accesses the internal address space of chip 4.

[0091] The address issued by the CPU of chip 1 will access different chips:

[0092] 0G-2G: Internal address space of chip 1;

[0093] 2G-4G: Internal address space of chip 2;

[0094] 4G-6G: Internal address space of chip 3;

[0095] 6G-8G: Internal address space of chip 4.

[0096] 7. Link Status Management and Reporting. Chip 1 is configured with a link reporting period T0 and a timeout period T1. The RC-side chip of each PCIe link is responsible for monitoring and collecting the status of this PCIe link and reporting it to the next higher level periodically according to the configured T0 time. If a link fails, such as the link between chip 2 and chip 3, chip 2 will mark it as faulty if it does not receive the status report from chip 3 within the timeout period. This status will then be sent to chip 1 through the PCIe link between chip 1 and chip 2 (e.g., an interrupt). Thus, the software on the CPU of chip 1 can know that the link between chip 1 and chip 2 is normal, but the link between chip 2 and chip 3 has failed. This information will then be further reported to the upper-layer software or presented to the user.

[0097] Figure 7 This is a schematic diagram of a star topology according to an embodiment of this application, such as... Figure 7As shown, N is 4, meaning 4 chips are interconnected, and each chip needs to access the internal space of all other chips. The address space sizes of chips 1-4 are 1 / 2 / 3 / 4G respectively, and unified addressing of the 4 chips requires 10G of address space. The specific steps include the following:

[0098] 1. Determine the hardware interconnection relationships between the chips. Based on system requirements, select a suitable star topology for the chip interconnection. To meet the connectivity requirements, chip 2 needs to be connected to chip 3 via PCIe controller 2, and chip 4 needs to be connected via PCIe controller 3.

[0099] 2. Determine the type of each PCIe controller within each chip relative to the bus. Since all chips need to access the internal space of other chips, the type of each chip's internal PCIe controller relative to the bus is both master and slave.

[0100] 3. Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip as follows:

[0101] Chip 1 PCIe Controller 1: 1G-10G;

[0102] Chip 2 PCIe controller 1: 0G-1G;

[0103] Chip 2 PCIe controller 2: 3G-6G;

[0104] Chip 2 PCIe controller 3: 6G-10G;

[0105] Chip 3PCIe controller 1: 0G-3G, 6G-10G;

[0106] Chip 4PCIe controller 1: 0G-6G.

[0107] 4. Initialize the inbound / outbound address mapping configuration module to configure the inbound and outbound registers for each PCIe controller of each chip, and determine the mapping relationship between the chip's internal bus address space and the external PCIe address space.

[0108] All PCIe links on the RC and EP sides do not perform address mapping for inbound / outbound, and all are transparently transmitted.

[0109] 5. Initialize the link management module. The main control chip is identified as chip 1. Then, the RC side of each PCIe link is responsible for completing the management initialization of this link and starting to monitor the link status.

[0110] 6. Initiate address access:

[0111] When the CPU of chip 1 initiates an address addr = 0G-1G, the bus is routed to the internal module, accessing the internal address space of chip 1; when the initiating address addr = 1G-3G, the bus is routed to PCIe controller 1 and transparently passed to the bus address space of chip 2, and the bus of chip 2 is routed to the internal module; when the initiating address addr = 3G-6G, the bus is routed to PCIe controller 1 and transparently passed to the bus address space of chip 2, the bus of chip 2 is routed to PCIe controller 2 and transparently passed to the bus address space of chip 3, and the bus of chip 3 is routed to the internal module; when the initiating address addr = 6G-10G, the bus is routed to PCIe controller 1 and transparently passed to the bus address space of chip 2, the bus of chip 2 is routed to PCIe controller 3 and transparently passed to the bus address space of chip 4, and the bus of chip 4 is routed to the internal module.

[0112] The CPU address routing process for chips 2, 3, and 4 is similar. The addresses issued by the CPUs of all chips will access different chips:

[0113] 0G-1G: Internal address space of chip 1;

[0114] 1G-3G: Internal address space of chip 2;

[0115] 4G-6G: Internal address space of chip 3;

[0116] 6G-10G: Internal address space of chip 4.

[0117] 7. Link Status Management and Reporting. Chip 1 is configured with a link reporting period T0 and a timeout period T1. The RC-side chip of each PCIe link is responsible for monitoring and collecting the status of this PCIe link and reporting it to the next higher level periodically according to the configured T0 time. If a link fails, such as the link between chip 2 and chip 3, chip 2 will mark it as faulty if it does not receive the status report from chip 3 within the timeout period. This status will then be sent to chip 1 through the PCIe link between chip 1 and chip 2 (e.g., an interrupt). Thus, the software on the CPU of chip 1 can know that the link between chip 1 and chip 2 is normal, but the link between chip 2 and chip 3 has failed. This information will then be further reported to the upper-layer software or presented to the user.

[0118] Figure 8 This is a schematic diagram of a ring topology according to an embodiment of this application, as shown below. Figure 8As shown, N is 4, meaning 4 chips are interconnected, and each chip needs to access the internal space of all other chips. The address space of chips 1-4 is 2GB each, and unified addressing of the 4 chips requires 8GB of address space. Since the address routing in a ring topology has two paths, clockwise and counterclockwise, each path occupies half of the address space, the upper-layer software decides which access path to take based on the address. For example, if chip 1 accesses the address space of chip 2, the counterclockwise address route is shorter than the clockwise path, so the counterclockwise path can be chosen; conversely, when chip 1 accesses the address space of chip 4, the clockwise path is shorter. The specific steps include the following:

[0119] 1. Determine the hardware interconnection relationships between the chips. Based on system requirements, select a suitable ring topology for the chip interconnection. To meet the connectivity requirements, chips 1-4 all need to have a PCIe controller 2 added to connect to other chips.

[0120] 2. Determine the type of each PCIe controller within each chip relative to the bus. Since all chips need to access the internal space of other chips, the type of each chip's internal PCIe controller relative to the bus is both master and slave.

[0121] 3. Initialize the bus address space configuration module to configure the internal bus address range (BAR space) for each PCIe controller of each chip as follows:

[0122] Chip 1 PCIe Controller 1: 5G-8G;

[0123] Chip 1 PCIe controller 2: 1G-4G;

[0124] Chip 2 PCIe controller 1: 4G-5G, 6G-8G;

[0125] Chip 2 PCIe controller 2: 0G-1G, 2G-4G;

[0126] Chip 3PCIe controller 1: 4G-6G, 7G-8G;

[0127] Chip 3PCIe controller 2: 0G-2G, 3G-4G;

[0128] Chip 4PCIe controller 1: 4G-7G;

[0129] Chip 4 PCIe controller 2: 0G-3G.

[0130] 4. Initialize the inbound / outbound address mapping configuration module to configure the inbound and outbound registers for each PCIe controller of each chip, and determine the mapping relationship between the chip's internal bus address space and the external PCIe address space.

[0131] All PCIe links on the RC and EP sides do not perform address mapping for inbound / outbound, and all are transparently transmitted.

[0132] 5. Initialize the link management module. The main control chip is identified as chip 1. Then, the RC side of each PCIe link is responsible for completing the management initialization of this link and starting to monitor the link status.

[0133] 6. Initiate address access:

[0134] When the CPU of chip 1 initiates an address addr = 0G-1G, the bus routes to the internal module and accesses the internal address space of chip 1. When the initiating address addr = 1G-2G, the bus routes to PCIe controller 2 and passes through to the bus address space of chip 2. Chip 2 then routes the bus to the internal module. When the initiating address addr = 2G-3G, the bus routes to PCIe controller 2 and passes through to the bus address space of chip 2. Chip 2 then routes the bus to PCIe controller 2 and passes through to the bus address space of chip 3. Chip 3 then routes the bus to the internal module. When the initiating address addr = 3G-4G, the bus routes to PCIe controller 2 and passes through to the bus address space of chip 2. Chip 2 then routes the bus to PCIe controller 2 and passes through to the bus address space of chip 4. Chip 4 then routes the bus to the internal module. In this case, the address routing is a counter-clockwise path.

[0135] When the CPU of chip 1 initiates an address addr of 4G-5G, the bus routes to the internal module, accessing the internal address space of chip 1. When the initiating address addr of 5G-6G, the bus routes to PCIe controller 1 and passes through to the bus address space of chip 4. Chip 4's bus routes to PCIe controller 1 and passes through to the bus address space of chip 3. Chip 3's bus routes to PCIe controller 1 and passes through to the bus address space of chip 2. Chip 2's bus routes to the internal module. When the initiating address addr of 6G-7G, the bus routes to PCIe controller 1 and passes through to the bus address space of chip 4. Chip 4's bus routes to PCIe controller 1 and passes through to the bus address space of chip 3. Chip 3's bus routes to the internal module. When the initiating address addr of 7G-8G, the bus routes to PCIe controller 1 and passes through to the bus address space of chip 4. Chip 4's bus routes to the internal module. At this time, the address routing is a clockwise path.

[0136] The CPU address routing process for chips 2, 3, and 4 is similar. The addresses issued by the CPUs of all chips will access different chips:

[0137] 0G-1G / 4G-5G: Internal address space of chip 1;

[0138] 1G-2G / 5G-6G: Internal address space of chip 2;

[0139] 2G-3G / 6G-7G: Internal address space of chip 3;

[0140] 3G-4G / 7G-8G: Internal address space of chip 4.

[0141] 7. Link Status Management and Reporting. Chip 1 is configured with a link reporting period T0 and a timeout period T1. The RC-side chip of each PCIe link is responsible for monitoring and collecting the status of this PCIe link and reporting it to the next higher level periodically according to the configured T0 time. If a link fails, such as the link between chip 2 and chip 3, chip 2 will mark it as faulty if it does not receive the status report from chip 3 within the timeout period. This status will then be sent to chip 1 through the PCIe link between chip 1 and chip 2 (e.g., an interrupt). Thus, the software on the CPU of chip 1 can know that the link between chip 1 and chip 2 is normal, but the link between chip 2 and chip 3 has failed. This information will then be further reported to the upper-layer software or presented to the user.

[0142] This application also provides a chip, the chip comprising: at least two controllers, the at least two controllers being connected to an internal bus, wherein...

[0143] The at least two controllers are used to interconnect with controllers of other chips based on the high-speed peripheral component interconnect PCIe bus.

[0144] This application also provides a computer program product, including computer program instructions, wherein the computer program instructions cause a computer to implement the steps in any of the above method embodiments.

[0145] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0146] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0147] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0148] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0149] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0150] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0151] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A chip interconnect processing method, characterized in that, Applied to a chip, the method includes: At least two controllers are disposed within some or all of the chips in a plurality of chips, wherein the at least two controllers are connected to an internal bus; The plurality of chips are interconnected via at least two controllers of some or all of the chips, based on a high-speed peripheral component interconnect PCIe bus.

2. The method according to claim 1, characterized in that, Interconnecting the plurality of chips via the at least two controllers of some or all of the chips, based on the high-speed peripheral component interconnect PCIe bus, includes: The interconnection topology of the multiple chips is determined based on system requirements; Based on the interconnection topology, the controllers of two chips to be connected among the plurality of chips are interconnected via the PCIe bus.

3. The method according to claim 1, characterized in that, The method further includes: Determine the type of controller for each chip relative to the bus; Configure the internal bus address range for the controller of each chip; Cross-chip address routing is performed based on the controller's type relative to the bus and the internal bus address range.

4. The method according to claim 3, characterized in that, Cross-chip address routing based on the controller's type relative to the bus and the internal bus address range includes: For each chip, if the controller is a master device relative to the bus type, it initiates a first address access request; if the controller is a slave device relative to the bus type, it receives a first address access request, wherein the first address access request carries the address to be accessed. If the address to be accessed is within the corresponding range of the internal bus address, the internal component is accessed according to the address to be accessed. If the address to be accessed is outside the corresponding internal bus address range, the first address access request is sent to the controller of the connected next-level chip via the PCIe bus.

5. The method according to claim 3, characterized in that, Cross-chip address routing based on the controller's type relative to the bus and the internal bus address range includes: For each chip, if the controller is a master device relative to the bus type, it initiates a first address access request; if the controller is a slave device relative to the bus type, it receives a first address access request, wherein the first address access request carries the address to be accessed. If the address to be accessed is within the corresponding range of the internal bus address, the internal component is accessed according to the address to be accessed. If the address to be accessed is outside the corresponding range of the internal bus address, the address to be accessed is converted into an external PCIe address based on the pre-set mapping relationship between the internal bus address and the external PCIe address. A second address access request is then sent to the controller of the next-level chip based on the PCIe bus, wherein the second address access request carries the converted external PCIe address.

6. The method according to claim 5, characterized in that, Based on a pre-set mapping relationship between internal bus addresses and external PCIe addresses, converting the address to be accessed into an external PCIe address includes: The address to be accessed is converted into the external PCIe address based on the mapping relationship in the controller's pre-configured inbound or outbound register.

7. The method according to claim 3, characterized in that, Determining the controller type for each chip relative to the bus includes: Determine the access requirements of the controller; The type of the controller relative to the bus is determined based on the controller's access requirements.

8. The method according to claim 7, characterized in that, Determining the type of the controller relative to the bus based on the controller's access requirements includes: When the controller's access requirement is to access the internal space of other chips via the PCIe bus, the controller type is set to master device, where master device indicates support for initiating access to the bus; When the controller's access requirement is to support other chips accessing the local space, the controller type is set to slave device, where slave device indicates support for responding to access from other master devices on the bus; When the controller's access requirement is to access the internal space of other chips via the PCIe bus and to support other chips accessing their local space, the controller type is set to master device and slave device.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: Configure the root component RC-side chip for the PCIe link between every two connected chips; The RC-side chip monitors and collects the status of the PCIe link and reports the link status to the next-level chip. If no link status is reported from the next-level chip within the preset timeout period, it is determined that the PCIe link with the next-level chip has failed, and the link status of the failed PCIe link is reported to the next-level chip.

10. A chip, characterized in that, The chip includes: at least two controllers, wherein the at least two controllers are connected to an internal bus, wherein... The at least two controllers are used to interconnect with controllers of other chips based on the high-speed peripheral component interconnect PCIe bus.

11. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 9 when it is run.

12. An electronic device, characterized in that, The method includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 9.

13. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 9.

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