A fault tree target event probability calculation method, device, storage medium and program product

Abstract

The application provides a fault tree target event probability calculation method, device, storage medium and program product. The method comprises the following steps: obtaining structure data of a fault tree, identifying input-output dependency relationship between event nodes and function nodes, and establishing topological mapping relationship therebetween; determining calculation parameters according to the topological mapping relationship, including occurrence probability of each basic event, position mask and total sampling number; in each round of sampling, occurrence state of each basic event is determined independently based on the occurrence probability of the basic event, and corresponding event node state information and operation state are established; according to a logic gate calculation rule of the function node, output event node state is iteratively updated, logic propagation calculation of the fault tree is realized; when the cumulative sampling number reaches a set value, the frequency of the target event appearing as true in all calculation results is counted, so as to determine the occurrence probability of the target event. The application realizes linear-time quantitative solution through mask coding and sampling propagation mechanism, and reduces the calculation complexity.

Description

Technical Field

[0001] This application relates to the field of system reliability analysis technology, and in particular to a method, device, storage medium and program product for calculating the probability of target events in a fault tree. Background Technology

[0002] Fault Tree Analysis (FTA) is a system reliability analysis method widely used in aerospace, power, transportation, communications, and industrial equipment fields. By constructing the logical relationships between system functional events and failure events, FTA can qualitatively and quantitatively analyze the causes of top-level failures in a system, thus providing an important basis for system safety assessment and reliability design.

[0003] In existing technologies, quantitative calculation of fault trees typically employs cut-set analysis methods based on Boolean algebra. This method enumerates logical combinations of bottom events, derives minimal cut sets, and calculates the probability of the top event based on the occurrence probability of the bottom events. However, when the system structure is complex and the number of bottom events is large, the Boolean algebra method requires calculation of a large number of logical combinations, and the computational load increases exponentially with the number of bottom events, resulting in high computational complexity and low operational efficiency. In practical engineering, when the scale of bottom events reaches a certain level, traditional quantitative analysis methods often struggle to complete the calculation within an acceptable timeframe, limiting the application of fault tree analysis in large-scale systems. Furthermore, Boolean algebra-based calculation methods lose the ability to calculate the probability of intermediate events. In the process of expressing the top event using bottom events, the probability calculation method for each intermediate event is omitted, thus lacking the ability to quantitatively analyze the intermediate nodes of the hierarchical logic of the system. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides a method, device, storage medium, and program product for calculating the probability of target events in a fault tree, which at least solves the problems of high complexity and low computational efficiency in quantitative calculation of fault trees in existing technologies.

[0005] To achieve the above objectives and other advantages, some embodiments of this application provide the following aspects:

[0006] In a first aspect, some embodiments of this application provide a method for calculating the probabilities of top events and intermediate events in a fault tree, including:

[0007] Obtain the structural data of the fault tree, identify the input-output dependencies between each event node and function node, and establish the topological mapping relationship between the event nodes and the function nodes;

[0008] The calculation parameters are determined based on the topological mapping relationship. The calculation parameters include: the probability of occurrence of each bottom event, the position mask corresponding to each bottom event, and the total number of samplings.

[0009] In each round of sampling, the computational state of the fault tree is reset to re-establish the computational environment of the current sampling, and the occurrence state of each bottom event is independently determined based on the occurrence probability of the bottom event, thereby establishing the event node state information and operation state in the current sampling computational environment.

[0010] Based on the topological mapping relationship, it is determined in turn whether each function node meets the preset calculation conditions. When the calculation conditions are met, the event node status information and operation status corresponding to the function node are iteratively updated according to the logic gate calculation rules of the function node, so as to realize the logic propagation calculation of the fault tree.

[0011] The sampling and logical propagation calculations are repeated, and the results of each round of calculations are recorded. When the cumulative number of samplings reaches the total number of samplings, the frequency of the target event being true in all calculation results is statistically analyzed to determine the probability of the target event occurring. The target event includes a top event or an intermediate event.

[0012] Secondly, some embodiments of this application also provide an electronic device, the electronic device comprising:

[0013] One or more processors; and a memory storing computer program instructions that, when executed, cause the processors to perform the fault tree target event probability calculation method as described above.

[0014] Thirdly, some embodiments of this application also provide a computer-readable storage medium having a computer program and / or instructions stored thereon, which, when executed by a processor, implement the fault tree target event probability calculation method as described above.

[0015] Fourthly, some embodiments of this application also provide a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the fault tree target event probability calculation method as described above.

[0016] Compared with existing technologies, the solution provided in this application effectively solves the problems of high computational complexity and exponential growth in computational load as the node size increases in Boolean algebra computation for reliability analysis of complex systems by introducing a data representation structure based on mask encoding and a logic propagation mechanism based on random sampling. This method establishes a topological mapping relationship between event nodes and logic gate nodes in the fault tree and represents them in binary form using position masks, input masks, and output masks. This transforms complex logical dependencies into a bitwise operable mask model, achieving efficient linear complexity solutions. Simultaneously, by combining a random sampling mechanism, the occurrence states of bottom events are independently sampled, and iterative propagation according to logic gate rules is performed in each round of sampling, enabling rapid convergence of the probability propagation from bottom events to target events within the sample space. After multiple rounds of sampling, an approximate estimate of the system failure probability can be obtained by statistically analyzing the frequency of the target event occurring as true in all samples. Therefore, this method significantly improves computational efficiency and scalability while reducing computational complexity, and the calculation results are deterministic and stable, enabling efficient probability calculation and risk assessment of fault trees in complex systems. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other implementation methods can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a method for calculating the probability of target events in a fault tree according to an embodiment of this application;

[0019] Figure 2 This is an example fault tree diagram provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The following terms are used in this document.

[0023] Fault tree: It is a logical modeling tool used for system reliability analysis. It takes the system failure event as the top-level target and analyzes the various intermediate events and bottom events that lead to the occurrence of the top event layer by layer from top to bottom. It describes the causal relationship between events through logical gate nodes, thereby determining the multiple possible combinations of system failures and their probabilities, and providing a quantitative basis for system safety design and risk control.

[0024] Top event: refers to the target event studied in fault tree analysis, that is, the system failure or accident event caused by the combined effect of multiple lower-level events.

[0025] Intermediate events: These are intermediate events located between the top and bottom events, and their occurrence is formed by combining several bottom events or other intermediate events through logic gates.

[0026] Bottom event: also known as basic event, refers to the most basic cause event in the fault tree that is no longer decomposed downwards. Its occurrence can be directly used as the input condition for the upper-level event and is the starting node for fault tree probability calculation.

[0027] First Embodiment

[0028] The first embodiment of this application relates to a method for calculating the probability of target events in a fault tree, referring to... Figure 1 As shown, the method may include the following steps:

[0029] Step S1: Obtain the structural data of the fault tree, identify the input-output dependencies between each event node and function node, and establish the topological mapping relationship between event nodes and function nodes.

[0030] The structure data of a fault tree can be derived from a fault tree model file created during the system design phase or exported using professional modeling tools. Its content includes the hierarchical number of each event node, node type, logic gate type, and the connection relationships between nodes. Event nodes represent specific failure events in the system and are categorized into top events, intermediate events, and bottom events. Function nodes represent logic gate nodes, such as AND gates and OR gates, used to describe the logical relationships between different events.

[0031] When identifying node dependencies, the set of input events and the output event node for each function node are determined by parsing the connection information in the fault tree structure data. For example, if the logic gate type of a function node is an "AND gate", then all its input events must occur before the output event will occur; if it is an "OR gate", then the occurrence of any input event will cause the output event to occur.

[0032] Building upon this foundation, a topological mapping between event nodes and function nodes is established by assigning unique identifiers to each event node and logic gate node and recording the pointer relationships between inputs and outputs. This mapping is used to characterize the hierarchical structure of the fault tree, enabling the logic propagation process to be traversed and computed in a bottom-up dependent order, thereby providing a structured data foundation for probabilistic analysis.

[0033] Step S2: Determine the calculation parameters based on the topological mapping relationship. The calculation parameters include: the occurrence probability of each bottom event, the position mask corresponding to each bottom event, and the total number of samplings.

[0034] Basic events are the fundamental units constituting system failures. Each basic event has an independent probability of occurrence, reflecting the likelihood of failure occurring within a unit of time or under specific operating conditions. This probability value can be set based on historical statistical data, component reliability manuals, or empirical parameters.

[0035] For each bottom event, a corresponding location mask is assigned based on its unique position in the fault tree to identify its logical location and its relationship with other nodes in subsequent calculations. The location mask can be encoded in binary, where each bit corresponds to an identifier bit of an event node, supporting logical calculations and fast addressing at the mask level.

[0036] After determining the base event probability parameters and the location mask, statistical parameters are further set to control the number of samplings. The total number of samplings limits the number of random sampling rounds performed during the sampling solution process; its size can be determined based on the target computational accuracy and system complexity. A larger number of samplings can improve the convergence accuracy of probability estimation, while a smaller number of samplings can reduce the computational load.

[0037] Step S3: In each round of sampling, the computational state of the fault tree is reset to re-establish the computational environment of the current sampling, and the occurrence state of each bottom event is independently determined based on the occurrence probability of the bottom event, thereby establishing the event node state information and operation state in the current sampling computational environment.

[0038] After configuring the calculation parameters, the sampling calculation phase begins. To ensure the independence and statistical validity of each round of sampling, the calculation state of the fault tree must be reset before each sampling begins. Resetting the calculation state includes restoring variables such as event node status codes, function node status codes, and operation status codes to their initial states. By initializing the above state information, it can be ensured that each round of sampling is performed in an independent and reproducible computational environment.

[0039] Subsequently, based on the preset occurrence probabilities of each base event, an independent random sampling method is used to determine the occurrence state of each base event in the current round. The state of a base event can be represented by a binary value, where "1" indicates that the event has occurred and "0" indicates that the event has not occurred. The sampling process for each base event is independent of each other and is only related to its corresponding occurrence probability. After the base event sampling is completed, the state of all event nodes in this round of sampling (including whether it has occurred or not) is uniformly encoded and stored, written into the event node status code to identify the logical state of the base event, and the operation status code is updated synchronously, establishing a unified and computable system state foundation for the logic propagation phase.

[0040] Step S4: Based on the topological mapping relationship, determine whether each function node meets the preset calculation conditions in turn. When the calculation conditions are met, update the event node status information and operation status corresponding to the function node according to the logic gate calculation rules of the function node to realize the logic propagation calculation of the fault tree.

[0041] After completing the sampling of the bottom events and forming the current sampling calculation environment, the logical propagation calculation stage of the fault tree begins. In this stage, based on the topological mapping relationship established in step S1, each function node is calculated and judged in sequence according to the hierarchical dependency order between function nodes, so as to realize the logical state transfer from the bottom event to the target event.

[0042] Specifically, the system first checks the function node status codes to determine which function nodes have not yet been computed. For each function node not identified as computed, the system checks whether the states of all its input events have been determined. When it is determined that the states of all input events for a function node have been determined, the logical operation process is triggered. During the logical operation, the system performs logical operations on the input events according to the logic gate type (e.g., AND gate, OR gate) corresponding to the function node, following preset logic gate computation rules, generating corresponding output results, and updating the event node status information and operation status corresponding to the output event based on these results. Simultaneously, the current function node status code is updated to "computed" to prevent duplicate computation.

[0043] Once all function nodes have completed their state updates, a full logical propagation calculation process is complete. This step achieves the logical transfer from the base event to the target event, enabling a complete calculation of the fault tree state under the current sampling. This process automatically traverses all node levels through iterative mask logic operations, avoiding the need for manual construction of minimum cut sets, thereby effectively improving computational efficiency and stability.

[0044] Step S5: Repeat the sampling and logical propagation calculations, record the calculation results of each round, and when the cumulative number of samplings reaches the total number of samplings, count the frequency of the target event being true in all calculation results to determine the probability of the target event occurring. The target event includes the top event or intermediate events.

[0045] The system cyclically executes the sampling and logic propagation process according to a preset total number of sampling attempts. After each round of sampling, the system reads the operation status code value corresponding to the target event in the current round. The target event can be the top event in the fault tree or an intermediate event located below the top event level. When the value at the corresponding position of the target event is "1", it indicates that the event occurred in this round of sampling; when the value is "0", it indicates that the event did not occur. This value is stored in the statistical cache to accumulate and record the results of each round of sampling.

[0046] As sampling rounds accumulate, the status of all recorded target events is continuously summarized. When the cumulative number of samplings reaches the preset total number of samplings, statistical analysis is performed on all sampling results to calculate the frequency of the target event appearing as "true" in all sampling results, and this frequency is used as an estimate of the probability of the target event occurring. Through this statistical method, the system-level failure probability of the top event and the hierarchical failure probability of a specified intermediate event can be obtained simultaneously, thereby achieving a unified probability assessment of events at different levels.

[0047] Through iterative execution of multiple rounds of independent sampling and logical propagation computation, it can directly obtain approximate values ​​of the probability distribution of the target event using statistical methods without relying on Boolean algebra solutions or minimal cut set derivations. Since each round of sampling is independent, the statistical estimation results have high stability and convergence when the sample size is sufficient, enabling high-precision inference of the probability of system failure or intermediate events.

[0048] Compared with existing technologies, the solution provided in this application effectively solves the problems of high computational complexity and exponential growth in computational load as the node size increases in Boolean algebra computation for reliability analysis of complex systems by introducing a data representation structure based on mask encoding and a logic propagation mechanism based on random sampling. This method establishes a topological mapping relationship between event nodes and logic gate nodes in the fault tree and represents them in binary form using position masks, input masks, and output masks. This transforms complex logical dependencies into a bitwise operable mask model, achieving efficient linear complexity solutions. Simultaneously, by combining a random sampling mechanism, the occurrence states of bottom events are independently sampled, and iterative propagation according to logic gate rules is performed in each round of sampling, enabling rapid convergence of the probability propagation from bottom events to target events within the sample space. After multiple rounds of sampling, an approximate estimate of the system failure probability can be obtained by statistically analyzing the frequency of the target event occurring as true in all samples. Therefore, this method significantly improves computational efficiency and scalability while reducing computational complexity, and the calculation results are deterministic and stable, enabling efficient probability calculation and risk assessment of fault trees in complex systems.

[0049] Second Embodiment

[0050] The second embodiment of this application relates to a method for calculating the probability of target events in a fault tree. The second embodiment is an improvement on the first embodiment, specifically in that it provides a specific implementation method for modeling the logical structure of a fault tree based on mask coding, that is, step S1 can further include the following steps:

[0051] Step S101: Parse the structural information of the fault tree to determine event nodes and function nodes;

[0052] Step S102: Identify the input and output events of each function node based on the connection relationship between event nodes and function nodes;

[0053] Step S103: Assign a unique location mask to each event node, and generate a corresponding input mask based on the location mask and the input event to identify the set of input events received by the function node, and generate a corresponding output mask based on the location mask and the output event to identify the target event output by the function node;

[0054] Step S104: Based on the correspondence between the location mask, input mask, and output mask, establish a topological mapping relationship to characterize the input-output dependency between event nodes and function nodes, so as to form a computable representation of the fault tree logic structure.

[0055] Specifically, a mask is a data encoding used to quantify the logical relationships between nodes. It consists of k binary bits, each bit taking the value 0 or 1 independently, used to identify the position of a node in the global logical space. Logical operations on a mask are performed bit-by-bit; a calculation at one position does not affect other positions. Basic logical operation rules include:

[0056] The logical OR operation (⊕): 0⊕0=0, 0⊕1=1, 1⊕0=1, 1⊕1=1;

[0057] Logic AND operation ( ): 0 0=0, 0 1=0, 1 0 = 0, 1 1 = 1;

[0058] Logical NOT operator (◎): 0◎=1, 1◎=0.

[0059] Read the hierarchical description file or node connection data of the fault tree, and analyze the node types and their connections. When a node directly corresponds to a basic failure event, it is identified as an event node. When a node connects multiple input events in the form of logic gates (such as AND gates, OR gates, etc.) and generates an output event, it is identified as a function node.

[0060] To uniquely identify event nodes in the fault tree, this embodiment uses sequential numbering for all event nodes (including bottom, middle, and top events). Assuming there are n event nodes in the fault tree, each node is assigned an n-bit binary mask, where only the i-th bit is 1 and the rest are 0. This mask represents the unique coordinate position of the node in the global data space and is called the position mask.

[0061] For example, in Figure 2 The fault tree example shown, "Motor not turning," has 9 event nodes with the following location masks:

[0062] Event Node 1: Human error caused the switch to fail to close, and its position mask is W(1)=100000000;

[0063] Event Node 2: The switch is faulty and cannot be closed. Its location mask is W(2)=010000000;

[0064] Event node 3: The switch is not closed, and its position mask is W(3)=001000000;

[0065] Event node 4: There is no power supply on the line, and its location mask is W(4)=000100000;

[0066] Event node 5: The motor does not turn, and its position mask is W(5)=000010000;

[0067] Event node 6: Motor failure, its location mask is W(6)=000001000;

[0068] Event node 7: Power failure, its location mask is W(7)=000000100;

[0069] Event node 8: After the switch is closed, there is no current in the line, and its position mask is W(8)=000000010;

[0070] Event node 9: Line fault, its location mask is W(9)=000000001.

[0071] Among them, the bottom events are event nodes 1, 2, 6, 7 and 9, the middle events are event nodes 3, 4 and 8, and the top event is event node 5.

[0072] It should be noted that the location mask is only used to uniquely identify the logical location of each event node in the computer data space, and its specific encoding order is not fixed. For example, it can be rearranged according to the topological hierarchy, logical dependency order, or numbering rules of the event nodes. As long as the mask position corresponding to each event node is not repeated in the same computing environment, the consistency of logical operations can be maintained.

[0073] For each function node (i.e., logic gate node), this embodiment defines two types of parameters: input mask and output mask. The input mask is used to describe the set of input events received by the function node, and can be obtained by performing a logical OR operation on the position masks corresponding to all its input events. The output mask is used to represent the position mask of the output event corresponding to the function node, and is used to identify the target event output by the function node.

[0074] by Figure 2 The fault tree shown contains 4 function nodes, and their input and output mask correspondences are as follows:

[0075] Function node M001 (OR gate): The input mask is R(1)=W(1)⊕W(2)=110000000, and its output mask is C(1)=W(3);

[0076] Function node M002 (OR gate): The input mask is R(2)=W(4)⊕W(6)=000101000, and its output mask is C(2)=W(5);

[0077] Function node M003 (OR gate): The input mask is R(3)=W(3)⊕W(8)=001000010, and its output mask is C(3)=W(4);

[0078] Function node M004 (OR gate): The input mask is R(4)=W(7)⊕W(9)=000000101, and the output mask is C(4)=W(8).

[0079] By analyzing the input and output masks of each function node, the logical dependency path of that function node in the fault tree structure can be determined. For example, when the bits of the input mask R(k) that are "1" correspond to the position masks of several event nodes, it indicates that the function node uses the states of these event nodes as input conditions; and the event nodes corresponding to the bits of the output mask C(k) that are "1" indicate that the calculation result of the function node will be updated to the output event node. Through this bit-by-bit encoding method, a bidirectional reference relationship between function nodes and event nodes can be established at the data structure level.

[0080] The function node numbers M001 to M004 are merely exemplary logical identifiers used to illustrate the logical dependencies between function nodes, rather than constraining structural relationships. The identifiers of function nodes can be dynamically generated based on the topological traversal order (e.g., bottom-up, level-first, or depth-first) and are used to uniquely identify the corresponding logical gate node during program computation.

[0081] This topological mapping transforms the node connections in the fault tree into masked logical relationships, allowing complex hierarchical dependencies (event-function-event) to be expressed as a set of bitwise operation models that can directly participate in logical operations. For example, in Figure 2 In the fault tree shown, the input mask R(1)=110000000 and the output mask C(1)=001000000 of function node M001 indicate that node M001 takes "human error caused the switch not to close" and "switch malfunction prevents it from closing" as input events and "switch not closed" as output event. Similarly, the input mask R(4)=000000101 and the output mask C(4)=000000010 of function node M004 indicate that its input events are "power supply failure" and "line failure" and its output event is "no current in the line after the switch is closed".

[0082] Through the above mapping relationships, the entire fault tree can be abstracted as a directed topological graph of event nodes and function nodes, with the logical dependencies of each node stored in mask form. This directed topological graph structure not only simplifies the access and calculation of the logical structure, but also provides a unified computational basis for subsequent mask-based logical propagation calculations, enabling the hierarchical logic of the fault tree to be efficiently implemented in a computer environment.

[0083] It is easy to see that the solution provided in this application, by introducing a node representation method based on mask encoding, achieves standardized and computable modeling of the fault tree logic structure. This mask model not only eliminates redundant operations in hierarchical traversal and node indexing in traditional graph structures, but also enables rapid determination of dependencies between nodes through bitwise logical operations, realizing direct calculation and storage of topological mapping relationships. With the help of this masked topological modeling method, the fault tree structure can be transformed into a logical vector model that can be directly manipulated by a computer, thereby significantly improving the addressing efficiency and computation speed in subsequent sampling calculations and logic propagation processes.

[0084] Third Embodiment

[0085] The third embodiment of this application relates to a method for calculating the probability of target events in a fault tree. The third embodiment is an improvement on the first embodiment, specifically in that it provides a specific implementation method for parametric modeling and sampling control, namely, step S2 can further include the following steps:

[0086] Step S201: Identify the bottom event nodes in the fault tree based on the topology mapping relationship, and set the corresponding occurrence probability parameters for each bottom event node.

[0087] Identifying bottom-level event nodes in a fault tree based on topological mapping relationships. A bottom-level event node is the smallest event unit in the structural hierarchy that is no longer expanded by other logic gates. For example, in... Figure 2 In the fault tree shown, event node 1 (human error causing the switch not to close), event node 2 (switch malfunction preventing closure), event node 6 (motor malfunction), event node 7 (power supply malfunction), and event node 9 (line malfunction) are all bottom events. The system sets a corresponding occurrence probability parameter P(k) for each bottom event node, such as P(1)=0.0010, P(2)=0.0006, P(6)=0.0003, P(7)=0.0007, and P(9)=0.0012, for use in the subsequent random sampling process.

[0088] Step S202: Combine the topological mapping relationship and the position mask corresponding to the bottom event node to establish the index correspondence between the event node and the function node, which is used to realize the fast location of input-output relationship and logic propagation calculation in mask logic operation.

[0089] Suppose there are n event nodes in the fault tree, numbered from 1 to n. Each event node corresponds to a unique position mask W(i), which is an n-bit binary code where the i-th bit is 1 and the rest are 0. Based on this, an input mask R(k) and an output mask C(k) are generated for each function node. The input mask R(k) is obtained by bitwise logical ORing of the position masks of all input events of the function node, and the output mask C(k) corresponds to the position mask of the output events of the function node.

[0090] Based on this, the system establishes two types of index structures: one is the function node forward index, used to describe the relationship between the input event set and the output event of each function node; the other is the event node reverse index, used to record the set of function nodes corresponding to each event node when it is used as input. The output event number is determined by the bits that are 1 in the output mask C(k), thus forming the function node forward index mapping F[k]={inputs: , output: o(k)}, where k represents the number of the function node (k∈[1,m], where m is the total number of function nodes); Represents the set of input events, which is the set of all input event numbers for function node k. That is, when a bit in the input mask R(k) is 1, the corresponding event number belongs to... o(k) represents the output event number, indicating the event node number corresponding to the output event of function node k. That is, when a certain bit in the output mask C(k) is 1, the event number corresponding to that bit is o(k); F[k] represents the forward index of function node k. At the same time, construct the reverse index B[i]={k|i∈ } is used to indicate the set of all function nodes associated with event node i. I represents the event node number (i∈[1,n], where n is the total number of event nodes); B[i] represents the set of inverted indices of event node i.

[0091] During the logical propagation calculation, the bitwise logical AND result of the event node status code S and the input mask R(k) can be used to quickly determine whether all input events of the function node are determined. When the condition is met, the output mask C(k) is used to directly locate and update the status information of the corresponding output event. When the status of an event changes, the affected function node can be quickly determined through the reverse index B[i], and its logical calculation operation can be triggered. Through the establishment of the above index correspondence, the logical propagation process of the fault tree does not need to perform a full table scan of all nodes, and can realize the bitwise association and efficient update of event status and function node status, thereby significantly improving the calculation speed.

[0092] Step S203: Set a calculation accuracy threshold to limit the allowable error range of probability calculation, and determine the number of samplings to control sampling convergence based on the expected occurrence probability of the target event and the calculation accuracy threshold.

[0093] A calculation precision threshold is set to limit the allowable error range for probability calculations. In probability sampling calculations, the total number of samples and the expected error satisfy an approximate Bernoulli sampling relationship:

[0094]

[0095] in, The expected probability of the target event is used to characterize the estimated failure probability under given conditions, and can be the top event or an intermediate event. The allowable calculation error threshold is used to limit the range of deviation between the estimated result and the true probability; This represents the total number of samplings, used to control the convergence accuracy of fault tree probability estimation.

[0096] In practical applications, settings can be configured according to the system reliability analysis requirements. The value of is given. For example, when the system tolerance error is 0.001 and the expected probability of the top event is P≈0.002, substituting into the formula yields: N≈200000. This result shows that after performing approximately 200,000 independent samplings, the probability error can be controlled within ±0.001, thus achieving credible convergence of the probability estimation results.

[0097] Based on this, the system can automatically determine the minimum number of samplings required to meet the accuracy requirements, thereby balancing computational load and estimation accuracy and improving the reliability of probability results.

[0098] Step S204: Initialize the sampling index, which is used to control the execution order and result recording of the sampling cycle.

[0099] Before performing fault tree probability calculations, the system needs to initialize a sampling index to control the execution order and result recording of subsequent sampling loops. Specifically, a sampling index variable `i` is first defined and initialized to 1 to identify the current sampling round. After each round of sampling and logic propagation calculations, the index value is incremented (i = i + 1) to proceed to the next round of calculation. When the sampling index reaches the preset total number of samplings N, the loop automatically terminates to avoid infinite iteration. After each round of calculation, the operation status code under the current sampling is stored along with the corresponding index `i` to form a structured data record, facilitating statistical analysis and probability calculations.

[0100] It is easy to see that the solution provided in this application achieves a dynamic balance between computational accuracy and computational load by introducing an adaptive determination mechanism for the computational accuracy threshold and the number of samplings, ensuring that computational overhead is minimized while meeting error requirements. Simultaneously, by combining the topological mapping relationship with the index correspondence established by the bottom event location mask, the logical dependencies between event nodes and function nodes can be quickly located and directly invoked, improving the addressing efficiency of mask logic operations. Through this index structure, the system does not need to repeatedly parse the fault tree logic structure during sampling calculations, thereby achieving efficient data access and structure reuse.

[0101] Fourth embodiment

[0102] The fourth embodiment of this application relates to a method for calculating the probability of target events in a fault tree. The fourth embodiment is an improvement on the first embodiment, specifically in that it provides a specific implementation method for random sampling of base events and state initialization, namely, step S3 can further include the following steps:

[0103] Step S301: Initialize the function node status code, event node status code, and operation status code to clear the calculation results of the previous round of sampling;

[0104] Step S302: Iterate through each bottom event node in sequence and perform independent random sampling based on the occurrence probability parameter corresponding to the bottom event node to determine the occurrence status of each bottom event under the current sampling.

[0105] Step S303: When the occurrence status indicates that the bottom event has not occurred, update the event node status code according to the position mask of the bottom event;

[0106] Step S304: When the occurrence of a state indicates that a bottom event has occurred, update the event node status code and the operation status code according to the position mask of the bottom event;

[0107] Step S305: Repeat the sampling and state update of each bottom event until all bottom event nodes have been sampled to form the event node state information and operation state under the current sampling.

[0108] Specifically, when using random sampling, each round of sampling corresponds to an independent experiment, equivalent to a complete simulation or deduction of the fault tree. To ensure that each round of experiments is statistically independent, the system must clear all state information accumulated during the previous round of calculation before starting a new round of sampling, to prevent data residue from interfering with subsequent sampling. This process is called "resetting the calculation state," which is equivalent to restoring the fault tree to its initial uncalculated state, thereby ensuring that each round of sampling is conducted independently under the same initial conditions.

[0109] The system iterates through each bottom event node in the fault tree and performs independent random sampling according to the occurrence probability parameter P(k) of each bottom event. For each bottom event node k, the system first updates the event node status code S according to its corresponding location mask W(k), i.e., performs a logical XOR operation S=S⊕W(k) to indicate that the bottom event node has been visited. Next, the system determines whether the bottom event has occurred based on the random sampling result: if the sampling result is 0, it means that the event has not occurred, and only S is updated, while the operation status code X remains unchanged; if the sampling result is 1, it means that the event has occurred, and in addition to updating S, the operation X=X⊕W(k) is also performed to indicate the occurrence of the event in the operation status.

[0110] by Figure 2 Taking the fault tree shown as an example, firstly, each status code is initialized by clearing all bits of the function node status code H, event node status code S, and operation status code X, i.e., setting H=0000, S=000000000, X=000000000, in order to clear the calculation results of the previous round of sampling and form a new initial sampling environment.

[0111] The position masks W(1), W(2), W(6), W(7), and W(9) corresponding to the bottom event nodes have corresponding probability parameters P(1)=0.0010, P(2)=0.0006, P(6)=0.0003, P(7)=0.0007, and P(9)=0.0012, respectively. The sampling process is as follows:

[0112] For W(1): execute S=S⊕W(1) and perform random sampling according to P(1)=0.0010. If the result is 1, then execute X=X⊕W(1);

[0113] For W(2): execute S=S⊕W(2) and perform random sampling according to P(2)=0.0006. If the result is 1, then execute X=X⊕W(2);

[0114] For W(7): execute S=S⊕W(7) and perform random sampling according to P(7)=0.0007. If the result is 1, then execute X=X⊕W(7);

[0115] For W(9): execute S=S⊕W(9) and perform random sampling according to P(9)=0.0012. If the result is 1, then execute X=X⊕W(9);

[0116] For W(6): execute S=S⊕W(6) and perform random sampling according to P(6)=0.0003. If the result is 1, then execute X=X⊕W(6).

[0117] After performing sampling and state update operations on all bottom events, the event node status code S and operation status code X for the current sampling round can be obtained. The event node status code S reflects the access status of all bottom event nodes in this sampling round, while the operation status code X reflects the actual occurrence of the corresponding bottom event. For example, in a single sampling process, after performing random sampling and state update operations on bottom events W(1), W(2), W(7), W(9), and W(6) in sequence, the resulting event node status code is S=110001101, indicating that the positions corresponding to these bottom events have all been accessed. The value of the operation status code X depends on the sampling results of each bottom event. Assuming that only the 1st and 6th bottom events occur in this sampling round, X=100001000, indicating that the events corresponding to the 1st and 6th positions are triggered, and the remaining events do not occur. The event node status code S and the operation status code X will serve as input variables for the subsequent logic propagation calculation stage. By performing a logical AND operation between the function node input mask and the event node status code S, it is determined whether all input events of the function node have participated in the calculation. Then, based on the logic gate type of the function node and the value of the operation status code X, the output event status of the function node is calculated, thereby advancing the logic propagation process of the fault tree layer by layer.

[0118] To achieve parallel execution of multi-round sampling, the total number of sampling attempts is first divided into several batches according to a preset batch size, and each batch is executed by an independent processing unit. Each processing unit can be an independent computing thread, a CPU computing unit, a GPU computing unit, or a distributed node. During execution, they all reuse the same set of logical structure data constructed by topological mapping relationships, including the input and output masks and index mapping table between event nodes and function nodes.

[0119] In practical implementation, each processing unit initializes its state code set (S, H, X) in its private computing space to clear the calculation results of the previous batch and generates the corresponding basic event occurrence state based on an independent random number seed. Subsequently, the processing unit uses logic gate operation rules to propagate and update the event node state and operation state of the current batch layer by layer, forming a local target event result. After each processing unit completes the batch calculation, the local statistics of each batch are merged and summed to obtain the frequency of occurrence of the target event in all samples, so as to calculate the overall failure probability of the system or the occurrence probability of the target event.

[0120] Since each batch of samples is statistically independent, and the mask logic operation can be processed in bit-level parallelism through vectorization or GPU parallel instruction set, the entire sampling calculation process does not require modification of the logical structure of the fault tree or the node dependency relationship, thus achieving high throughput parallelization and fast initialization of the calculation process.

[0121] It is easy to see that the scheme provided in this application ensures statistical independence between different sampling rounds by resetting the computational state of the fault tree before each round of sampling, which conforms to the independent experiment assumption of the Monte Carlo method. By using position masks to uniformly encode the bottom event nodes and implementing bit-by-bit updates of event status codes and operation status codes through logical XOR operations, the activation and inactivation states of bottom events can be efficiently expressed in a unified binary space, avoiding the complex operations of node-by-node judgment and state storage in traditional methods, and significantly reducing computational overhead. This scheme can achieve rapid initialization and parallel execution of multi-round sampling without changing the logical structure of the fault tree, thus improving sampling efficiency and scalability while ensuring computational accuracy.

[0122] Fifth embodiment

[0123] The fifth embodiment of this application relates to a method for calculating the probability of target events in a fault tree. The fifth embodiment is an improvement on the fourth embodiment, specifically an improvement that provides a specific implementation method for fault tree logic propagation oriented towards function nodes, namely, step S4 can further include the following steps:

[0124] Step S401: Sequentially detect the function nodes that are not marked as calculated in the current sampled function node status codes, and determine whether all the input events of the function node are determined based on the logical operation result between the input mask of the function node and the event node status code.

[0125] Step S402: When it is determined that not all input events of the function node have been determined, the state update operation related to the function node is not performed, the state identifier of the function node and its corresponding output are kept in the current state, and the next function node that has not been identified as calculated is detected.

[0126] Step S403: When all input events of the function node are determined, update the corresponding event node status code according to the output mask of the function node, and mark the corresponding bit of the function node status code as calculated;

[0127] Step S404: Based on the logic gate type of the function node and according to the preset logic conditions, perform the corresponding logic operation on the operation status code to update the operation status under the current sampling.

[0128] Step S405: Use the event node status code, function node status code, and operation status code after each function node completes its status update as the input basis for the next function node logic propagation calculation. Repeat the function node judgment and logic update until all function nodes under the current sampling have completed the calculation.

[0129] Specifically, in each round of sampling, the system traverses the function nodes in the function node status code H that have not yet been marked as "calculated" under the current sampling, takes the current node number k, its corresponding input mask R(k) and output mask C(k), and calculates the logical AND result R(k) between the input mask and the current event node status code S. S. If the calculation result is not equal to the input mask R(k), it means that the input events of the function node have not been fully determined and the calculation conditions of the current function node have not been met. At this time, the state identifier of the node remains unchanged, and the next function node that has not been identified as having been calculated is detected.

[0130] When the detection result satisfies R(k) When S=R(k), it indicates that all input events for the function node have been determined. Then, the following operations are performed: based on the output mask C(k) of the function node, update the event node status code S so that S=S⊕C(k); set the corresponding k-th bit in the function node status code H to "1", indicating that the function node has completed its calculation.

[0131] Simultaneously, once the input event of a function node has been determined, the operation state under the current sampling is further updated according to its logic gate type. That is, step S404, which specifically includes:

[0132] Step S4041: When the logic gate of the function node is an AND gate, if the result of the logical AND operation between the input mask of the function node and the current operation status code is equal to the input mask, then the logic condition is satisfied. Perform a logical OR operation between the operation status code and the output mask of the function node to update the operation status of the corresponding output event.

[0133] When the logic gate of a function node is an AND gate, calculate the result R(k) of the logical AND operation between the input mask R(k) of the function node and the current operation status code X. X. If the result is equal to the input mask R(k), it indicates that all input events of the function node are in the "occurring" state, satisfying the logical condition. At this time, the system performs a logical OR update on the operation status code, i.e., X = X ⊕ C(k), where C(k) is the output mask corresponding to the function node, used to represent the logical triggering of the output event node. If the logical condition is not satisfied, no operation is performed, and the current operation state remains unchanged.

[0134] Step S4042: When the logic gate of the function node is an OR gate, if the result of the logical AND operation between the input mask of the function node and the current operation status code is not zero, it is determined that the logical condition is met, and the logical OR operation between the operation status code and the output mask of the function node is performed to update the operation status of the corresponding output event.

[0135] When the logic gate of the function node is an "OR gate", the logical AND result R(k) of the input mask R(k) and the current operation status code X is calculated. X. If the result is not zero, it indicates that at least one input event is in the "occurred" state, satisfying the logical condition. In this case, X = X ⊕ C(k) is executed again to update the operation status code to identify the occurrence of the output event node. If the logical condition is not satisfied, no operation is performed, and the current operation state remains unchanged.

[0136] Step S4043: When the logical condition is not met, the operation state update operation is not performed, and the operation state code remains in the previous round state.

[0137] When the input logic condition of the current function node is not met, if the function node is an AND gate, and the result of the logical AND operation between the input mask and the current operation status code is not equal to the input mask, it indicates that at least one input event has not occurred. If the function node is an OR gate, and the result of the logical AND operation between the input mask and the current operation status code is zero, it indicates that all input events have not occurred. In the above cases, no update operation is performed on the operation status code X or the event node status code S to avoid error propagation or premature calculation, thereby maintaining the correctness and stability of the logic propagation process. Through this processing mechanism, it is possible to prevent logic paths that have not yet been triggered from being activated prematurely, ensuring that the logic propagation under each round of sampling strictly depends on the determined input event state, and guaranteeing the reliability of the calculation results and the consistency of their physical meaning.

[0138] In a single sampling, once a function node completes its state update, the system uses the updated event node status code S, function node status code H, and operation status code X as the input basis for the next function node logic propagation calculation, in order to determine whether other function nodes that have not yet completed their calculations meet the logic propagation conditions.

[0139] Combination Figure 2 The fault tree structure shown illustrates the process of function node state checking and logic propagation. Assume there are 4 function nodes in the current sampling round, with corresponding input masks R(k) and output masks C(k) as follows:

[0140] Function node M001: R(1)=110000000, C(1)=001000000;

[0141] Function node M002: R(2)=000101000, C(2)=000010000;

[0142] Function node M003: R(3)=001000010, C(3)=000100000;

[0143] Function node M004: R(4)=000000101, C(4)=000000010.

[0144] When entering the function node state check phase, the event node status code S and the operation status code already carry the underlying event state information of this round of sampling, i.e., S=110001101, X=100001000. The function node status code is reset to H=0000 to indicate that all function nodes are in an uncomputed state. This ensures that the logic propagation calculation for each round of sampling is performed in an independent initial environment. The computation conditions of each function node are checked sequentially:

[0145] First round of inspection:

[0146] When H(1)=0 is detected, given the input mask R(1)=110000000, calculate R(1). S=110000000=R(1), indicating that all input events of the function node have been determined. At this point, S=S⊕C(1)=111001101 is executed, and the function node status code is updated to H=1000. The logic gate type corresponding to this node is "OR gate," so R(1) is calculated. X=100000000, the result is not 0, which meets the logical condition, so execute X=X⊕C(1)=101001000.

[0147] When H(2)=0 is detected, calculate R(2). S=000001000≠R(2), the logical condition is not met, so the state update is not performed;

[0148] When H(3)=0 is detected, calculate R(3). S=001000000≠R(3), so no state update is performed;

[0149] When H(4)=0 is detected, calculate R(4). S=000000101=R(4), indicating that all input events of this function node have been determined. At this time, execute S=S⊕C(4)=111001111 and update the function node status code to H=1001. The logic gate type corresponding to this node is "OR gate", calculate R(4). X=000000000=0, the result is 0, the logical condition is not met, and the operation status code X remains unchanged.

[0150] At the end of the first round of checks, the function node status code H=1001, the event node status code S=111001111, and the operation status code X=101001000.

[0151] Second round of inspections:

[0152] H(1) = 1, no action is taken;

[0153] When H(2)=0 is detected, calculate R(2). S=000001000≠R(2), the logical condition is not met, so the state update is not performed;

[0154] When H(3)=0 is detected, calculate R(3). S=001000000=R(3), indicating that all input events of this function node have been determined. At this time, execute S=S⊕C(3)=111101111 and update the function node status code to H=1011. The logic gate type corresponding to this node is "OR gate", calculate R(3). X=001000000, the result is not 0, which meets the logical condition, so execute X=X⊕C(3)=101101000.

[0155] H(4) = 1, no action is taken;

[0156] At the end of the second round of checks, the function node status code H=1011, the event node status code S=111101111, and the operation status code X=101101000.

[0157] Third round of inspections:

[0158] H(1) = 1, no action is taken;

[0159] When H(2)=0 is detected, calculate R(2). S=000101000=R(2), indicating that all input events of this function node have been determined. At this time, execute S=S⊕C(2)=111111111, and update the function node status code to H=1111. The logic gate type corresponding to this node is "OR gate", calculate R(2). X=000101000, the result is not 0, which meets the logical condition, so execute X=X⊕C(2)=101111000.

[0160] H(3) = 1, no action is taken;

[0161] H(4) = 1, no action is taken;

[0162] At the end of the third round of checks, the function node status code H=1111, the event node status code S=111111111, and the operation status code X=101111000. The position corresponding to the target event is X(5), and its value is 1, indicating that the target event has occurred, which is the top event.

[0163] As can be seen from the above logic propagation process, when event node 4 (no power supply on the line) is taken as the target event, its occurrence state is also automatically determined by the logic propagation process. When the input events (events 3 and 8) of its upstream logic gate M003 have been determined in the current sampling round and meet the corresponding logic gate triggering conditions, the system will update the event node status code and operation status code bit by bit according to the output mask, thereby setting the corresponding position of event node 4 to 1, to determine that the intermediate event has occurred in the current sampling. By statistically analyzing the frequency of the corresponding position of the intermediate event in all sampling rounds, the probability estimate of the intermediate event can be obtained.

[0164] It should be noted that the logic propagation mechanism used to update event states in this embodiment does not fundamentally differ in its calculation method for intermediate events and top events. Both are based on bitwise logic calculations between the input mask of a function node and the status code of an event node. When all input events of a function node are determined and the triggering conditions of the corresponding logic gates are met, the system updates the event node status code and the operation status code according to the output mask of that function node. The only difference lies in the position of the event in the fault tree hierarchy. An intermediate event simultaneously serves as the output event of a function node and may continue to serve as the input event of other function nodes; while the top event, as the final output target event of the fault tree, will no longer serve as the input of other function nodes. This difference reflects a hierarchical difference in the direction of propagation, rather than a difference in the calculation rules.

[0165] Furthermore, in this example, the judgment of the top event is only used for the final output of the fault tree at this level. If this fault tree is embedded in a larger-scale system for analysis, the event can also continue to participate in the propagation of the upper-level logic as an intermediate event. Its calculation method is consistent with the processing method of event node 4 in this embodiment.

[0166] In a certain sampling round, when a function node completes its state update, the updated event node status code S, function node status code H, and operation status code X are used as the input basis for the next function node logic propagation calculation. This is used to determine whether other function nodes that have not yet completed their calculations meet the logic propagation conditions, until the function node status code H◎=0.

[0167] When the function node status code H◎=0, it indicates that all function nodes in the current sampling round have completed the logic propagation calculation. The calculation result of this round is recorded to the sampling result set, and the sampling index value i=i+1 is updated to start a new round of sampling. In the new sampling round, the bottom event sampling step is re-executed, that is, new random sampling results are independently generated based on the occurrence probability parameters of each bottom event, and the event node status code, function node status code, and operation status code are reset, thereby forming a new computing environment. Subsequently, according to the topological mapping relationship of the fault tree, the status check and logic propagation calculation are performed on each function node again to obtain the operation result of the target event in the current sampling.

[0168] In large-scale sampling scenarios, different sampling rounds may produce identical combinations of bottom-level event states. For the first occurrence of a state combination, the system performs function node logic propagation calculations and stores the calculation results of this state combination along with the corresponding top and intermediate events in a cache. For the same state combination that reappears in subsequent sampling processes, there is no need to repeat the logic propagation calculations; the corresponding calculation results can be directly read from the cache. For example, if a fault tree contains 5 bottom-level events, and the bottom-level event state in a certain sampling round is (1,0,0,0,0), the system performs a complete calculation the first time it encounters this state. If the same state is sampled again in subsequent rounds, the cached results can be reused directly. This mechanism can significantly reduce redundant derivations and improve overall computational efficiency.

[0169] It is readily apparent that the solution provided in this application introduces a round-by-round checking and logic propagation mechanism based on function node status codes during fault tree calculation, achieving dynamic iterative updates of event states and operational states. This solution determines the determinism of the input events to function nodes and performs corresponding logical operations based on the logic gate type, enabling the event states to propagate layer by layer according to topological dependencies, thereby accurately reflecting the logical transmission relationship from the base event to the target event. This method significantly improves the execution efficiency of fault tree logic solving while ensuring computational accuracy, supporting automated and traceable calculation processes for multi-layer function nodes in complex systems.

[0170] Sixth Embodiment

[0171] The sixth embodiment of this application relates to a method for calculating the probability of target events in a fault tree. The sixth embodiment is an improvement on the first embodiment, specifically an improvement that provides a specific implementation method for sampling cyclic control and result probability statistics, namely, step S5 can further include the following steps:

[0172] Step S501: Initialize the sampling cycle counter to accumulate the number of samplings;

[0173] Step S502: After each round of sampling, record the value of the target event in the current operation status code and use the value as the calculation result of that round;

[0174] Step S503: The sampling cycle counter is incremented. When the current sampling count has not reached the total sampling count, the next round of sampling and logic propagation calculation is continued.

[0175] Step S504: When the cumulative number of samplings reaches the total number of samplings, the ratio of the number of times the target event is true in all sampling results to the total number of samplings is used as the probability of the target event occurring.

[0176] Specifically, the sampling cycle counter i=1 is initialized to accumulate the number of samples already performed. The counter increments by 1 after each round of sampling calculation is completed, until the preset total number of samples N is reached.

[0177] After each round of sampling completes the logical propagation calculation, the system reads the value of the position corresponding to the target event in the current operation status code X. For example, if the position corresponding to the target event is X(5), its value is 0 to indicate that the top event has not occurred, and 1 to indicate that the top event has occurred. This value is recorded as the calculation result of the current sampling round for subsequent statistics. For example, after the i-th round of sampling, if X(5)=1, it indicates that a system fault event has occurred in this sampling. The result is written to the result buffer Result[i]=1 in binary vector or Boolean value form.

[0178] After recording is complete, the sampling cycle counter i increments by 1. It is then checked whether i is less than or equal to the total number of samples N. If i ≤ N, a new round of sampling begins. Before the new round of sampling, the sampling operation is re-executed for each basic event node to independently determine its occurrence state based on the probability of the basic event. After completing the basic event sampling, the system initializes the event node status code S, function node status code H, and operation status code X to clear the calculation results of the previous round and rebuild the new sampling calculation environment. Subsequently, a new round of function node logic propagation calculation begins. When i > N, it indicates that all sampling rounds have been completed, and the system exits the sampling cycle and enters the result statistics stage.

[0179] When the cumulative number of samplings reaches N, count the number of times the target event has a value of 1 in all N rounds of sampling. Read the record result Result[i] of all sampling rounds from the result buffer, where Result[i] = 1 indicates that the target event occurred in the i-th round of sampling, and Result[i] = 0 indicates that the target event did not occur. Summarize all sampling results, count the total number n1 of samples where Result[i] is 1, and calculate the estimated probability of the target event occurring. = n1 / N. For example, when N=200000 and the number of times the target event is true is n1=396, then The value is approximately 0.00198, which is very close to the theoretical prediction P=0.002, indicating good sampling convergence. This ratio reflects the failure probability of the system under long-term operation and can be used as an important indicator for reliability assessment.

[0180] It should be noted that the target event can be either the top event of the fault tree or any intermediate event. For example, when the target event is the top event, its occurrence frequency can be used to estimate the overall failure probability of the system; when the target event is an intermediate event, its occurrence frequency can be used to estimate the triggering probability of that intermediate event under given sampling conditions.

[0181] It is easy to see that in the solution provided in this application embodiment, after each round of sampling, the occurrence result of the top event under the current sampling is automatically recorded, and after all sampling is completed, the frequency of occurrence of the target event in all samplings is calculated by statistically summarizing the results in the cache. This method can achieve efficient probability inference through statistical sampling without explicitly enumerating event combinations, which not only significantly reduces computational complexity, but also ensures the accuracy and stability of probability estimation.

[0182] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this application.

[0183] Furthermore, some embodiments of this application also provide an electronic device. The electronic device can be various forms of digital computer, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, etc. The electronic device can also be various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices.

[0184] The electronic device includes: one or more processors; and a memory storing computer program instructions, which, when executed, cause the processor to perform a fault tree target event probability calculation method as provided in any one or more of the above embodiments. Figure 3An exemplary structural diagram of the electronic device is disclosed. The electronic device includes one or more processors 1101, a memory 1102, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components are interconnected via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations. The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0185] The electronic device may further include an input device 1103 and an output device 1104. The processor 1101, memory 1102, input device 1103, and output device 1104 may be connected via a bus or other means. Figure 3 Taking the example of a connection between China and Israel via a bus.

[0186] Input device 1103 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 1104 may include a display device, auxiliary lighting device (e.g., LED), and haptic feedback device (e.g., vibration motor). The display device may include, but is not limited to, a liquid crystal display, a light-emitting diode display, and a plasma display. In some embodiments, the display device may be a touch screen.

[0187] To provide interaction with the user, the electronic device can be a computer. The computer has: a display device (e.g., a cathode ray tube or LCD monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback); and input from the user can be received in any form (e.g., voice input or tactile input).

[0188] In this embodiment, a computer-readable medium stores a computer program / instructions, which, when executed by a processor, implement a fault tree target event probability calculation method provided in any one or more of the above embodiments. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable medium carries one or more computer-readable instructions.

[0189] The memory 1102 can serve as a non-transitory computer-readable storage medium, used to store non-transitory software programs, non-transitory computer-executable programs, and modules. The processor 1101 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 1102, thereby implementing the program instructions / modules corresponding to the methods provided in any one or more of the embodiments described above in this application.

[0190] The memory 1102 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 1102 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1102 may optionally include memory remotely located relative to the processor 1101, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0191] It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, electrical connections having one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0192] Computer-readable media include permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory, static random access memory, dynamic random access memory, other types of random access memory, read-only memory, electrically erasable programmable read-only memory, flash memory or other memory technologies, read-only optical discs, digital versatile optical discs or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0193] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including local area networks (LANs) or wide area networks (WANs), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0194] In the above embodiments, all or part of the implementation can be achieved through software, hardware, firmware, or any combination thereof. For example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of this application can be executed by a processor to implement the above steps or functions. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, magnetic or optical drives, floppy disks, and similar devices. In addition, some steps or functions of this application can be implemented in hardware, for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0195] The computer program product provided in this application includes one or more computer programs / instructions. When executed by a processor, these computer programs / instructions generate, in whole or in part, the processes or functions described in this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0196] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0197] The scope of this application is defined by the appended claims rather than the foregoing description, and is therefore intended to encompass all variations falling within the meaning and scope of equivalents of the claims. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device in software or hardware. Terms such as "first," "second," etc., are used only for distinguishing descriptions and do not indicate any particular order, nor should they be construed as indicating or implying relative importance.

[0198] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A method for calculating the probability of target events in a fault tree, characterized in that, include: Obtain the structural data of the motor non-rotation fault tree for system reliability analysis, identify the input-output dependencies between each event node and function node, and establish the topological mapping relationship between the event nodes and the function nodes. The fault tree takes the motor non-rotation as the top event, and includes intermediate events from top to bottom such as switch not closed, no power supply on the line, and no current on the line after the switch is closed. It also includes bottom events such as human error causing the switch not to close, switch failure preventing it from closing, motor failure, power supply failure, and line failure. Analyze the various intermediate events and bottom events that lead to the occurrence of the top event layer by layer. The calculation parameters are determined based on the topological mapping relationship. The calculation parameters include: the probability of occurrence of each bottom event, the position mask corresponding to each bottom event, and the total number of samplings. In each round of sampling, the computational state of the fault tree is reset to re-establish the computational environment for the current sampling. Event node status codes, function node status codes, and operation status codes are initialized. The occurrence state of each base event is independently determined based on the occurrence probability of the base event. Then, the event node status codes and operation status codes are updated through the location mask to establish the event node status information and operation state in the current sampling computational environment. The event node status codes reflect the access status of all base event nodes in this round of sampling, the operation status codes reflect the triggering status of the corresponding base event, and the function node status codes are used to determine whether the function node participates in the computation. Based on the topological mapping relationship, it is determined in turn whether each function node meets the preset calculation conditions. When the calculation conditions are met, bitwise logical operations are performed on the event node status code and operation status code according to the input mask, output mask and logic gate type of the function node. The event node status information and operation status corresponding to the function node are iteratively updated to realize the logical propagation calculation of the fault tree. The sampling and logical propagation calculations are repeatedly performed, and the results of each round of calculations are recorded. When the cumulative number of samplings reaches the total number of samplings, the frequency of the target event being true in all calculation results is statistically analyzed to determine the probability of the target event occurring when the system fails. The target event includes a top event or an intermediate event.

2. The fault tree target event probability calculation method according to claim 1, characterized in that, The steps of acquiring the structural data of the fault tree, identifying the input-output dependencies between each event node and function node, and establishing the topological mapping relationship between the event nodes and the function nodes include: Analyze the structural information of the fault tree to determine event nodes and function nodes; Based on the connection relationship between the event node and the function node, identify the input and output events of each function node; A unique location mask is assigned to each event node, and a corresponding input mask is generated based on the location mask and the input event to identify the set of input events received by the function node, and a corresponding output mask is generated based on the location mask and the output event to identify the top event output by the function node; Based on the correspondence between the location mask, the input mask, and the output mask, a topological mapping relationship is established to characterize the input-output dependency between the event node and the function node, so as to form a computable representation of the fault tree logic structure.

3. The method for calculating the probability of target events in a fault tree according to claim 1, characterized in that, The step of determining the calculation parameters based on the topological mapping relationship includes: Based on the topological mapping relationship, the bottom event nodes in the fault tree are identified, and a corresponding occurrence probability parameter is set for each bottom event node; By combining the topological mapping relationship and the position mask corresponding to the bottom event node, an index correspondence relationship between the event node and the function node is established, which is used to realize the fast location of input-output relationship and logic propagation calculation in mask logic operation; Set a calculation accuracy threshold to limit the allowable error range of probability calculation, and determine the number of samplings to control sampling convergence based on the expected occurrence probability of the target event and the calculation accuracy threshold. Initialize the sampling index, which controls the execution order and result recording of the sampling loop.

4. The method for calculating the probability of target events in a fault tree according to claim 1, characterized in that, The steps of resetting the computational state of the fault tree in each round of sampling to re-establish the computational environment for the current sampling, and independently determining the occurrence state of each bottom event based on the occurrence probability of the bottom event, thereby establishing the event node state information and computational state in the current sampling computational environment, include: Initialize the function node status code, event node status code, and operation status code to clear the calculation results of the previous round of sampling; Each bottom event node is traversed sequentially, and independent random sampling is performed based on the occurrence probability parameter corresponding to the bottom event node to determine the occurrence status of each bottom event under the current sampling. When the occurrence status indicates that the bottom event has not occurred, the event node status code is updated according to the position mask of the bottom event; When the occurrence status indicates that a bottom event has occurred, the event node status code and the operation status code are updated according to the position mask of the bottom event. Repeat the sampling and state update of each bottom event node until all bottom event nodes have been sampled to form the event node state information and operation state under the current sampling.

5. The method for calculating the probability of target events in a fault tree according to claim 4, characterized in that, The step of determining whether each function node satisfies the preset calculation conditions based on the topological mapping relationship, and iteratively updating the event node state information and operation state corresponding to the function node according to the logic gate calculation rules of the function node to realize the logic propagation calculation of the fault tree, includes: The function nodes that are not identified as having been calculated are sequentially detected in the current sampled function node status codes, and the input events of the function node are determined based on the logical operation result between the input mask of the function node and the event node status code. When it is determined that not all input events of the function node have been determined, the state update operation related to the function node is not performed, the state identifier of the function node and its corresponding output are kept in the current state, and the next function node that has not been identified as having been calculated is detected. When it is determined that all input events of the function node are determined, the corresponding event node status code is updated according to the output mask of the function node, and the corresponding bit of the function node status code is marked as calculated. Based on the logic gate type of the function node, and according to the preset logic conditions, the corresponding logic operation is performed on the operation status code to update the operation status under the current sampling. The event node status code, the function node status code, and the operation status code after each function node completes its status update are used as the input basis for the next function node logic propagation calculation. The function node judgment and logic update are repeated until all function nodes under the current sampling have completed the calculation.

6. The method for calculating the probability of target events in a fault tree according to claim 5, characterized in that, The step of performing corresponding logical operations on the operation status code based on the logic gate type of the function node and according to preset logical conditions to update the operation status under the current sampling includes: When the logic gate of the function node is an AND gate, if the result of the logical AND operation between the input mask of the function node and the current operation status code is equal to the input mask, it is determined that the logical condition is met, and the logical OR operation between the operation status code and the output mask of the function node is performed to update the operation status of the corresponding output event. When the logic gate of the function node is an OR gate, if the result of the logical AND operation between the input mask of the function node and the current operation status code is not zero, it is determined that the logical condition is met, and the logical OR operation between the operation status code and the output mask of the function node is performed to update the operation status of the corresponding output event. When the logical condition is not met, the operation state update operation is not performed, and the operation state code remains in the previous round state.

7. The method for calculating the probability of target events in a fault tree according to claim 1, characterized in that, The step of repeatedly performing sampling and logical propagation calculations, recording the calculation results of each round, and determining the probability of the occurrence of the target event by statistically analyzing the frequency of the target event being true in all calculation results when the cumulative number of samplings reaches the total number of samplings includes: Initialize the sampling cycle counter to accumulate the number of samples; After each round of sampling, the value of the position corresponding to the target event in the current operation status code is recorded, and the value is used as the calculation result of that round. The sampling cycle counter increments, and when the current sampling count has not reached the total sampling count, the next round of sampling and logic propagation calculation continues. When the cumulative number of samplings reaches the total number of samplings, the ratio of the number of times the target event is true in all sampling results to the total number of samplings is used as the probability of the target event occurring.

8. An electronic device, characterized in that, The electronic device includes: One or more processors; and a memory storing computer program instructions, which, when executed, cause the processors to perform the fault tree target event probability calculation method as described in any one of claims 1-7.

9. A computer-readable storage medium having a computer program and / or instructions stored thereon, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the fault tree target event probability calculation method as described in any one of claims 1-7.

10. A computer program product comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the fault tree target event probability calculation method as described in any one of claims 1-7.

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