An inductive module, resonant cavity structure, oscillator, chip and device

Abstract

This invention discloses an inductor module, a resonant cavity structure, an oscillator, a chip, and a device, belonging to the field of integrated circuit technology. The inductor module includes 10 inductors in a symmetrical structure; inductors L1, L9, and L4 are connected in series in sequence, with one end of inductor L1 serving as port 1; one end of inductor L4 serving as port 2; and inductors L2, L... 10 Inductors L2 and L3 are connected in series in sequence, with one end of L2 serving as port 3; one end of L3 serving as port 4; and inductors L5 and L6... 10 Inductors L5, L6, L7, and L8 are connected in series in sequence, with one end of L5 serving as port 5 and one end of L8 serving as port 6. Inductors L6, L9, and L7 are also connected in series in sequence, with one end of L6 serving as port 7 and one end of L8 serving as port 8. Inductors L1 and L2 are coupled together, inductors L3 and L4 are coupled together, inductors L5 and L6 are coupled together, inductors L7 and L8 are coupled together, and inductors L9 and L1 are coupled together. 10 Mutual coupling. This invention employs a symmetrical inductor topology, solving the problem of asymmetry between the core inductor and the core inductor in a quad-core processor.

Description

Technical Field

[0001] This invention relates to a local oscillator generation circuit for mixing in a wireless communication system, and more particularly to an inductor module, a resonant cavity structure, an oscillator, a chip, and a device. Background Technology

[0002] To achieve ultra-wideband frequencies, the first existing technology uses a resonant cavity composed of two inductor and capacitor arrays connected in parallel, with the inductors mutually coupled. These two resonant cavities are connected in parallel via a shared power ground. By switching a switch, the coupling relationship between the two inductors is changed, resulting in two equivalent inductance values. Ultimately, under these two different equivalent inductance modes, by adjusting the capacitance values ​​in the capacitor array, two frequency bands with lower coverage are generated, achieving ultra-wideband frequency signal output. However, this scheme only has two modes, resulting in a narrow frequency range.

[0003] The second existing technical solution uses four identical inductor and capacitor arrays connected in parallel to form a resonant cavity. Differential cross-pair transistors are connected to the two ends of the resonant cavity respectively. The four resonant cavities are connected in parallel through mode switches to form a multi-core oscillator. There are two relationships between these four resonant cavities: (1) there is a strong coupling relationship between the inductors of the resonant cavities; (2) the resonant cavities are capacitively coupled through external capacitors. By switching the switches, the phase relationship of the waveform of each resonant cavity is changed, thereby changing the inductive coupling relationship and increasing / canceling the capacitive coupling relationship. Then, by adjusting the capacitor array, four frequency bands with low coverage are formed to achieve ultra-wideband frequency signal output. However, this solution has capacitive coupling and a large parasitic capacitance.

[0004] The third existing technical solution uses four identical inductor and capacitor arrays connected in parallel to form a resonant cavity. Differential cross pairs are connected to the two ends of the resonant cavity respectively. The four resonant cavities are connected in parallel through switches to form a multi-core oscillator. In these four resonant cavities, there are two relationships: 1) the two inductors at the top and bottom and the two inductors in the middle have strong inductive coupling relationships; 2) there is a common inductance between the two inductors in the middle. By changing the phase relationship of the oscillation waveform between the cores through mode switches, the inductive coupling relationship in relationship (1) and the generation and cancellation of the common inductance in relationship (2) are changed, generating four equivalent inductance modes. Then, by adjusting the capacitor array, four frequency bands with low coverage are generated to achieve ultra-wideband frequency signal output. However, in this solution, there is a problem of inductance mismatch between the inductors of the cores in the inductive coupling. Summary of the Invention

[0005] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide an inductor module, a resonant cavity structure, an oscillator, a chip, and a device.

[0006] The first technical solution adopted in this invention is:

[0007] An inductor module includes inductors L1, L2, L3, L4, L5, L6, L7, L8, L9, and L1. 10 Furthermore, the structure of these 10 inductors is symmetrical.

[0008] Inductors L1, L9, and L4 are connected in series in sequence, with one end of inductor L1 serving as port 1 and one end of inductor L4 serving as port 2.

[0009] Inductors L2, L 10 L2 and L3 are connected in series in sequence, with one end of inductor L2 serving as port 3 and the other end of inductor L3 serving as port 4.

[0010] Inductors L5, L 10 L5 and L8 are connected in series in sequence, with one end of inductor L5 serving as port 5 and the other end of inductor L8 serving as port 6.

[0011] Inductors L6, L9, and L7 are connected in series in sequence, with one end of inductor L6 serving as port 7 and one end of inductor L8 serving as port 8.

[0012] Among them, inductors L1 and L2 are coupled to each other, inductors L3 and L4 are coupled to each other, inductors L5 and L6 are coupled to each other, inductors L7 and L8 are coupled to each other, and inductors L9 and L... 10 They are mutually coupled.

[0013] Furthermore, the inductor module also includes functions for adjusting inductors L1 and L2, L3 and L4, L5 and L6, L7 and L8, L9 and L1. 10 The three sets of switch modules with coupling relationships;

[0014] The first set of switch modules includes switch SWE1 and switch SWO1; when SWE1 is closed and SWO1 is open, the coupling mechanism between L1 and L2, and between L3 and L4 is anti-coupling; when SWE1 is open and SWO1 is closed, the coupling mechanism between L1 and L2, and between L3 and L4 is positive coupling.

[0015] The second set of switch modules includes switch SWE3 and switch SWO3; when SWE3 is closed and SWO3 is open, the coupling mechanism between L5 and L6, and between L7 and L8 is anti-coupling; when SWE3 is open and SWO3 is closed, the coupling mechanism between L5 and L6, and between L7 and L8 is positive coupling.

[0016] The third set of switch modules includes switch SWE2 and switch SWO2; when SWE2 is closed, SWO2 is open, and when SWE1 and SWE3 are closed, SWO1 and SWO3 are open, L9 and L 10The coupling mechanism is anti-coupling; when SWE2 is open and SWO2 is closed, and when SWE1 and SWE3 are closed and SWO1 and SWO3 are open, L9 and L 10 The potentials at both ends are equal; therefore, L9 and L 10 Theoretically, they are not visible in the resonant cavity; when SWE2 is closed and SWO2 is open, and when SWE1 and SWE3 are open and SWO1 and SWO3 are closed, L9 and L 10 The coupling mechanism is positive coupling; when SWE2 is open and SWO2 is closed, and when SWE1 and SWE3 are open and SWO1 and SWO3 are closed, L9 and L 10 The potentials at both ends are equal; therefore, L9 and L 10 Theoretically, it cannot be seen in the resonant cavity.

[0017] Furthermore, the eight ports are also symmetrically matched, with port 1 and port 2 being symmetrically matched, port 3 and port 4 being symmetrically matched, port 5 and port 6 being symmetrically matched, and port 7 and port 8 being symmetrically matched.

[0018] Furthermore, inductors L1 and L2, inductors L3 and L4, inductors L5 and L6, inductors L7 and L8, inductors L9 and L... 10 They are all strongly coupled with a turns ratio of 1:1.

[0019] The second technical solution adopted in this invention is:

[0020] A resonant cavity includes four variable capacitor modules and the aforementioned inductor module, wherein the four capacitor modules and the four series branches in the inductor module respectively form four resonant cavities;

[0021] The two ends of the first variable capacitor module are connected to port 1 and port 2 respectively, forming a first parallel resonant cavity with inductors L1, L9 and L4;

[0022] The two ends of the second variable capacitor module are connected to port 3 and port 4 respectively, and are connected to inductors L2 and L... 10 L3 and L4 form the second parallel resonant cavity;

[0023] The two ends of the third variable capacitor module are connected to port 5 and port 6 respectively, and are connected to inductors L5 and L6. 10 L8 forms the third parallel resonant cavity;

[0024] The two ends of the fourth variable capacitor module are connected to port 7 and port 8 respectively, forming a fourth parallel resonant cavity with inductors L6, L9 and L7.

[0025] Furthermore, the variable capacitor module includes a capacitor array and a varactor unit connected in parallel;

[0026] The capacitor array is composed of switches S WPA controlled 5-bit switched capacitor array;

[0027] The variable capacitance tube unit includes two variable capacitance tubes connected in series, with a control voltage V input at the series connection point. TUNE .

[0028] Furthermore, the variable capacitor module includes a first capacitor array and a second capacitor array connected in parallel;

[0029] The first capacitor array is composed of switch S WP A controlled 5-bit switched capacitor array;

[0030] The second capacitor array is composed of switch S Wv A controlled 128-bit switched capacitor array.

[0031] It should be noted that the variable capacitor module of the present invention is not limited to two parallel branches; it can also employ a single capacitor branch or multiple (more than two) branches. For example, the variable capacitor module may only include the branch of the varactor unit, controlled by the input control voltage V. TUNE Control the capacitor value.

[0032] The third technical solution adopted in this invention is:

[0033] An oscillator includes four active drive modules, four variable capacitor modules, and the aforementioned inductor module;

[0034] The two ends of the first variable capacitor module are connected to port 1 and port 2 respectively, forming a first parallel resonant cavity with inductors L1, L9 and L4; the two ends of the first active drive module are connected to port 1 and port 2 respectively.

[0035] The two ends of the second variable capacitor module are connected to port 3 and port 4 respectively, and are connected to inductors L2 and L... 10 L3 and L4 form the second parallel resonant cavity; the two ends of the second active drive module are connected to port 3 and port 4 respectively;

[0036] The two ends of the third variable capacitor module are connected to port 5 and port 6 respectively, and are connected to inductors L5 and L6. 10 L8 forms the third parallel resonant cavity; the two ends of the third active drive module are connected to port 5 and port 6 respectively;

[0037] The two ends of the fourth variable capacitor module are connected to port 7 and port 8 respectively, forming a fourth parallel resonant cavity with inductors L6, L9 and L7; the two ends of the fourth active drive module are connected to port 7 and port 8 respectively.

[0038] Furthermore, the active drive module is implemented using differential cross-pair transistors, which include two NMOS transistors;

[0039] The first active driving module includes transistor M1 and transistor M2. The gate of transistor M1 and the drain of transistor M2 are both connected to port 2, and the gate of transistor M2 and the drain of transistor M1 are both connected to port 1.

[0040] The second active drive module includes transistor M3 and transistor M4. The gate of transistor M3 and the drain of transistor M4 are both connected to port 4, and the gate of transistor M4 and the drain of transistor M3 are both connected to port 3.

[0041] The third active drive module includes transistor M5 and transistor M6. The gate of transistor M5 and the drain of transistor M6 are both connected to port 6.

[0042] The fourth active drive module includes transistor M7 and transistor M8. The gate of transistor M7 and the drain of transistor M8 are both connected to port 8, and the gate of transistor M8 and the drain of transistor M7 are both connected to port 7.

[0043] Among them, inductors L9 and L 10 The tap is connected to the bias voltage V. DD The sources of all transistors are grounded.

[0044] Furthermore, the active driving module is implemented using a CMOS structure, which includes two NMOS transistors and two PMOS transistors;

[0045] The first active driving module includes NMOS transistor M1, NMOS transistor M2, and PMOS transistor M... 11 and PMOS transistor M 12 The gate of transistor M1 and the drain of transistor M2 are both connected to port 2, and the gate of transistor M2 and the drain of transistor M1 are both connected to port 1; transistor M 11 Gate and transistor M 12 The drains of transistors M are all connected to port 2. 12 Gate and transistor M 11 The drains of all terminals are connected to port 1;

[0046] The second active driving module includes NMOS transistor M3, NMOS transistor M4, and PMOS transistor M. 13 and PMOS transistor M 14 The gate of transistor M3 and the drain of transistor M4 are both connected to port 4, and the gate of transistor M4 and the drain of transistor M3 are both connected to port 3; transistor M 13 Gate and transistor M 14 The drains of all transistors are connected to port 4, transistor M 14 Gate and transistor M13 The drains of all terminals are connected to port 3;

[0047] The third active driving module includes NMOS transistor M5, NMOS transistor M6, and PMOS transistor M... 15 and PMOS transistor M 16 The gate of transistor M5 and the drain of transistor M6 are both connected to port 6, and the gate of transistor M6 and the drain of transistor M5 are both connected to port 5; transistor M 15 Gate and transistor M 16 The drains of all transistors are connected to port 6, transistor M. 16 Gate and transistor M 15 The drains of all terminals are connected to port 5;

[0048] The fourth active drive module includes NMOS transistor M7, NMOS transistor M8, and PMOS transistor M... 17 and PMOS transistor M 18 The gate of transistor M7 and the drain of transistor M8 are both connected to port 8, and the gate of transistor M8 and the drain of transistor M7 are both connected to port 7; transistor M 17 Gate and transistor M 18 The drains of all transistors are connected to port 8, transistor M 18 Gate and transistor M 17 The drains of all terminals are connected to port 7;

[0049] In this configuration, the sources of all NMOS transistors are grounded, and the sources of all PMOS transistors are connected to a bias voltage.

[0050] Furthermore, the oscillator also includes NMOS transistor M9 and NMOS transistor M 10 ;

[0051] The gate of transistor M9 is connected to the drain of transistor M1, and the drain outputs a signal V. out+ The source is grounded;

[0052] transistor M 10 The gate of transistor M2 is connected to the drain of transistor M2, and the drain output signal V. out- The source electrode is grounded.

[0053] The fourth technical solution adopted in this invention is:

[0054] A chip includes the aforementioned inductor module, the aforementioned resonant cavity, or the aforementioned oscillator.

[0055] The fifth technical solution adopted in this invention is:

[0056] An electronic device comprising the chip described above.

[0057] The beneficial effects of this invention are: It employs a symmetrical inductor topology, solving the problem of asymmetry in the core inductor in a quad-core processor. Optionally, the connection between the tap and the two ends of the differential pair is identical in both the inductor's inductance value and its topology, thereby achieving a symmetrical core inductor. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a structural diagram of the quad-core quad-mode voltage-controlled oscillator in Embodiment 1 of the present invention;

[0060] Figure 2 This is a schematic diagram of the inductor module in an embodiment of the present invention;

[0061] Figure 3 This is a schematic diagram of the inductive coupling principle in an embodiment of the present invention;

[0062] Figure 4 This is a schematic diagram of the tuning range test results in Embodiment 1 of the present invention;

[0063] Figure 5 This is a phase noise test curve of Embodiment 1 of the present invention at 17.995 GHz;

[0064] Figure 6 This is a phase noise test curve of Embodiment 1 of the present invention at 38.1287 GHz;

[0065] Figure 7 These are phase noise test diagrams at 1MHz and 10MHz frequency offsets at various frequency points according to Embodiment 1 of the present invention;

[0066] Figure 8 This is a test graph of FoM and FoMT values ​​at a frequency offset of 10MHz in Embodiment 1 of the present invention.

[0067] Figure 9 This is a chip diagram of a four-mode quad-core voltage-controlled oscillator based on switchable inter-core inductive coupling technology in this invention embodiment;

[0068] Figure 10 This is a structural diagram of the quad-core quad-mode voltage-controlled oscillator in Embodiment 2 of the present invention;

[0069] Figure 11This is a structural diagram of the quad-core quad-mode voltage-controlled oscillator in Embodiment 3 of the present invention;

[0070] Figure 12 This is a schematic diagram illustrating the implementation of switches SWE and SWO in Embodiment 1 of the present invention. Detailed Implementation

[0071] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0072] The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only and is not intended to limit the embodiments of this application. The singular forms "a," "described," and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise expressly limited, terms such as "set," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0073] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0074] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0075] In the description of this application, "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship.

[0076] To address the shortcomings of existing technical solutions, the present invention aims to solve the following technical problems:

[0077] (1) Solve the problem of excessive parasitic capacitance caused by capacitive coupling in mode adjustment;

[0078] (2) Solve the problem of core inductance and inductance asymmetry in quad-core processors;

[0079] (3) Solve the problem of inter-core inductance mismatch in different modes of ultra-wideband oscillators;

[0080] (4) Achieving low phase noise in CMOS process

[0081] To solve the technical problem (1), one technical solution adopted by this invention is: using a fully symmetrical quad-core inductor topology, four different equivalent inductance values ​​are achieved through a combination of two inductor coupling mechanisms. The first coupling mechanism involves mutual inductance M1 between the two inductors. By changing the phase relationship between the cores, the mutual inductance coefficient (M1 or -M1) is changed, thus switching between the two equivalent inductance values. The second coupling mechanism involves a common inductance between the inductors. By changing the phase relationship between the cores, the direction of the current in the two cores is changed, resulting in two states of the common inductance (cancellation / generation). In addition, there is also mutual inductance M2 between the two common inductors. As the direction of the common inductor current changes, the mutual inductance coefficient (M2 or -M2) is changed, thus strengthening / weakening the common inductance. Since these four equivalent inductance values ​​are all generated by changing the coupling between the inductors, there is no problem of introducing excessive parasitic capacitance.

[0082] To solve the technical problem (2), one technical solution adopted by the present invention is to adopt a symmetrical inductor topology, wherein the connection between the tap and the two ends of the differential pair is the same in terms of the inductance value and the inductor topology, thereby realizing a symmetrical core inductor.

[0083] To solve the technical problem (3), one technical solution adopted by the present invention is that each inductor between the cores can be affected by the above two inductor coupling mechanisms. Under the unified mode, the inductors between the cores can generate equal equivalent inductance, thereby avoiding the problem of mismatch in the inductance values ​​between the cores.

[0084] To solve the technical problem (4), one technical solution adopted by the present invention is: by connecting the four resonant cavities in parallel, a quad-core oscillator is realized. Compared with a single-core oscillator, the phase noise is theoretically optimized by 6dB, thereby reducing the phase noise of the oscillator.

[0085] The following detailed explanation is provided in conjunction with specific embodiments.

[0086] Example 1

[0087] See Figure 1 This embodiment provides a fully differential, low phase noise, ultra-wideband voltage-controlled oscillator (quad-core quad-mode ultra-wideband oscillator), and the specific circuit connection is as follows:

[0088] In the NMOS transistor, the gate of M1 is connected to the drain of M2, and the drain of M1 is connected to the gate of M2. The gate of M3 is connected to the drain of M4, and the drain of M3 is connected to the gate of M4. The gate of M5 is connected to the drain of M6, and the drain of M5 is connected to the gate of M6. The gate of M7 is connected to the drain of M8, and the drain of M7 is connected to the gate of M8. M9, M... 10 The gate of M1 is connected to the drain of M2, and the gate of M9 is connected to the drain of M2. 10 The drain is connected to the signal output V out+ V out- . M1, M2, M3, M4, M5, M6, M7, M8, M9, M 10 The source is grounded. (By C) P1 (C P3 C P5 C P7 C P2 (C P4 C P6 C P8 ) and S WP1 (S WP2 S WP3 S WP4 The two ends of the 5-bit switched capacitor array and the varactor C are composed of v1 (C v3 C v5 C v7 C v2 (C v4 C v6 C v8 Connecting at both ends, variable capacitance tube C v1 (C v3 C v5 C v7 C v2 (C v4 C v6 C v8 The common terminal of the signal is connected to the voltage control signal V. tune Inductors L1, L9, and L4 are connected in series and connected to C. P1 C P2 And C v1 C v2 They are connected in parallel to form a parallel resonant cavity. L1 connects the drain of M1 and the gate of M2, as well as the gate of M9. L4 connects the drain of M2 and the gate of M1, as well as M... 10 The gate of the inductor; inductors L2 and L10 L3 is connected in series with C P3 C P4 And C v3 C v4 They are connected in parallel to form a parallel resonant cavity. L2 connects the drain of M3 and the gate of M4, and L3 connects the drain of M4 and the gate of M3; inductors L5 and L6 are connected in parallel to form a parallel resonant cavity. 10 L8 is connected in series and connected to C P7 C P8 And C v7 C v8 The inductors are connected in parallel to form a parallel resonant cavity. L5 connects the drain of M7 and the gate of M8, and L8 connects the drain of M8 and the gate of M7. Inductors L6, L9, and L7 are connected in series and connected to C. P5 C P6 And C v5 C v6 They are connected in parallel to form a parallel resonant cavity. L6 connects the drain of M5 and the gate of M6, and L7 connects the drain of M6 and the gate of M5; L9 and L... 10 tap connected to V DD .

[0089] In this embodiment, L1 (L2, L5, L6) and L9 (L 10 L4 (L3, L8, L7) in series plus L9, L 10 A 10-port inductor with taps, power supply, and ground wires, such as... Figure 2 As shown, the interface sequence is as follows: ① and ② correspond to the positive terminal of L1 and the negative terminal of L4, respectively; ③ and ④ correspond to the positive terminal of L2 and the negative terminal of L3, respectively; ⑤ and ⑥ correspond to the positive terminal of L5 and the negative terminal of L8, respectively; ⑦ and ⑧ correspond to the positive terminal of L6 and the negative terminal of L7, respectively; ⑨ and ⑩ correspond to the power supply and ground, respectively. In the eight-port inductor, L1 and L2 are coupled to each other, L3 and L4 are coupled to each other, L5 and L6 are coupled to each other, L7 and L8 are coupled to each other, and L9 and L... 10 They are mutually coupled. Among them, they are all strongly coupled with a turns ratio of 1:1.

[0090] See Figure 1 In this embodiment, the active driving section is implemented using NMOS cross-pair transistors. The differential cross-pair transistors consist of two NMOS transistors (M1, M2, M3, M4, M5, M6, M7, and M8, respectively), which are used to provide negative resistance to the oscillator and maintain oscillation. DD Provides the required power supply voltage for the circuit, with DC current from V DD Starting from L9 and L respectively 10The current flows into the circuit, then through inductors L1, L2, L3, L4, L5, L6, L7, and L8 before exiting the inductor. It then flows through inductors M1 and M2, M3 and M4, M5 and M6, and M7 and M8 respectively, finally converging to ground. Four differential pairs of transistors are connected to the two ends of a parallel resonant cavity, which consists of inductors L1, L9, and L4 and a capacitor array C. P1 C P2 and variable capacitance tube C v1 C v2 Inductors L2, L 10 L3 and capacitor array C P3 C P4 and variable capacitance tube C v3 C v4 Inductors L6, L9, L7 and capacitor array C P5 C P6 It consists of varactors Cv5 and Cv6; inductors L5, L10, and L8; and capacitor arrays CP7 and CP8. The four resonant cavities are connected in parallel. Compared to a single-core VCO, the quad-core VCO formed by connecting four resonant cavities in parallel has a lower input impedance. Therefore, a large amount of current enters the resonant cavities, and a large amount of energy is stored in the inductors and capacitors of the resonant cavities, thus achieving extremely low phase noise.

[0091] In some embodiments, respectively by C P1 and C P2 and SW P1 C P3 and C P4 and SW P2 C P5 and C P6 and SW P3 C P7 and C P8 and SW P4 A five-bit switched capacitor array is used for coarse tuning of the oscillation frequency. This is achieved by changing the varactor capacitor C... V1 and C V2 C V3 and C V4 C V5 and C V6 C V7 and C V8 Control voltage V TUNE This enables continuous frequency tuning.

[0092] Furthermore, as a preferred embodiment, the switchable in-core inductive coupling technology allows for the adjustment of inductors L1 and L2, L3 and L4, L5 and L6, L7 and L8, L9 and L1. 10 The coupling relationship is implemented, such as Figure 3As shown, by switching SWE and SWO, the phase relationship of the inductors in each core is changed, thus altering the current flowing through the inductors and changing the coupling relationship (positive coupling / anti-coupling) between adjacent inductors, resulting in different equivalent inductances. Specifically, when SWE1 is closed and SWO1 is open, the coupling mechanism between L1 and L2, and L3 and L4 is anti-coupled; when SWE1 is open and SWO1 is closed, the coupling mechanism between L1 and L2, and L3 and L4 is positively coupled. When SWE3 is closed and SWO3 is open, the coupling mechanism between L5 and L6, and L7 and L8 is anti-coupled; when SWE3 is open and SWO3 is closed, the coupling mechanism between L5 and L6, and L7 and L8 is positively coupled. When SWE2 is closed and SWO2 is open, and when SWE1 and SWE3 are closed and SWO1 and SWO3 are open, the coupling mechanism between L9 and L... 10 The coupling mechanism is anti-coupling. When SWE2 is open, SWO2 is closed, and when SWE1 and SWE3 are closed, SWO1 and SWO3 are open, L9 and L 10 The potentials at both ends are equal; therefore, L9 and L 10 Theoretically, they are not visible in the resonant cavity; when SWE2 is closed and SWO2 is open, and when SWE1 and SWE3 are open and SWO1 and SWO3 are closed, L9 and L 10 The coupling mechanism is positive coupling. When SWE2 is open, SWO2 is closed, and when SWE1 and SWE3 are open, and SWO1 and SWO3 are closed, L9 and L 10 The potentials at both ends are equal; therefore, L9 and L 10 Theoretically, it is invisible within the resonant cavity. This technique achieves complete symmetry in the inductance of the four cores and the coupling between the cores, generating an equivalent inductance of the same value in each frequency mode, thus achieving high inter-core symmetry. By changing the equivalent inductance, four frequency bands with smaller coverage are generated, achieving broadband frequency output.

[0093] Specifically, switches SWE and SWO use two NMOS transistors as switching transistors, connected to the P and N terminals of the oscillator respectively. Figure 12 In this example, switches SWO and SWE are mode switches between two VCOs (CORE 1 and CORE 2), each composed of two NMOS transistors, SWO1 and SWO2, and SWE1 and SWE2, respectively. Specifically, the drain of SWO1 is connected to the P-terminal of CORE 2, and its source is connected to the P-terminal of CORE 1. The drain of SWO2 is connected to the N-terminal of CORE 2, and its source is connected to the N-terminal of CORE 1. Similarly, the drain of SWE1 is connected to the P-terminal of CORE 2, and its source is connected to the N-terminal of CORE 1; the drain of SWE2 is connected to the N-terminal of CORE 2, and its source is connected to the P-terminal of CORE 1.

[0094] The tuning range of this embodiment is 11.86–40.15 GHz, and the tuning range test curve is shown below. Figure 4 As shown. Figure 5 and Figure 6 The phase noise test results curves at oscillation frequencies of 17.995 GHz and 38.1287 GHz are shown respectively. Figure 7 The phase noise at various frequency points with frequency offsets of 1MHz and 10MHz is shown, where the phase noise at 1MHz is -100.5 to -112.8 dBc / Hz and at 10MHz is -124.5 to -134 dBc / Hz. The power consumption of this embodiment is 3.6 to 20.8 mW, and the FoM and FoM values ​​at 10MHz are also shown. T The values ​​are 180.3–190.7 dBc / Hz and 201–211 dBc / Hz, respectively. Figure 8 As shown. Figure 9 A photograph of a chip according to an embodiment of the present invention is shown, occupying a chip core area of ​​0.132 mm². 2 .

[0095] In summary, the embodiments of the present invention realize a differential voltage-controlled oscillator with an ultra-wideband frequency range and low noise. Compared with existing technical solutions, the present invention has at least the following advantages:

[0096] (1) This invention proposes an ultrawideband voltage-controlled oscillator based on switchable core inductive coupling technology, which solves the problem of asymmetric inductive coupling in voltage-controlled oscillators and achieves lower phase noise under wide frequency tuning conditions.

[0097] (2) This invention proposes an equivalent inductance switching technology based on inductive coupling. The switching of multiple modes of the oscillator can be achieved by changing the equivalent inductance alone, without the need to add an additional coupling capacitor, thus reducing the parasitic capacitance in the resonant cavity.

[0098] (3) This invention proposes a fully symmetrically coupled quad-core inductor layout, which solves the problem of inductance mismatch between cores due to the asymmetry of the inductor coupling mechanism during mode switching.

[0099] Example 2

[0100] See Figure 10 This embodiment provides an ultra-wideband oscillator based on a CMOS structure. Most of the structure is the same as the oscillator in Embodiment 1. The main difference is that the active driving part is implemented using a CMOS structure.

[0101] The active drive section consists of n-transistors M1 and M2, and p-transistor M... 11 M 12 n-tube M3 and M4 and p-tube M13 M 14 n-tube M5, M6 and p-tube M 15 M 16 n-tube M7, M8 and p-tube M 17 M 18 The CMOS structure consists of p-tubes and M-tubes. 11 M 12 M 13 M 14 M 15 M 16 M 17 M 18 The source is connected to the power supply V. DD The power supply is input from the p-transistor and the n-transistor is grounded, ensuring a high swing amplitude for the oscillator. When one of the PMOS and NMOS transistors is turned on, the other is necessarily turned off, maintaining a high degree of complementarity. Current is output from both the p-transistor and the n-transistor, achieving current multiplexing.

[0102] The resonant cavity in this embodiment has the same structure as the resonant cavity in Embodiment 1. The resonant cavity consists of L1, L2, L3, L4, L5, L6, L7, L8, L9, L... 10 An 8-port inductor composed of C p1 C p2 C p3 C p4 C p5 C p6 C p7 C p8 and switch S WP1 S WP2 S WP3 S WP4 The four capacitor arrays, plus the varactor C v1 C v2 C v3 C v4 C v5 C v6 C v7 C v8 Parallel quad-core resonant cavity.

[0103] Example 3

[0104] See Figure 11 This embodiment provides an ultra-wideband numerically controlled oscillator, which has most of the same structure as the oscillator in Embodiment 1. The main difference is that the variable capacitor module is implemented using two parallel capacitor arrays.

[0105] The resonant cavity consists of L1, L2, L3, L4, L5, L6, L7, L8, L9, L... 10 A 10-port inductor composed of Cp1 C p2 C p3 C p4 C p5 C p6 C p7 C p8 and switch S WP1 S WP2 S WP3 S WP4 Four five-bit capacitor arrays are formed, plus capacitor C v1 C v2 C v3 C v4 C v5 C v6 C v7 C v8 , and S Wv1 S Wv2 S Wv3 S Wv4 The quad-core resonant cavity is formed by four 128-bit switched capacitor arrays connected in parallel. The active drive section consists of NMOS cross-pair transistors M1, M2; M3, M4; M5, M6; and M7, M8. More precise control of the capacitance values ​​is achieved by controlling the 128-bit capacitor array with digital control signals.

[0106] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0107] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A resonant cavity structure, characterized in that, Includes four variable capacitor modules and an inductor module; The inductor module includes inductors L1, L2, L3, L4, L5, L6, L7, L8, L9, and L1. 10 Furthermore, the structure of these 10 inductors is symmetrical. Inductors L1, L9, and L4 are connected in series in sequence, with one end of inductor L1 serving as port 1 and one end of inductor L4 serving as port 2. Inductors L2, L 10 L2 and L3 are connected in series in sequence, with one end of inductor L2 serving as port 3 and the other end of inductor L3 serving as port 4. Inductors L5, L 10 L5 and L8 are connected in series in sequence, with one end of inductor L5 serving as port 5 and the other end of inductor L8 serving as port 6. Inductors L6, L9, and L7 are connected in series in sequence, with one end of inductor L6 serving as port 7 and one end of inductor L7 serving as port 8. Among them, inductors L1 and L2 are coupled to each other, inductors L3 and L4 are coupled to each other, inductors L5 and L6 are coupled to each other, inductors L7 and L8 are coupled to each other, and inductors L9 and L... 10 Mutual coupling; The two ends of the first variable capacitor module are connected to port 1 and port 2 respectively, forming a first parallel resonant cavity with inductors L1, L9 and L4; The two ends of the second variable capacitor module are connected to port 3 and port 4 respectively, and are connected to inductors L2 and L... 10 L3 and L4 form the second parallel resonant cavity; The two ends of the third variable capacitor module are connected to port 5 and port 6 respectively, and are connected to inductors L5 and L6. 10 L8 forms the third parallel resonant cavity; The two ends of the fourth variable capacitor module are connected to port 7 and port 8 respectively, forming a fourth parallel resonant cavity with inductors L6, L9 and L7; The inductor module also includes functions for adjusting inductors L1 and L2, L3 and L4, L5 and L6, L7 and L8, L9 and L1. 10 The three sets of switch modules with coupling relationships; The first set of switch modules includes switch SWE1 and switch SWO1; when SWE1 is closed and SWO1 is open, the coupling mechanism between L1 and L2, and between L3 and L4 is anti-coupling; when SWE1 is open and SWO1 is closed, the coupling mechanism between L1 and L2, and between L3 and L4 is positive coupling. The second set of switch modules includes switch SWE3 and switch SWO3; when SWE3 is closed and SWO3 is open, the coupling mechanism between L5 and L6, and between L7 and L8 is anti-coupling; when SWE3 is open and SWO3 is closed, the coupling mechanism between L5 and L6, and between L7 and L8 is positive coupling. The third set of switch modules includes switch SWE2 and switch SWO2; when SWE2 is closed, SWO2 is open, and when SWE1 and SWE3 are closed, SWO1 and SWO3 are open, L9 and L 10 The coupling mechanism is anti-coupling; when SWE2 is open and SWO2 is closed, and when SWE1 and SWE3 are closed and SWO1 and SWO3 are open, L9 and L 10 The potentials at both ends are equal; when SWE2 is closed and SWO2 is open, and when SWE1 and SWE3 are open and SWO1 and SWO3 are closed, L9 and L 10 The coupling mechanism is positive coupling; when SWE2 is open and SWO2 is closed, and when SWE1 and SWE3 are open and SWO1 and SWO3 are closed, L9 and L 10 The potentials at both ends are equal.

2. The resonant cavity structure according to claim 1, characterized in that, The variable capacitor module includes a capacitor array and a varactor unit connected in parallel. The capacitor array is a switch-controlled switched capacitor array; The variable capacitance tube unit includes two variable capacitance tubes connected in series, with a control voltage V input at the series connection point. TUNE .

3. The resonant cavity structure according to claim 1, characterized in that, The variable capacitor module includes a first capacitor array and a second capacitor array connected in parallel. The first capacitor array is composed of switch S WP A controlled m-bit switched capacitor array; The second capacitor array is composed of switch S Wv A controlled n-bit switched capacitor array; Where m and n are positive integers, and m < n.

4. An oscillator, characterized in that, It includes four active driving modules and the resonant cavity structure according to any one of claims 1-3; The two ends of the first active driver module are connected to port 1 and port 2, respectively; The two ends of the second active driver module are connected to port 3 and port 4 respectively; The two ends of the third active driver module are connected to port 5 and port 6 respectively; The two ends of the fourth active driver module are connected to port 7 and port 8, respectively.

5. An oscillator according to claim 4, characterized in that, The active drive module is implemented using differential cross-pair transistors, which include two NMOS transistors. The first active driving module includes transistor M1 and transistor M2. The gate of transistor M1 and the drain of transistor M2 are both connected to port 2, and the gate of transistor M2 and the drain of transistor M1 are both connected to port 1. The second active drive module includes transistor M3 and transistor M4. The gate of transistor M3 and the drain of transistor M4 are both connected to port 4, and the gate of transistor M4 and the drain of transistor M3 are both connected to port 3. The third active drive module includes transistor M5 and transistor M6. The gate of transistor M5 and the drain of transistor M6 are both connected to port 6. The fourth active drive module includes transistor M7 and transistor M8. The gate of transistor M7 and the drain of transistor M8 are both connected to port 8, and the gate of transistor M8 and the drain of transistor M7 are both connected to port 7. Among them, inductors L9 and L 10 The tap is connected to the bias voltage V. DD The sources of all transistors are grounded.

6. An oscillator according to claim 5, characterized in that, The active driving module is implemented using a CMOS structure, which includes two NMOS transistors and two PMOS transistors. The first active driving module includes NMOS transistor M1, NMOS transistor M2, and PMOS transistor M... 11 and PMOS transistor M 12 The gate of transistor M1 and the drain of transistor M2 are both connected to port 2, and the gate of transistor M2 and the drain of transistor M1 are both connected to port 1; transistor M 11 Gate and transistor M 12 The drains of transistors M are all connected to port 2. 12 Gate and transistor M 11 The drains of all terminals are connected to port 1; The second active driving module includes NMOS transistor M3, NMOS transistor M4, and PMOS transistor M. 13 and PMOS transistor M 14 The gate of transistor M3 and the drain of transistor M4 are both connected to port 4. transistor M 13 Gate and transistor M 14 The drains of all transistors are connected to port 4, transistor M 14 Gate and transistor M 13 The drains of all terminals are connected to port 3; The third active driving module includes NMOS transistor M5, NMOS transistor M6, and PMOS transistor M... 15 and PMOS transistor M 16 The gate of transistor M5 and the drain of transistor M6 are both connected to port 6, and the gate of transistor M6 and the drain of transistor M5 are both connected to port 5; transistor M 15 Gate and transistor M 16 The drains of all transistors are connected to port 6, transistor M. 16 Gate and transistor M 15 The drains of all terminals are connected to port 5; The fourth active drive module includes NMOS transistor M7, NMOS transistor M8, and PMOS transistor M... 17 and PMOS transistor M 18 The gate of transistor M7 and the drain of transistor M8 are both connected to port 8, and the gate of transistor M8 and the drain of transistor M7 are both connected to port 7; transistor M 17 Gate and transistor M 18 The drains of all transistors are connected to port 8, transistor M 18 Gate and transistor M 17 The drains of all terminals are connected to port 7; In this configuration, the sources of all NMOS transistors are grounded, and the sources of all PMOS transistors are connected to a bias voltage.

7. An oscillator according to claim 5 or 6, characterized in that, The oscillator also includes NMOS transistor M9 and NMOS transistor M. 10 ; The gate of transistor M9 is connected to the drain of transistor M1, and the drain outputs a signal V. out+ The source is grounded; transistor M 10 The gate of transistor M2 is connected to the drain of transistor M2, and the drain output signal V. out- The source electrode is grounded.

8. A chip, characterized in that, It includes the resonant cavity as described in any one of claims 1-3 or the oscillator as described in any one of claims 4-7.

9. An electronic device, characterized in that, Includes the chip described in claim 8.

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