Continuous time linear equalizer and high-speed serial communication receiver thereof

Abstract

The invention provides a continuous-time linear equalizer and a high-speed serial communication receiver thereof, and belongs to the technical field of integrated circuits, and the continuous-time linear equalizer comprises a plurality of differential input pairs with different input common-mode voltage ranges; the input selection circuit is configured to select one of all the differential input pairs to be used as a target differential input pair; the differential load circuit is coupled to the output end of the differential input stage module and has adjustable equivalent impedance; the load control circuit is configured to determine load configuration information in response to the input mode selection signal and adjust an equivalent impedance of the differential load circuit according to the load configuration information. According to the high-speed interface circuit, a linkage mechanism of input stage switching and load impedance adjustment is established through the input mode selection signal, corresponding calibration parameters are automatically called to eliminate offset voltages in different modes while the input common-mode voltage range is expanded, and the adaptability and the signal transmission quality of the high-speed interface circuit are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a continuous-time linear equalizer and its high-speed serial communication receiver applied to the receiver of a high-speed serial link (SerDes). Background Technology

[0002] In high-speed communication systems, the analog front-end circuitry at the receiver is responsible for compensating for and recovering signals attenuated by the channel. With the evolution of semiconductor process nodes and the diversification of interface protocol standards, the common-mode voltage output by the transmitter driver exhibits differentiated distribution characteristics, which places stringent physical layer requirements on the signal processing capabilities of the receiver circuitry under different voltage environments.

[0003] In existing technologies, to compensate for high-frequency channel losses, differential amplifier circuits based on source degeneration technology are typically used to implement the continuous time linear equalizer (CTLE) function. A typical circuit architecture includes a differential input stage, a source degeneration network, and a load stage. During the circuit design phase, based on a given technology library and a predetermined application scenario, designers usually utilize metal-oxide-semiconductor (MOSFET) field-effect transistors of specific polarities to construct differential input pairs, such as N-channel MOSFETs (NMOS) or P-channel MOSFETs (PMOS). During operation, the input signal drives the differential input pair to convert the voltage signal into a current signal, which is then used to establish the output voltage through the load stage. Simultaneously, a trimming circuit at the load end calibrates the DC offset voltage caused by manufacturing process variations.

[0004] However, circuits employing the aforementioned architecture have inherent limitations in their actual physical characteristics. First, the linear amplification of a transistor is highly dependent on the bias relationship between its gate-source voltage and threshold voltage. A transistor of a specific polarity can only maintain operation in the saturation region within a specific common-mode voltage range. When the common-mode voltage of the input signal deviates from the conduction threshold or operating range of that specific transistor, the transconductance efficiency of the transistor will nonlinearly decay or even turn off, causing the circuit to fail to maintain the expected gain and bandwidth characteristics. Second, since the DC offset voltage of a transistor originates from the random mismatch of physical parameters such as device size and doping concentration, this mismatch characteristic is strictly bound to its physical structure. Existing trimming circuits typically perform fixed compensation for the load based on a single configuration parameter. When the circuit's operating state or the operating point of the core device changes, the original compensation parameter no longer corresponds to the current mismatch characteristic, resulting in a residual DC voltage deviation at the output, which in turn causes the signal eye diagram to close. Summary of the Invention

[0005] To address the technical problems of existing continuous-time linear equalizers, such as limited input common-mode voltage operating range, incompatibility with input signals in different voltage domains, and inability to adaptively eliminate DC offset voltage under different operating conditions, which leads to a decline in signal transmission quality, this invention provides a continuous-time linear equalizer and its high-speed serial communication receiver.

[0006] In a first aspect, the present invention provides a continuous-time linear equalizer, comprising: The differential input stage module includes multiple differential input pairs with different input common-mode voltage ranges; An input selection circuit is configured to, in response to an input mode selection signal, select one of all said differential input pairs as the target differential input pair for current operation. A differential load circuit is coupled to the output of the differential input stage module, and the differential load circuit has an adjustable equivalent impedance. A load control circuit is configured to, in response to the input mode selection signal, determine load configuration information corresponding to the target differential input pair, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0007] In one possible implementation, the differential input pair is two, including: a first differential input pair and a second differential input pair.

[0008] In one possible implementation, the first differential input pair consists of PMOS transistors and the second differential input pair consists of NMOS transistors; The input common-mode voltage range of the first differential input pair is higher than that of the second differential input pair.

[0009] In one possible implementation, the load control circuit includes a storage unit; The storage unit is used to store calibration codes corresponding to each of the differential input pairs; The load control circuit is configured to read the storage unit and use the calibration code corresponding to the target differential input pair as the load configuration information to adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0010] In one possible implementation, the storage unit includes a first register group and a second register group, and the load control circuit further includes a multiplexer; The first register group stores a first calibration code corresponding to the first differential input pair, and the second register group stores a second calibration code corresponding to the second differential input pair; The multiplexer is controlled by the input mode selection signal to switch the output between the first register group and the second register group.

[0011] In one possible implementation, the differential load circuit includes a variable resistor array; The load configuration information is used to adjust the resistance value of the variable resistor array so that when the differential signal input to the continuous-time linear equalizer is zero, the differential output voltage of the continuous-time linear equalizer is substantially zero.

[0012] In one possible implementation, the continuous-time linear equalizer further includes: A configurable equalization network, coupled to the signal amplification path of the continuous-time linear equalizer, is configured to adjust its equivalent impedance in response to an equalization control signal to set the low-frequency gain and high-frequency gain in the frequency response characteristics of the CTLE.

[0013] In one possible implementation, the configurable equalization network includes a resistor array and / or a capacitor array: The resistor array includes multiple resistor elements that are controlled and connected by a first switch; The capacitor array includes multiple capacitor elements connected under the control of a second switch; The equalization control signal adjusts the equivalent impedance by controlling the opening and closing states of the first switch and / or the second switch.

[0014] In one possible implementation, the continuous-time linear equalizer has a first gain in frequency bands below the operating frequency; and a second gain higher than the first gain in frequency bands above the operating frequency.

[0015] In one possible implementation, the continuous-time linear equalizer further includes a transmission gate structure; The transmission gate structure is coupled between the signal input pad of the continuous-time linear equalizer and the differential input stage module. The transmission gate structure is configured to provide a signal path when the continuous-time linear equalizer is in operation, and to provide a high-impedance isolation or electrostatic discharge protection path when the continuous-time linear equalizer is not in operation.

[0016] In one possible implementation, the transmission gate structure includes NMOS transmission transistors and PMOS transmission transistors connected in parallel; The input selection circuit controls the on / off state of the signal path by controlling the gate voltages of the NMOS and PMOS transmission transistors.

[0017] In one possible implementation, the input mode selection signal, the load configuration information, and the equalization control signal are all digital signals that can be configured via software programming.

[0018] In a second aspect, the present invention provides a high-speed serial communication receiver, including a continuous-time linear equalizer as described in any of the first aspects.

[0019] Compared with the prior art, the continuous-time linear equalizer and its high-speed serial communication receiver provided by the present invention have the following advantages: (1) By setting up multiple differential input pairs with different input common-mode voltage ranges and using an input selection circuit to select one to enable, the present invention breaks the limitation of the input voltage range of a single transistor type, enabling the continuous-time linear equalizer to flexibly adapt to different input common-mode voltages, significantly improving the versatility of the circuit and its compatibility with upstream drivers.

[0020] (2) This invention innovatively establishes a linkage mechanism between input mode selection and load impedance adjustment. The load control circuit can automatically call up the load configuration information (such as calibration code) that matches the target differential input pair according to the current input mode selection signal. This linkage mechanism ensures that no matter which input mode is switched to, the load control circuit can obtain accurate DC offset calibration for the device characteristics in that mode, thereby ensuring that the output always maintains DC balance, effectively preventing eye diagram closure and reducing the bit error rate.

[0021] (3) The present invention achieves flexible programming of frequency response characteristics, input mode and load calibration through a fully digital control method, such as register configuration. Combined with the high impedance isolation and electrostatic protection functions provided by the transmission gate structure, the reliability and flexibility of system integration are further improved. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the CTLE circuit structure commonly used in existing technologies.

[0024] Figure 2 This is a schematic diagram of the circuit structure of CTLE provided by the present invention.

[0025] Figure 3 This is a schematic diagram of the overall architecture of CTLE provided by the present invention.

[0026] Figure 4 This is a schematic diagram showing the connection relationship between the load control circuit and the differential load circuit provided by the present invention.

[0027] Figure 5 This is a schematic diagram of the structure of the high-speed serial communication receiver provided by the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] It should be noted that in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The terms "upper," "lower," "front," "rear," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0031] In high-speed serial communication systems, signals are affected by channel attenuation and distortion during transmission, leading to decreased signal quality and increased bit error rate. This attenuation is particularly severe at high frequencies because the physical characteristics of the channel (e.g., cables, backplane traces) exhibit the characteristics of a low-pass filter. The role of a CTLE (Channel-to-Low-Pass Filter) is to compensate for channel attenuation and restore signal integrity. Simply put, a CTLE can be viewed as an inverse filter that not only enhances high-frequency signals but also moderately attenuates low-frequency signals, thereby offsetting the adverse effects of the channel. This allows the receiver to more accurately recover the original data.

[0032] The skin effect refers to the phenomenon where the current density of alternating current flowing in a conductor decreases exponentially with increasing conductor depth. In semiconductors, the current of high-frequency signals (such as radio frequency and microwave signals) tends to concentrate within a thin layer on the surface of the material, resulting in a significant reduction in the current density inside the conductor. Common high-pass filter (CTLE) is primarily used to address the problem of higher frequency attenuation than lower frequency attenuation during signal transmission due to the skin effect and dielectric loss. This frequency-dependent loss causes signal pulses to spread and overlap, generating inter-symbol interference (ISI), leading to eye diagram closure at the receiver and increased bit error rate. Essentially, a CTLE is an analog high-pass filter (or one with peaked frequency response). It compensates for high-frequency losses by providing higher gain to the high-frequency components of the signal than to the low-frequency components, flattening the frequency response of the entire transmission link, thereby reducing ISI and reopening the eye diagram. The value of CTLE lies in its purely analog implementation, enabling real-time processing of high-speed signals without digital sampling, and relatively low power consumption. However, it also amplifies high-frequency noise. Therefore, CTLE is often used in combination with digital equalization technologies such as Decision Feedback Equalizer (DFE) to form a hybrid equalization scheme to achieve better overall performance.

[0033] Figure 1 This is a schematic diagram of a CTLE circuit structure commonly used in existing technologies, such as... Figure 1 As shown, the differential input transistors M1 and M2 of the differential pair are typically NMOS transistors, receiving the differential input signal V. in+ and V in- Current sources M3 and M4 provide bias current for the differential pair. Source degradation resistor R... s and source degradation capacitor C s The constructed source degradation network determines the equalization characteristics of CTLE and adjusts the gain compensation range. Among them, R... s The degree to which low-frequency attenuation is affected by C s The load resistance R affects the degree of high-frequency enhancement. L Located at the output terminal, it affects the output voltage V. out .

[0034] according to Figure 1 As shown, the key to understanding the working principle of CTLE, which is commonly used in existing technologies, lies in understanding the source degradation resistance R. s and source degradation capacitor C s The resulting frequency-dependent impedance: 1) In low-frequency / DC operating mode, i.e., when the input signal frequency is very low, or even a DC signal, C s The impedance is extremely high, equivalent to an open circuit, at which point the current can only flow through R.s Therefore, the total impedance of the source degenerate network is R. s The resistance value of R. s The presence of this effect creates a negative feedback effect, significantly reducing the circuit's voltage gain. This can be understood as a portion of the input signal's energy being consumed by R. s This limits the amplification capability. Therefore, in low-frequency / DC operation, the gain of CTLE is relatively low, and this gain is determined by R. s and R L The ratio is roughly determined in order to attenuate low-frequency components.

[0035] 2) In high-frequency operating mode, i.e. when the input signal frequency is very high, C s The impedance becomes very small, approaching a short circuit, at which point R s C s The circuit is "short-circuited" or "bypassed." Current will preferentially flow through the Cs path, which has extremely low impedance. Therefore, the total impedance of the source-degraded network is approximately zero, and the CTLE is equivalent to an ideal differential amplifier without source degradation. Thus, in high-frequency operation, the CTLE's gain reaches its maximum value and is almost unaffected by R. s and C s The gain is mainly influenced by the transistor's own transconductance (gm) and load resistance R. L The decision was made to enhance (or not attenuate) the high-frequency components.

[0036] 3) In the mid-frequency transition region, i.e., as the input signal frequency changes from low to high, C s The impedance gradually decreases from infinity to zero. Therefore, the total impedance of the source degenerate network also smoothly decreases from R... s Reducing it to zero causes the total gain of CTLE to smoothly transition from a low-gain state to a high-gain state as the input signal frequency increases. The inflection point frequency at which this gain begins to rise (called the zero point) is f. zero By R s and C s The product determines: f zero ≈1 / (2 R s C s ).

[0037] In summary, Figure 1 The working principle of the existing CTLE can be summarized as follows: it can be regarded as a special amplifier, and its gain curve exhibits the characteristics of a high-pass filter that attenuates low frequencies and allows high frequencies to pass. Through R... s The low-frequency portion of the attenuated signal is attenuated through C. s Bypass R at high frequencys This allows high-frequency signals to achieve maximum gain. In high-speed communication, the transmission channel (such as a cable) itself acts like a low-pass filter, severely attenuating the high-frequency components of the signal. This CTLE circuit can indeed provide the opposite frequency response, actively boosting (or compensating) the high-frequency components attenuated by the channel, while preventing low-frequency components from being over-amplified. Ultimately, this allows the signal at the receiving end to recover a clearer waveform, thereby compensating for channel loss and reducing the bit error rate.

[0038] However, the existing CTLE has very obvious drawbacks, mainly in the following aspects: 1) The input common-mode voltage range depends on the type of input transistor in the design, and its applicability is limited.

[0039] NMOS transistors require their gate (input) voltage to be higher than their source voltage by a certain threshold voltage to conduct. Simultaneously, to ensure they operate in amplification mode, their input voltage cannot be too high, otherwise it will squeeze the voltage space at the output. This makes the NMOS transistor input stage more suitable for processing input signals with low DC levels. However, if a PMOS transistor is used as the input transistor in the design, the situation is reversed. PMOS transistors are more suitable for processing input signals with higher DC levels (closer to the supply voltage VDD). Therefore, once the input transistor type is selected as either an NMOS or PMOS input transistor during the design, this CTLE can only efficiently process signals within a specific voltage range.

[0040] In a complex System-on-a-Chip (SoC), different functional modules may be designed by different teams or come from different IP vendors. Their DC bias (common-mode voltage) output signals can vary widely. If a CTLE can only accept input signals in the range of, for example, 0.2V to 0.6V, then when an upstream module outputs a 0.9V input signal, this CTLE will not be able to interface properly with it.

[0041] Therefore, the rigid hardware design results in the lack of flexibility and versatility at the electrical interface level of the existing CTLE, making it impossible for it to become a widely reusable IP module.

[0042] 2) Increasing bandwidth often requires increasing current, resulting in higher power consumption.

[0043] The bandwidth of CTLE (which can be understood as the highest signal frequency it can handle) is ∝ 1 / (RL) Cload is related to several factors, the most important of which is the R of the output node. C Time constant. Where Cload is the total capacitance at the output (including the input capacitance and parasitic capacitance of the next stage circuit).

[0044] To achieve higher bandwidth (i.e., to handle faster input signals), a direct approach is to reduce the load resistance R. L However, the gain of the circuit is approximately equal to gm × R. L Where gm (transconductance) is the amplification capability of the input transistor. When R is decreased... L When increasing bandwidth, the gain decreases. To maintain sufficient gain, gm must be increased. The transistor's gm is closely related to the bias current flowing through it (provided by M3 and M4), and is usually proportional to the current. Therefore, to increase gm, the operating current of the entire circuit must be increased, and a larger operating current means higher power consumption.

[0045] 3) The compensation does not have an adaptive algorithm, so the three major variables affecting chip performance (process, voltage and temperature, PVT) have a significant impact.

[0046] Specifically, this refers to microscopic physical variations that occur during chip manufacturing. Even on the same wafer, transistors in one corner may exhibit slightly different characteristics than those in another. This can lead to... Figure 1 R in s C s R L The actual values ​​and transistor characteristics deviate from the design values.

[0047] The supply voltage of a chip is not absolutely constant and fluctuates. These fluctuations directly affect the operating point and current of the transistors, thus altering the gain and frequency response of the CTLE. Furthermore, the chip manufacturing process also contributes to gain drift in the CTLE. Additionally, the chip generates heat during operation, and ambient temperature changes significantly alter transistor mobility and resistance, again causing drift in the CTLE's equalization characteristics.

[0048] like Figure 1 The CTLE used in the prior art shown is generally a static circuit whose characteristics are determined by physical components, and it has no sensing and feedback mechanism to cope with the changes brought about by PVT.

[0049] 4) Offset affects the shape of the eye diagram. An eye diagram is a graph on an oscilloscope formed by superimposing numerous digital signal waveforms. The open area in the center of the eye diagram represents the margin for signal decision. The larger and clearer the eye, the better the signal quality and the stronger the anti-interference capability.

[0050] Offset is an undesirable DC voltage difference present at the differential output. Its impact on the eye diagram is mainly reflected in: Because of the vertical closure (reduced eye height), the offset shifts the entire eye diagram vertically. The originally symmetrical "1" and "0" levels become asymmetrical. This reduces the voltage margin for decision-making. The receiver is more prone to errors when distinguishing between high and low levels.

[0051] Horizontal closure (increased jitter): Voltage deviation causes a shift in the timing of the input signal crossing the decision threshold (zero level). This time uncertainty is called deterministic jitter. It reduces the time margin (i.e., eye width) of the decision.

[0052] The height and width of the eye diagram are key metrics for evaluating the performance of a communication system. Eye height represents noise immunity, while eye width represents jitter immunity. Offset compresses the shape of the eye diagram in both dimensions, making the eye smaller. A small eye means the system is very fragile; any additional noise or jitter can cause data transmission errors, i.e., a spike in the bit error rate (BER).

[0053] Figure 2 This is a schematic diagram of the circuit structure of CTLE provided by the present invention, as shown below. Figure 2 As shown, in view of the above-mentioned problems existing in the prior art, the present invention provides a new CTLE, which mainly makes the following improvements: (1) By using the digital control signal (REG_IN_SEL signal) to control the input selection switch Tgate, a differential input pair with different input common mode voltage ranges can be selected as the input stage.

[0054] For example, considering the different characteristics of PMOS and NMOS transistors, PMOS transistors are better suited for processing signals close to the power supply voltage, while NMOS transistors are better suited for processing signals close to ground. By selecting the appropriate input type, the dynamic range of the input signal can be maximized, thus improving CTLE performance.

[0055] (2) The equalization characteristics of CTLE can be flexibly adjusted through the configurable equalization network (controlled by REG_R_SEL and REG_C_SEL) to adapt to different channel conditions. This adjustability allows CTLE to maintain optimal performance in different working environments.

[0056] Specifically, by adjusting the values ​​of REG_R_SEL and REG_C_SEL, the frequency response curve of CTLE can be changed to better match the channel characteristics. When the channel characteristics change, the equalization effect can be optimized by reconfiguring the values ​​of REG_R_SEL and REG_C_SEL, thereby improving signal quality.

[0057] (3) The input link offset can be eliminated by controlling the value of the adjustable load resistor through TRIM_CODEP and TRIM_CODEN.

[0058] Specifically, by adjusting the values ​​of TRIM_CODEP and TRIM_CODEN, the output voltage of the CTLE can be changed to be closer to the desired value. This can reduce the bit error rate and improve the reliability of the CTLE.

[0059] (4) The values ​​of REG_R_SEL and REG_C_SEL can be configured in software according to the channel characteristics to change the zero position and achieve adaptive compensation effects.

[0060] Specifically, the REG_R_SEL and REG_C_SEL can be configured in software, allowing the CTLE to dynamically adjust according to actual channel conditions without requiring manual adjustment of hardware parameters. This greatly simplifies the system design and debugging process and improves the flexibility of the CTLE.

[0061] The following is combined with Figures 2-5 The content shown describes in detail the continuous-time linear equalizer and its high-speed serial communication receiver provided by this invention.

[0062] Figure 3 This is a schematic diagram of the overall architecture of CTLE provided by the present invention, as shown below. Figure 3 As shown, this embodiment provides a continuous-time linear equalizer, which mainly includes, but is not limited to: The differential input stage module includes multiple differential input pairs with different input common-mode voltage ranges; An input selection circuit is configured to, in response to an input mode selection signal, select one of all said differential input pairs as the target differential input pair for current operation. A differential load circuit is coupled to the output of the differential input stage module, and the differential load circuit has an adjustable equivalent impedance. A load control circuit is configured to, in response to the input mode selection signal, determine load configuration information corresponding to the target differential input pair, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0063] This embodiment provides that CTLE can be integrated as an independent analog IP core into various systems on a chip (SoC), or as a front-end module of a high-speed serial communication receiver (such as a SerDes Receiver).

[0064] The differential input stage module is a functional unit that integrates multiple differential input pairs, such as... Figure 3The differential input pairs shown are 1, 2, and N. "Multiple" here refers to two or more pairs. Each differential input pair is used to convert the input differential voltage signal into a differential current signal.

[0065] Different differential input pairs have different input common-mode voltage ranges, meaning that each differential input pair maintains normal amplification characteristics within a different common-mode voltage range. For example, differential input pair 1 can effectively handle input signals close to the high supply voltage (VDD), while differential input pair 2 can effectively handle input signals close to the low supply voltage (GND or VSS). This difference in input common-mode voltage range can be achieved by using transistors with different conductivity types (e.g., PMOS and NMOS transistors), transistors with different threshold voltages, or transistors with different physical sizes, thus enabling the entire differential input stage module to cover a wider voltage operating range.

[0066] An input selection circuit is a hardware circuit that selects the input path. Its physical implementation can be a multiplexer, an array of analog switches, or a bias current guiding circuit controlled by logic gates. The control terminal of the input selection circuit receives an input mode selection signal. This signal can be an instruction signal—a digital code written to an internal register by an external processor via a bus—or a level signal provided by an upstream circuit, informing the input selection circuit which differential input pair should be selected for operation.

[0067] In this embodiment, the input selection circuit is configured to respond to the input mode selection signal, meaning that when the logic state of the input mode selection signal changes, the input selection circuit will perform a corresponding switching action.

[0068] The specific switching action includes: selectively activating one of all differential input pairs as the target differential input pair for current operation. Activating a differential input pair can be achieved by directing the main bias current to the selected target differential input pair while simultaneously cutting off the bias current of the other unselected differential input pairs, thus ensuring that only one set of differential input pairs is consuming static power and processing signals at any given time.

[0069] The differential load circuit is coupled to the output of the differential input stage module. This coupling can be a direct electrical connection; for example, the drain output of the differential input stage module can be directly connected to the input of the differential load circuit. The function of the differential load circuit is to convert the differential current signal output from the differential input stage module into a differential voltage signal.

[0070] It should be noted that the differential load circuit used has an adjustable equivalent impedance, which can be changed according to an external control signal. For example... Figure 3 As shown, it can contain a variable resistor array. The equivalent impedance can be adjusted by selectively connecting or disconnecting parallel resistive elements through a digitally controlled switch array, thereby changing the overall parallel equivalent resistance value of the differential load circuit.

[0071] The load control circuit is as follows Figure 3 The digital control and calibration logic shown is configured to respond to an input mode selection signal, meaning its operating logic is associated with the input mode selection signal. When the load control circuit receives the input mode selection signal, it performs an action to determine the load configuration information corresponding to the target differential input pair.

[0072] The method for determining the load configuration information here can be: using the value of the input mode selection signal as the address or index in a pre-set lookup table or memory to find the pre-stored load configuration information that matches the mode.

[0073] The load configuration information here is a set of information used to characterize and set the target state of the differential load circuit, and its specific form can be varied.

[0074] In one possible implementation, the load configuration information may be an analog voltage or analog current signal generated by a digital-to-analog converter (DAC) inside the load control circuit, which directly controls the on-resistance of an active load (such as a MOSFET operating in the linear region).

[0075] In another possible implementation, the load configuration information is a set of digital codes, such as binary codes, that represent the desired load impedance value.

[0076] As an optional embodiment, the determined load configuration information can also be physical configuration status information. After determining the load configuration information, the load control circuit performs the action of adjusting the equivalent impedance of the differential load circuit according to the load configuration information. The adjustment method adopted can be that the load control circuit applies the load configuration information (such as digital code) as a control signal to the control terminal of the differential load circuit (such as a variable resistor array), driving the switch array therein to switch, thereby accurately adjusting the equivalent impedance of the differential load circuit to the value corresponding to the load configuration information.

[0077] The CTLE provided by this invention establishes a linkage between the input mode selection signal, the input selection circuit, and the load control circuit. This allows the CTLE to automatically and appropriately adjust its load impedance while switching input differential pairs to adapt to different input common-mode voltages. This, in turn, specifically compensates for the inherent offset voltage introduced by different differential input pairs, ensuring the signal integrity of the circuit over a wide voltage input range.

[0078] As an optional embodiment, the differential input pair is two, including: a first differential input pair and a second differential input pair.

[0079] Specifying two differential input pairs is a preferred technical choice derived from a trade-off between overall circuit performance, area overhead, and control logic complexity. Specifically, in current mainstream high-speed serial interface standards such as PCIe, USB, and Ethernet, despite the variety of protocol versions, the output common-mode voltage of their physical layer transmit drivers can generally be categorized into two main types: one is a high common-mode level close to the high supply voltage VDD, and the other is a low common-mode level close to ground GND. Therefore, employing two differential input pairs, each optimized for these two voltage ranges, can achieve compatibility coverage for the vast majority of application scenarios with minimal hardware resource cost, possessing extremely high engineering and commercial value.

[0080] Those skilled in the art will understand that the differential input pairs are not limited to two. In other embodiments, three or more differential input pairs can be configured to meet more complex application requirements. For example, a third differential input pair, constructed using a zero-threshold transistor, can be added to efficiently handle the intermediate common-mode voltage that lies precisely between high and low levels. Alternatively, in systems requiring extremely low-power standby modes, a fourth differential input pair, designed with a sub-threshold transistor and characterized by slower speed but extremely low static power consumption, can be added. These all fall within the scope of protection of this invention.

[0081] In one alternative embodiment, by setting up two core paths—a first differential input pair and a second differential input pair—the basic architecture for achieving wide-range input adaptation of the entire circuit is formed. This dual-path design is key to solving the technical pain point of limited input range in traditional CTLE circuits. Furthermore, it also achieves a circuit implementation scheme that achieves an optimal balance between performance coverage and resource consumption.

[0082] As an alternative embodiment, in order to efficiently construct two input paths with significantly different input common-mode voltage ranges, the most basic and complementary device types in CMOS technology are employed: the first differential input pair consists of PMOS transistors, while the second differential input pair consists of NMOS transistors.

[0083] like Figure 2 As shown, the PMOS differential input pair and the NMOS differential input pair are connected in parallel. The gate terminals of both receive the differential signal input from the external source, while the drain terminals of both are connected to the subsequent differential load circuit.

[0084] The technical principle behind this design is rooted in the fundamental physical characteristics of MOS transistors. NMOS transistors require a significantly higher gate voltage than source voltage to conduct, making them suitable for handling low common-mode signals close to ground (GND). When the common-mode voltage of the input signal is in, for example, a low range of 0.2V to 0.6V, the transistors in the NMOS differential input pair can easily remain in the saturation region, providing a stable and sufficiently large transconductance (gm), thus ensuring effective signal amplification.

[0085] In contrast, PMOS transistors require their gate voltage to be significantly lower than their source voltage to turn on. In typical circuit designs, the source of a PMOS differential input pair is usually connected to a high supply voltage VDD, making it suitable for handling high-level signals with common-mode levels close to VDD. When the common-mode voltage of the input signal is in, for example, a high-level range of 0.8V to 1.2V, the PMOS differential input pair enters its optimal operating state, also providing ideal signal amplification performance.

[0086] Based on the aforementioned physical principles, this embodiment employs a complementary design of PMOS and NMOS transistors, naturally resulting in a higher input common-mode voltage range for the first differential input pair compared to the second differential input pair. This is not a simple stacking of devices, but rather a clever combination of the advantageous operating ranges of the two types of transistors through a deep understanding of their physical characteristics. This expands the effective input voltage window of the entire CTLE from a single narrow range to a broad range covering low to high levels.

[0087] Those skilled in the art will understand that this is not the only way to achieve different input common-mode ranges. In other embodiments, two differential input pairs of the same conductivity type (e.g., both NMOS) but with different threshold voltages can also be used. For example, an NMOS differential input pair with a standard threshold voltage and an NMOS differential input pair with a low threshold voltage can be combined; their optimized operating ranges will also differ, thus achieving the goal of widening the input common-mode voltage range.

[0088] In summary, this embodiment directly and efficiently solves the fundamental problem of limited input voltage range in existing CTLE circuits by constructing two differential input pairs using PMOS and NMOS transistors respectively. When the input mode selection signal (REG_IN_SEL) switches, the circuit can select the physical path most suitable for the current input signal common-mode level, ensuring that the signal amplification stage operates at its most efficient and linear state in any supported input mode, providing high-quality input for subsequent signal processing.

[0089] Based on the content of the embodiments, as an optional embodiment, the load control circuit includes a storage unit; The storage unit is used to store calibration codes corresponding to each of the differential input pairs; The load control circuit is configured to read the storage unit and use the calibration code corresponding to the target differential input pair as the load configuration information to adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0090] Considering the use of PMOS and NMOS transistors, two differential input pairs with vastly different physical characteristics, an inevitable technical challenge arises: due to inherent and random process variations during manufacturing, these two different differential input pairs will each introduce DC offsets of completely independent magnitude and direction. Therefore, simply using a fixed set of calibration parameters according to existing technology will inevitably fail to accurately compensate for the offsets in both modes simultaneously.

[0091] To address this technical challenge, this invention proposes an innovative solution: the load control circuit includes a storage unit. The function of this storage unit is to establish and store unique calibration codes for each of the two differential input pairs with different physical characteristics.

[0092] The calibration code is a specific digital representation of the load configuration information in this embodiment. The calibration code can be a set of digital codes, which are iteratively calculated using a closed-loop feedback algorithm during the calibration phase of chip final testing or system power-on initialization. For example, when an NMOS differential input pair is enabled, the calibration algorithm finds a set of digital codes that can precisely bring its output offset voltage to zero and defines it as "Group A Code"; similarly, when switching to a PMOS differential input pair, the algorithm is run independently again to obtain another completely different set of digital codes, which is defined as "Group B Code".

[0093] like Figure 2 As shown, during real-time operation, the load control circuit is configured to read the storage unit and use the calibration code corresponding to the target differential input pair as the load configuration information to adjust the equivalent impedance of the differential load circuit. Figure 2 The input mode selection signal REG_IN_SEL shown not only controls the transmission gate Tgate switch to select the physical input path, but is also sent to the load control circuit. The logic inside the load control circuit will accurately retrieve the corresponding calibration code from the memory cell based on the value of REG_IN_SEL (for example, '0' represents NMOS mode and '1' represents PMOS mode), that is, '0' corresponds to Group A Code and '1' corresponds to Group B Code.

[0094] The specific physical implementation of the storage unit can vary. In one optional embodiment of this application, the storage unit consists of a set of programmable registers. This SRAM-based implementation offers high flexibility within the system, allowing the software to rewrite and update the calibration code at any time.

[0095] In other possible embodiments, the storage unit can also be non-volatile memory (NVM), such as a fuse or an eFuse. This approach is suitable for scenarios where the calibration code, once determined, does not need to be changed and can be programmed once before leaving the factory, thereby reducing chip area and the complexity of power-on initialization.

[0096] In addition, the storage unit can also be a shared RAM block in the system-on-chip, and the load control circuit accesses the memory block through the internal bus interface to obtain the calibration code.

[0097] By introducing mode-bound memory cells, this invention acknowledges and respects the independence of mismatches between different physical devices. Instead of attempting to use a single "master key" to open two different "locks," it precisely matches each "lock" (PMOS pair and NMOS pair) with a unique "key" (its own calibration code). This "dedicated code for dedicated use" design ensures that regardless of the input mode in which the CTLE operates, its DC operating point can be precisely calibrated to its optimal state, thereby providing the signal with maximized dynamic range and eye diagram margin, significantly improving the robustness and signal transmission quality of the entire link.

[0098] Based on the above embodiments, as an optional embodiment, the storage unit includes a first register group and a second register group, and the load control circuit further includes a multiplexer; The first register group stores a first calibration code corresponding to the first differential input pair, and the second register group stores a second calibration code corresponding to the second differential input pair; The multiplexer is controlled by the input mode selection signal to switch the output between the first register group and the second register group.

[0099] Figure 4 This is a schematic diagram showing the connection relationship between the load control circuit and the differential load circuit provided by the present invention, as shown below. Figure 4 As shown, in order to achieve independent storage and fast switching of calibration codes in PMOS and NMOS modes, the storage unit is specifically defined as a first register group (denoted as register group A) and a second register group (denoted as register group B). At the same time, the load control circuit also includes a multiplexer as the core selection device.

[0100] In the specific implementation of the circuit, the first register group (register group A) is specifically used to store the first calibration code corresponding to the first differential input pair (PMOS mode). Similarly, the second register group (register group B) is specifically used to store the second calibration code corresponding to the second differential input pair (NMOS mode). These two register groups are physically independent storage units and can be written to separately by software via a standard configuration bus (such as the APB bus), thereby embedding the Group A Code and Group B Code obtained during the testing phase into the circuit.

[0101] The key to the circuit architecture provided in this embodiment lies in the introduction of a multiplexer, such as... Figure 4 As shown, the two parallel multi-bit data input ports of the multiplexer are connected to the outputs of register group A and register group B, respectively. Its selection control terminal directly receives the input mode selection signal from an external source.

[0102] When the CTLE circuit needs to operate, the multiplexer is controlled by the input mode selection signal to switch the output between the first register group and the second register group. The specific process can be as follows: When the logic level of the input mode selection signal indicates that PMOS mode is enabled (e.g., the signal is logic '1'), the logic gates inside the multiplexer will automatically open the path to register group A and pass the corresponding calibration code (denoted as the first calibration code) to its output.

[0103] Conversely, when the input mode selection signal indicates that NMOS mode is enabled (e.g., the signal is logic '0'), the multiplexer will immediately switch to open the path to register group B and select the corresponding calibration code (denoted as the second calibration code) to its output.

[0104] Finally, the selected digital code output from the multiplexer is converted into the final load configuration information and sent directly to the control port of the differential load circuit to precisely set its equivalent impedance.

[0105] This embodiment employs a digital circuit design with a dual register set and a multiplexer, achieving high speed and high reliability in calibration code switching. Since the multiplexer is a purely combinational logic circuit, its selection and switching delay is extremely low (typically on the nanosecond level), ensuring that the corresponding calibration code takes effect instantly within the same clock cycle of the input mode switching, meeting the requirements of high-speed dynamic switching. Simultaneously, this standardized, all-digital implementation offers better noise immunity and predictability compared to other possible analog selection schemes, greatly simplifying the circuit design, simulation, and verification process.

[0106] Those skilled in the art will understand that other equivalent circuit configurations exist to implement the same selection logic. For example, the multiplexer can be replaced by two sets of tri-state buffers, with the outputs of the two sets of buffers connected in parallel. The enable terminals of the two sets of buffers are mutually exclusive, and the same two-to-one output effect can be achieved. These equivalent substitutions all fall within the scope of the embodiments of the present invention.

[0107] As an optional embodiment, the provided differential load circuit may further include a variable resistor array; the load configuration information is used to adjust the resistance value of the variable resistor array so that when the differential signal input to the CTLE is zero, the differential output voltage of the CTLE is substantially zero.

[0108] Optionally, the differential load circuit is specifically implemented as a pair of variable resistor arrays, symmetrically connected between the output of the differential amplifier and the power supply or ground.

[0109] Specifically, in the differential load circuit section, the variable resistor array on each side consists of multiple parallel resistor branches. Each resistor branch can contain a fixed resistor element and a digitally controlled switch (such as a MOSFET switch). This structure allows the equivalent resistance value of the entire differential load circuit to be finely adjusted through digital control.

[0110] Once the load control circuit determines the final load configuration information (such as Group A Code or Group B Code) based on the input mode selection signal, each bit of this digital code is sent to the control terminal of the corresponding switch in the variable resistor array. By changing the value of this digital code, the on / off combinations of different switches in the variable resistor array can be controlled.

[0111] For example, when a bit is '1', its corresponding switch is closed, and the resistor of that branch is connected in parallel to the circuit; when a bit is '0', its corresponding switch is open, and the resistor of that branch is removed from the circuit. The total equivalent resistance of the circuit is the result of all the conducting branch resistors connected in parallel. By using binary weighting or thermometer coding to design the values ​​of the parallel resistive elements, linear and monotonic adjustment of the equivalent resistance of the variable resistor array can be achieved.

[0112] It is important to emphasize that the ultimate goal of finely adjusting the resistance values ​​of the variable resistor array described above is to ensure that the differential output voltage of the CTLE circuit is essentially zero when the differential signal input to the CTLE circuit is zero. This is a crucial performance indicator that directly relates to the eye diagram quality of the signal.

[0113] Ideally, when the differential input is zero (i.e., IN_P = IN_N), the currents flowing through both sides of the differential amplifier should be exactly equal. If the load resistances on both sides are also exactly equal, the differential output voltage will naturally be zero. However, due to random deviations in the manufacturing process, the two transistors in the differential input pair cannot be perfectly symmetrical. This mismatch causes the currents on both sides to be unequal even at zero input, resulting in a non-zero differential output voltage across the load. This is known as DC offset.

[0114] This invention, by fine-tuning the equivalent resistance value on one or both sides of a differential load, can actively and asymmetrically change the load size on both sides, thereby precisely offsetting the effects of input stage current asymmetry. For example, if the current on the left side of the input stage is too large, the resistance value of the load on the left side can be slightly increased or the resistance value of the load on the right side can be decreased, thus reducing the voltage drop (I) on both sides. R) restores balance.

[0115] The load configuration information is repeatedly adjusted and the differential output is monitored through a closed-loop calibration algorithm until the best combination code that makes the differential output closest to zero is found and stored.

[0116] In this embodiment, a variable resistor array is used as a differential load, and digital load configuration information is used to fine-tune it. Essentially, this provides a post-compensation mechanism, which offers an efficient, accurate, and easily digitally controlled correction method to solve the unavoidable physical mismatch problem of the front-end input stage. This ensures that the CTLE circuit has a clean and symmetrical DC output operating point in any operating mode, providing the maximum dynamic range and signal-to-noise ratio for subsequent signal processing.

[0117] As an optional embodiment, a preferred structure for enhancing the core equalization function of the CTLE circuit is further provided. To enable the circuit to flexibly compensate for varying degrees of high-frequency loss caused by different physical channels, this embodiment also integrates a configurable equalization network into the CTLE circuit.

[0118] refer to Figure 2 and Figure 3 As shown, the configurable equalizer network can be a resistor-capacitor (RC) network coupled in the signal amplification path of the CTLE circuit. Specifically, the coupling method involves connecting the configurable equalizer network across the two source terminals of the differential input pair in a source-degraded manner, aiming to achieve high-frequency enhancement and low-frequency suppression.

[0119] In actual operation, the configurable equalization network adjusts its equivalent impedance in response to an equalization control signal. This equalization control signal, like the aforementioned input mode selection signal and load configuration information, originates from... Figure 3 The digital control and calibration logic shown can also be a digital code that can be configured through software programming.

[0120] For example, the equalization control signals used include REG_R_SEL and REG_C_SEL. REG_R_SEL is a multi-bit digital code, each bit of which controls the switching of a resistive element. These switches determine which resistive elements are connected in parallel or series to form a total equivalent resistance Rs. Similarly, REG_C_SEL is another digital code used to form the equivalent capacitance Cs.

[0121] By writing different digital codes (e.g., from 0001 to 1111) into REG_R_SEL and REG_C_SEL, the zero position and gain peak of the configurable equalization network can be changed precisely and discretely, thereby achieving accurate compensation for different channels.

[0122] Specifically, the impedance of a configurable equalizer network exhibits different characteristics at different frequencies. At low frequencies, the capacitors in the configurable equalizer network exhibit high impedance (approximately open circuit), and the total impedance of the network is primarily determined by its internal resistance. However, at high frequencies, the capacitor impedance decreases with increasing frequency, beginning to dominate the total impedance of the configurable equalizer network, thus reducing the effective impedance of the entire network at high frequencies.

[0123] When this frequency-dependent impedance network is placed at the source of a differential input pair, it changes the relationship between the amplifier's gain and frequency: in the low-frequency range where the equivalent impedance is large, the source degradation effect is strong, and the amplifier gain is low; in the high-frequency range where the equivalent impedance decreases, the source degradation effect is weakened, and the amplifier gain will increase accordingly.

[0124] This embodiment allows for the adjustment of the equalization control signal, which alters the combination of resistors and capacitors within the configurable equalization network, thereby changing the value of its equivalent impedance and the inflection point of impedance change with frequency. This ultimately impacts the overall performance of the CTLE circuit, enabling flexible setting of the zero-point frequency and high-frequency gain in the frequency response characteristics. For example, in a channel with particularly severe losses (such as long PCB traces), the software can configure the equalization control signal to increase the high-frequency gain, providing a stronger high-frequency boost to the signal; simultaneously, the position of the zero-point frequency can be adjusted to precisely align with the inflection point where the signal spectrum begins to roll off, achieving the most effective compensation.

[0125] Those skilled in the art will understand that implementing a configurable equalization network is not limited to source-degraded structures. In other embodiments, the configurable equalization network can also be placed at the load end, in parallel with a differential load circuit, to achieve high-frequency enhancement by introducing a frequency-dependent shunt path. Alternatively, a cascaded multi-stage amplifier structure can be used, introducing adjustable RC components in the interstage coupling network. Although these different topologies differ in specific circuitry, they all utilize adjustable frequency-dependent impedance to shape the amplifier's gain curve.

[0126] By integrating this configurable equalization network, the CTLE circuit provided in this embodiment not only possesses a wide input range and accurate offset calibration capabilities, but also boasts powerful channel adaptability. This allows a single CTLE IP core to not only span different voltage domains but also different physical channels. Whether facing short-distance, low-loss chip-to-chip interconnects or long-distance, high-loss backplane applications, it can find its optimal operating equalization parameters through software configuration, greatly improving the design's versatility and system robustness.

[0127] As an optional embodiment, a further embodiment provides an internal implementation structure of a digitally configurable equalization network. To achieve flexible and precise adjustment of the equivalent impedance, this embodiment abandons complex analog designs such as using analog voltage to control variable resistors, and instead employs a fully digitally controlled array structure.

[0128] Specifically, the configurable equalization network includes a resistor array and / or a capacitor array: The resistor array includes multiple resistor elements that are controlled and connected by a first switch; The capacitor array includes multiple capacitor elements connected under the control of a second switch; The equalization control signal adjusts the equivalent impedance by controlling the opening and closing states of the first switch and / or the second switch.

[0129] In this embodiment, decoupling control of low-frequency gain and high-frequency gain can be achieved using a separate resistor array or a separate capacitor array. However, decoupling control of low-frequency gain and high-frequency gain can also be achieved by having both resistor arrays and capacitor arrays coexist and work together. Specifically, the resistor array consists of multiple parallel resistor branches, for example, M resistor branches from RS1 to RSM. Each resistor branch contains a fixed resistive element and a path controlled by a first switch (such as a MOSFET switch).

[0130] Similarly, the capacitor array also adopts a similar structure, consisting of multiple parallel capacitor branches, such as K capacitor branches from CS1 to CSK. Each capacitor branch contains a fixed capacitor element and a second switch.

[0131] Through the array design described above, the complex problem of analog parameter adjustment is transformed into a simple digital logic control problem. The equalization control signals REG_R_SEL and REG_C_SEL are physically two sets of multi-bit digital buses. Each bit of REG_R_SEL is connected to the control terminal of the corresponding first switch in the resistor array, while each bit of REG_C_SEL is connected to the control terminal of the corresponding second switch in the capacitor array.

[0132] When the software needs to adjust the equalization characteristics, it simply writes different digital codes to these two registers. The equalization control signal adjusts the equivalent impedance by controlling the opening and closing states of the first switch and / or the second switch. For example, when a bit in REG_R_SEL is high, the corresponding first switch is closed, and that resistor branch is connected in parallel to the circuit; conversely, the branch is disconnected. By changing the digital value of REG_R_SEL, different resistor branches can be flexibly combined, thereby achieving adjustments to the total equivalent resistance. The step-by-step adjustment is the same as that of a capacitor array, which controls the total equivalent capacitance by the value of REG_C_SEL. Size.

[0133] CTLE zero frequency Mainly composed of total equivalent resistance Total equivalent capacitance The product determines The high-frequency gain peak is related to the total equivalent resistance. This is related to the ratio of the load resistance. By isolating the resistor array and capacitor array and controlling them with two independent sets of digital codes, this embodiment achieves approximately orthogonal adjustment of low-frequency and high-frequency gain, greatly simplifying the design of the system-level adaptive equalization algorithm. The algorithm can first fix a parameter (such as the total equivalent resistance). ), scan another parameter (such as total equivalent capacitance) Find the local optimum and then fine-tune it to efficiently converge to the global optimum.

[0134] Based on the above principles, this embodiment employs a fully digitally controlled resistor / capacitor array structure, providing an extremely flexible, precise, and easily integrated interface with digital control logic for frequency response adjustment of the CTLE circuit. It transforms complex analog tuning tasks into simple register read / write operations, significantly improving the robustness of the design and the efficiency of automated calibration.

[0135] The impedance of the configurable equalization network is a function of frequency. As analyzed in the previous examples, it exhibits higher impedance at low frequencies, primarily due to the total equivalent resistance of the resistor array. The impedance is determined by the bypass effect of the capacitor array; however, due to this effect, it exhibits lower impedance at high frequencies. According to the gain theory of negative feedback amplifiers, the gain of the entire differential amplifier stage is approximately proportional to the load impedance and inversely proportional to the source degradation impedance.

[0136] Therefore, this frequency-dependent source degradation impedance directly leads to the frequency dependence of the amplifier gain. That is, the CTLE circuit provided in this embodiment has a first gain in the frequency band below the operating frequency and a second gain higher than the first gain in the frequency band above the operating frequency.

[0137] Specifically, at lower signal frequencies, the equivalent impedance of the configurable equalization network is high and approximately constant, resulting in a low initial gain, or DC gain, in the circuit. As the signal frequency increases, the equivalent impedance of the configurable equalization network begins to decrease significantly, reducing source degradation and gradually increasing the amplifier gain. Eventually, the gain reaches a peak, a second gain higher than the initial gain, also known as the high-frequency peak gain.

[0138] The zero-point frequency is precisely the inflection point where the gain curve begins to rise from the first gain to the second gain. The physical significance of this frequency point is that it marks the starting point for CTLE to perform "high-frequency compensation" on the signal. This can be achieved by adjusting the total equivalent resistance in the configurable equalization network. and / or total equivalent capacitance The value of can precisely shift the position of this zero-point frequency.

[0139] This frequency response characteristic, capable of generating two distinct gain flat regions and a controllable gain boost, is crucial for the recovery of high-speed serial signals. A typical high-speed signal, after passing through physical channels such as PCB traces and connectors, experiences more severe attenuation of its high-frequency components than its low-frequency components, leading to inter-symbol interference and eye diagram closure. The CTLE circuit provided in this embodiment generates a gain curve opposite to the channel loss characteristics—maintaining a moderate gain at low frequencies and providing a reverse-compensating gain peak at high frequencies—effectively pulling the attenuated high-frequency components back to their proper amplitude. This reopens the signal's eye diagram, providing a clear and reliable waveform for subsequent data decision-making.

[0140] In summary, this embodiment, by introducing a configurable equalization network, enables the CTLE circuit to have frequency-selective amplification capabilities, which can accurately improve the intelligent equalization of damaged high-frequency components.

[0141] As an optional embodiment, the CTLE circuit provided by the present invention may further include a transmission gate structure; the transmission gate structure is coupled between the signal input pad of the CTLE and the differential input stage module; the transmission gate structure is configured to provide a signal path when the CTLE is in the working state, and to provide a high-impedance isolation or electrostatic discharge protection path when the CTLE is not in the working state.

[0142] refer to Figure 2 and Figure 3 As shown, the transmission gate structure Tgate is coupled between the signal input pads of the CTLE (i.e., the input + and input - of the chip's physical pins) and the differential input stage module. This coupling method can be a series insertion relationship, meaning that all differential input signals entering and exiting the CTLE circuit must first pass through this transmission gate structure.

[0143] This transmission gate structure is essentially a high-performance differential analog switch, whose on and off states are strictly controlled by an independent digital control signal (such as the EN signal). Its introduction provides the CTLE circuit with two distinct but crucial functional modes: When the entire CTLE is enabled, the transmission gate structure is configured to be fully on, exhibiting the lowest possible linear on-resistance to ensure that external input signals can be transmitted to the internal differential input stage module with minimal distortion and attenuation.

[0144] The transmission gate structure is configured to be off when the CTLE is in a non-operating state, providing high-impedance isolation or electrostatic discharge (ESD) protection path, such as when the entire chip enters low-power sleep mode or when the CTLE's function is not used. In this state, it primarily provides high-impedance isolation. The off transmission gate structure exhibits extremely high impedance, effectively isolating sensitive internal core circuitry from external input pads that may contain noise or have uncertain voltage levels, preventing unwanted signal crosstalk and static power leakage.

[0145] Secondly, and more importantly, the transmission gate structure is typically designed in conjunction with the chip's electrostatic discharge (ESD) protection circuitry, or it may be part of the ESD protection strategy itself. When a high-energy electrostatic pulse strikes the input pad, the transmission gate structure, in its off state, can withstand the high voltage and direct the large instantaneous current to a specially designed ESD discharge path (such as using its parasitic diodes or dedicated ESD devices in parallel), thereby protecting the more advanced and vulnerable core amplifier circuitry behind it from permanent physical damage.

[0146] Those skilled in the art will understand that transmission gate structures are not the only way to achieve signal path control. For example, the module can be switched by controlling the bias current of the differential input stage module itself, but this method may not provide effective protection against external ESD events. Therefore, adding an independent transmission gate structure at the input is the best engineering practice to balance functional switching and physical protection.

[0147] In summary, this embodiment significantly improves the practicality and reliability of the CTLE circuit by adding a controllable transmission gate structure to the input path. It not only saves power consumption through high-impedance isolation and provides module-level power management capabilities, but more importantly, it builds a robust physical defense, significantly enhancing the chip's robustness against electrostatic discharge (ESD). This is crucial for ensuring product yield and long-term reliability in complex environments.

[0148] Based on the above embodiments, as an optional embodiment, the transmission gate structure includes NMOS transmission transistors and PMOS transmission transistors connected in parallel; The input selection circuit controls the on / off state of the signal path by controlling the gate voltages of the NMOS and PMOS transmission transistors.

[0149] refer to Figure 2 The details of the transmission gate structure Tgate shown can be seen in the diagram. Each differential signal path (e.g., the IN_P path) consists of an NMOS transistor and a PMOS transistor connected in parallel. The source and drain of these two transistors are interconnected, forming the signal input and output terminals. This parallel design cleverly utilizes the complementary conduction characteristics of NMOS and PMOS transistors to overcome the inherent limitations of using a single type of transistor as a switch. When an NMOS transistor is used as a switch, it can transmit low-level signals close to the low level GND very well. However, when the input signal level increases, its gate-source voltage difference decreases, and the on-resistance increases sharply, resulting in a deterioration in the ability to transmit high-level signals and signal amplitude attenuation.

[0150] Conversely, when used as a switch, a PMOS transistor can transmit high-level signals close to the high level VDD very well, but its ability to transmit low-level signals will decrease.

[0151] By connecting an NMOS transistor and a PMOS transistor in parallel, the NMOS transistor is in a low-resistance on-state when the input signal is low, and the PMOS transistor is in a low-resistance on-state when the input signal is high; in the intermediate voltage range, both transistors are in a certain on-state. The superimposed on-resistance curves of these two transistors maintain a relatively low and flat total on-resistance across the entire voltage range from low level GND to high level VDD. This ensures that the transmission gate structure can achieve low-loss transmission of signals at different levels, greatly reducing signal distortion.

[0152] To control the switching state of the transmission gate structure, the input selection circuit or a separate enable control logic controls the on / off state of the signal path by controlling the gate voltages of the NMOS and PMOS transmission transistors. These two gate voltages are typically a pair of complementary control signals, such as EN and the inverted signal EN_B.

[0153] When the transmission gate structure needs to be turned on, a high level VDD is applied to the gate of the NMOS transistor, and a low level GND is applied to the gate of the PMOS transistor, so that both transistors enter a strong conduction state.

[0154] When it is necessary to turn off the transmission gate structure, the operation is reversed: a low level GND is applied to the gate of the NMOS transistor, and a high level VDD is applied to the gate of the PMOS transistor, so that both transistors enter a reliable off state.

[0155] This embodiment provides a high-performance signal switch by employing a CMOS transmission gate structure with PMOS and NMOS transistors connected in parallel. This not only overcomes the limitations of a single transistor switch in terms of signal swing and ensures the fidelity of high-speed signals, but also provides a clear and reliable switching interface controlled by complementary digital signals, perfectly matching the digital and modular design concept of the entire CTLE circuit.

[0156] Based on the above embodiments, as an optional embodiment, all the key control signals used to regulate the behavior of CTLE, namely the input mode selection signal, load configuration information, and equalization control signal mentioned in the aforementioned implementation, are ultimately digital signals that can be configured by software programming. That is, in the physical implementation of the circuit, the values ​​of these control signals are not fixed by hardware logic, nor are they directly set by analog voltage, but are stored in a series of programmable configuration registers inside the CTLE module.

[0157] For example, the value of the input mode selection signal corresponds to a register named REG_IN_SEL. The value of the load configuration information corresponds to the aforementioned Group A Code and Group B Code register groups. The value of the equalization control signal corresponds to the REG_R_SEL and REG_C_SEL registers.

[0158] Alternatively, these registers can be connected to the chip's central processing unit (CPU) or a dedicated microcontroller via a standard on-chip bus interface, such as the Advanced Peripheral Bus (APB) or a similar low-speed configuration bus.

[0159] This embodiment employs a fully digital, software-programmable architecture, which brings multiple profound technical advantages: First, the software can dynamically change any key parameter of the CTLE at runtime through simple bus write operations. This allows the same CTLE hardware design to be easily configured to support multiple different communication protocols. For example, it can adapt to Universal Serial Bus (USB) or Peripheral Component Interconnect Express (PCIe) by changing the equalization parameters, or adjust the equalization code to adapt to different channel environments through adaptive algorithms, or be compatible with interface chips from different manufacturers by switching input modes and calibration codes.

[0160] Secondly, it simplifies the implementation of automated calibration and adaptive algorithms. Whether it's offset calibration at power-on or adaptive equalization during runtime, the core is a closed-loop iterative process of "read-calculate-write". Since all control signals are digital registers, upper-level firmware or software algorithms can easily perform precise quantitative control and status readback of CTLE, greatly simplifying the development and integration of complex control algorithms.

[0161] Furthermore, it enhances testability and debuggability. During chip production testing and system debugging, test engineers or software engineers can directly access these configuration registers, force CTLE into a specific operating mode, or scan the settings of a parameter one by one to quickly locate design defects or performance bottlenecks. This white-box observability and controllability is crucial for ensuring product quality and accelerating problem-solving.

[0162] In summary, this embodiment unifies all core control nodes of CTLE into a software-programmable digital interface, encapsulating a originally complex analog circuit module into a highly software-friendly and predictable digital peripheral, greatly improving reusability, adaptability, and maintainability, and fully aligning with the design trends of modern large-scale integrated circuits.

[0163] To enable those skilled in the art to gain a deeper understanding of the specific circuit implementation of the proposed solution, this embodiment will combine... Figure 2 To elaborate in detail, such as Figure 2 As shown, it illustrates in detail the complete circuit principle of the CTLE circuit in a specific embodiment of the present invention, which integrates all functions such as dual-mode input selection, configurable equalization, and offset calibration with mode linkage.

[0164] First, the differential signal of the CTLE circuit is input from the external pad PAD, and first passes through a CMOS transmission gate structure Tgate controlled by the input mode selection signal REG_IN_SEL and its inverted signal REG_SELB. Tgate is responsible for turning the external signal path on or off and providing electrostatic discharge protection.

[0165] After passing through the Tgate, the signal path is split into two parallel differential amplification paths: lie in Figure 2 The PMOS path above consists of a pair of PMOS transistors forming the main differential input pair, used to process input signals with high common-mode voltage.

[0166] lie in Figure 2The NMOS path below consists of a pair of NMOS transistors forming the main differential input pair, used to process low common-mode voltage input signals. The REG_IN_SEL signal not only controls the front-end Tgate but also controls the switching of the bias current sources for both paths, ensuring that only one path is enabled at any given time, thereby saving power consumption.

[0167] A configurable equalizer network is connected between the source terminals of these two differential paths. This configurable equalizer network consists of a variable resistor and a variable capacitor connected in series, whose resistance and capacitance values ​​are digitally controlled by external equalizer control signals REG_R_SEL and REG_C_SEL, respectively. By adjusting these two equalizer control signals, the low-frequency and high-frequency gains of the CTLE circuit can be precisely set to compensate for different channel losses.

[0168] In the load section of the equalization control signal circuit, the upper and lower paths each correspond to their respective differential active loads. Each active load consists of a pair of cross-coupled PMOS transistors, providing negative resistance to enhance gain. Crucially, each differential active load integrates an adjustable resistor for offset calibration. The control signals for these adjustable resistors—the final load configuration information TRIM_CODEP for the positive output and TRIM_CODEN for the negative output—are not fixed but dynamically generated by the calibration code selection logic.

[0169] It should be noted that the calibration code selection logic is the key hardware for realizing the core idea of ​​this invention: the circuit has two sets of independent calibration code registers REG_TRIM_CODEP_A and REG_TRIM_CODEN_A, which together constitute the A set of calibration codes, for example, corresponding to NMOS mode; the calibration code registers REG_TRIM_CODEP_B and REG_TRIM_CODEN_B together constitute the B set of calibration codes, for example, corresponding to PMOS mode.

[0170] The core function of the two multiplexers (MUX) is to perform "two-to-one" switching. The selection control terminals of both MUXs are connected to the input mode selection signal REG_IN_SEL.

[0171] When REG_IN_SEL selects NMOS mode, the MUX will send the outputs of calibration codes REG_TRIM_CODEP_A and REG_TRIM_CODEN_A from group A to the load as TRIM_CODEP and TRIM_CODEN.

[0172] When REG_IN_SEL switches to PMOS mode, MUX will simultaneously switch the outputs of calibration codes REG_TRIM_CODEP_B and REG_TRIM_CODEN_B to TRIM_CODEP and TRIM_CODEN.

[0173] Finally, the outputs OUTP and OUTN of the two differential paths are ultimately selected by another set of switches controlled by REG_IN_SEL, ensuring that only the output signal of the currently enabled path is passed to the final output of the CTLE circuit.

[0174] in addition, Figure 2 The diagram also shows a reference voltage VREF for stabilizing the output common-mode level, which is typically connected to the input of a common-mode feedback (CMFB) circuit to ensure that the DC level of the output signal is stable at a preset value.

[0175] This embodiment fully demonstrates how to use a unified control signal REG_IN_SEL to simultaneously achieve triple linkage control of the input physical path, load offset calibration code, and final output path, thereby forming a high-performance, highly flexible, and robust adaptive CTLE circuit.

[0176] Figure 5 This is a schematic diagram of the structure of the high-speed serial communication receiver provided by the present invention, as shown below. Figure 5 As shown, the high-speed serial communication receiver (hereinafter referred to as the communication receiver) integrates the CTLE described in any of the foregoing embodiments as a core functional module in the receiving link, thereby significantly improving the performance and adaptability of the entire communication receiver.

[0177] Optionally, a complete high-speed signal reception and recovery process performed by the communication receiver provided in this embodiment mainly includes the following key stages: Communication signals enter the chip from the receiving pad. The receiving pad serves as the physical interface connecting the chip to external physical channels (such as PCB traces, cables, or backplanes). The received differential signals are usually subject to severe inter-symbol interference due to high-frequency loss of the channel, and the signal eye diagram may be completely closed.

[0178] The communication signal is first fed into the CTLE circuit provided in any of the embodiments, which serves as the first-stage core circuit of the Analog Front-End (AFE). The CTLE circuit undertakes the preliminary but crucial equalization task of the communication signal, including compensatory boosting of the high-frequency components of the communication signal through its configurable frequency response characteristics, with the aim of reopening the eye diagram of the signal.

[0179] Because the CTLE circuit provided by this invention has a wide input common-mode voltage range, the entire receiver can directly interface with transmitters from different voltage domains without the need for additional complex level conversion circuits, which greatly enhances the system's compatibility and interoperability.

[0180] More importantly, because the CTLE circuit employs a high-precision offset calibration capability linked to the input mode, it ensures that the output signal to subsequent circuits is an extremely clean, offset-free analog signal with an extremely clean DC operating point, regardless of the operating mode. This is crucial for the performance of the entire receiver link, as any residual DC offset can lead to amplifier saturation or deviation of the decision threshold of the decision circuit, resulting in a large number of bit errors.

[0181] The signal, after initial equalization by the CTLE circuit, is then fed into a Variable Gain Amplifier (VGA). The VGA's function is to amplify input signals with varying degrees of attenuation to a essentially constant swing suitable for subsequent circuit processing through an automatic gain control loop. Because the CTLE circuit of this invention provides a clean, offset-free signal, the VGA's AGC loop can lock more stably and quickly, and the VGA's dynamic range is not occupied by DC offset, thus enabling more effective handling of signal amplitude variations.

[0182] The amplitude-normalized communication signal is further fed into a Decision Feedback Equalizer (DFE). A DFE is a non-linear equalizer that uses previously decided data bits to eliminate post-bill pulse interference caused by them. The CTLE circuit already handles most of the high-frequency losses, providing the DFE with a higher-quality input signal. This reduces the workload of the DFE, allowing it to achieve equivalent performance with fewer orders, thus saving power and area, or achieving a lower bit error rate with the same complexity.

[0183] Finally, the fully equalized communication signal is sent to the Clock and Data Recovery (CDR) unit. The CDR circuit extracts the clock signal from the serial data stream, which lacks an independent clock, and uses this clock signal to sample the data at the optimal decision point, thereby recovering the original parallel data and clock. A high-quality, wide-aperture eye diagram is a prerequisite for the CDR to lock onto and extract a low-jitter clock. The CTLE circuit provided by this invention, through its superior equalization and calibration capabilities, provides such an ideal input signal for the CDR, directly guaranteeing the reliability of the final data recovery.

[0184] In summary, by integrating the CTLE circuit provided by this invention, which has wide-range input adaptation capability and mode linkage for precise calibration, into the communication receiver, the communication receiver achieves a significant performance improvement at the system level. It can not only flexibly adapt to more diverse interface standards and physical channels, but more importantly, it can ensure signal quality from the very beginning of the signal processing link, laying a solid foundation for the stable and efficient operation of all subsequent modules. Ultimately, this results in a lower bit error rate and stronger environmental robustness for the entire communication system.

[0185] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A continuous-time linear equalizer characterized by, The application comprises: a differential input stage module comprising a plurality of differential input pairs with different input common-mode voltage ranges; an input selection circuit configured to enable one of the differential input pairs as a target differential input pair in response to an input mode selection signal; a differential load circuit coupled to an output of the differential input stage module, the differential load circuit having an adjustable equivalent impedance; a load control circuit configured to determine load configuration information corresponding to the target differential input pair in response to the input mode selection signal, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

2. The continuous-time linear equalizer of claim 1, wherein, The differential input pairs are two, comprising a first differential input pair and a second differential input pair.

3. The continuous-time linear equalizer of claim 2, wherein, The first differential input pair is composed of PMOS transistors, and the second differential input pair is composed of NMOS transistors. The input common-mode voltage range of the first differential input pair is higher than that of the second differential input pair.

4. Continuous-time linear equalizer according to any of claims 2-3, characterized in that, The load control circuit comprises a storage unit; The storage unit is used to store calibration codes corresponding to each of the differential input pairs respectively; The load control circuit is configured to read the storage unit, take the calibration code corresponding to the target differential input pair as the load configuration information, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

5. The continuous-time linear equalizer of claim 4, wherein, The storage unit comprises a first register group and a second register group, and the load control circuit further comprises a multiplexer; The first register group stores a first calibration code corresponding to the first differential input pair, and the second register group stores a second calibration code corresponding to the second differential input pair; The multiplexer is controlled by the input mode selection signal to switch between the first register group and the second register group.

6. The continuous-time linear equalizer of claim 1, wherein, The differential load circuit comprises a variable resistance array; The load configuration information is used to adjust the resistance value of the variable resistance array, so that when the differential signal input into the continuous-time linear equalizer is zero, the differential output voltage of the continuous-time linear equalizer is substantially zero.

7. The continuous-time linear equalizer of claim 1, wherein, Further comprising: A configurable equalization network coupled in a signal amplification path of the continuous-time linear equalizer, configured to adjust its equivalent impedance in response to an equalization control signal to set low frequency gain and high frequency gain in frequency response characteristics of the continuous-time linear equalizer.

8. The continuous-time linear equalizer of claim 7, wherein, The configurable equalization network comprises a resistance array and / or a capacitance array: The resistance array comprises a plurality of resistance elements controlled by a first switch; The capacitance array comprises a plurality of capacitance elements controlled by a second switch; The equalization control signal adjusts the equivalent impedance by controlling the on-off state of the first switch and / or the second switch.

9. The continuous-time linear equalizer of claim 7, wherein, In a frequency band lower than the use frequency, the continuous-time linear equalizer has a first gain; in a frequency band higher than the use frequency, the continuous-time linear equalizer has a second gain higher than the first gain.

10. The continuous-time linear equalizer of claim 1, wherein, Further comprising a transmission gate structure; The transmission gate structure is coupled between a signal input pad of the continuous-time linear equalizer and the differential input stage module; The transmission gate structure is configured to provide signal pass in an active state of the continuous-time linear equalizer and to provide high-impedance isolation or electrostatic discharge protection path in an inactive state of the continuous-time linear equalizer.

11. The continuous-time linear equalizer of claim 10, wherein, The transmission gate structure includes an NMOS pass transistor and a PMOS pass transistor in parallel connection; The input selection circuit controls the on-off of signal pass by controlling gate voltages of the NMOS pass transistor and the PMOS pass transistor.

12. The continuous-time linear equalizer of claim 7, wherein, The input mode selection signal, the load configuration information, and the equalization control signal are all digital signals programmable by software.

13. A high-speed serial communication receiver, characterized by An apparatus comprising the continuous-time linear equalizer of any one of claims 1 to 12.

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