Page stripe construction technology supporting Zoned NameSpace

Abstract

The invention provides a page stripe construction technology supporting Zoned NameSpace, and relates to a page stripe construction technology supporting Zoned NameSpace. The storage command processing method for accessing the Zone comprises the steps that in response to a received first storage command for accessing a first Zone and indicating write operation, a first page stripe in a first large block corresponding to the first Zone is obtained, and a plurality of physical blocks included in the first large block all come from a first LUN; generating a first media interface command, the first media interface command indicating to write user data to the first page stripe, the first media interface command being processed by a first LUN controller corresponding to the first LUN; the Zone and the large block are in one-to-one correspondence, all physical blocks included in the large block are from the same LUN, and when the large blocks corresponding to the multiple Zone correspond to different LUNs, access to the multiple Zone is processed in parallel by the multiple LUN controllers. According to the invention, a large block construction mode is improved, and the storage bandwidth obtained by the host from the storage device is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to page stripe construction technology supporting Zoned Namespace. Background Technology

[0002] Figure 1A A block diagram of a storage device is shown. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and storage device 102 can be coupled in various ways, including but not limited to using storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device in the above ways, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] Interface 103 can be adapted to exchange data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] Figure 1B A detailed block diagram of the control components of the storage device is shown.

[0008] The host accesses the storage device using I / O commands that conform to the storage protocol. The control unit generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) that conform to the NVM chip's interface protocol based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from a single I / O command and indicates the processing results of the I / O commands to the host.

[0009] See Figure 1BThe control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit. A storage command may access a storage space of the same size, such as 4KB. The data unit recorded in the NVM chip corresponding to the data accessed by a storage command is called a data frame. A physical page records one or more data frames. For example, if the size of a physical page is 17664 bytes and the size of a data frame is 4KB, then one physical page can store four data frames.

[0010] The storage media management unit (SMMU) maintains a logical address to physical address translation for each storage command. For example, the SMMU includes an FTL table. For a read command, the SMMU outputs the physical address corresponding to the logical address accessed by the storage command; for a write command, the SMMU allocates an available physical address and records the mapping between the accessed logical address and the allocated physical address. The SMMU also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0011] The storage command processing unit, based on the physical address provided by the storage media management unit, operates the media interface controller to issue storage media access commands to the NVM chip. For clarity, commands sent from the host to the storage device are called I / O commands, commands sent from the host command processing unit to the storage command processing unit are called storage commands, commands sent from the storage command processing unit to the media interface controller are called media interface commands, and commands sent from the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0012] SSDs (Solid State Drives) consist of multiple NVM chips. Each NVM chip includes one or more LUNs (Logical Units), and each logical unit includes multiple physical blocks. As storage capacity increases, so does the number of NVM chips / LUNs / blocks, which also increases the likelihood of storage media failure. To ensure the reliability of the stored data delivered to users, enterprise-grade SSDs use technologies similar to RAID (Redundant Arrays of Independent Disks) to construct data protection units across NVM chips / logical units. This ensures that even if a single NVM chip / logical unit fails, data is not lost. This also addresses the occasional data errors that may occur during SSD operation.

[0013] Large blocks serve as the unit for allocating and reclaiming storage media resources in an SSD. When allocating storage media resources to carry write data, free large blocks are selected. Within the selected large block, data is written sequentially. When reclaiming storage media resources, the entire large block is reclaimed, and after the valid data has been reclaimed, all physical blocks within the large block are erased. Therefore, within an SSD, all physical blocks within a large block typically have the same number of write / erase cycles.

[0014] Page stripes are data protection units within an SSD, constructed using RAID technology. Page stripes are built into large blocks, which consist of multiple page stripes. A large block comprises physical blocks from multiple logical units; these logical units that provide physical blocks to the large block are called a logical unit group. Each logical unit in a logical unit group can provide one physical block for the large block. For example, in... Figure 2A The schematic diagram of the large block shows that it is constructed across N+1 logical units. Each large block comprises N+1 physical blocks, each derived from one of the N+1 logical units. The large block stores user data and checksum data. The checksum data for the large block is calculated based on the user data stored within it. For example, the checksum data is stored in the last physical block of the large block. Alternatively, other physical blocks within the large block can be selected to store the checksum data. Other construction methods can also be used to construct the large block, as described in [reference needed]. Figure 2B The diagram illustrates how to construct large blocks within a multi-plane logic unit.

[0015] See Figure 3A as well as Figure 3B As shown, a large block comprises multiple page strips, and each page strip comprises multiple physical pages, which come from different physical blocks within the same large block. For example, P pages in a page strip might be used to store user data, while Q pages might be used to store validation data. Figure 3A and Figure 3B In this context, Q = 1). The data written to page i is denoted as D(i). The checksum D(Q) is generated from the user data of page P according to the specified error correction algorithm. For example, if the checksum is determined based on the XOR operation, then D(Q) = D(0)XOR D(1)XOR…XOR D(P-1). Therefore, in writing data to the page stripe, D(Q) can only be calculated if D(0) to D(P-1) are known. The typical size of D(i) is, for example, 2KB, 4KB, 16KB, etc.

[0016] In TLC (Triple-Level Cell) flash memory, a one-shot programming mode is typically used, requiring the programming of three physical pages on the same word line in a single ONFI command. This means a single programming command operates on three physical pages. Accordingly, to improve write performance, page stripes are constructed in groups of three physical pages, resulting in a typical D(Q) size of 48KB. In multi-plane TLB (Translation Lookaside Buffer) flash memory, a multi-plane programming mode can be used to improve write performance. This allows a single programming command to operate on, for example, 12 physical pages (each logical cell includes four planes). Accordingly, the D(Q) size is typically 192KB.

[0017] To use RAID technology, parity data D(Q) needs to be calculated for the data written to the page stripe. Calculating the parity data involves numerous XOR operations. To accelerate this process, a dedicated hardware unit (called the XOR calculation unit) is typically used to perform the calculation of D(Q) = D(0)XOR D(1)XOR…XOR D(P-1). The XOR calculation unit also includes an XOR cache to cache the data D(i) and intermediate results of each XOR calculation, such as the result of D(0)XOR D(1), the result of D(0)XOR D(1)XOR D(2), until the final D(Q) is obtained, which is then written to the page stripe. Therefore, the XOR cache needs to be large enough to hold the entire D(i), and once a page stripe is allocated, the entire XOR cache is needed to support the data writing operations until the page stripe is full.

[0018] To improve SSD performance, data can be written to multiple large page stripes simultaneously. Accordingly, each page stripe written concurrently needs its own dedicated XOR cache. As mentioned earlier, the D(Q) size can reach 192KB (including some out-of-band data), thus requiring a single XOR cache of approximately 200KB. However, on-chip cache resources are very expensive, therefore the number of XOR caches in an XOR computation unit is typically small (e.g., 1-4).

[0019] In typical existing technologies, the XOR calculation unit is located in the media interface controller, such as... Figure 4A and Figure 4BAs shown. The XOR calculation unit is used to adapt page stripes with different data protection capabilities. The data protection level of the page stripe is determined by the relationship between the size of the parity data and the user data, that is, the values ​​of P and Q represent the data protection capability of the page stripe. Furthermore, the XOR calculation is completed during the process of the media interface controller providing data (e.g., D(0)) to the NVM chip (e.g., physical page P0-0) through the (Program) programming command. For example, suppose XOR cache 0 is allocated for page stripe 0 (initialized to all 0s). During the process of moving D(0) to page stripe 0 at P0-0, 0XOR D(0) is calculated, and the result is D(0) and stored in XOR cache 0. Next, D(1) is moved to page stripe 0 at P0-1, and D(0)XOR D(1) is calculated. D(0) is inside XOR cache 0, and D(1) is obtained during the data movement. Subsequently, XOR cache 0 records the result of D(0)XOR D(1). Next, D(2) is moved to page stripe 0 at P0-2. The result of D(0)XOR D(1) recorded in XOR cache 0 is XORed with the moved D(2), and the result is still stored in XOR cache 0. Following this logic, after moving D(P-1) to P0-(P-1) of page stripe 0, D(Q) is obtained in XOR cache 0, and then D(Q) is moved to P0-P of page stripe 0. At this point, page stripe 0 is full, and XOR cache 0 is released.

[0020] As an optimization method, the media interface controller receives media interface commands that only include instructions to write D(0) to D(P-1) to the respective physical addresses of the page stripe, but not instructions to write D(Q) to the page stripe. The media interface controller automatically calculates D(Q) and writes it to the page stripe.

[0021] During the writing of data to page stripes, the XOR cache needs to be continuously occupied. As the number of logical units in an SSD increases and the number of concurrent operations increases, the required amount of XOR cache also increases. However, due to cost limitations, the control unit cannot provide a sufficient number of XOR caches.

[0022] Chinese patent application No. 201711174050.1 provides a solution to shorten the time the XOR cache is occupied. This application notes that after sending D(Q) to the NVM chip using the Program command, the use of the XOR cache is complete. The reason the XOR cache cannot be released immediately is that the Program command has a small probability of failure, and in such cases, the Program operation needs to be re-executed using the data in the XOR cache. However, for the vast majority of Program commands that execute successfully, there is no need to prolong the occupation of the XOR cache.

[0023] By adding a data path between the XOR cache and DRAM, the intermediate result of calculating the parity data D(Q) in the XOR cache (e.g., D(0)XOR D(1)XOR(2)) can be temporarily moved to the external DRAM, and the XOR cache can be released. Subsequently, data can be moved from DRAM (e.g., the previously saved result of D(0)XOR D(1)XOR(2)) to the XOR cache, and subsequent operations can continue (e.g., XORing with D(3) again). After the XOR cache is released, it can be allocated to the operation of writing data to other page stripes. Thus, during the process of writing D(Q) to a page strip (e.g., page strip 3), if the data transfer to the NVM chip is completed, it is not necessary to wait for the NVM chip to confirm the successful processing of the Program command before moving the current result in the XOR cache to DRAM and releasing the XOR cache. If the Program command fails to process, the XOR cache is re-allocated for processing page stripe 3 (the re-allocated XOR cache may be different from the previously re-allocated XOR cache), and the previously stored result is loaded from DRAM as D(Q) and written to the NVM chip. The media interface controller also adds the operation of moving data between the XOR cache and DRAM, so that the data movement between the XOR cache and DRAM can be operated by issuing media interface commands to the media interface controller.

[0024] Besides handling programming failures of D(Q), the data path between the XOR cache and DRAM also plays a positive role in other scenarios. For example, during the writing of data to a page stripe (e.g., page stripe 3), if a Program command that moves user data (e.g., D(4)) fails, the current result in the XOR cache is moved to DRAM. This frees up the XOR cache, and error handling is performed to resolve the impact of the Program failure. After error handling is complete, the XOR cache is reallocated for processing page stripe 3, and the previously stored intermediate result is loaded from DRAM, and processing of other data in page stripe 3 continues (e.g., continuing to process D(4)).

[0025] In another scenario, it's desirable to prioritize processing read commands from users. However, data writing to the page stripe might have already begun before the read command is processed. In this case, the Program operation is aborted to allow the NVM chip to process the read command. However, the additional read command processing prolongs the occupation of the XOR cache. Therefore, when the Program operation is aborted, the data in the XOR cache is also moved to DRAM, and the XOR cache is released so that it can be allocated to other page stripes.

[0026] For a media interface controller, it needs to manage multiple logic units, such as Figure 5As shown. For performance purposes, such as performance optimization, the ability to process commands in parallel across multiple logic units is fully utilized. It is also desirable to control the cost of the media interface controller and reduce its circuit size. In the prior art (such as Chinese patent application 201610861793.5), a media interface controller including multiple threads is provided. Threads, as schedulable task processing units, are dynamically bound to logic units, and access to the logic units bound to them is operated through the threads. In Chinese patent application number "2022117373066", coroutines are used as task processing units corresponding to logic units. Microinstruction sequences are executed through coroutines to operate access to the logic units. The prior art also includes providing a corresponding flash controller for each flash channel or logic unit, and operating the bound logic units by providing commands to the flash controller.

[0027] Whether based on software or firmware threads and coroutines, or on hardware flash memory controllers, from the perspective of the storage command processing unit, what is operable is a task processing unit bound to a logical unit. Multiple task processing units can work in parallel. For clarity, this is referred to as a LUN controller. Its implementation includes existing media interface controllers with threads, coroutines, flash memory controllers, and other implementations with similar functionality, as well as future implementations in media interface controllers that are bound to logical units for operating access to those logical units. Thus, in the media interface commands provided to the media interface controller, the LUN controller is specified to process the media interface commands and access the logical unit by describing the logical unit to be accessed (e.g., the LUN number).

[0028] In existing solutions, besides performing XOR calculations during the process of the media interface controller providing data (e.g., D(0)) to the NVM chip via programming commands, an additional function is added to the media interface controller, enabling it to perform XOR operations on specified data in DRAM without necessarily writing that specified data to the NVM chip. Therefore, when operating on page stripes with larger P values, the calculation of D(Q) is divided into multiple segments. For example, in the first segment, D(0) XOR D(1) XOR (D2)... XOR D(m) (resulting in temp) is calculated, while in the second segment, temp XOR D(m+1) XOR... XOR D(P-1) is calculated to obtain D(Q). The temp value transmitted to the XOR calculation unit in the second segment is not written to the NVM chip.

[0029] The operation of performing an XOR calculation on specified data in DRAM without writing that specified data to the NVM chip is called a parity data calculation operation (abbreviated as R operation). In an R operation, two operations participate in the XOR calculation: one from the XOR cache and one from DRAM. Therefore, the media interface command instructing the media interface controller to perform the R operation needs to describe the DRAM address and specify the XOR cache to be used. The result of the XOR calculation in the R operation is retained in the XOR cache.

[0030] The media interface command that instructs the media interface controller to perform a programming operation means writing specified data from DRAM to a specified physical address of the NVM chip via the Program command, and incidentally performing an XOR calculation between the specified data and data in the XOR cache, with the result stored in the XOR cache. This operation is simply referred to as the P operation. Summary of the Invention

[0031] Storage devices use large blocks to leverage RAID technology to improve data reliability when storing data on NVM chips. When a small number of data points fail, RAID technology can be used for data recovery to obtain the correct data. Large blocks also provide the ability to operate on individual logical units within the storage device in parallel, thereby maximizing the read and write bandwidth of the NVM chips. When all NVM chips in the storage device provide logical units or physical blocks for large blocks, the storage device can fully utilize the NVM chip bandwidth by maintaining a single large block at any given time. Maintaining large blocks also requires resources (called large block resources). For example, the XOR cache used to compute the parity data required for the large block is an important large block resource. The XOR cache is implemented using SRAM (Static Random Access Memory) within the control unit. SRAM is expensive for the control unit chip, so the number of XOR caches is usually small. For example, the control unit provides XOR caches for 1, 2, or 4 page stripes. This results in a relatively small number of large blocks that the control unit maintains simultaneously at any given time (e.g., 1, 2, or 4).

[0032] In the NVMe Zoned Namespace protocol (in https: / / nvmexpress.org / wp-content / uploads / NVM-Express-Zoned-Namespace-Command-Set-Specification-1.1c- 2022.10.03-Ratified.pdfIn this protocol, hosts are allowed to create and use multiple Zones. A Zone is an object defined by the protocol at the functional level for storing data. Typically, large blocks provide storage space for Zones, with a one-to-one correspondence between Zones and blocks, allowing hosts to perceive and manipulate these blocks. Host creation and use of Zones are largely driven by application needs. For example, for servers in data centers or cloud computing platforms, a corresponding Zone is maintained for each user's data stream served simultaneously, and each Zone is expected to act as an independent storage device for the user's data stream. Therefore, hosts tend to maintain and use a larger number of Zones at any given time.

[0033] In storage devices, zones are implemented using blocks, with a one-to-one correspondence between blocks and zones. However, the number of blocks that a storage device can maintain simultaneously is limited by the number of block resources available, resulting in a smaller number of blocks that the storage device can provide than the number of zones required by the host. Therefore, there is an urgent need to improve storage devices so that they can support a larger number of zones simultaneously.

[0034] Furthermore, the host tends to allocate different zones for each user's data stream to reduce the interference of different data streams on the performance of the storage device. Thus, the host expects each zone to have reserved performance, that is, as the number of zones used increases, the host can obtain further storage bandwidth from the storage device, and the impact of fluctuations in the data stream bandwidth of one zone on the performance of other zones is suppressed.

[0035] The design goal of existing large blocks is to provide the ability to operate multiple LUNs in parallel. By providing physical blocks for large blocks with different LUNs, read and write access to large blocks is transformed into parallel access to multiple physical blocks. However, this also means that increasing the number of large blocks does not, or is difficult to, bring performance improvements, because a single or a few large blocks have already exhausted the read and write bandwidth of multiple NVM chips.

[0036] Therefore, using existing technologies to construct large blocks to implement Zones makes it difficult to achieve the goals of increasing the number of Zones, obtaining further storage bandwidth from the storage device, and suppressing the impact of Zone data stream bandwidth fluctuations on the performance of other Zones. It also suffers from the drawback of long XOR cache occupancy times. Based on this, embodiments of this application provide a new method for constructing large blocks, improving the structure of the large blocks so that the constructed large blocks can achieve the above objectives.

[0037] In a first aspect, embodiments of this application provide a storage command processing method for accessing a Zone, applied to a storage device, the storage device including multiple LUNs;

[0038] In response to receiving a first storage command indicating a write operation to access the first Zone, the first page stripe in the first block corresponding to the first Zone is retrieved, wherein the multiple physical blocks included in the first block all come from the first LUN;

[0039] A first media interface command is generated, which instructs the writing of user data to the first page stripe. The first media interface command is processed by the first LUN controller corresponding to the first LUN.

[0040] In this context, each Zone corresponds one-to-one with a block. All physical blocks included in a block come from the same LUN. When multiple Zones correspond to different blocks that correspond to different LUNs, access to these multiple Zones is processed in parallel by multiple LUN controllers.

[0041] Optionally, in response to a second storage command that accesses the second Zone and indicates a write operation, a second page stripe in the second block corresponding to the second Zone is retrieved, wherein the multiple physical blocks included in the second block all come from the second LUN;

[0042] A second media interface command is generated, which instructs the writing of user data to the second page stripe. The second media interface command is processed by the second LUN controller corresponding to the second LUN.

[0043] The processing of the first medium interface command by the first LUN controller and the processing of the second medium interface command by the second LUN controller occur in parallel.

[0044] Optionally, the first page strip includes multiple physical pages, which are ordered and all originate from the physical blocks of the first LUN.

[0045] Optionally, the second page strip includes multiple physical pages, which are ordered and all originate from the physical blocks of the second LUN.

[0046] Optionally, the user data written to the first page strip is written sequentially to multiple sorted physical pages of the first page strip in the order in which it was written. The multiple physical pages of the first page strip are sorted according to the physical block number of the physical block in the first LUN.

[0047] Optionally, the user data written to the second page strip is written sequentially to multiple sorted physical pages of the second page strip in the order in which it was written. The multiple physical pages of the second page strip are sorted according to the physical block number of the physical block in the second LUN.

[0048] Secondly, embodiments of this application provide a storage command processing method for accessing a Zone, applied to a storage device, the storage device including multiple LUNs;

[0049] In response to receiving a first storage command indicating a write operation to access the first Zone, the first page stripe in the first block corresponding to the first Zone is retrieved, wherein the first block includes multiple physical blocks from the first LUN and the second LUN;

[0050] A first media interface command is generated, which instructs the writing of user data to the first page stripe. The first media interface command is processed by a first LUN controller corresponding to the first LUN or by a second LUN controller corresponding to the second LUN.

[0051] In this context, each Zone corresponds one-to-one with a block. All physical blocks included in a block come from two different LUNs. When multiple Zones correspond to different LUN groups that include two LUNs, access to the multiple Zones is processed in parallel by the LUN controllers corresponding to the multiple blocks.

[0052] Optionally, in response to a second storage command that accesses the second Zone and indicates a write operation, a second page stripe in the second block corresponding to the second Zone is retrieved, wherein the second block comprises multiple physical blocks from the third LUN and the fourth LUN;

[0053] A second media interface command is generated, which instructs the writing of user data to the second page stripe. The second media interface command is processed by the third LUN controller corresponding to the third LUN or by the fourth LUN controller corresponding to the fourth LUN.

[0054] The processing of the first media interface command by the first LUN controller or the second LUN controller occurs in parallel with the processing of the second media interface command by the third LUN controller or the fourth LUN controller.

[0055] Optionally, the first page strip includes a first subpage strip and a second subpage strip, wherein all physical pages of the first subpage strip come from physical blocks of the first LUN, and all physical pages of the second subpage strip come from physical blocks of the second LUN;

[0056] The command to access the media interface of the first subpage stripe is processed by the first LUN controller, and the command to access the media interface of the second subpage stripe is processed by the second LUN controller.

[0057] Optionally, adjacent user data written to the first page strip is stored in the first subpage strip and the second subpage strip, respectively; or

[0058] After the first subpage strip is filled, user data is written to the second subpage strip;

[0059] Specifically, user data written to the first subpage stripe is sequentially written to multiple sorted physical pages of the first subpage stripe, and the multiple physical pages of the first subpage stripe are sorted according to the physical block number of the physical block they belong to in the first LUN; user data written to the second subpage stripe is sequentially written to multiple sorted physical pages of the second subpage stripe, and the multiple physical pages of the second subpage stripe are sorted according to the physical block number of the physical block they belong to in the second LUN.

[0060] Optionally, the second page strip includes a third subpage strip and a fourth subpage strip, wherein all physical pages of the third subpage strip come from physical blocks of the third LUN, and all physical pages of the fourth subpage strip come from physical blocks of the fourth LUN;

[0061] The command to access the media interface of the third subpage stripe is processed by the third LUN controller, and the command to access the media interface of the fourth subpage stripe is processed by the fourth LUN controller.

[0062] Optionally, adjacent user data written to the second page strip is stored in the third subpage strip and the fourth subpage strip, respectively; or

[0063] After the third subpage strip is filled, user data is written to the fourth subpage strip;

[0064] Specifically, user data written to the third subpage strip is sequentially written to multiple sorted physical pages of the third subpage strip, and the multiple physical pages of the third subpage strip are sorted according to the physical block number of the physical block they belong to in the third LUN; user data written to the fourth subpage strip is sequentially written to multiple sorted physical pages of the fourth subpage strip, and the multiple physical pages of the fourth subpage strip are sorted according to the physical block number of the physical block they belong to in the fourth LUN.

[0065] Optionally, the first media interface command carries a first XOR cache allocated for the first page stripe, and the first media interface command is used to instruct the computed parity data to be stored in the first XOR cache.

[0066] Optionally, the first media interface command is further used to instruct the LUN controller corresponding to the first block to move the data in the first XOR cache to DRAM after processing the first media interface command;

[0067] The LUN controller corresponding to the first large block allocates a DRAM address in the DRAM to store the data in the first XOR cache.

[0068] Record the association between the DRAM address and the first page stripe.

[0069] Optionally, the first media interface command also carries a DRAM address for accommodating the data in the first XOR cache. The DRAM address is used to instruct the LUN controller corresponding to the first block to move the data in the first XOR cache to DRAM after processing the first media interface command.

[0070] Optionally, the method further includes:

[0071] After generating the first media interface command, a third media interface command is generated that instructs the data in the first XOR cache to be moved to DRAM;

[0072] The LUN controller corresponding to the first large block moves the data in the first XOR cache to DRAM according to the third media interface command, and provides the DRAM address;

[0073] Record the association between the DRAM address and the first page stripe.

[0074] Optionally, the method further includes:

[0075] In response to a third storage command that accesses the third Zone and indicates a write operation, the third page stripe in the third block corresponding to the third Zone is retrieved;

[0076] Allocate the first XOR cache to the third page stripe;

[0077] A fourth media interface command is generated, carrying the first XOR cache. The fourth media interface command instructs the writing of user data to the third page stripe and the calculation of the check data stored in the first XOR cache.

[0078] Thirdly, embodiments of this application provide a storage device, including a control component and a plurality of LUNs. The control component includes a storage command processing unit and a media interface controller, and the media interface controller includes a plurality of LUN controllers.

[0079] In response to a first storage command that accesses the first Zone and indicates a write operation, the storage command processing unit retrieves the first page stripe in the first block corresponding to the first Zone and generates a first media interface command; wherein, the multiple physical blocks included in the first block all come from the first LUN, and the first media interface command indicates writing user data to the first page stripe;

[0080] The first LUN controller corresponding to the first LUN processes the first media interface command;

[0081] In this context, each Zone corresponds one-to-one with a block. All physical blocks included in a block come from the same LUN. When multiple Zones correspond to different blocks that correspond to different LUNs, access to these multiple Zones is processed in parallel by multiple LUN controllers.

[0082] Optionally, in response to a second storage command that accesses the second Zone and indicates a write operation, the storage command processing unit obtains the second page stripe in the second block corresponding to the second Zone and generates a second media interface command, wherein the multiple physical blocks included in the second block all come from the second LUN, and the second media interface command indicates writing user data to the second page stripe;

[0083] The second LUN controller corresponding to the second LUN processes the second media interface command;

[0084] The processing of the first medium interface command by the first LUN controller and the processing of the second medium interface command by the second LUN controller occur in parallel.

[0085] Optionally, the first page strip includes multiple physical pages, which are ordered and all originate from the physical blocks of the first LUN.

[0086] Optionally, the second page strip includes multiple physical pages, which are ordered and all originate from the physical blocks of the second LUN.

[0087] Optionally, the user data written to the first page strip is written sequentially to multiple sorted physical pages of the first page strip in the order in which it was written. The multiple physical pages of the first page strip are sorted according to the physical block number of the physical block in the first LUN.

[0088] Optionally, the user data written to the second page strip is written sequentially to multiple sorted physical pages of the second page strip in the order in which it was written. The multiple physical pages of the second page strip are sorted according to the physical block number of the physical block in the second LUN.

[0089] Fourthly, embodiments of this application provide a storage device, including a control component and a plurality of LUNs. The control component includes a storage command processing unit and a media interface controller, and the media interface controller includes a plurality of LUN controllers.

[0090] In response to receiving a first storage command that accesses the first Zone and indicates a write operation, the storage command processing unit obtains the first page stripe in the first block corresponding to the first Zone and generates a first media interface command; wherein, the first block includes multiple physical blocks from the first LUN and the second LUN, and the first media interface command indicates writing user data to the first page stripe;

[0091] The first LUN controller corresponding to the first LUN or the second LUN controller corresponding to the second LUN processes the first media interface command.

[0092] In this context, each Zone corresponds one-to-one with a block. All physical blocks included in a block come from two different LUNs. When multiple Zones correspond to different LUN groups that include two LUNs, access to the multiple Zones is processed in parallel by the LUN controllers corresponding to the multiple blocks.

[0093] Optionally, in response to receiving a second storage command that accesses the second Zone and indicates a write operation, the storage command processing unit obtains the second page stripe in the second block corresponding to the second Zone and generates a second media interface command; wherein the multiple physical blocks included in the second block come from the third LUN and the fourth LUN, and the second media interface command indicates writing user data to the second page stripe;

[0094] The third LUN controller corresponding to the third LUN or the fourth LUN controller corresponding to the fourth LUN processes the second media interface command.

[0095] The processing of the first media interface command by the first LUN controller or the second LUN controller occurs in parallel with the processing of the second media interface command by the third LUN controller or the fourth LUN controller.

[0096] Optionally, the first page strip includes a first subpage strip and a second subpage strip, wherein all physical pages of the first subpage strip come from physical blocks of the first LUN, and all physical pages of the second subpage strip come from physical blocks of the second LUN;

[0097] The first LUN controller processes the media interface command to access the first subpage stripe, and the second LUN controller processes the media interface command to access the second subpage stripe.

[0098] Optionally, adjacent user data written to the first page strip is stored in the first subpage strip and the second subpage strip, respectively; or

[0099] After the first subpage strip is filled, user data is written to the second subpage strip;

[0100] Specifically, user data written to the first subpage stripe is sequentially written to multiple sorted physical pages of the first subpage stripe, and the multiple physical pages of the first subpage stripe are sorted according to the physical block number of the physical block they belong to in the first LUN; user data written to the second subpage stripe is sequentially written to multiple sorted physical pages of the second subpage stripe, and the multiple physical pages of the second subpage stripe are sorted according to the physical block number of the physical block they belong to in the second LUN.

[0101] Optionally, the second page strip includes a third subpage strip and a fourth subpage strip, wherein all physical pages of the third subpage strip come from physical blocks of the third LUN, and all physical pages of the fourth subpage strip come from physical blocks of the fourth LUN;

[0102] The third LUN controller processes the media interface command to access the third subpage stripe, and the fourth LUN controller processes the media interface command to access the fourth subpage stripe.

[0103] Optionally, adjacent user data written to the second page strip is stored in the third subpage strip and the fourth subpage strip, respectively; or

[0104] After the third subpage strip is filled, user data is written to the fourth subpage strip;

[0105] Specifically, user data written to the third subpage strip is sequentially written to multiple sorted physical pages of the third subpage strip, and the multiple physical pages of the third subpage strip are sorted according to the physical block number of the physical block they belong to in the third LUN; user data written to the fourth subpage strip is sequentially written to multiple sorted physical pages of the fourth subpage strip, and the multiple physical pages of the fourth subpage strip are sorted according to the physical block number of the physical block they belong to in the fourth LUN.

[0106] Optionally, the first media interface command carries a first XOR cache allocated for the first page stripe, and the first media interface command is used to instruct the computed parity data to be stored in the first XOR cache.

[0107] Optionally, the first media interface command is further used to instruct the LUN controller corresponding to the first block to move the data in the first XOR cache to DRAM after processing the first media interface command;

[0108] The LUN controller corresponding to the first large block allocates a DRAM address in the DRAM to store the data in the first XOR cache, and provides the DRAM address to the storage command processing unit;

[0109] The storage command processing unit records the association between the DRAM address and the first page stripe.

[0110] Optionally, the first media interface command also carries a DRAM address for storing data in the first XOR cache;

[0111] After processing the first media interface command, the LUN controller corresponding to the first block moves the data in the first XOR cache to DRAM.

[0112] Optionally, after generating the first media interface command, the storage command processing unit generates a third media interface command instructing the data in the first XOR cache to be moved to the DRAM.

[0113] The LUN controller corresponding to the first large block moves the data in the first XOR cache to DRAM according to the third media interface command, and provides the DRAM address;

[0114] The storage command processing unit records the association between the DRAM address and the first page stripe.

[0115] Optionally, in response to a third storage command that accesses the third Zone and indicates a write operation, the storage command processing unit obtains the third page stripe in the third block corresponding to the third Zone and allocates the first XOR cache to the third page stripe.

[0116] The storage command processing unit generates a fourth media interface command carrying the first XOR cache;

[0117] The LUN controller corresponding to the third block processes the fourth media interface command, writes user data to the third page stripe, and calculates and stores the check data in the first XOR cache.

[0118] According to the embodiments of this application, by improving the construction method of large blocks, large blocks are constructed on the basis of LUNs, which realizes the isolation between different Zones, eliminates the impact of IO commands accessing a Zone on the performance of other Zones, and as the number of Zones increases, the read and write bandwidth implemented by the storage device is the sum of the read and write bandwidth of each large block, enabling the host to obtain further storage bandwidth from the storage device and experience a significant performance improvement as the number of Zones increases. Attached Figure Description

[0119] Figure 1A A block diagram representing a storage device;

[0120] Figure 1B A detailed block diagram of the control components of the storage device is shown;

[0121] Figure 2A Diagram 1 showing a large block;

[0122] Figure 2B Diagram 2 showing a large block;

[0123] Figure 3A A schematic diagram illustrating page stripes;

[0124] Figure 3B Schematic diagram 2 showing page stripes;

[0125] Figure 4A A schematic diagram illustrating the interaction between the media interface controller, DRAM, and NVM chip;

[0126] Figure 4B Schematic diagram 2 illustrating the interaction between the media interface controller, DRAM, and NVM chip;

[0127] Figure 5 A schematic diagram illustrating the interaction between the media interface controller and the host and logic units;

[0128] Figure 6 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write data to a page strip according to an embodiment of this application.

[0129] Figure 7 A flowchart illustrating how a storage command processing unit processes storage commands according to an embodiment of this application;

[0130] Figure 8 A schematic diagram illustrating the interrupted page stripe writing process provided in an embodiment of this application;

[0131] Figure 9A A flowchart illustrating the process of releasing the XOR cache after a page stripe is full, provided as an embodiment of this application;

[0132] Figure 9BA flowchart for releasing the XOR cache after the page stripe is full, provided as another embodiment of this application;

[0133] Figure 10 This illustration shows a schematic diagram of processing a storage command to access a Zone and write data to a page stripe in an application scenario according to an embodiment of this application.

[0134] Figure 11 This illustration shows a schematic diagram of processing a storage command to access a Zone and write data to a page stripe in another application scenario according to an embodiment of this application.

[0135] Figure 12 A schematic diagram of a bulk construction method provided in one embodiment of this application is shown;

[0136] Figure 13 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write data to a large block, according to an embodiment of this application.

[0137] Figure 14 This illustration shows a schematic diagram of a bulk construction method provided in yet another embodiment of this application;

[0138] Figure 15 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write data to a large block, according to another embodiment of this application.

[0139] Figure 16 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write large blocks of data according to another embodiment of this application;

[0140] Figure 17 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write data to a large block, according to another embodiment of this application.

[0141] Figure 18 A flowchart illustrating the process of a storage command processing unit for processing storage commands, provided in another embodiment of this application. Detailed Implementation

[0142] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0143] In this embodiment, the host perceives and operates on large blocks through Zones, directly managing the physical address space of the storage device without needing to access the storage device based on the mapping relationship between LBA and PPA. By introducing Zones, the need to deploy and maintain FTL tables for logical address to physical address translation within the storage device is avoided.

[0144] According to embodiments of this application, a host is allowed to use a greater number of Zones at the same time. The number of Zones that can be used simultaneously can be the same as the number of Zone descriptors, and far exceed the number of bulk resources owned by the media interface controller. This eliminates or reduces the impact of the limitation on the number of bulk resources that can be used simultaneously, caused by the limitation of the bulk resources themselves, on the number of available Zones.

[0145] Figure 6 This illustration shows a schematic diagram of the storage command processing unit controlling the media interface controller to write data to the page strip according to an embodiment of this application.

[0146] The NVMe protocol defines various host commands for accessing zones, including read commands, write commands, and Open Zone commands. Host commands for accessing zones carry the zone index to specify the zone to be accessed. The control unit maintains a Zone descriptor for each zone. The Zone descriptor records information such as the Zone ID (used to identify the zone), the block index corresponding to the zone, and the zone's status. The control unit also maintains a Zone descriptor table, where entries record the zone descriptor and its corresponding page stripe. Page stripes are used to carry data written to their corresponding zones. It can be understood that there is a one-to-one correspondence between zone descriptors and blocks, thus page stripes in the Zone descriptor table belong to different blocks.

[0147] The control unit receives host commands from the host to access a Zone via the host interface. For example, the host interface sends the host command to the host command processing unit. For example, for an Open Zone command, the Zone's state is recorded or updated in the Zone descriptor corresponding to the Zone index. The host command processing unit generates a storage command to access the Zone based on the host command and sends it to the storage command processing unit.

[0148] The storage command processing unit processes storage commands to access the Zone and generates media interface commands to provide to the media interface controller. According to embodiments of this application, the storage command processing unit processes storage commands through, for example, three independent processing procedures. Figure 6The diagram illustrates the processing of storage commands for accessing a Zone, the process of interrupting page stripe writing, and the process of releasing the XOR cache after the page stripe is full. These processes will be described in detail below.

[0149] The media interface controller includes, for example, a media interface command processing unit, a LUN controller corresponding to each LUN, and an XOR calculation unit. The XOR calculation unit includes multiple XOR buffers. As an example, Figure 6 The text shows XOR cache 0 and XOR cache 1.

[0150] The control unit is also coupled to the DRAM. The DRAM includes multiple cache cells corresponding to the XOR cache. Figure 6 (This is denoted as B). Data in the XOR cache can be moved to the DRAM cache cells. Data in the DRAM cache cells can then be used to populate the XOR cache.

[0151] For example, with the Open Zone command, the host command processing unit also generates a corresponding storage command to access the Zone and provides it to the storage command processing unit. According to embodiments of this application, the control unit does not limit the number of Zones in the Open state at any given time. Therefore, the host can set any number of Zones to the Open state using the Open Zone command. These Zones are recorded in a Zone descriptor table.

[0152] Optionally, the storage command processing unit allocates blank page stripes to a zone based on the storage command that accesses the zone, and records the mapping relationship between zone descriptors and page stripes in the zone descriptor table. For example... Figure 6 The mapping relationship between Zone descriptor 0 and page stripe 0, Zone descriptor 1 and page stripe 1, Zone descriptor 2 and page stripe 2, and Zone descriptor 3 and page stripe 3 are recorded.

[0153] For host commands that access a Zone to write data, such as IO command 1 sent by the host to access a Zone and indicate a write operation, the host interface receives IO command 1 and provides it to the host command processing unit. IO command 1 indicates that data D(0) should be written to a certain Zone. The host command processing unit receives IO command 1 from the host interface and generates a corresponding storage command 1 for accessing the Zone, which is then provided to the storage command processing unit. The storage command processing unit responds to storage command 1 by processing it according to the storage command processing procedure for accessing a Zone. The storage command processing unit obtains the Zone descriptor based on the Zone accessed by storage command 1, retrieves the corresponding page stripe based on the mapping relationship between the Zone descriptor and page stripes (e.g., page stripe 0), and allocates a large block of resources (e.g., XOR cache 0) for page stripe 0. (This is understandable; see also...) Figure 6 In the Zone descriptor table, a page stripe represents a page stripe that has been allocated to carry write data to the Zone, but it may not have large blocks of resources. Therefore, according to embodiments of this application, when processing a storage command to write data to a page stripe, it is necessary to allocate large blocks of resources, such as XOR cache, for that page stripe.

[0154] If XOR cache allocation fails, the storage command is temporarily cached without further processing. Upon successful XOR cache allocation, the storage command processing unit generates Media Interface Command 1 carrying the allocated XOR cache (e.g., XOR cache 0) and sends it to the Media Interface Controller. The Media Interface Controller includes the Media Interface Command Processing Unit and multiple LUN controllers, each corresponding to one LUN. The Media Interface Command Processing Unit processes the received Media Interface Command 1 indicating a write operation to generate LUN Controller Write Command 1. Neither Media Interface Command 1 nor LUN Controller Write Command 1 carries a physical address. When writing data to page stripe 0, data is written sequentially to the corresponding physical pages of page stripe 0, such as sequentially writing data to physical pages P0-0, P0-1, P0-2, P0-3…P0-(P-1). Since the first physical page is P0-0, the corresponding LUN is LUN0. According to the correspondence between LUN controllers and LUNs, the media interface command processing unit provides LUN controller write command 1 to LUN controller 0 corresponding to LUN0. LUN controller 0 responds to the received LUN controller write command 1 to generate storage media access command 1 (programming command 1) and writes data D(0) to physical page P0-0 of page stripe 0 based on programming command 1. Thus, the writing of data D(0) is completed.

[0155] During the process of writing data to page stripe 0, the checksum data to be written to page stripe 0 is also calculated. XOR cache 0 is allocated for the first time for page stripe 0, so the initial value in XOR cache 0 is 0. When writing data to physical page P0-0 of page stripe 0, 0XOR D(0) is calculated, and the calculation result is cached in XOR cache 0.

[0156] Next, the host instructs the host to write data D(1) to the Zone corresponding to Zone descriptor 0 via a host command to access the Zone. The host command processing unit generates a storage command 2 to access the Zone and provides it to the storage command processing unit. In response to storage command 2, the storage command processing unit retrieves the corresponding page stripe 0 from the Zone descriptor table. At this time, page stripe 0 still occupies XOR cache 0, and no XOR cache needs to be allocated. The storage command processing unit generates a media interface command 2 carrying the allocated XOR cache 0 and sends the media interface command 2 to the media interface controller's media interface command processing unit. The media interface command processing unit processes the media interface command 2 to generate LUN controller write command 2. When writing data to page stripe 0, data needs to be written to physical page P0-1 of page stripe 0 in sequence. Since physical page P0-1 is the second physical page in page stripe 0, the corresponding LUN is LUN1. According to the correspondence between LUN controller and LUN, the media interface command processing unit provides LUN controller write command 2 to LUN controller 1 corresponding to LUN1. LUN controller 1 responds to the received LUN controller write command 2 to generate storage media access command 2 (programming command 2), and writes data D(1) to physical page P0-1 of page stripe 0 based on programming command 2. Thus, the writing of data D(1) is completed.

[0157] Since page stripe 0 still occupies XOR cache 0 at this time, and XOR cache 0 caches the calculation result of 0XOR D(0), when writing data to physical page P0-1 of page stripe 0, 0XOR D(0)XOR D(1) is calculated, and the calculation result continues to be cached in XOR cache 0.

[0158] Similarly, by processing storage commands that access the Zone, data is continuously written to the page stripe, and checksum data is calculated.

[0159] For the storage command processing unit, upon receiving a storage command to access a Zone, it retrieves the corresponding page stripe. This page stripe can be a blank page stripe or a page stripe already containing data. Accordingly, when allocating an XOR cache for this page stripe, if the page stripe is blank, an XOR cache is allocated for the first time. If the page stripe contains data, the allocated XOR cache can be the same as or different from the previously allocated XOR cache. It is understood that since the release of the XOR cache does not always occur, if the page stripe contains data, the allocated XOR cache could also be an XOR cache that has already been allocated to that page stripe and has not yet been released.

[0160] According to embodiments of this application, even if the number of XOR caches is limited, all Zones represented by the Zone descriptors recorded in the Zone descriptor table can be in an Open state and carry data written to them by the host. Compared with the prior art, the binding relationship between the page stripe currently being written data and the XOR cache is broken. When a storage command to access a Zone needs to be processed, an XOR cache is allocated to its corresponding page stripe, so that a small amount of XOR cache can be used for a larger number of page stripes and a larger number of Zones.

[0161] Figure 7 This is a flowchart illustrating how a storage command processing unit, as provided in an embodiment of this application, processes storage commands.

[0162] Step 710: Obtain the corresponding page stripe based on the Zone accessed by the storage command.

[0163] After receiving a storage command from the host command processing unit to access a Zone, the storage command processing unit obtains the Zone descriptor based on the Zone accessed by the storage command, and retrieves the corresponding page stripe based on the mapping relationship between the Zone descriptor and page stripes. Optionally, for a Zone without page stripes, a blank page stripe is also retrieved from its corresponding block.

[0164] Step 720: Allocate an XOR cache for the obtained page stripes.

[0165] Page stripes obtained based on Zone descriptors can be either blank page stripes or page stripes with written data. If XOR cache allocation for a page stripe fails, the store command is cached and retried at an appropriate time. Figure 7 The demonstrated processing flow handles the cache storage commands.

[0166] If the obtained page stripe is a blank page stripe, the allocated XOR cache is the first XOR cache allocated for that page stripe, and this XOR cache is initialized to a specified value, for example, all zeros. If the obtained page stripe is a page stripe with written data, the allocated XOR cache can be the same XOR cache as the XOR cache corresponding to the previous page stripe, or it can be a different XOR cache.

[0167] For page stripes with written data, the intermediate calculation results of their corresponding parity data are stored in DRAM. After reallocating XOR cache for that page stripe, the intermediate calculation results stored in DRAM need to be moved to the newly allocated XOR cache. That is, when the writing process of a page stripe is interrupted, the intermediate calculation results of the parity data are moved to DRAM to release the XOR cache currently occupied by the page stripe. When writing data to that page stripe again, the XOR cache is reallocated, and the intermediate calculation results stored in DRAM are moved to the newly allocated XOR cache to continue calculating the parity data for the data written to that page stripe.

[0168] If the obtained page strip is a page strip for writing data, the address of the intermediate calculation result required for the current page strip in DRAM can be obtained according to the pre-recorded association between page strip and move address, and the intermediate calculation result can be moved to the newly allocated XOR cache.

[0169] Furthermore, in the case where the obtained page strip is a page strip for writing data, the allocated XOR cache can also be an XOR cache that has been previously allocated to the page strip and has not been released. In this case, the XOR cache already records the intermediate calculation results required for the current page strip, without needing to move data from DRAM.

[0170] Step 730: Generate a media interface command carrying the allocated XOR cache and send the media interface command to the media interface controller.

[0171] The media interface controller responds to the received media interface command by writing data to the page stripe and calculating checksum data. The specific operation of the media interface controller is as follows: the media interface command processing unit processes the media interface command to generate a LUN controller write command, determines which physical page in the page stripe to write data to based on the page stripe indicated by the media interface command, determines the LUN based on the corresponding physical page, and then determines the LUN controller, providing the LUN controller write command to the corresponding LUN controller. The LUN controller responds to the received LUN controller write command by generating a programming command, writes data to the corresponding physical page in the page stripe based on the programming command, and calculates new checksum data using the written data and data in the XOR cache. This new calculated data is also cached in the allocated XOR cache. According to embodiments of this application, since the number of Zones in the Open state may be much greater than the number of large block resources, the available large block resources are insufficient, which may cause failure when allocating XOR cache for storage commands accessing Zones. To reduce the probability of XOR cache allocation failures, or to handle XOR cache allocation failure events, the storage command processing unit also interrupts the page stripe write process to store intermediate calculation results cached in the XOR cache to DRAM, thereby obtaining usable XOR cache. The usable XOR cache can then be allocated to other page stripes to make efficient use of XOR cache resources and enable zones that support greater concurrency.

[0172] The storage command storage unit initiates an interrupt page stripe write process at an appropriate time. For example, an interrupt page stripe write process is initiated when it is identified that a page stripe occupying the XOR cache has not been written to for a long time, or when a high-priority storage command is pending and allocating XOR cache for it fails.

[0173] Figure 8 A flowchart illustrating the interrupted page stripe writing process provided in this application embodiment.

[0174] Step 810: Determine whether to interrupt the write process of a certain page stripe and release the XOR cache occupied by that page stripe.

[0175] Figure 8 The processing shown is initiated based on specific conditions. For example, if a page stripe has not received new data for an extended period, the write process for that page stripe will be interrupted; or, if a high-priority storage command is pending and the allocation of the XOR cache fails, the write process for that page stripe will be interrupted.

[0176] When the storage command processing unit determines that the write process of a certain page stripe needs to be interrupted, it releases the corresponding XOR cache so that the XOR cache can be allocated to other page stripes. This allows different page stripes to share the same XOR cache, avoiding long-term occupation of XOR cache resources by a single page stripe. It enables the use of a small amount of XOR cache resources to support any number of zones used by the host at the same time, and to make efficient use of XOR cache resources.

[0177] Step 820: Generate a media interface command that instructs the transfer of data from the released XOR cache to DRAM.

[0178] Since the XOR cache is used to cache intermediate calculation results of page stripe check data, the stored intermediate calculation results need to be moved to DRAM when the XOR cache is released so that the intermediate calculation results can continue to be stored in DRAM.

[0179] Upon receiving a media interface command from the storage command processing unit, the media interface controller, in response to the command, moves the intermediate calculation results stored in the XOR cache to the DRAM. These intermediate calculation results can be moved to any free location in the DRAM (such as a free cache cell corresponding to the XOR cache). By moving the intermediate calculation results from the XOR cache to the DRAM and releasing the XOR cache, the intermediate calculation results can be preserved while the XOR cache is being cleared. Since no data is stored in the XOR cache at this time, it can be allocated to other page stripes.

[0180] Step 830: Record the association between the record page stripe and the relocation address.

[0181] After the media interface controller moves the intermediate calculation results from the XOR cache to the DRAM, the storage command processing unit records the association between the page strip corresponding to the intermediate calculation result in the XOR cache and the move address. This allows the intermediate calculation result to be retrieved again based on the move address when it is needed in the future. When recording the association, the storage command processing unit can also record the association between Zone, page strip, and move address to determine the corresponding move address of the Zone in the DRAM based on the association.

[0182] It should be noted that the interrupt page stripe writing process and the storage command processing unit's processing of storage commands are two relatively independent processes. The storage command processing unit's processing of storage commands is executed based on the storage commands for accessing the Zone generated by the host's IO commands. The initiation of the interrupt page stripe writing process is not directly related to the host's IO commands, but is initiated by the storage command processing unit based on specific conditions.

[0183] The above content describes the process of interrupting page stripe writing by the storage command processing unit and the process of processing storage commands to access the Zone by the storage command processing unit. The following describes the process of releasing the XOR cache after the page stripe is full.

[0184] For the storage command processing unit, after determining that the media interface controller has completed the calculation of the verification data for a certain page strip (all user data of that page strip has been sent to the NVM chip), it instructs the media interface controller to write the verification data to the specified location of the NVM chip by sending a media interface command.

[0185] Figure 9A This is a flowchart illustrating the process of releasing the XOR cache after a page strip is full, as provided in one embodiment of this application.

[0186] Step 901: Determine that the verification data of a certain page strip is written to the NVM chip.

[0187] For a page stripe comprising P physical pages, after the storage command processing unit provides the media interface controller with user data to be written to P-1 physical pages, the final checksum data for the page stripe is generated. Further media interface commands instruct the storage command processing unit to write the checksum data of the page stripe to a specified location on the NVM chip. After the media interface controller completes the calculation of the checksum data corresponding to the page stripe through the XOR calculation unit, the generated checksum data is located in the XOR cache. In response to the media interface command, the media interface controller writes the data in the XOR cache to the specified location on the NVM chip, such as writing to the last physical page of the page stripe. Optionally, the storage command processing unit sends a media interface command to the media interface controller instructing the write of the checksum data of the page stripe to the specified location on the NVM chip; this media interface command serves as the basis for the write of the checksum data of the page stripe to the NVM chip. Again, optionally, the NVM chip reports a status after successfully processing the programming command; this status is then reported by the media interface controller to the storage command processing unit, which uses this status to identify that the checksum data of the page stripe has been written to the NVM chip.

[0188] Step 902: Release the XOR cache corresponding to this page stripe. The released XOR cache can be allocated to other page stripes to calculate their parity data.

[0189] Figure 9B This is a flowchart illustrating the release of the XOR cache after a page strip is filled, as provided in another embodiment of this application.

[0190] Step 910: Instruct the verification data to be written to the specified location on the NVM chip.

[0191] For a page stripe comprising P physical pages, the storage command processing unit provides the media interface controller with user data to be written to P-1 physical pages. Then, it instructs the media interface controller via further media interface commands to write the parity data of the page stripe to a specified location on the NVM chip. After the media interface controller calculates the parity data corresponding to the page stripe using the XOR calculation unit, the generated parity data is located in the XOR cache. In response to this media interface command, the media interface controller writes the data in the XOR cache to the specified location on the NVM chip, such as writing to the last physical page of the page stripe.

[0192] Step 920: Generate a media interface command to instruct the parity data stored in the XOR cache corresponding to the page stripe to be moved to DRAM.

[0193] After instructing the media interface controller to write the verification data to the NVM chip, the storage command processing unit, unsure whether the verification data can be successfully written and wanting to release the XOR cache as soon as possible, backs up the verification data stored in the XOR cache. The storage command processing unit generates a media interface command instructing the transfer of the verification data and sends it to the media interface controller. The media interface controller then moves the verification data to the DRAM according to the media interface command, thus backing up the verification data in the DRAM.

[0194] Step 930: Release the XOR cache corresponding to the page stripe.

[0195] Since the parity data stored in the XOR cache has been backed up in DRAM, the storage command processing unit can directly release the XOR cache corresponding to the page stripe. It can be understood that the storage command processing unit does not need to issue a media interface command to the media interface controller to release the XOR cache, but only needs to mark the XOR cache as available for reallocation.

[0196] Step 940: Identify whether the verification data has been successfully written to the NVM chip. If the verification data has been successfully written, proceed to step 950; otherwise, proceed to step 960.

[0197] After writing verification data to the NVM chip, the NVM chip can provide corresponding instructions based on the writing status of the verification data. The media interface controller determines whether the verification data has been successfully written by recognizing the instructions given by the NVM chip and informs the storage command processing unit accordingly.

[0198] Step 950: Release the parity data corresponding to the page stripe stored in DRAM.

[0199] After confirming that the verification data has been successfully written to the NVM chip, the backup verification data is no longer needed. At this point, the verification data stored in DRAM can be released. It is understood that the storage command processing unit does not need to issue a media interface command to the media interface controller to release the verification data stored in DRAM; it only needs to mark the storage space in the DRAM as available for accommodating data from other XOR caches.

[0200] Step 960: Generate a media interface command to instruct the NVM chip to write the parity data corresponding to the page stripe stored in DRAM.

[0201] If it is determined that the verification data has not been successfully written to the NVM chip, a media interface command is sent to the media interface controller to instruct the verification data in the DRAM to be written to the NVM chip. In response to the media interface command, the media interface controller retrieves the verification data from the DRAM and writes the retrieved verification data to the NVM chip, so that if the verification data has not been successfully written to the NVM chip, the backup verification data can be used to rewrite the data to the NVM chip.

[0202] It should be noted that the interruption of page stripe writing, the process of the storage command processing unit processing storage commands, and the process of releasing the XOR buffer after the page stripe is full are three independent processes. The storage command processing unit processes storage commands based on the receipt of a storage command to access the Zone. The interruption of page stripe writing is initiated by the storage command processing unit based on specific conditions. The process of releasing the XOR buffer after the page stripe is full occurs based on the generation of page stripe checksum data.

[0203] The storage command processing unit has the ability to process storage commands to access Zones, interrupt page stripe writing processes, and release the XOR cache after a page stripe is full, executing the three mutually independent processes mentioned above. After the page stripe writing process is interrupted, the data in the XOR cache is moved and the XOR cache is released to achieve XOR cache sharing and enable the host to use a larger number of Zones at the same time with a smaller XOR cache.

[0204] The following examples illustrate the implementation process of interrupted page strip writing and rewriting data to the page strip based on trigger conditions in different scenarios to achieve breakpoint continuation writing.

[0205] Figure 10 This illustration shows a schematic diagram of processing a storage command to access a Zone and write data to a page strip in an application scenario according to an embodiment of this application.

[0206] exist Figure 10In the demonstrated application scenario, the host issues an IO command to write 3 copies of data to Zone1. After a period of time, the host stops writing data to Zone1, and then issues another IO command to write 4 copies of data to Zone1. Zone1 is associated with page stripe 1, and the size of page stripe 1 can accommodate 7 copies of user data written by the host.

[0207] like Figure 10 As shown, based on the write command to access Zone 1 issued by the host, three consecutive storage commands to access Zone 1 are generated (denoted as storage command 1, storage command 2, and storage command 3, respectively). The storage command processing unit obtains page stripe 1 based on the mapping relationship between the Zone descriptor and page stripe of the accessed Zone 1.

[0208] When processing storage command 1, the storage command processing unit allocates XOR cache 1 to page stripe 1, generates media interface command 1, and the media interface controller processes media interface command 1 to generate storage media access command 1 (programming command 1). Based on programming command 1, data D(0) is written to page stripe 1. During the data writing process, the media interface controller calculates check data for data D(0) through the XOR calculation unit, and the calculation result is located in XOR cache 1.

[0209] Next, storage command 2 is processed. Storage command 2 also accesses Zone 1, and therefore also needs to write data to page stripe 1. Since XOR cache 1 has already been allocated to page stripe 1, and storage command 2 and storage command 1 are received consecutively, XOR cache 1 has not yet been released. Therefore, when allocating XOR cache to page stripe 1 according to storage command 2, it is still allocated to XOR cache 1. Furthermore, XOR cache 1 already stores the check data for page stripe 1, so there is no need to move data from DRAM to XOR cache 1. Accordingly, the storage command processing unit generates media interface command 2. The media interface controller writes data D(1) to page stripe 1 based on media interface command 2, and uses the XOR calculation unit to calculate check data for data D(1). The calculation result is located in XOR cache 1.

[0210] When processing storage command 3, storage command 3 also accesses Zone 1, and therefore also writes data to page stripe 1. Since XOR cache 1 has been allocated to page stripe 1, and storage command 3 and storage command 2 are received consecutively, when allocating XOR cache to page stripe 1 according to storage command 3, it is still allocated to XOR cache 1, and XOR cache 1 stores the check data for page stripe 1. Based on this, the media interface controller writes data D(2) to page stripe 1 based on media interface command 3 provided by the storage command processing unit, and uses the XOR calculation unit to calculate check data for data D(2). The calculation result is located in XOR cache 1.

[0211] Next, the storage command processing unit has not received a storage command for accessing Zone1 (associated page strip 1) for a long time. According to the instruction of the storage command processing unit, the media interface controller moves the data in XOR cache 1 (the intermediate calculation result of the parity data corresponding to page strip 1) to DRAM. The storage command processing unit correspondingly records <Zone descriptor 1, page strip 1, move address>, and releases XOR cache 1. Since the data in XOR cache 1 is moved to DRAM and XOR cache 1 is released, at this time, the writing process of page strip 1 is interrupted. According to the embodiments of the present application, it is allowed to interrupt the writing process of the page strip, so that when writing data to the page strip, it is not necessary to continuously occupy the XOR cache before the page strip is full, so that a small amount of XOR cache can be used for multiple page strips being written concurrently.

[0212] After a period of time, the storage command processing unit receives a storage command 4 for accessing Zone1 (associated page strip 1) again. When processing storage command 4, the storage command processing unit allocates XOR cache 0 to page strip 1. Based on the recorded association relationship between page strip 1 and the move address (<Zone descriptor 1, page strip 1, move address>), the data stored at this move address in DRAM (the intermediate calculation result of the parity data corresponding to page strip 1) is moved to XOR cache 0. The storage command processing unit generates media interface command 4, and the media interface controller writes data D(3) to page strip 1 based on media interface command 4, and uses the XOR calculation unit to calculate the parity data for data D(3), and the obtained calculation result is located in XOR cache 0. Based on the data D(3) written based on media interface command 4 and the data D(2) written based on media interface command 3 being adjacent on page strip 1, continue to write data to page strip 1 to realize the restoration of the data writing of the page strip and continue writing the data of the page strip at the breakpoint.

[0213] In response to storage command 5 for associated page strip 1 received after storage command 4, the storage command processing unit allocates an XOR cache to page strip 1. Since XOR cache 0 has been allocated to page strip 1 before, and storage command 5 and storage command 4 are received continuously, and XOR cache 0 has not been released at this time, when allocating an XOR cache to page strip 1 according to storage command 5, XOR cache 0 is still allocated. The storage command processing unit generates media interface command 5, and the media interface controller writes data D(4) to page strip 1 based on media interface command 5, and uses the XOR calculation unit to calculate the parity data for data D(4), and the obtained calculation result is located in XOR cache 0.

[0214] In response to the storage command 6 received after storage command 5 for associated page stripe 1, the storage command processing unit also allocates page stripe 1 to XOR cache 0, generates media interface command 6, and the media interface controller writes data D(5) into page stripe 1 based on media interface command 6. The XOR calculation unit calculates the check data for data D(5), and the obtained calculation result is located in XOR cache 0.

[0215] In response to the storage command 7 received after storage command 6 for associated page stripe 1, the storage command processing unit also allocates page stripe 1 to XOR cache 0, generates media interface command 7, and the media interface controller writes data D(6) into page stripe 1 based on media interface command 7. The XOR calculation unit calculates the check data for data D(6), and the calculation result is located in XOR cache 0.

[0216] At this point, the first 7 physical pages of page strip 1 have been filled with user data D(0) to user data D(6). The storage command processing unit instructs the media interface controller to write the calculated parity data of page strip 1 into the 8th physical page of page strip 1, thus achieving successful writing of user data and parity data. After completing the writing of the parity data, the XOR cache 0 is released.

[0217] Figure 11 This illustration shows a schematic diagram of processing a storage command to access a Zone and write data to a page strip in another application scenario according to an embodiment of this application.

[0218] exist Figure 11 In the demonstrated application scenario, the host is simultaneously writing data to four Zones. This includes two available XOR caches: XOR cache 0 and XOR cache 1. Zone 1 is associated with page stripe 1 of block 1, Zone 2 with page stripe 2 of block 2, Zone 3 with page stripe 3 of block 3, and Zone 4 with page stripe 4 of block 4.

[0219] The host issues I / O commands to write 3 copies of data to Zone 1 and 4 copies of data to Zone 3. After a period of time, the host stops writing data to Zone 1 and Zone 3, but writes 3 copies of data to Zone 2 and 2 copies of data to Zone 4. After another period of time, the host stops writing data to Zone 2 and Zone 4, but writes 4 copies of data to Zone 1 and 3 copies of data to Zone 3. After another period of time, the host stops writing data to Zone 1 and Zone 3, but writes 4 copies of data to Zone 2 and 5 copies of data to Zone 4.

[0220] When processing storage command CMD1-1 associated with page stripe 1, the storage command processing unit allocates XOR cache 1 for page stripe 1, generates a media interface command, and the media interface controller processes this command to generate a storage media access command (programming command). Based on this programming command, data is written to page stripe 1. During the data writing process, the media interface controller calculates checksum data for the written data through the XOR calculation unit and stores the calculation result in XOR cache 1. When processing storage command CMD3-1 associated with page stripe 3, the storage command processing unit allocates XOR cache 0 for page stripe 3, generates a media interface command, and the media interface controller processes this command to generate a storage media access command (programming command). Based on this programming command, data is written to page stripe 3. During the data writing process, the media interface controller calculates checksum data for the written data through the XOR calculation unit and stores the calculation result in XOR cache 0.

[0221] Next, the storage command processing unit processes storage commands CMD1-2 and CMD1-3 associated with page stripe 1, and storage commands CMD3-2, CMD3-3, and CMD3-4 associated with page stripe 3. When processing storage command CMD1-2, since XOR cache 1 has already been allocated to page stripe 1, and storage commands CMD1-2 and CMD1-1 are received consecutively, XOR cache 1 has not yet been released. Therefore, when allocating XOR cache for page stripe 1 according to storage command CMD1-2, it is still allocated to XOR cache 1. Furthermore, XOR cache 1 already stores the checksum data for page stripe 1, so there is no need to move data from DRAM to XOR cache 1. Accordingly, the storage command processing unit generates a media interface command based on storage command CMD1-2, the media interface controller writes data to page stripe 1 based on the media interface command, and the XOR calculation unit calculates checksum data for the written data. The calculation result is located in XOR cache 1. The process of processing memory command CMD1-3 is similar to that of processing memory command CMD1-2, and will not be elaborated here. When processing memory command CMD3-2, since XOR cache 0 has already been allocated to page stripe 3, and memory commands CMD3-2 and CMD3-1 are received consecutively, XOR cache 0 has not yet been released. Therefore, when allocating XOR cache for page stripe 3 according to memory command CMD3-2, it is still allocated to XOR cache 0. Furthermore, XOR cache 0 already stores the checksum data for page stripe 3, so there is no need to move data from DRAM to XOR cache 0. Accordingly, the memory command processing unit generates a media interface command based on memory command CMD3-2, the media interface controller writes data to page stripe 3 based on the media interface command, and the XOR calculation unit calculates the checksum data for the written data. The calculation result is located in XOR cache 0. The processes of processing memory commands CMD3-3 and CMD3-4 are similar to those of processing memory command CMD3-2, and will not be elaborated here.

[0222] Following this, the storage command processing unit did not receive storage commands for associated page stripe 1 or page stripe 3, but received storage command CMD2-1 for associated page stripe 2. Since both XOR caches were occupied at this time, there was no available XOR cache. The data in XOR cache 1 was moved to DRAM to free up XOR cache 1, interrupting the write process of page stripe 1. The association between page stripe 1 and the moved address was recorded, and XOR cache 1 was allocated to page stripe 2. Next, the storage command processing unit generated the media interface command corresponding to storage command CMD2-1. The media interface controller processed this media interface command, generating a storage media access command (programming command), and wrote data to page stripe 2 based on this programming command. During the data writing process, the media interface controller calculated checksum data for the written data through the XOR calculation unit and stored the calculated result in XOR cache 1. At this stage, the write process of page stripe 1 was interrupted, and XOR cache 1 occupied by page stripe 1 was allocated to page stripe 2. The processes of writing data to page stripe 2 and page stripe 1 were concurrent, and they shared XOR cache 1.

[0223] Next, the storage command processing unit receives storage command CMD4-1 associated with page stripe 4 and storage command CMD2-2 associated with page stripe 2. Since XOR cache 1 has already been allocated to page stripe 2, and storage commands CMD2-2 and CMD2-1 are received consecutively, XOR cache 1 is allocated to page stripe 2. Furthermore, XOR cache 1 already stores the checksum data for page stripe 2, so there is no need to move data from DRAM to XOR cache 1. Accordingly, the storage command processing unit generates a media interface command corresponding to storage command CMD2-2. The media interface controller writes data to page stripe 2 based on this command, and the XOR calculation unit calculates the checksum data for the written data. The calculation result is located in XOR cache 1. For storage command CMD4-1, since there is no available XOR cache at this time, the data in XOR cache 0 is moved to DRAM to release XOR cache 0, interrupting the writing process of page stripe 3. The association between page stripe 3 and the moved address is recorded, and XOR cache 0 is allocated to page stripe 4. The storage command processing unit generates the media interface command corresponding to storage command CMD4-1. The media interface controller processes this command and generates a storage media access command (programming command). Based on this programming command, data is written to page stripe 4. During the data writing process, the media interface controller calculates checksum data for the written data through the XOR calculation unit and stores the calculation result in XOR cache 0. At this stage, the writing process of page stripe 3 is interrupted, and the XOR cache 0 occupied by page stripe 3 is allocated to page stripe 4. The processes of writing data to page stripe 4 and page stripe 3 are concurrent, and they share XOR cache 0.

[0224] Subsequently, the storage command processing unit receives storage command CMD2-3 associated with page stripe 2 and storage command CMD4-2 associated with page stripe 4. Since storage commands CMD2-3 and CMD2-2 are received consecutively, XOR buffer 1 is allocated to page stripe 2. The storage command processing unit generates a media interface command corresponding to storage command CMD2-3. The media interface controller writes data to page stripe 2 based on this media interface command, and the XOR calculation unit calculates checksum data for the written data. The calculated result is located in XOR buffer 1. Since storage commands CMD4-2 and CMD4-1 are received consecutively, XOR buffer 0 is allocated to page stripe 4. The storage command processing unit generates a media interface command corresponding to storage command CMD4-2. The media interface controller writes data to page stripe 4 based on this media interface command, and the XOR calculation unit calculates checksum data for the written data. The calculated result is located in XOR buffer 0.

[0225] Next, the storage command processing unit receives storage commands CMD1-4 associated with page stripe 1 and CMD3-5 associated with page stripe 3. At this time, both XOR cache 0 and XOR cache 1 are occupied. The two XOR caches are released by interrupting the write process of page stripe 2 and page stripe 4, and XOR caches are allocated for page stripe 1 and page stripe 3. When the write process of page stripe 2 is interrupted, the data in XOR cache 1 (the intermediate calculation result of the parity data corresponding to page stripe 2) is moved to DRAM to release XOR cache 1, and the association between page stripe 2 and the moved address is recorded. When the write process of page stripe 4 is interrupted, the data in XOR cache 0 (the intermediate calculation result of the parity data corresponding to page stripe 4) is moved to DRAM to release XOR cache 0, and the association between page stripe 4 and the moved address is recorded. After XOR cache 1 and XOR cache 0 are released, XOR cache 1 is allocated for page stripe 3, and XOR cache 0 is allocated for page stripe 1. Based on the recorded association between page stripe 1 and the move address, the data stored at that move address in DRAM (the intermediate calculation result of the check data corresponding to page stripe 1) is moved to XOR cache 0. Based on the recorded association between page stripe 3 and the move address, the data stored at that move address in DRAM (the intermediate calculation result of the check data corresponding to page stripe 3) is moved to XOR cache 1. The storage command processing unit generates media interface commands corresponding to storage commands CMD1-4. The media interface controller writes data to page stripe 1 based on the media interface commands and uses the XOR calculation unit to calculate check data for the written data. The calculation result is located in XOR cache 0. The storage command processing unit generates media interface commands corresponding to storage commands CMD3-5. The media interface controller writes data to page stripe 3 based on the media interface commands and uses the XOR calculation unit to calculate check data for the written data. The calculation result is located in XOR cache 1. During this phase, data writing to page stripe 1 and page stripe 3 was resumed.

[0226] Subsequently, the continuously received storage commands CMD1-5, CMD1-6, and CMD1-7 associated with page stripe 1 are processed. Storage commands CMD1-5 and CMD1-4 are received consecutively. When processing storage commands CMD1-5, CMD1-6, and CMD1-7, page stripe 1 corresponds to XOR cache 0. The specific processing procedure is not detailed here. Correspondingly, the continuously received storage commands CMD3-6 and CMD3-7 associated with page stripe 3 are processed. Page stripe 3 corresponds to XOR cache 1. The specific processing procedure is not detailed here.

[0227] Next, the storage command processing unit receives storage command CMD4-3 for page stripe 4. At this time, both XOR cache 0 and XOR cache 1 are occupied. XOR cache 1 is released by interrupting, for example, the write process of page stripe 3, and XOR cache 1 is allocated for page stripe 4. When the write process of page stripe 3 is interrupted, the data in XOR cache 1 (the intermediate calculation result of the parity data corresponding to page stripe 3) is moved to DRAM to release XOR cache 1, and the association between page stripe 3 and the moved address is recorded. Based on the previously recorded association between page stripe 4 and the moved address, the data stored at that moved address in DRAM (the intermediate calculation result of the parity data corresponding to page stripe 4) is moved to XOR cache 1. The storage command processing unit generates a media interface command corresponding to storage command CMD4-3. The media interface controller writes data to page stripe 4 based on this media interface command, and uses the XOR calculation unit to calculate the parity data for the written data. The calculated result is located in XOR cache 1.

[0228] Then, the storage command processing unit receives storage command CMD4-4 associated with page stripe 4 and storage command CMD2-4 associated with page stripe 2. Since XOR cache 1 has already been allocated to page stripe 4, and storage commands CMD4-4 and CMD4-3 are received consecutively, XOR cache 1 continues to be allocated to page stripe 4. Furthermore, XOR cache 1 already stores the checksum data for page stripe 4, so there is no need to move data from DRAM to XOR cache 1. Accordingly, the storage command processing unit generates a media interface command corresponding to storage command CMD4-4. The media interface controller writes data to page stripe 4 based on this command, and uses the XOR calculation unit to calculate the checksum data for the written data. The calculated result is located in XOR cache 1. For storage command CMD2-4, since there is no available XOR cache at this time, the data in XOR cache 0 is moved to DRAM to release XOR cache 0, interrupting the write process of page stripe 1. The association between page stripe 1 and the moved address is recorded, and XOR cache 0 is allocated to page stripe 2. Based on the previously recorded association between page stripe 2 and the move address, the data stored at that move address in DRAM (the intermediate calculation result of the parity data corresponding to page stripe 2) is moved to XOR cache 0. The storage command processing unit generates a media interface command corresponding to storage command CMD2-4. The media interface controller writes data to page stripe 2 based on this media interface command, and uses the XOR calculation unit to calculate the parity data for the written data. The calculation result is located in XOR cache 0.

[0229] Subsequently, the continuously received storage commands CMD4-5, CMD4-6, and CMD4-7 associated with page stripe 4 are processed. Storage commands CMD4-5 and CMD4-4 are received consecutively. When processing storage commands CMD4-5, CMD4-6, and CMD4-7, page stripe 4 corresponds to XOR cache 1. The specific processing procedure is not detailed here. Correspondingly, the continuously received storage commands CMD2-5, CMD2-6, and CMD2-7 associated with page stripe 2 are processed. Page stripe 2 corresponds to XOR cache 0. The specific processing procedure is not detailed here.

[0230] Figure 11 The implementation process shown involves the host concurrently writing data to four page stripes, with two XOR caches shared by the four large blocks, in order to support the host using a large number of zones simultaneously.

[0231] The storage device according to the embodiments of this application supports hosts in creating and simultaneously writing data to virtually any number of zones via the NVMe Zoned Namespace protocol without being limited by large blocks of resources in the control unit. Furthermore, the host tends to provide different zones for each user, and the host expects each zone to have reserved performance; that is, as the number of zones used increases, the host can obtain further storage bandwidth from the storage device, and fluctuations in data bandwidth accessed to each zone have a limited impact on the performance of other zones.

[0232] In the embodiments of this application, by improving the construction method of large blocks, large blocks are constructed on the basis of LUNs, which realizes the isolation between different Zones, eliminates the impact of IO commands accessing Zones on the performance of other Zones, and as the number of Zones increases, the read and write bandwidth implemented by the storage device is the sum of the read and write bandwidth of accessing each Zone (large block), enabling the host to obtain further storage bandwidth from the storage device and experience a significant performance improvement as the number of Zones increases.

[0233] Figure 12 A schematic diagram of a bulk construction method provided in one embodiment of this application is shown.

[0234] like Figure 12 As shown, a large block is composed of multiple physical blocks from a single LUN, transforming access to the large block from parallel access to physical blocks from multiple LUNs into access to physical blocks from the same LUN. Each physical block of the large block provides physical pages to construct page stripes. For each large block, it includes a specified number of physical blocks, and the number of page stripes the large block has is, for example, the number of physical pages that a single physical block has.

[0235] Large blocks are used to store user data and verification data. The verification data is determined based on the user data and can be stored in, for example, the last physical block of the large block. In existing large block construction methods, verification data is stored in the physical block provided by the last LUN. In the large block construction method of this application embodiment, the last physical block of the large block is the physical block with the largest block address or block number among all its physical blocks (such as physical block P). This physical block P is used to store the verification data determined based on the user data corresponding to physical blocks 0 to P-1. For example, each page strip in the M+1 page strips included in the large block includes P+1 physical pages, and the last physical page is used to store the verification data determined based on the user data corresponding to the previous P physical pages.

[0236] Figure 13 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write large blocks of data according to an embodiment of this application.

[0237] Figure 13 The situation shown is the same as Figure 6 The situation shown is similar, the difference being that... Figure 13 In the embodiments, the bulk construction method is similar to Figure 6 Different. With Figure 6 Medium to large blocks consist of physical blocks from multiple LUNs that are different. Figure 13 In this configuration, multiple physical blocks of a large block originate from a single LUN. Upon receiving a storage command 1 indicating a write operation to Zone 0, the storage command processing unit retrieves the corresponding page stripe (e.g., page stripe 0) based on the Zone descriptor and allocates large block resources (e.g., XOR cache 0) to page stripe 0. The storage command processing unit generates a media interface command 1 carrying the allocated XOR cache (e.g., XOR cache 0) and sends it to the media interface controller. The media interface command processing unit in the media interface controller processes the received media interface command 1 indicating a write operation to generate a LUN controller write command 1. Since Zone 0 corresponds to large block 0, and the physical blocks of large block 0 are provided by LUN 0, which corresponds to LUN controller 0, the media interface command processing unit provides the LUN controller write command 1 to LUN controller 0. LUN controller 0, in response to the received LUN controller write command 1, generates storage medium access command 1 (programming command 1). Based on programming command 1, it writes data D(0) to the first physical page of page stripe 0 in block 0, thus completing the writing of data D(0). During the process of writing data to page stripe 0 in block 0, the checksum data to be written to page stripe 0 in block 0 is also calculated. XOR cache 0 is initially allocated for page stripe 0 in block 0, therefore the initial value in XOR cache 0 is 0. When writing data to the first physical page of page stripe 0 in block 0, calculations are performed based on the data to be written and the initial value 0, and the calculation result is cached in XOR cache 0.

[0238] Next, in response to storage command 2, which accesses Zone 1 and indicates a write operation, the storage command processing unit retrieves the corresponding page stripe, such as page stripe 1, based on the Zone descriptor and allocates bulk resources (such as XOR cache 1) to page stripe 1. The storage command processing unit generates a media interface command 2 carrying the allocated XOR cache 1 and sends it to the media interface command processing unit of the media interface controller. The media interface command processing unit processes the media interface command 2 to generate a LUN controller write command 2. Since Zone 1 corresponds to bulk 1, and the physical blocks of bulk 1 are provided by LUN 1, the media interface command processing unit provides the LUN controller write command 2 to the LUN controller 1 corresponding to LUN 1. The LUN controller 1, in response to the received LUN controller write command 2, generates a storage media access command 2 (programming command 2) and writes data to the first physical page of page stripe 1 in bulk 1 based on the programming command 2. During the process of writing data to the first physical page of page stripe 1 in bulk 1, checksum data is calculated based on the written data and the initial value corresponding to XOR cache 1, and the calculation result is cached in XOR cache 1.

[0239] Similarly, by processing storage commands that access the Zone, data is continuously written to the page stripe, and checksum data is calculated. It should be noted that when writing data to a large block, data can be written to the page stripe sequentially, and after one page strip is filled, data is written to the next page stripe.

[0240] In the above implementation, all media interface commands accessing Zone 0 are processed by LUN controller 0, while all media interface commands accessing Zone 1 are processed by LUN controller 1. LUN controller 1's processing of media interface commands does not affect the processing performance of LUN controller 0, thus achieving isolation between Zone 0 and Zone 1 and eliminating the impact of IO commands accessing different Zones on the performance of other Zones. Furthermore, as the number of Zones increases, the read / write bandwidth achieved by the storage device is the sum of the read / write bandwidths of all accessing zones, enabling the host to obtain further storage bandwidth from the storage device.

[0241] Figure 14 A schematic diagram of a bulk construction method provided in another embodiment of this application is shown.

[0242] like Figure 14As shown, the physical blocks constituting a large block are no longer limited to those from a single LUN, but rather from two LUNs. Physical blocks from two LUNs form a large block, transforming access to the large block from parallel access to physical blocks from multiple LUNs into access to physical blocks from two LUNs. Each physical block of the large block provides physical pages to construct page stripes. For each large block, it includes a specified number of physical blocks, and the number of page stripes corresponding to the large block is, for example, the number of physical pages that a single physical block has. Figure 14 In this context, since the physical blocks that make up the large block come from two LUNs, page stripe 0-0 in LUN0 is the first half of page stripe 0 corresponding to large block 0, and page stripe 0-1 in LUN1 is the second half of page stripe 0 corresponding to large block 0.

[0243] In the bulk block construction method of this application embodiment, the last physical block of the bulk block is the last physical block corresponding to the latter LUN of the two LUNs, for example, as Figure 14 As shown, block 0 consists of physical blocks from LUN0 and LUN1. The last physical block of block 0 is physical block P corresponding to LUN1, which is used to store parity data. This parity data is determined based on the user data corresponding to the other physical blocks in block 0. For example, each page stripe in the M+1 page stripes included in the block comprises a corresponding number of physical pages. The last physical page is used to store parity data, which is determined based on the user data corresponding to the other physical pages within the page stripe.

[0244] for Figure 14 The block construction method shown corresponds to a single block IO command, which can utilize the read and write bandwidth provided by two LUNs to achieve better performance; and since there is a one-to-one correspondence between blocks and zones, host users can also experience improved IO performance as the number of zones increases.

[0245] Figure 15 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write large blocks of data according to another embodiment of this application.

[0246] Figure 15 The situation shown is the same as Figure 13 Similar, the difference is, Figure 15 A single block in the LUN consists of physical blocks from two LUNs. Since there is a one-to-one correspondence between LUNs and LUN controllers, access to a single block is handled by both LUN controllers.

[0247] For host commands that access a Zone to write data, such as IO command 1 sent by the host to access a Zone and indicate a write operation, the host interface receives IO command 1 and provides it to the host command processing unit. IO command 1 indicates that data D(0) should be written to a certain Zone (e.g., Zone0). The host command processing unit receives IO command 1 from the host interface and generates a corresponding storage command 1 to access the Zone, which is then provided to the storage command processing unit. The storage command processing unit responds to storage command 1 by obtaining the Zone descriptor based on the Zone accessed by storage command 1, and obtains the corresponding page stripe based on the mapping relationship between the Zone descriptor and page stripes, such as page stripe 0 in block 0. It then allocates block resources (e.g., XOR cache 0) to page stripe 0. Page stripe 0-0 in LUN0 is the first half of page stripe 0, and page stripe 0-1 in LUN1 is the second half of page stripe 0.

[0248] Data written to Zone0 is sequentially written to the page stripes of the larger 0 block, and the writing of data within each page strip is also sequential; this order can be specified. For example, in... Figure 14 In this embodiment, adjacent data within a Zone is stored in two page stripes (0-0 and 0-1), respectively. The first data in a Zone is stored in physical page P0-0 of page stripe 0-0, the second data in a Zone is stored in physical page P0-1 of page stripe 0-1, and the third data in a Zone is stored in physical page provided by physical block 1 of page stripe 0-0. This sequence distributes adjacent writes to a Zone across two LUNs, thereby improving the average bandwidth of the write process and preventing excessive LUN usage due to continuous writes to a Zone, thus reserving bandwidth for writing data to other Zones.

[0249] For example, the sequence is manifested as first writing page stripe 0-0, then writing page stripe 0-1. During the writing of page stripe 0-0, the physical pages provided for page stripe 0-0 are written in the order of physical block 0, physical block 1... physical block P. This sequence can restrict the data written to a Zone to a single LUN, thereby reserving sufficient bandwidth for writing data to other Zones.

[0250] The storage command processing unit generates a media interface command 1 carrying the allocated XOR cache (e.g., XOR cache 0) and sends it to the media interface controller. The media interface command processing unit in the media interface controller processes the received media interface command 1 indicating a write operation to generate a LUN controller write command 1. Based on the LUN to which the physical address to be accessed by the media interface command 1 (e.g., belonging to page stripe 0-0) belongs, the media interface command processing unit provides the LUN controller write command 1 to the LUN controller 0. The LUN controller 0, in response to the received LUN controller write command 1, generates a storage media access command 1 (programming command 1) and writes data D(0) to physical page P0-0 of page stripe 0-0 in block 0. This completes the writing of data D(0). During the data writing process, checksum data is calculated for the written data, and the calculation result is cached in XOR cache 0.

[0251] For the host to send IO command 2 (sent consecutively with IO command 1) to access Zone and indicate a write operation, the host interface receives IO command 2 and provides it to the host command processing unit. IO command 2 indicates that data D(1) should be written to Zone 0. The host command processing unit generates a corresponding storage command 2 to access Zone and provides it to the storage command processing unit. The storage command processing unit obtains the Zone descriptor based on the Zone accessed by storage command 2, obtains page stripe 0 in block 0 based on the mapping relationship between the Zone descriptor and page stripes, and allocates XOR cache 0 for page stripe 0. The storage command processing unit generates a media interface command 2 carrying the allocated XOR cache 0 and sends the media interface command 2 to the media interface controller. The media interface command processing unit in the media interface controller processes the received media interface command 2 indicating a write operation to generate LUN controller write command 2. Based on the LUN to which the physical address to be accessed by Media Interface Command 2 (e.g., belonging to page stripe 0-1) belongs, the Media Interface Command Processing Unit provides LUN Controller Write Command 2 to LUN Controller 1. LUN Controller 1, in response to the received LUN Controller Write Command 2, generates Storage Media Access Command 2 (Programming Command 2), and writes data D(1) to physical page P0-1 of page stripe 0-1 in block 0. Thus, the writing of data D(1) is completed. During the data writing process, checksum data is calculated for the written data, and the calculation result is cached in XOR cache 0.

[0252] For the host sending IO command 3, which indicates a write operation to access a Zone, the host interface receives IO command 3 and provides it to the host command processing unit. IO command 3 indicates that data D(2) should be written to Zone 0. The host command processing unit generates a corresponding storage command 3 to access the Zone and provides it to the storage command processing unit. The storage command processing unit obtains the Zone descriptor based on the Zone accessed by storage command 3, retrieves page stripe 0 in block 0 based on the mapping relationship between the Zone descriptor and page stripes, and allocates XOR cache 0 for page stripe 0. The storage command processing unit generates a media interface command 3 carrying the allocated XOR cache 0 and sends the media interface command 3 to the media interface controller. The media interface command processing unit in the media interface controller processes the received media interface command 3 indicating a write operation to generate a LUN controller write command 3. Based on the LUN to which the physical address to be accessed by the media interface command 3 (e.g., belonging to page stripe 0-0) belongs, the media interface command processing unit provides the LUN controller write command 3 to the LUN controller 0. The LUN controller 0, in response to the received LUN controller write command 3, generates a storage media access command 3 (programming command 3). Based on the programming command 3, it writes data D(2) to the physical page provided by physical block 1 in page stripe 0-0 of block 0. Thus, the writing of data D(2) is completed. During the data writing process, checksum data is calculated for the written data, and the calculation result is cached in XOR cache 0.

[0253] For the host sending IO command 4, which indicates a write operation to access a Zone, the host interface receives IO command 4 and provides it to the host command processing unit. IO command 4 indicates that data D(3) should be written to Zone 0. The host command processing unit generates a corresponding storage command 4 to access the Zone and provides it to the storage command processing unit. The storage command processing unit obtains the Zone descriptor based on the Zone accessed by storage command 4, retrieves page stripe 0 in block 0 based on the mapping relationship between the Zone descriptor and page stripes, and allocates XOR cache 0 for page stripe 0. The storage command processing unit generates a media interface command 4 carrying the allocated XOR cache 0 and sends the media interface command 4 to the media interface controller. The media interface command processing unit in the media interface controller processes the received media interface command 4 indicating a write operation to generate a LUN controller write command 4. Based on the LUN to which the physical address to be accessed by the media interface command 4 (e.g., belonging to page stripe 0-1) belongs, the media interface command processing unit provides the LUN controller write command 4 to the LUN controller 1. The LUN controller 1, in response to the received LUN controller write command 4, generates a storage media access command 4 (programming command 4). Based on the programming command 4, it writes data D(3) to the physical page provided by physical block 1 in page stripe 0-1 of block 0. Thus, the writing of data D(3) is completed. During the data writing process, checksum data is calculated for the written data, and the calculation result is cached in XOR cache 0.

[0254] In the above implementation process, for multiple data written to block 0, the corresponding LUN controller write commands are processed by LUN controller 0 and LUN controller 1 to maximize the processing capabilities of the two LUN controllers and obtain better performance.

[0255] When writing data to the same page stripe, the time required for the NVM chip to perform programming operations is significantly longer (e.g., 100µs) than the time required to calculate parity data using the same written data (e.g., 1µs). Therefore, the XOR cache is wasted while waiting for the NVM chip to perform programming operations. Although interrupting the page stripe writing process based on specific conditions can release the XOR cache, the timing of the interruption is determined by the host's I / O commands, and the storage command processing unit cannot decide when to interrupt. Furthermore, while releasing the XOR cache by only interrupting the writing process based on specific conditions reduces the waste of XOR cache resources to some extent, it does not fully and rationally utilize XOR cache resources. In cases where the writing process of other page stripes is interrupted based on host-sent I / O commands to obtain available XOR cache resources, the data movement in the XOR cache also affects the host-perceived performance of accessing the zone.

[0256] To ensure that the host experiences independent performance when accessing each Zone, and to minimize the impact of accessing one or more Zones on the host's performance when accessing other Zones, according to another embodiment of this application, Figure 13 and Figure 15 In this embodiment, the independently scheduled interrupted page stripe write process is bound to the storage command processing process for accessing a Zone. The storage command processing unit actively interrupts the page stripe write process while processing storage commands for accessing a Zone. After processing each storage command, it initiates an interrupted page stripe write process to release the XOR cache, binding the data transfer from the XOR cache to DRAM to the data write. Each time data is written to a Zone, the corresponding data in the XOR cache is transferred to DRAM, and the XOR cache is released promptly. Therefore, the overhead of releasing the XOR cache becomes part of the overall overhead of writing data to a Zone, rather than the overhead of writing data to another Zone. This way, when writing data to other Zones, there is no need to transfer data from the XOR cache again, and performance is not affected by transferring data from the XOR cache. Thus, the overhead of writing data to each Zone is more consistent, and the host will not experience different performance when writing data to different Zones due to some Zones requiring additional XOR transfer operations compared to others. Furthermore, it allows new storage commands to be allocated to the XOR cache earlier, preventing a single page stripe or large block from continuously occupying the XOR cache, thus achieving relatively fair utilization of the XOR cache.

[0257] In the embodiments of this application Figure 12 and Figure 14 In the provided bulk block construction method, each host user can exclusively occupy a large block, with different host users corresponding to different zones. By actively interrupting the page stripe write process and releasing the XOR cache after each storage command is processed, the situation of a single host user continuously occupying the XOR cache can be avoided. This allows new storage commands to be allocated to the XOR cache more quickly, and different host users can compete for resources relatively fairly, better adapting to the needs of host users. This ensures that hosts experience independent performance when accessing each zone, and accessing one zone will not affect the performance of other zones, thus improving the host user experience.

[0258] Figure 16 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write large blocks of data according to another embodiment of the present application.

[0259] Figure 16 The situation shown is the same as Figure 13 Similar, the difference is: Figure 13The storage command processing unit in the diagram is shown as the processing procedure for accessing the Zone storage command, the processing procedure for interrupting the page stripe writing process, and the processing procedure for releasing the XOR cache after the page stripe is full. Figure 16 The storage command processing unit is presented as two processes, which combine the processing of storage commands that access the Zone for the XOR cache active release operation and the processing of releasing the XOR cache after the page stripe is full.

[0260] exist Figure 16 In the process, for a storage command that indicates a write operation to access the Zone, the storage command processing unit generates a corresponding media interface command and provides it to the media interface controller. The media interface controller processes the media interface command to write data to the NVM chip. After the data is written and the verification data is calculated, the data in the XOR cache is moved to DRAM and the XOR cache is released. This process interrupts the write process and releases the XOR cache after each storage command is processed, so that the XOR cache can be allocated earlier when processing subsequent storage commands.

[0261] For example, the host sends an IO command to access a Zone and indicate a write operation. The host interface receives the IO command and provides it to the host command processing unit. The host command processing unit generates a corresponding storage command to access the Zone and provides it to the storage command processing unit. The storage command processing unit obtains the Zone descriptor based on the Zone accessed by the storage command, and obtains the corresponding page stripe based on the mapping relationship between the Zone descriptor and page stripes, such as page stripe 1 of block 1, and allocates block resources (such as XOR cache 1) to page stripe 1. The storage command processing unit generates a media interface command carrying the allocated XOR cache 1 and sends the media interface command to the media interface command processing unit. The media interface command processing unit processes the media interface command to generate a LUN controller write command. Since block 1 corresponds to LUN1, and LUN1 corresponds to LUN controller 1, the media interface command processing unit provides the LUN controller write command to LUN controller 1. LUN controller 1 processes the LUN controller write command and writes data to the first physical page of page stripe 1 in block 1. During the data writing process, checksum data for the written data is calculated, and the calculation result is cached in XOR cache 1.

[0262] Next, the media interface controller moves the data from XOR cache 1 to DRAM to proactively interrupt the page stripe writing process and promptly release the XOR cache after completing the processing of a memory command. The media interface controller provides the address in DRAM containing the moved data to the memory command processing unit. The memory command processing unit records the association between the page stripe and the moved address so that the intermediate calculation results associated with the page stripe can be retrieved again based on the moved address later.

[0263] Optionally, the media interface command generated by the storage command processing unit, carrying the allocated XOR cache, implies that after processing the LUN controller write command to write data to the physical page, the LUN controller immediately moves the data in the XOR cache to the DRAM. The LUN controller allocates an address in the DRAM to store the data in the XOR cache and feeds back the allocated address to the storage command processing unit.

[0264] Optionally, the media interface command generated by the storage command processing unit may also include the DRAM address used to hold the data in the XOR cache, in order to indicate to the LUN controller that after processing the LUN controller write command to write data to the physical page, the data in the XOR cache should be moved to DRAM immediately.

[0265] Alternatively, after generating a media interface command carrying the allocated XOR cache, the storage command processing unit may also explicitly indicate that the data in the XOR cache is being moved to DRAM by issuing another media interface command to the media interface controller, which instructs the data in the XOR cache to be moved to DRAM.

[0266] For subsequent storage commands to access Zone, when retrieving the corresponding page stripe (e.g., page stripe 1 of block 1) and allocating available XOR cache for page stripe 1, the already released XOR cache 1 can be allocated to page stripe 1 in a timely manner to ensure that new storage commands are allocated to the XOR cache earlier.

[0267] Figure 17 This illustration shows a schematic diagram of a storage command processing unit controlling a media interface controller to write large blocks of data according to another embodiment of this application.

[0268] Figure 17 The situation shown is the same as Figure 15 Similar, the difference is: Figure 15 The storage command processing unit in the diagram is shown as the processing procedure for accessing the Zone storage command, the processing procedure for interrupting the page stripe writing process, and the processing procedure for releasing the XOR cache after the page stripe is full. Figure 17 The storage command processing unit is presented as two processes: the processing of storage commands accessing the Zone for proactive XOR cache release operations, and the processing of releasing the XOR cache after the page stripe is full. Figure 17 In this embodiment, the bulk block comprises physical blocks from two LUNs (see also...). Figure 14 ).

[0269] For example, the host sends an IO command A to access a Zone and indicate a write operation. The host interface receives the IO command A and provides it to the host command processing unit. The host command processing unit generates a corresponding storage command A to access the Zone and provides it to the storage command processing unit. The storage command processing unit obtains the Zone descriptor based on the Zone accessed by storage command A, and obtains the corresponding page stripe based on the mapping relationship between the Zone descriptor and page stripes, such as page stripe 0 of block 0, and allocates block resources (such as XOR cache 0) to page stripe 0. The storage command processing unit generates a media interface command A carrying the allocated XOR cache 0 and sends the media interface command A to the media interface command processing unit. The media interface command processing unit processes the media interface command A to generate a LUN controller write command A. For example, the media interface command processing unit provides the LUN controller write command A to LUN controller 0, and LUN controller 0 processes the LUN controller write command A to write data to physical page P0-0 (provided by physical block 0) of page stripe 0-0 in block 0. During the data writing process, the verification data for the written data is calculated, and the calculation result is cached in XOR cache 0.

[0270] Next, the media interface controller moves the data from XOR cache 0 to DRAM to proactively interrupt the page stripe writing process and promptly release the XOR cache after completing memory command A. The memory command processing unit records the association between the page stripe and the move address.

[0271] For the subsequent received storage command B indicating a write operation to access Zone 1, after obtaining the corresponding page stripe 1, an available XOR cache 0 is allocated for page stripe 1. The storage command processing unit generates a media interface command B carrying the allocated XOR cache 0 and sends the media interface command B to the media interface command processing unit. The media interface command processing unit processes the media interface command B to generate a LUN controller write command B. For example, the media interface command processing unit provides the LUN controller write command B to LUN controller 2, and LUN controller 2 processes the LUN controller write command B to write data to the physical page of page stripe 1 in block 1. During the data writing process, checksum data for the written data is calculated, and the calculation result is cached in XOR cache 0.

[0272] Subsequently, the media interface controller moves the data from XOR cache 0 to DRAM to proactively interrupt the page stripe writing process and promptly release the XOR cache after completing the processing of memory command B. The memory command processing unit records the association between the page stripe and the move address.

[0273] exist Figure 16 as well as Figure 17In the processing shown, after each storage command processing unit finishes processing a storage command, it moves the data in the XOR cache to DRAM to release the XOR cache. This can achieve timely release of the XOR cache, avoid host users continuously occupying the XOR cache, and allow new storage commands to be allocated to the XOR cache more quickly. Different host users can also compete for resources relatively fairly, improving the host user experience.

[0274] Figure 18 A flowchart illustrating the process of a storage command processing unit for processing storage commands, provided in another embodiment of this application.

[0275] Step 1810: Obtain the corresponding page stripe based on the Zone accessed by the storage command.

[0276] After receiving a storage command from the host command processing unit that accesses the Zone and indicates a write operation, the storage command processing unit obtains the corresponding page stripe based on the mapping relationship between the Zone descriptor and the page stripe.

[0277] Step 1820: Allocate an XOR cache for the acquired page stripes.

[0278] The allocated XOR cache is a free XOR cache (not allocated to other page stripes). If there is no free XOR cache available at the moment, processing of the store command is paused, and the system waits for a free XOR cache to become available.

[0279] Step 1830: Generate a media interface command A1 carrying the allocated XOR cache, and send the media interface command A1 to the media interface controller.

[0280] In response to the received media interface command A1, the media interface controller writes data to the page stripe and calculates check data.

[0281] Step 1840: Generate media interface command A2. Media interface command A2 instructs the release of the XOR cache and the transfer of intermediate calculation results in the XOR cache to DRAM.

[0282] After generating a media interface command A1 carrying an XOR cache and sending it to the media interface controller, the storage command processing unit, in order to release the occupied XOR cache, instructs the media interface controller, based on the media interface command A2, to move the intermediate calculation results in the XOR cache to DRAM, so as to actively interrupt the page stripe writing process and release the occupied XOR cache in a timely manner after processing a storage command.

[0283] Step 1850: Record the association between the current page strip and the relocation address.

[0284] By recording the association between page stripes and relocation addresses, intermediate calculation results associated with page stripes can be retrieved again based on the relocation addresses to continue calculating verification data.

[0285] In the above implementation process, when the media interface command carrying the XOR cache is provided to the media interface controller, and the media interface controller writes data to the NVM chip and calculates the check data, actively releasing the XOR cache can make new storage commands more quickly allocated to the XOR cache, so as to make reasonable use of the XOR cache and avoid the waste of the XOR cache to the greatest extent.

[0286] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for processing a storage command accessing a Zone, applied to a storage device, characterized in that, The storage device comprises a plurality of LUNs; in response to receiving a first storage command indicating a write operation accessing a first Zone, obtaining a first page stripe in a first large block corresponding to the first Zone, wherein the first large block comprises a plurality of physical blocks from a first LUN; generating a first media interface command indicating writing user data to the first page stripe, the first media interface command being processed by a first LUN controller corresponding to the first LUN; wherein a Zone corresponds to one large block, and all physical blocks in one large block are from the same LUN, and when large blocks corresponding to a plurality of Zones correspond to different LUNs respectively, access to the plurality of Zones is processed in parallel by a plurality of LUN controllers.

2. The method of claim 1, wherein, wherein, in response to receiving a second storage command indicating a write operation accessing a second Zone, obtaining a second page stripe in a second large block corresponding to the second Zone, wherein the second large block comprises a plurality of physical blocks from a second LUN; generating a second media interface command indicating writing user data to the second page stripe, the second media interface command being processed by a second LUN controller corresponding to the second LUN; wherein the processing of the first media interface command by the first LUN controller and the processing of the second media interface command by the second LUN controller occur in parallel.

3. A method for processing a storage command accessing a Zone, applied to a storage device, characterized in that, The storage device comprises a plurality of LUNs; in response to receiving a first storage command indicating a write operation accessing a first Zone, obtaining a first page stripe in a first large block corresponding to the first Zone, wherein the first large block comprises a plurality of physical blocks from a first LUN and a second LUN; generating a first media interface command indicating writing user data to the first page stripe, the first media interface command being processed by a first LUN controller corresponding to the first LUN or by a second LUN controller corresponding to the second LUN; wherein a Zone corresponds to one large block, and all physical blocks in one large block are from two different LUNs, and when large blocks corresponding to a plurality of Zones correspond to different LUN groups each comprising two LUNs, access to the plurality of Zones is processed in parallel by LUN controllers corresponding to large blocks respectively.

4. The method of claim 3, wherein, in response to receiving a second storage command indicating a write operation accessing a second Zone, obtaining a second page stripe in a second large block corresponding to the second Zone, wherein the second large block comprises a plurality of physical blocks from a third LUN and a fourth LUN; generating a second media interface command indicating writing user data to the second page stripe, the second media interface command being processed by a third LUN controller corresponding to the third LUN or by a fourth LUN controller corresponding to the fourth LUN; The processing of the first media interface command by the first LUN controller or the second LUN controller occurs in parallel with the processing of the second media interface command by the third LUN controller or the fourth LUN controller.

5. The method according to any one of claims 1 to 4, characterized in that, The first media interface command carries a first XOR cache allocated for the first page stripe, and the first media interface command is used to instruct to store the calculated parity data in the first XOR cache.

6. The method of claim 5, wherein, The first media interface command is further used to instruct the first large block corresponding LUN controller to move the data in the first XOR cache to DRAM after processing the first media interface command; The first large block corresponding LUN controller allocates a DRAM address in the DRAM for storing the data in the first XOR cache; An association between the DRAM address and the first page stripe is recorded.

7. The method of claim 5, wherein, The first media interface command further carries a DRAM address for accommodating the data in the first XOR cache, and the DRAM address is used to instruct the first large block corresponding LUN controller to move the data in the first XOR cache to DRAM after processing the first media interface command.

8. The method of claim 5, wherein, Further comprising: generating a third media interface command instructing to move the data in the first XOR cache to DRAM after generating the first media interface command; The first large block corresponding LUN controller moves the data in the first XOR cache to DRAM according to the third media interface command and provides a DRAM address; An association between the DRAM address and the first page stripe is recorded.

9. The method according to any one of claims 6 to 8, characterized in that, Further comprising: in response to a third storage command indicating a write operation accessing a third Zone, obtaining a third page stripe in a third large block corresponding to the third Zone; allocating the first XOR cache for the third page stripe; generating a fourth media interface command carrying the first XOR cache, and the fourth media interface command instructs to write user data to the third page stripe and to store the calculated parity data in the first XOR cache.

10. A storage device comprising a control component and a plurality of LUNs, the control component comprising a storage command processing unit and a media interface controller, the media interface controller comprising a plurality of LUN controllers, wherein, the storage command processing unit, in response to a first storage command indicating a write operation accessing a first Zone, obtains a first page stripe in a first large block corresponding to the first Zone, and generates a first media interface command; wherein the first large block comprises a plurality of physical blocks all from a first LUN, and the first media interface command instructs to write user data to the first page stripe; a first LUN controller corresponding to the first LUN processes the first media interface command; The Zone and the large block are one-to-one correspondence, all physical blocks included in the large block are from the same LUN, when the large blocks corresponding to multiple Zones correspond to different LUNs respectively, the access to the multiple Zones is processed in parallel by multiple LUN controllers.

Images