A risc-v based vector micro-operation splitting method and system

Abstract

The application belongs to the field of vector splitting, and particularly relates to a vector micro-operation splitting method and system based on RISC-V. The method comprises the following steps: obtaining a first RISC-V instruction and a second RISC-V instruction, decoding the first RISC-V instruction, judging whether there is a mask instruction in the decoding stage, if there is no mask instruction in the query stage, no mask instruction in the renaming stage, and no mask instruction in the scheduling disorder stage, obtaining a mask instruction of the second RISC-V instruction; according to the mask instruction, the element width, the vector register width and the vector register multiple, micro-splitting the second RISC-V instruction to obtain a splitting result; according to the mask instruction, the element width, the vector register width and the vector register multiple, micro-splitting to obtain a splitting result. The application has the effect of improving the running efficiency of the processor.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of vector splitting, and particularly relates to a vector micro-operation splitting method and system based on RISC-V. BACKGROUND

[0002] RISC-V is the abbreviation of the fifth generation of reduced instruction set, and is a widely used reduced instruction set at present. RISC-V vector is a variable-length configuration mode. One instruction may operate on multiple pairs of vector registers, and each pair of vector registers contains multiple elements. The conventional method is to set one uop (micro-operation) for each pair of vector registers. RISC-V defines two types of active elements and non-active elements for vector element layout. The non-active elements can optionally not update the corresponding destination position, or can optionally set the corresponding destination position to all 1s. The hardware implementation can be implemented by not performing any operation.

[0003] Generally, in an out-of-order processor, micro-operation splitting occurs in the decoding stage before renaming. Although vl and vstart are vector state control registers and can be known in the decoding stage, mask is special. The speciality is that risc-v vector does not define mask as a control state register, but only puts it into the vector architecture register v0 (the first register of the vector register file). When the new result of mask is written into v0 for a certain instruction, the behavior is as usual, and it does not trigger pipeline flushing like writing a CSR (state control register) in an out-of-order processor. This is equivalent to adding a mask source operand to each instruction that needs mask to participate in the calculation. Since there are some vector operations or loading instructions that update the mask data in v0, the mask operand needs to be awakened according to the data correlation in order to be transmitted and executed during the process of each mask operation instruction.

[0004] This means that mask, although a state control data, is used as an operation data, no matter whether the value written into v0 is mask type or not, it can be used as mask. So when a instruction enters the decode stage, the mask it needs cannot be known. This is because the instruction that the mask data comes from may not have started execution, may be in the dispatch stage, may be in the dispatch queue, or may be in operation, and at this moment, the mask data has not been generated. So if you want to know which elements are masked according to the mask, and then optimize the inactive uop, it is impossible. If you always stay in the decode stage and wait for the data-dependent mask instruction to write back to the register and then read it, and then optimize, it is a very unreasonable behavior, and the time cost of blocking is large, which directly affects the execution of subsequent instructions and reduces the operation efficiency of the processor. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a vector micro-operation splitting method and system based on RISC-V, which improves the operation efficiency of the processor.

[0006] A vector micro-operation splitting method based on RISC-V, comprising:

[0007] Obtaining a first RISC-V instruction and a second RISC-V instruction, the first RISC-V instruction being before the second RISC-V instruction;

[0008] Setting the element width, the vector register width, and the vector register multiple;

[0009] Decoding the second RISC-V instruction, determining whether there is a mask instruction of the second RISC-V instruction in the decode stage, the decode stage including the query stage, the renaming stage, and the dispatch out-of-order stage, if there is no mask instruction in the query stage, no mask instruction in the renaming stage, and no mask instruction in the dispatch out-of-order stage, obtaining the mask instruction of the second RISC-V instruction according to the first RISC-V instruction;

[0010] Micro-splitting the second RISC-V instruction according to the mask instruction, the element width, the vector register width, and the vector register multiple, to obtain a splitting result.

[0011] Optionally, if there is a mask instruction in the query stage or there is a mask instruction in the renaming stage or there is a mask instruction in the dispatch out-of-order stage, performing a preliminary splitting on the second RISC-V instruction according to the preset mask instruction, the element width, the vector register width, and the vector register multiple, to obtain a preliminary splitting result, and deleting the invalid splitting in the preliminary splitting result according to the mask instruction after the mask instruction is obtained, to obtain the splitting result.

[0012] Optionally, the obtaining the mask instruction of the second RISC-V instruction according to the first RISC-V instruction comprises:

[0013] renaming the first RISC-V instruction to obtain a renamed instruction;

[0014] sending the renamed instruction to a dispatch out-of-order stage to obtain a reorder identification of the renamed instruction;

[0015] recording the reorder identification to obtain a record item;

[0016] calculating the renamed instruction in the dispatch out-of-order stage to obtain a calculation result, and obtaining the mask instruction according to the calculation result and the record item;

[0017] judging whether there is an old mask instruction in a register;

[0018] if there is the old mask instruction in the register, covering the mask instruction with the old mask instruction as the mask instruction of the second RISC-V instruction;

[0019] if there is no old mask instruction in the register, covering the mask instruction as the mask instruction of the second RISC-V instruction.

[0020] Optionally, if there are multiple mask instructions in the first RISC-V instruction, the reorder identification of the mask instruction at the most rear sequence in the first RISC-V instruction is selected to be recorded.

[0021] Optionally, the micro-disassembling the second RISC-V instruction according to the mask instruction, the element width, the vector register width, and the vector register multiple to obtain a disassembled result comprises:

[0022] obtaining a vector starting element number;

[0023] obtaining an effective element number according to the mask instruction;

[0024] micro-disassembling the second RISC-V instruction according to the vector starting element number, the element width, the vector register width, the vector register multiple, and the effective element number to obtain the disassembled result.

[0025] Optionally, the micro-disassembling the second RISC-V instruction according to the vector starting element number, the element width, the vector register width, the vector register multiple, and the effective element number to obtain the disassembled result comprises:

[0026] obtaining a total number of elements of the second RISC-V instruction;

[0027] obtaining a number of effective elements of the second RISC-V instruction;

[0028] According to the total number of elements, the number of valid elements, and the vector starting element number, an active element number is obtained;

[0029] According to the active element number and the valid element number, the second RISC-V instruction is micro-disassembled to obtain a disassembly result.

[0030] A RISC-V-based vector micro-operation disassembly system comprises:

[0031] An acquisition module is configured to acquire a first RISC-V instruction and a second RISC-V instruction, wherein the first RISC-V instruction is before the second RISC-V instruction;

[0032] A setting module is configured to set an element width, a vector register width, and a vector register multiple;

[0033] A query module is configured to decode the second RISC-V instruction to determine whether there is a mask instruction of the second RISC-V instruction in a decoding stage, wherein the decoding stage comprises a query stage, a renaming stage, and a dispatch out-of-order stage, and if there is no mask instruction in the query stage, no mask instruction in the renaming stage, and no mask instruction in the dispatch out-of-order stage, a mask instruction of the second RISC-V instruction is acquired according to the first RISC-V instruction;

[0034] A disassembly module is configured to disassemble the second RISC-V instruction according to the mask instruction, the element width, the vector register width, and the vector register multiple to obtain a disassembly result.

[0035] Optionally, the query module comprises:

[0036] A renaming unit is configured to rename the first RISC-V instruction to obtain a renamed instruction;

[0037] An identification unit is configured to send the renamed instruction after renaming into the dispatch out-of-order stage to obtain a reordering identifier of the renamed instruction;

[0038] A recording unit is configured to record the reordering identifier to obtain a record item;

[0039] A matching unit is configured to calculate the renamed instruction in the dispatch out-of-order stage to obtain a calculation result, and obtain the mask instruction according to the calculation result and the record item;

[0040] A judgment unit is configured to determine whether there is an old mask instruction in a register;

[0041] If there is the old mask instruction in the register, the mask instruction is used to replace the old mask instruction as the mask instruction of the second RISC-V instruction;

[0042] If the old mask instruction does not exist in the register, the mask instruction is taken as the mask instruction of the second RISC-V instruction.

[0043] A terminal device comprises a memory and a processor, the memory stores a computer program capable of running on the processor, and when the processor loads and executes the computer program, a RISC-V-based vector micro-operation splitting method and system are adopted.

[0044] A computer readable storage medium stores a computer program, and when the processor loads and executes the computer program, a RISC-V-based vector micro-operation splitting method and system are adopted.

[0045] The beneficial effects of the present application are:

[0046] 1. The present application mainly observes that if the program has a long time not updating the mask instruction, and the mask itself contains a large number of non-active elements, always splitting the micro-operation according to the speculative full active will bring a large number of invalid uops and performance loss. Therefore, the strategy is improved, so that in the case of long-term mask update, the micro-operation is split according to the accurate non-active element, and the performance is improved.

[0047] 2. The present application adds monitoring "write v0 instruction active" logic in the early decoding stage of the out-of-order processor, uses sequential stage flow monitoring, and combines the write v0 monitoring of the out-of-order execution window to determine whether the v0 register copy added in the current decoding stage can be directly used. Through the identification record of the instruction after renaming, the latest record is covered by the oldest instruction, and the write-back v0 instruction is compared with the identification, the update behavior of the v0 register is synchronized to the v0 register copy in the decoding stage in the fastest way, so that accurate non-active element information can be obtained in the decoding stage, the generation of invalid uops is maximized, and the performance waste is reduced. In the case of write v0 instruction active, the mask element is still split according to the speculative full active.

[0048] 3. The main protection point of the present application is the processing method, the splitting uop strategy has two kinds of prediction splitting and accurate splitting, when the write v0 instruction is active, that is, there is a write v0 instruction in the subsequent pipeline after decoding, the prediction splitting is performed, and when it is not active, the accurate splitting is performed. The method for monitoring v0 uses a record item to determine whether the write v0 instruction is active in the subsequent pipeline, and the latest mask in the v0 register is obtained in advance through the copy, and there is no need to care about the renaming mapping relationship and whether the instruction is retired. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1Flowchart for uop splitting strategy of the present application;

[0050] Figure 2 Overall framework diagram for vector splitting of the present application;

[0051] Figure 3 Comparison between accurate splitting and predictive splitting of the present application. DETAILED DESCRIPTION

[0052] 1. A RISC-V-based vector micro-operation splitting method, as shown in Figure 1 The present application comprises:

[0053] S1, obtaining a first RISC-V instruction and a second RISC-V instruction, the first RISC-V instruction being before the second RISC-V instruction;

[0054] Specifically, the vector instructions have a sequence before processing, and are processed according to the sequence.

[0055] S2, setting an element width, a vector register width, and a vector register multiple;

[0056] Specifically, Vlen: vector length, bit width of a vector register, if vlen = 256, it indicates that the vector register width of the system is 256 bits.

[0057] Sew: selection element width, a vector register is composed of multiple elements arranged in low-to-high order, and an element can be considered as a "scalar". If vlen = 256, i.e. the vector register width is 256 bits, and sew = 32, it indicates that the element width is 32 bits. Then a vector register contains 256 / 32 = 8 elements. That is, if a 256-bit vector register is regarded as a row of 256-bit binary data, the 8 elements will be arranged in a row with each occupying a 32-bit position. RISC-V vector specifies that sew can only take one of 8, 16, 32, and 64.

[0058] Lmul: Vector register multiple, this is a major feature of RISC-V as a variable-length vector. Its value can be 8, 4, 2, 1, 1 / 2, 1 / 4, 1 / 8. For other instruction sets that do not support variable-length vectors. Consider a vector register as a "vector", but the RISC-V vector variable architecture adds the lmul setting. When the system sets lmul=8, it is considered that 8 vector registers constitute a "vector". For example, lmul=8, vlen=256, sew=32. It is considered that each vector register is 256 bits, and each element is 32 bits, (8 elements constitute a vector register), lmul=8, so it is known that 8 vector registers constitute a vector (or 8x8=64 elements constitute a vector). If lmul=4, then 4 vector registers constitute a vector, (32 elements). If lmul=1 / 2, then 1 / 2 vector registers constitute a vector, that is, only half of the bit width of the vector register is valid, the default low 128 bits is a vector, at this time a vector only has 4 elements. When lmul is greater than 1, the following may be referred to as "multiple lmul".

[0059] mask: mask number, in the RISC-V vector architecture, mask is used to indicate whether some elements of a vector are valid (or masked), each bit of mask corresponds to each element of a vector in the same order, that is, the 0th bit of mask corresponds to the 0th element of the vector. When the mask function is turned on, the value of the bit of mask is 0, indicating that the element at that position is an active element and is not masked and is valid; if the value of the bit is 1, it indicates that the element at that position is an inactive element and is masked and invalid.

[0060] Tail element: tail element, a kind of invalid element specified by RISC-V vector. The number of elements in the vector register is always a power of 2. However, sometimes the number of times of loop vectorization of a program is not a power of 2, so the last loop vectorization is left empty and is specified as a tail element, that is, a tail element. The tail element is considered to be extra data that is not used. From a logical point of view, these elements do not exist in the vector, but are caused by the hardware representing too many elements. The introduction of Tail setting also makes the freedom of the number of elements of RISC-V vector not limited to a power of 2, but to 1, 2, 3, 4, which is divided by 1 as a granularity.

[0061] Vl: Vector length, minimum is 0, maximum "vlmax" is the number of all elements valid. The position layout of tail elements can be determined by this value and lmul, sew, vlen. Assuming that the vector vstart = 0, the mask is all 0 unmasked, for example, a configuration instruction of lmul = 1, sew = 32, vlen = 256, using vl = 3 to control the calculation, it can be known that if all valid, this vector has 8 32-bit elements, vlmax is 8, but it is additionally informed that vl = 3, that is, the vector length is only 3, then the 8 elements, only the lower 3 elements are valid active elements, and the high 5 elements are tail elements, invalid.

[0062] Vstart: The index number of the starting element of the vector, that is, the first element is numbered. If vstart = 0, it means that the first element (0 is the first in the number system, 0 is the first position) is the element numbered 0. In the example of the above vl explanation, if vstart = 1, and assuming that the 8 elements from high to low are e7, e6, e5, e4, e3, e2, e1, e0, the high 5 are tails, vstart = 1 indicates that the first element is e1, e0 is an invalid element (referred to as a prestart element). Finally, 8 elements, tail minus 5, prestart minus 1, only two elements are active and valid, that is, only e2, e1 are valid.

[0063] S3, decode the second RISC-V instruction, judge whether there is a mask instruction of the second RISC-V instruction in the decoding stage, the decoding stage includes a query stage, a renaming stage and a scheduling and out-of-order stage, if there is no mask instruction in the query stage and there is no mask instruction in the renaming stage and there is no mask instruction in the scheduling and out-of-order stage, the mask instruction of the second RISC-V instruction is obtained according to the first RISC-V instruction;

[0064] Specifically, the mask instruction of the second RISC-V instruction may have been saved after the previous RISC-V instruction has been decoded, because in the decoding stage, it is only necessary to query whether there is a mask instruction, if there is none, it indicates that the mask instruction of the second RISC-V instruction is being decoded, and the decoding result needs to be waited.

[0065] If there is a mask instruction in the query stage or there is a mask instruction in the renaming stage or there is a mask instruction in the scheduling and out-of-order stage, the second RISC-V instruction is initially split according to the preset mask instruction, element width, vector register width and vector register multiple, to obtain an initial split result, and after the mask instruction is obtained, the invalid split in the initial split result is deleted according to the mask instruction to obtain a split result.

[0066] Specifically, if there is a mask instruction in the first RISC-V instruction, it means that the mask instruction required by the second RISC-V instruction has been in the first RISC-V instruction.

[0067] The mask instruction of the second RISC-V instruction is obtained according to the first RISC-V instruction.

[0068] The first RISC-V instruction is renamed to obtain a renamed instruction;

[0069] The renamed instruction is sent to a dispatch out-of-order stage to obtain a reorder identification of the renamed instruction;

[0070] The reorder identification is recorded to obtain a record item;

[0071] The renamed instruction in the dispatch out-of-order stage is calculated to obtain a calculation result, and the mask instruction is obtained according to the calculation result and the record item;

[0072] It is judged whether there is an old mask instruction in a register;

[0073] If there is an old mask instruction in the register, the mask instruction is used to replace the old mask instruction as the mask instruction of the second RISC-V instruction;

[0074] If there is no old mask instruction in the register, the mask instruction is used as the mask instruction of the second RISC-V instruction.

[0075] If there are multiple mask instructions in the first RISC-V instruction, the reorder identification of the mask instruction at the most rear sequence in the first RISC-V instruction is selected for recording.

[0076] Specifically, because the decoding stage is still in the sequential stage in the out-of-order processor, all instructions after decoding are instructions executed before the vector instruction currently in the decoding stage. For example, Figure 1As shown, when the vector instruction in the long vector mode reaches the decode split stage, it is determined whether there is a write-v0 instruction earlier than the current instruction still running by detecting three places, the first is the same group of instructions (i.e. the query stage), in this case, mainly because the decoding width of the modern out-of-order processor is generally greater than 1, so there may be a write-v0 instruction of the current vector instruction in the front position of the same group of instructions, such as a four-shot processor, four instructions are decoded each time, and the four instructions are in order, so if the later instruction needs to use the mask in v0, and there is a write-v0 instruction in the front instruction, it means that the later instruction using v0 cannot obtain the mask it needs at this moment. Because the instruction that generates the mask it needs is also in the decoding stage, it still needs a certain time to get the mask calculation result, so the instruction that needs to use the mask result cannot get the mask data it needs at this moment. Similarly, if there is a write-v0 instruction in the renaming stage, it means that the mask needed in the current decoding stage cannot be obtained. The two stages are sequential flow, and the v0 register has not completed the renaming, so it can be directly determined whether it is a write-v0 instruction by judging whether the destination vector register is 0.

[0077] The register number of the vector instruction after renaming is dispatched to the dispatch out-of-order stage. The dispatch out-of-order stage includes a dispatch queue and an out-of-order execution window. In order to monitor the write v0 instruction, the write v0 instruction also needs to be monitored at the dispatch queue and the execution unit (out-of-order execution window). Since the register number of the instruction has been renamed, the write v0 instruction cannot be directly monitored by judging whether the register is 0. Meanwhile, the dispatch queue has multiple instructions, and the execution unit includes a memory unit, all of which may have write v0 instructions. Directly monitoring all of the above pipeline information is very complex, and there may be more than dozens of information. Based on this, in order to simplify the monitoring of the write v0, a record item is made when the instruction is dispatched to the dispatch queue. When the instruction is dispatched to the dispatch queue after completing the renaming, and it is a write v0 instruction, the reorder identification of the instruction is recorded, and a state bit of "out-of-order window exists write v0 instruction" is marked. However, whether the instruction is completed or not at the time of recording, as long as there is a new write v0 instruction passing through this stage, the record item will be updated to the reorder identification of the latest write v0, that is, the old write v0 is covered by the new write v0 instruction, and only the latest write v0 instruction is recorded. If a group of dispatched instructions contains multiple write v0 instructions, the reorder identification of the write v0 instruction with the latest sequence is selected and stored in the record item. With the record item, the result bus of the execution unit is monitored. When the execution unit sends the operation result to the result bus, the reorder identification is also sent to the result bus. Then, the record item records the latest write v0 instruction, and the information on the result bus is compared. If the identification is the same, it means that the result of the write v0 instruction in the record item has appeared on the result bus. When the identification is the same, the result on the result bus is copied to a register in the decoding module as a copy of the v0 register to participate in micro-operation splitting. And the state bit of "out-of-order window exists write v0 instruction" in the record item is set to 0, indicating that the result of the last write v0 has been obtained in advance. In this monitoring process, the renamed register renaming relationship does not need to be recorded, the physical address of the write v0 instruction result does not need to be concerned (the destination address after renaming is no longer 0), and whether the instruction is in the retirement state does not need to be concerned. The calculation result of the write v0 instruction with the latest sequence can be obtained, that is, the mask data required by the following instruction is placed in the v0 copy in the decoding stage in advance and smoothly. After the mask information is determined, the decoding and splitting uop can be split according to the accurate non-active element, thereby maximizing the reduction of performance loss caused by invalid micro-operations due to the speculation of active elements.

[0078] S4, micro-disassemble the second RISC-V instruction according to the mask instruction, the element width, the vector register width, and the vector register multiple, to obtain a disassembled result.

[0079] The micro-disassembling the second RISC-V instruction according to the mask instruction, the element width, the vector register width, and the vector register multiple, to obtain a disassembled result includes:

[0080] obtaining a vector starting element number;

[0081] obtaining an effective element number according to the mask instruction;

[0082] micro-disassembling the second RISC-V instruction according to the vector starting element number, the element width, the vector register width, the vector register multiple, and the effective element number, to obtain a disassembled result.

[0083] The micro-disassembling the second RISC-V instruction according to the vector starting element number, the element width, the vector register width, the vector register multiple, and the effective element number, to obtain a disassembled result includes:

[0084] obtaining a total number of elements of the second RISC-V instruction;

[0085] obtaining a number of effective elements of the second RISC-V instruction;

[0086] obtaining an active element number according to the total number of elements, the number of effective elements, and the vector starting element number;

[0087] micro-disassembling the second RISC-V instruction according to the active element number and the effective element number, to obtain a disassembled result.

[0088] If there is a mask instruction in the first RISC-V instruction or there is a write-masked instruction in the renaming stage or there is a write-masked instruction in the dispatch queue and the out-of-order execution window, then performing a primary disassembly on the second RISC-V instruction according to a preset mask instruction, an element width, a vector register width, and a vector register multiple, to obtain a primary disassembled result, and then performing a secondary disassembly on the primary disassembled result according to the mask instruction, to obtain a disassembled result.

[0089] Specifically, the preset mask instruction is to disassemble according to each vector register.

[0090] Specifically, as Figure 2As shown, during the decoding phase, an inactive element table is generated using vl, vstart, and a potentially available mask. If the mask is unavailable, the masked portion of this table is defaulted to active elements. Subsequently, during the decoding and renaming phases, it is determined whether a write v0 instruction exists. Since the signals from the decoding phase are in one phase, they are not included in the initial decoding process. Figure 2 This is reflected in the process where renaming requires feedback on the existence of a write v0 instruction. In later pipeline stages, the entire out-of-order window (scheduling queue and execution unit) after dispatch monitors the latest write v0 instruction through a record. Once this record is calculated and copied to a copy in the decoding stage, the copy is available. This copy is available only if there is no write v0 register in the decoding and renaming stages, and also if there is no write v0 register in the out-of-order window; both conditions must be met simultaneously. After obtaining a definite mask and a definite list of inactive elements, precise splitting can be performed.

[0091] Figure 3 This demonstrates the case where lmul=4, vlen / vsew = 8, vl=30, and vstart=2. This means a vector consists of 4 vector registers, each with 8 elements. Therefore, if all vector elements were active, there should be 4 x 8 = 32. However, vl=30 indicates that the last two elements, e31 and e30, are inactive tail elements. Figure 3 Let T represent this. Since vstart=2, the first element of the vector starts from e2, so e1 and e0 are inactive prestart elements. Figure 3 The symbol 'S' represents this. For elements between e2 and e29 that are neither 'tail' nor 'prestart', their activity level will be determined based on the mask. Figure 3 In the upper part of the code, the predicted split assumes that the mask is currently unknown. To ensure program correctness, all masks are assumed to be active elements. This inferred active element... Figure 3 In, X is used to represent. Figure 3 In the lower part, assuming the mask value can be obtained during the decoding stage, N represents invalid inactive elements, and M represents valid active elements. Figure 3 The example shows that the middle N invalid elements can be split by removing two invalid uops, and only two uops are needed to complete the calculation of all active elements.

[0092] RISC-V has a wide variety of vector instruction types, and while the methods for splitting each UOP may differ, they won't necessarily be the same. Figure 3In the program of infrequently updating mask, it is a common optimization way to get the accurate mask, and some special instructions can no longer produce various invalid uops because of predicting all elements are valid. In the early decoding stage, only the active elements are processed, which improves the efficiency and obtains performance improvement.

[0093] A RISC-V-based vector micro-operation splitting system, comprising:

[0094] An acquisition module is configured to acquire a first RISC-V instruction and a second RISC-V instruction, wherein the first RISC-V instruction is before the second RISC-V instruction;

[0095] A setting module is configured to set an element width, a vector register width, and a vector register multiple;

[0096] A query module is configured to decode the second RISC-V instruction, determine whether there is a mask instruction of the second RISC-V instruction in a decoding stage, and acquire the mask instruction of the second RISC-V instruction according to the first RISC-V instruction if there is no mask instruction in a query stage, no mask instruction in a renaming stage, and no mask instruction in a dispatch stage.

[0097] A splitting module is configured to split the second RISC-V instruction according to the mask instruction, the element width, the vector register width, and the vector register multiple, and obtain a splitting result.

[0098] Optionally, the query module comprises:

[0099] A renaming unit is configured to rename the first RISC-V instruction and obtain a renamed instruction;

[0100] An identification unit is configured to send the renamed instruction after renaming into the dispatch stage and obtain a reorder identification of the renamed instruction;

[0101] A recording unit is configured to record the reorder identification and obtain a record item;

[0102] A matching unit is configured to calculate the renamed instruction in the dispatch stage and obtain a calculation result, and obtain the mask instruction according to the calculation result and the record item;

[0103] A judgment unit is configured to determine whether there is an old mask instruction in a register;

[0104] If there is the old mask instruction in the register, the mask instruction is used to replace the old mask instruction as the mask instruction of the second RISC-V instruction.

[0105] If the old mask instruction does not exist in the register, the mask instruction is taken as a mask instruction of the second RISC-V instruction.

[0106] The embodiment of the present application also discloses a terminal device, comprising a memory and a processor, the memory stores a computer program capable of running on the processor, and when the processor loads and executes the computer program, a RISC-V-based vector micro-operation splitting method and system are adopted.

[0107] The terminal device can be a computer device such as a desktop computer, a notebook computer or a cloud server, and the terminal device comprises but is not limited to a processor and a memory. For example, the terminal device can also comprise an input / output device, a network access device and a bus.

[0108] The processor can be a central processing unit (CPU), and of course, according to the actual use, other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), ready-to-program gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. can also be used. The general-purpose processor can be a microprocessor or any conventional processor, etc. The present application does not limit this.

[0109] The memory can be an internal storage unit of the terminal device, for example, a hard disk or a memory of the terminal device, or an external storage device of the terminal device, for example, a plug-in hard disk, a smart memory card (SMC), a secure digital card (SD) or a flash memory card (FC) equipped on the terminal device, etc. The memory can also be a combination of the internal storage unit and the external storage device of the terminal device. The memory is used to store computer programs and other programs and data required by the terminal device. The memory can also be used to temporarily store data that has been output or will be output. The present application does not limit this.

[0110] The terminal device stores the RISC-V-based vector micro-operation splitting method and system in the memory of the terminal device, and loads and executes the method and system on the processor of the terminal device, which is convenient to use.

[0111] The embodiment of the present application also discloses a computer readable storage medium, and the computer readable storage medium stores a computer program, wherein when the computer program is executed by the processor, the RISC-V-based vector micro-operation splitting method and system in the above embodiment are adopted.

[0112] The computer program can be stored in the computer readable medium, the computer program includes computer program code, the computer program code can be in the form of source code, object code, executable file or some middleware form, etc., the computer readable medium includes any entity or device, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc., which can carry computer program code, it needs to be explained that the computer readable medium includes but is not limited to the above components.

[0113] The computer readable storage medium stores the XXX in the computer readable storage medium in the above embodiment, and is loaded and executed on the processor to facilitate the storage and application of the above method.

[0114] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the protection scope of the present application is limited to these examples; under the idea of the present application, the above embodiments or technical features in different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of one or more embodiments of the present application as described above, which are not provided in details for brevity.

[0115] One or more embodiments of the present application are intended to cover all such alternatives, modifications and variations falling within the broad scope of the present application. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principles of one or more embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A RISC-V-based vector micro-operation decomposition method, characterized by comprising: Obtain the first RISC-V instruction and the second RISC-V instruction, wherein the first RISC-V instruction precedes the second RISC-V instruction; Set the element width, vector register width, and vector register multiplier; The second RISC-V instruction is decoded, and it is determined whether there is a mask instruction for the second RISC-V instruction during the decoding stage. The decoding stage includes a query stage, a renaming stage, and a scheduling out-of-order stage. If there is no mask instruction in the query stage, no mask instruction in the renaming stage, and no mask instruction in the scheduling out-of-order stage, then the mask instruction for the second RISC-V instruction is obtained according to the first RISC-V instruction. The second RISC-V instruction is micro-splitted according to the mask instruction, element width, vector register width, and vector register multiple to obtain the splitting result; If a mask instruction exists in the query phase, the renaming phase, or the scheduling out-of-order phase, the second RISC-V instruction is initially split according to the preset mask instruction, element width, vector register width, and vector register multiple to obtain the initial split result. After obtaining the mask instruction, invalid splits in the initial split result are deleted according to the mask instruction to obtain the final split result.

2. The RISC-V-based vector micro-operation decomposition method as described in claim 1, characterized in that, The mask instruction for obtaining the second RISC-V instruction based on the first RISC-V instruction includes: The first RISC-V instruction is renamed to obtain the rename instruction; The rename instruction is sent to the scheduling out-of-order stage to obtain the reordering identifier of the rename instruction. Record the reordering identifier to obtain the record item; The renaming instructions in the scheduling out-of-order phase are calculated to obtain the calculation results, and the mask instructions are obtained based on the calculation results and the record items. Determine if the old mask instruction exists in the register; If the old mask instruction exists in the register, the mask instruction will overwrite the old mask instruction and become the mask instruction for the second RISC-V instruction. If the old mask instruction is not present in the register, the mask instruction will be used as the mask instruction for the second RISC-V instruction.

3. The RISC-V-based vector micro-operation decomposition method as described in claim 2, characterized in that, If there are multiple mask instructions in the first RISC-V instruction set, the reordering identifier of the mask instruction that appears last in the first RISC-V instruction set is selected and recorded.

4. The RISC-V-based vector micro-operation decomposition method as described in claim 1, characterized in that, The step of micro-splitting the second RISC-V instruction based on the mask instruction, element width, vector register width, and vector register multiple to obtain the splitting result includes: Get the starting element number of the vector; The valid element number is obtained based on the mask instruction; The second RISC-V instruction is micro-split based on the starting element number of the vector, the element width, the vector register width, the vector register multiple, and the effective element number to obtain the splitting result.

5. The RISC-V-based vector micro-operation decomposition method as described in claim 4, characterized in that, The second RISC-V instruction is micro-decomposed based on the vector's starting element number, the element width, the vector register width, the vector register multiple, and the valid element number to obtain the decomposition result, including: Get the total number of elements in the second RISC-V instruction; Get the number of valid elements in the second RISC-V instruction; The active element number is obtained based on the total number of elements, the number of valid elements, and the starting element number of the vector; The second RISC-V instruction is micro-split based on the active element number and the effective element number to obtain the splitting result.

6. A vector micro-operation decomposition system based on RISC-V, characterized in that, include: An acquisition module is used to acquire a first RISC-V instruction and a second RISC-V instruction, wherein the first RISC-V instruction precedes the second RISC-V instruction; The settings module is used to set the element width, vector register width, and vector register multiplier. The query module is used to decode the second RISC-V instruction and determine whether there is a mask instruction for the second RISC-V instruction during the decoding stage. The decoding stage includes a query stage, a renaming stage, and a scheduling out-of-order stage. If there is no mask instruction in the query stage, no mask instruction in the renaming stage, and no mask instruction in the scheduling out-of-order stage, then the mask instruction for the second RISC-V instruction is obtained according to the first RISC-V instruction. The splitting module is used to perform micro-splitting of the second RISC-V instruction based on the mask instruction, element width, vector register width, and vector register multiple, to obtain the splitting result; If a mask instruction exists in the query phase, the renaming phase, or the scheduling out-of-order phase, the second RISC-V instruction is initially split according to the preset mask instruction, element width, vector register width, and vector register multiple to obtain the initial split result. After obtaining the mask instruction, invalid splits in the initial split result are deleted according to the mask instruction to obtain the final split result.

7. The system as described in claim 6, characterized in that, The query module includes: The renaming unit renames the first RISC-V instruction to obtain a renaming instruction; The identification unit is used to send the renaming instruction that has been renamed into the scheduling out-of-order stage to obtain the reordering identifier of the renaming instruction. A recording unit is used to record the reordering identifier to obtain a record item; The matching unit calculates the renaming instructions in the scheduling out-of-order phase, obtains the calculation result, and obtains the mask instruction based on the calculation result and the record item. The judgment unit determines whether the old mask instruction exists in the register; If the old mask instruction exists in the register, the mask instruction will overwrite the old mask instruction and become the mask instruction for the second RISC-V instruction. If the old mask instruction is not present in the register, the mask instruction will be used as the mask instruction for the second RISC-V instruction.

8. A terminal device, comprising a memory and a processor, characterized in that, The memory stores a computer program that can run on a processor, and when the processor loads and executes the computer program, it employs the method described in any one of claims 1 to 5.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is loaded and executed by the processor, it employs the method described in any one of claims 1 to 5.

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