Electronic device and light turning on control method

Abstract

This application provides an electronic device and a lighting control method, which can be applied to the field of hardware technology. The electronic device includes a processor, a storage controller, a management controller, and a hard disk backplane. The hard disk backplane has a backplane controller, multiple hard disk connectors, and multiple indicator lights corresponding to the multiple hard disk connectors. The backplane controller is connected to the multiple hard disk connectors and the multiple indicator lights. The management controller is connected to the backplane controller. The hard disk backplane is a first type of hard disk backplane. The processor controls the backplane controller to set the DIP switch value of the hard disk backplane to a first DIP switch value or a second DIP switch value; or the hard disk backplane is a second type of hard disk backplane. The processor is configured to detect if the hard disk connectors on the hard disk backplane are directly connected, and if so, assign a third DIP switch value to the backplane controller. The management controller, in response to the DIP switch command, sets the DIP switch value of the hard disk backplane to a third DIP switch value or a fourth DIP switch value, depending on whether the backplane controller has been assigned a third DIP switch value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of hardware, and more particularly to an electronic device and a light-on control method. BACKGROUND

[0002] Traditional hard disk backplanes rely on physical dial switches to tell CPLD (Complex Programmable Logic Device) which group of uplink ports each hard disk interface is connected to. For example, maintenance or production line workers move small switches, and CPLD lights up after reading back the binary value, the logic is simple but there are human risks - hundreds of backplanes need to be dialled one by one, and fatigue and distraction can easily cause the switches to be misaligned, and the light sequence will be wrong, and on-site troubleshooting will consume more manpower. To eliminate mechanical operation, a "virtual dial" solution has appeared in recent years: factory measurement software writes topology values as instructions directly to CPLD through a management bus, without touching the hardware. But this process still requires factory workers to manually identify the backplane model and cable connection first, and then trigger the corresponding configuration script in the system; once the code scanning is wrong or the script matching fails, the virtual dial value will also deviate from the real topology, causing light-on logic errors, and the risk is moved from "manual dial" to "data entry", still relying on people. SUMMARY

[0003] According to a first aspect of the present application, an electronic device is provided, the electronic device comprising a processor, a storage controller, a management controller and a hard disk backplane, the hard disk backplane being provided with a backplane controller, a plurality of hard disk connectors and a plurality of indicator lights corresponding to the plurality of hard disk connectors respectively, the backplane controller being connected with the plurality of hard disk connectors and the plurality of indicator lights; the management controller is connected with the backplane controller; wherein: the hard disk backplane is a first type hard disk backplane, the processor is connected with the plurality of hard disk connectors through a first storage controller, the first storage controller has a first port and a second port, the management controller is configured to, in response to a dial instruction, set a dial value of the hard disk backplane to a first dial value or a second dial value according to whether the plurality of hard disk connectors of the hard disk backplane are connected with the first port or the second port of the first storage controller, the dial value of the hard disk backplane being used for light-on control of the indicator lights on the hard disk backplane; or the hard disk backplane is a second type hard disk backplane, the processor is connected with the plurality of hard disk connectors through a second storage controller or directly connected with the plurality of hard disk connectors, the processor is configured to detect whether the processor is directly connected with the plurality of hard disk connectors on the hard disk backplane, and if so, assign a third dial value to the backplane controller; the management controller is configured to, in response to the dial instruction, set the dial value of the hard disk backplane to the third dial value or a fourth dial value according to whether the backplane controller is assigned the third dial value.

[0004] The second aspect of the present application provides an electronic device, the electronic device comprising a processor, a management controller, a first storage controller, a second storage controller, a serial bus hub and a plurality of hard disk backplanes, the hard disk backplanes being provided with a backplane controller, a plurality of hard disk connectors and a plurality of indicator lights corresponding to the plurality of hard disk connectors, the processor and the management controller being connected with the backplane controllers of the plurality of hard disk backplanes through the serial bus hub; the plurality of hard disk backplanes comprising a first type hard disk backplane and a second type hard disk backplane, the plurality of hard disk connectors on the first type hard disk backplane being connected with the processor through the first storage controller, the plurality of hard disk connectors on the second type hard disk backplane being connected with the processor through the second storage controller or being directly connected with the processor; the processor being configured to determine, for each hard disk backplane in the plurality of hard disk backplanes, whether the hard disk backplane is the first type hard disk backplane or the second type hard disk backplane, and enter a first mode if the hard disk backplane is the first type hard disk backplane or enter a second mode if the hard disk backplane is the second type hard disk backplane; in the first mode, the management controller is configured to, in response to a dial code instruction, set a dial code value of the hard disk backplane to a first dial code value or a second dial code value according to whether the plurality of hard disk connectors of the hard disk backplane are connected with a first port or a second port of the storage controller; in the second mode, the processor is configured to determine whether the processor is directly connected with the plurality of hard disk connectors on the hard disk backplane, and assign a third dial code value to the backplane controller if the processor is directly connected with the plurality of hard disk connectors; the management controller is configured to, in response to the dial code instruction, set the dial code value of the hard disk backplane to the third dial code value or a fourth dial code value according to whether the backplane controller is assigned the third dial code value, the dial code value of the hard disk backplane being used for lighting control of the indicator lights on the hard disk backplane.

[0005] The third aspect of the present application provides a lighting control method, the lighting control method being performed by the electronic device described above, the lighting control method comprising: in the case where the hard disk backplane is the first type hard disk backplane, the management controller, in response to a dial code instruction, setting a dial code value of the hard disk backplane to a first dial code value or a second dial code value according to whether the plurality of hard disk connectors of the hard disk backplane are connected with a first port or a second port of the first storage controller, the dial code value of the hard disk backplane being used for lighting control of the indicator lights on the hard disk backplane; in the case where the hard disk backplane is the second type hard disk backplane, the processor detecting whether the processor is directly connected with the plurality of hard disk connectors on the hard disk backplane, and assigning a third dial code value to the backplane controller if the processor is directly connected with the plurality of hard disk connectors; the management controller, in response to the dial code instruction, setting the dial code value of the hard disk backplane to the third dial code value or a fourth dial code value according to whether the backplane controller is assigned the third dial code value.

[0006] According to the embodiments of the present application, different dial values are issued to the backplane controller of the hard disk backplane according to the type of the different hard disk backplanes, and according to whether the second type of hard disk backplane is directly connected with the processor, so that the global address of the hard disk connector on the uplink hard disk backplane can be informed in the lighting program of the hard disk backplane, and meanwhile the first type of hard disk and the second type of hard disk are compatible, and a unified dial value issuing scheme is realized. By accurately issuing the dial value according to the preset logic, the global address parameter of the hard disk is directly corresponded, so that it can be ensured that the lighting program can accurately identify the position of the hard disk, the address matching deviation and the lighting abnormality caused by the human operation error are reduced, and reliable address guidance is provided for subsequent hard disk positioning and maintenance. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above content and other purposes, features and advantages of the present application will be more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings.

[0008] Figure 1A A schematic diagram of an electronic device according to a first embodiment of the present application is shown.

[0009] Figure 1B A schematic diagram of an electronic device according to another embodiment of the present application is shown.

[0010] Figure 2A A schematic diagram of an electronic device according to still another embodiment of the present application is shown.

[0011] Figure 2B A schematic diagram of a hard disk window of a server according to an embodiment of the present application is shown.

[0012] Figure 2C A schematic diagram of an electronic device according to still another embodiment of the present application is shown.

[0013] Figure 3 A schematic diagram of a first type of hard disk backplane according to an embodiment of the present application is shown.

[0014] Figure 4A A schematic diagram of an NVMe hard disk backplane directly connected with a CPU according to an embodiment of the present application is shown.

[0015] Figure 4B A schematic diagram of an NVMe hard disk backplane not directly connected with a CPU according to an embodiment of the present application is shown.

[0016] Figure 5 A schematic diagram of a second type of hard disk backplane according to an embodiment of the present application is shown.

[0017] Figure 6 A schematic diagram of an electronic device according to a second embodiment of the present application is shown.

[0018] Figure 7An operation flowchart of a lighting control method according to an embodiment of the present application is shown.

[0019] Figure 8 A schematic diagram of a backplane automatic dialing code flow according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present application, and is not intended to limit the scope of the present application. In the following detailed description of the embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present application.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "including" "comprising" and the like are meant to be inclusive, and are intended to mean that there are additions to the claimed elements, steps, operations, and / or components, but not excluding the presence of one or more other features, steps, operations, and / or components.

[0022] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein are defined as having meanings that are consistent with the context of the specification in which the terms are used, and should not be interpreted in an idealized or overly formal way.

[0023] In the case of using expressions similar to "at least one of A, B, and C, etc.", it should generally be interpreted to include at least one of each item enumerated, in the sense of the meaning commonly understood by one of ordinary skill in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C together, etc.).

[0024] In the technical solutions of the present application, the user information (including but not limited to user personal information, user image information, user equipment information, such as location information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved are information and data authorized by the user or authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of related data comply with relevant laws, regulations and standards, necessary security measures are taken, do not violate public order and good customs, and provide corresponding operation portal for user to choose authorization or refusal.

[0025] In the scenario of making automated decisions by using personal information, the method, device and system provided by the embodiments of the present application all provide corresponding operation entrances for users to select to agree or reject the automated decision result; if the user selects to reject, the expert decision process is entered. The expression "automated decision" herein refers to an activity of automatically analyzing, evaluating the behavior habit, interest and hobby or economic, health and credit status of a person by a computer program and making decisions. The expression "expert decision" herein refers to an activity of making decisions by a person who is engaged in a certain field, has special experience, knowledge and skills and reaches a certain professional level.

[0026] Inside the server, the hard disk is not directly inserted into the mainboard, but is first slid into a layer of metal bracket and then pushed into the front window of the case as a whole. The tail of the bracket is connected with a vertical circuit board, which is called a hard disk backboard. The hard disk backboard can lead the power supply and data signals to the hard disk at the same time, and send the status signals returned by the hard disk to the upper controller. The most intuitive item in the status signals is the LED (Light-Emitting Diode) indicator light on the front panel. The color and flashing rhythm of the LED indicator light correspond to different events such as the in-place, reading and writing, fault and positioning of the hard disk, so that the operation and maintenance personnel can locate the problem hard disk at a glance without disassembling the server. Therefore, there must be a CPLD in the hard disk backboard. The CPLD first identifies which port of the hard disk backboard each hard disk is connected to, and then identifies the storage card or CPU (Central Processing Unit) to which the port is finally connected, and then accurately connects the corresponding lamp control signal. Through the process of "identification-mapping-lighting", the hard disk backboard ensures that any hard disk in the server mass disk position can be quickly discovered when an abnormality occurs.

[0027] Two SATA (Serial Advanced Technology Attachment) hard disk backplanes and NVMe (Non-Volatile Memory Express) hard disk backplanes are used in a server system. The SATA hard disk backplane and the NVMe hard disk backplane need to be recognized by a CPLD (Complex Programmable Logic Device) uplink to be correctly lighted. For the two SATA hard disk backplanes, one SGPIO (Serial General Purpose Input / Output) bus of a storage card fixedly carries 4 disk light control signals, and the two SATA hard disk backplanes are only provided with 2 hard disks. The CPLD needs to determine which two ports of the 4 ports the 2 hard disks fall into, and then connect the corresponding light paths to the corresponding time slots of the SGPIO to avoid light sequence disorder. For the NVMe hard disk backplane, a DIP switch (Dual In-line Package) informs the CPLD whether the NVMe hard disk backplane is connected to a CPU or a storage card. The lighting protocols of the two uplinks are different, and the CPLD switches the logic according to this to make the LED on the slot of the NVMe hard disk accurately reflect the state.

[0028] In the related art, eight hard disk ports can be sequentially read and written. The CPLD is configured to record the read and write states of the hard disks on the plurality of hard disk interfaces, and communicate with the control component through the bus to obtain the correspondence between the hard disk interfaces and the ports; if the CPLD receives a lighting command sent by the control component through the SGPIO signal line, the lighting command is analyzed based on the correspondence between the hard disk interfaces and the ports to perform a lighting operation. This scheme can only process SATA backplanes, so it needs to distinguish the types of hard disk backplanes and cannot be used for NVMe backplane topology DIP processing.

[0029] In the related art, the CPLD DIP value of the backplane can be controlled by a virtual instruction to distinguish which port is connected to the SATA backplane uplink, and to distinguish whether the CPU or the storage card is connected to the NVMe backplane uplink. However, this scheme needs to recognize the system topology and then send the DIP value according to the configuration due to the multiple configurations of the server, and nearly 100 instructions need to be developed to implement the configuration. The DIP instructions of different projects and different configurations need to be developed separately, and the development cycle is long. The configuration distinction needs to rely on the material coding of the backplane and cable, and frequent physical changes lead to frequent maintenance of the DIP development.

[0030] Embodiments of the present application provide an electronic device and a lighting control method to solve at least one of the above technical problems.

[0031] Figure 1A A schematic diagram of an electronic device according to a first embodiment of the present application is shown.

[0032] Figure 1BA schematic diagram of an electronic device according to another embodiment of the application is shown.

[0033] As shown in Figure 1A and Figure 1B , the electronic device comprises a processor 110, a storage controller 130, a management controller 120 and a hard disk backboard 140. The hard disk backboard 140 is provided with a backboard controller 141, a plurality of hard disk connectors 142 and a plurality of indicator lights 143 corresponding to the plurality of hard disk connectors 142 respectively. The backboard controller 141 is connected with the plurality of hard disk connectors 142 and the plurality of indicator lights 143. The management controller 120 is connected with the backboard controller 141.

[0034] As shown in Figure 1A , the hard disk backboard 140 is a first type hard disk backboard, and the storage controller 130 is a first storage controller. The processor 110 is connected with the plurality of hard disk connectors 142 through the first storage controller, the first storage controller has a first port and a second port, and the management controller 120 is configured to, in response to a dial code instruction, set a dial code value of the hard disk backboard 140 to a first dial code value or a second dial code value according to whether the plurality of hard disk connectors 142 of the hard disk backboard are connected with the first port or the second port of the first storage controller, and the dial code value of the hard disk backboard 140 is used for lighting control of the indicator lights 143 on the hard disk backboard 140.

[0035] As shown in Figure 1B , the hard disk backboard 140 is a second type hard disk backboard, and the storage controller 130 is a second storage controller. The processor 110 is connected with the plurality of hard disk connectors 142 through the second storage controller or directly connected with the plurality of hard disk connectors 142, and the processor 110 is configured to detect whether the processor 110 is directly connected with the plurality of hard disk connectors 142 on the hard disk backboard 140, and if so, assign a third dial code value to the backboard controller 141; and the management controller 120 is configured to, in response to a dial code instruction, set the dial code value of the hard disk backboard 140 to a third dial code value or a fourth dial code value according to whether the backboard controller 141 is assigned the third dial code value.

[0036] In the case of the hard disk backboard 140 being a first type hard disk backboard, the dial code value of the first type hard disk backboard can be set according to whether the hard disk connector 142 is connected with the first port or the second port of the first storage controller, and the lighting operation of the first type hard disk backboard can be performed based on the dial code value of the first type hard disk backboard.

[0037] In the case of the second type of hard disk backplane, different dial code values can be issued by determining whether the processor 110 is directly connected to the plurality of hard disk connectors 142 on the hard disk backplane. A third dial code value is set based on the direct connection. In the case where the backplane controller of the second type of hard disk backplane is assigned the third dial code value, the processor 110 can perform the lighting operation of the plurality of hard disk connectors 142 based on the third dial code value. In the case where the backplane controller of the second type of hard disk backplane is not assigned the third dial code value, the processor 110 can perform the lighting operation of the plurality of hard disk connectors 142 based on the fourth dial code value.

[0038] For the first type of hard disk backplane, the first type of hard disk backplane can be a SAS (Serial Attached Small Computer System Interface) hard disk or a SATA hard disk. For example, a 2-port SATA hard disk backplane can be set to a first dial code value or a second dial code value according to whether the hard disk connector is connected to the first port or the second port of the first storage controller, to distinguish between the first two disks or the last two disks of the 2-port SATA hard disk backplane that are fixedly carried by the SGPIO bus. For the second type of hard disk backplane, such as an NVMe hard disk backplane, different dial code values are issued according to whether the second type of hard disk backplane is directly connected to the processor 110, and the uplink can perform different lighting protocols.

[0039] According to embodiments of the present application, different dial code values are issued to the backplane controller of the hard disk backplane according to the type of the different hard disk backplane and whether the second type of hard disk backplane is directly connected to the processor, so that the global address of the hard disk connector on the hard disk backplane can be informed in the lighting program of the hard disk backplane, and the first type of hard disk and the second type of hard disk are compatible, and a unified dial code value issuing scheme is implemented. By accurately issuing dial code values according to the preset logic, the global address parameters of the hard disk are directly corresponded, which can ensure that the lighting program can accurately identify the position of the hard disk, reduce the address matching deviation and lighting abnormalities caused by human operation errors, and provide reliable address guidance for subsequent hard disk positioning and maintenance.

[0040] According to embodiments of the present application, the dial code instruction is provided by a user or generated in the process of running a system diagnostic program before leaving the factory.

[0041] In mass production of devices such as servers, if the hard disk backplane physical dial code is dialed one by one by manual, the process is tedious and time-consuming. The electronic device of the embodiment of the application can run a system diagnosis program before leaving the factory, and can simultaneously batch issue dial code values to multiple hard disk backplanes, greatly shortening the configuration time. Moreover, when the user demand changes or the hard disk configuration needs to be iterated, there is no need to manually re-dial the switch, and only the parameters in the diagnosis program need to be modified, so that the dial code value can be quickly updated, the new hard disk global address rule or the lighting logic can be adapted, and the delivery efficiency and configuration iteration flexibility are greatly improved.

[0042] According to the embodiment of the application, the management controller 120 is a baseboard management controller (BMC), and the backplane controller 141 is a complex programmable logic device (CPLD). The processor 110 can be a CPU.

[0043] According to the embodiment of the application, the hard disk backplane is a first type hard disk backplane, and the management controller is configured to determine whether the hard disk backplane is connected to the first port or the second port of the first storage controller in response to the dial code instruction. If the multiple hard disk connectors of the hard disk backplane are connected to the first port of the first storage controller, the backplane controller is controlled to set the dial code value of the hard disk backplane to a first dial code value. If the multiple hard disk connectors of the hard disk backplane are connected to the second port of the first storage controller, the backplane controller is controlled to set the dial code value of the hard disk backplane to a second dial code value. The first port can be a serial attached small computer system (SAS) interface or a serial advanced technology attachment (SATA) interface. The second port can be a SAS / SATA interface.

[0044] According to the embodiment of the application, the number of hard disk backplanes is multiple, and the electronic device further comprises a serial bus arbitrator and a serial bus hub. The processor and the management controller are connected to an upstream port of the serial bus hub through the serial bus arbitrator. Multiple downstream ports of the serial bus hub are respectively connected to the backplane controllers of the multiple hard disk backplanes. The serial bus arbitrator is configured to communicate and connect one of the processor and the management controller to the upstream port of the serial bus hub according to a preset arbitration strategy.

[0045] Figure 2A A schematic diagram of an electronic device according to another embodiment of the application is shown.

[0046] The hard disk backplane is a first type hard disk backplane. The first type hard disk backplane can be a SAS hard disk backplane, or a SATA hard disk backplane. For the hardware design topology of the first type hard disk backplane as shown in Figure 2A The number of hard disk backplanes can be multiple, and the hard disk backplane can be a SAS / SATA hard disk backplane. The electronic device comprises multiple SAS / SATA hard disk backplanes.

[0047] As Figure 2A shown, the processor can be a CPU 201, and the management controller can be a BMC 202. The CPU 201 and the BMC 202 are located on a mainboard 111. The mainboard 111 can also be provided with a serial bus arbiter 112 and a serial bus hub 113. The backplane controller can be a CPLD 203. The first storage controller can be a PCIe (Peripheral Component Interconnect Express) storage card 131.

[0048] The CPU 201 can connect the hard disk connectors 142 on different SAS / SATA hard disk backplanes through the PCIe storage card 131, so as to connect the SAS / SATA hard disks corresponding to the hard disk connectors 142. The CPU 201 and the BMC 202 can be connected to the serial bus arbiter 112 through an I2C bus (Inter-Integrated Circuit). The serial bus arbiter 112 can be connected to at least one serial bus hub 113. The CPU 201 and the BMC 202 are connected to the upstream port of the serial bus hub through the serial bus arbiter 112, and the plurality of downstream ports of the serial bus hub are respectively connected to the backplane controllers of the plurality of hard disk backplanes.

[0049] The serial bus arbiter 112 can realize mutual exclusion of the CPU 201 and the BMC 202 in accessing the same I2C channel, and the serial bus hub 113 can isolate the devices of the same I2C address on the same I2C channel to avoid I2C address conflicts.

[0050] Since the SGPIO signal needs to distinguish whether the hard disk belongs to the first two disks or the last two disks of the four SAS / SATA hard disks in controlling the hard disk lighting behavior, for two SAS / SATA hard disks, the first two disks and the last two disks can be sequentially divided according to the front and rear order of the SAS / SATA hard disk backplane. The SAS / SATA hard disk backplane where the first two disks are located is connected to a specific channel of the serial bus hub, for example, an odd channel. The SAS / SATA hard disk backplane where the last two disks are located is connected to another specific channel of the serial bus hub, for example, an even channel. Figure 2AAs shown, the first downstream port S0 (odd channel) of the serial bus hub is connected with the first SAS / SATA hard disk backplane B0, and the second downstream port S1 (even channel) of the serial bus hub is connected with the second SAS / SATA hard disk backplane B1. The first SAS / SATA hard disk backplane B0 and the second SAS / SATA hard disk backplane B1 each include two hard disk connectors 142, and the first SAS / SATA hard disk backplane B0 and the second SAS / SATA hard disk backplane B1 can be connected with the first two and the last two of the four SAS / SATA hard disks respectively.

[0051] For the first SAS / SATA hard disk backplane B0 on which the first two hard disks connected with the first downstream port S0 of the serial bus hub are located, the BMC 202 sends a first dial code value to the CPLD 203 of the first SAS / SATA hard disk backplane B0 through the I2C link, representing that the first SAS / SATA hard disk backplane B0 is located on the first two hard disks, and the first dial code value is 0x01 (1), as shown in Table 1. For the second SAS / SATA hard disk backplane B1 on which the last two hard disks connected with the second downstream port S1 of the serial bus hub are located, the BMC 202 sends a second dial code value to the CPLD 203 of the second SAS / SATA hard disk backplane B1 through the I2C link, representing that the second SAS / SATA hard disk backplane B1 is located on the last two hard disks, and the second dial code value is 0x02 (2), as shown in Table 1.

[0052] The CPLD 203 can store the first dial code value or the second dial code value in a UFM (User Flash Memory) 204 on the CPLD 203, and the UFM 204 can be a non-volatile storage space. The first dial code value or the second dial code value can be used by the CPLD 203 to identify whether the SAS / SATA hard disk backplane currently located belongs to the first two hard disks or the last two hard disks.

[0053] According to the topology agreement that the different channels of the serial bus hub are connected with the first two hard disks and the last two hard disks respectively, the different channels of the serial bus hub are bound with the dial code values to form the 2-port SATA dial code value list in Table 1.

[0054] Table 1

[0055]

[0056] Figure 2B A schematic diagram of a hard disk window of a server according to an embodiment of the application is shown.

[0057] As Figure 2BAs shown, the hard disk window of the server can include server model A configuration 1 (front window) and server model B configuration 2 (rear window). The server model A configuration 1 (front window) and the server model B configuration 2 (rear window) each include 4 hard disk areas, and each hard disk area can be connected with two hard disks.

[0058] In combination with Figure 2A , Figure 2B and Table 1, the 8 downstream ports S0-S7 of the serial bus hub correspond to the 8 channels (denoted as Ch in Table 1) in the second column of Table 1, and the 8 hard disk areas of the server model A configuration 1 (front window) and the server model B configuration 2 (rear window) correspond to the 8 hard disk backboard types (denoted as BP Type in Table 1) in the third column of Table 1.

[0059] The first hard disk area Q0 corresponds to the first hard disk backboard type FBP0, the first SAS / SATA hard disk backboard B0 corresponding to the first hard disk area Q0 is connected with the first downstream port S0 (odd channel) of the serial bus hub, and a dial code value of 1 is issued, representing that the first hard disk backboard type FBP0 is front 2 ports. The second hard disk area Q1 corresponds to the second hard disk backboard type FBP1, the second SAS / SATA hard disk backboard B1 corresponding to the second hard disk area Q1 is connected with the second downstream port S1 (even channel) of the serial bus hub, and a dial code value of 2 is issued, representing that the second hard disk backboard type FBP1 is rear 2 ports. The third hard disk area Q2 corresponds to the third hard disk backboard type FBP2, the third SAS / SATA hard disk backboard corresponding to the third hard disk area Q2 is connected with the third downstream port S2 (odd channel) of the serial bus hub, and a dial code value of 1 is issued, representing that the third hard disk backboard type FBP2 is front 2 ports. The fourth hard disk area Q3 corresponds to the fourth hard disk backboard type FBP3, the fourth SAS / SATA hard disk backboard corresponding to the fourth hard disk area Q3 is connected with the fourth downstream port S3 (even channel) of the serial bus hub, and a dial code value of 2 is issued, representing that the fourth hard disk backboard type FBP3 is rear 2 ports.

[0060] The seventh hard disk area Q6 corresponds to the fifth hard disk backboard type RBP0. The fifth SAS / SATA hard disk backboard corresponding to the seventh hard disk area Q6 is connected with the fifth downstream port S4 (odd channel) of the serial bus hub, and a dial code value of 1 is issued, representing that the fifth hard disk backboard type RBP0 is the front 2 ports. The eighth hard disk area Q7 corresponds to the sixth hard disk backboard type RBP1. The sixth SAS / SATA hard disk backboard corresponding to the eighth hard disk area Q7 is connected with the sixth downstream port S5 (even channel) of the serial bus hub, and a dial code value of 2 is issued, representing that the sixth hard disk backboard type RBP1 is the rear 2 ports. The fifth hard disk area Q4 corresponds to the seventh hard disk backboard type RBP2. The seventh SAS / SATA hard disk backboard corresponding to the fifth hard disk area Q4 is connected with the seventh downstream port S6 (odd channel) of the serial bus hub, and a dial code value of 1 is issued, representing that the seventh hard disk backboard type RBP2 is the front 2 ports. The sixth hard disk area Q5 corresponds to the eighth hard disk backboard type RBP3. The eighth SAS / SATA hard disk backboard corresponding to the sixth hard disk area Q5 is connected with the eighth downstream port S7 (even channel) of the serial bus hub, and a dial code value of 2 is issued, representing that the eighth hard disk backboard type RBP3 is the rear 2 ports.

[0061] Based on the physical connection relationship with the downstream ports of the serial bus hub, the first dial code value or the second dial code value is issued to set the SAS / SATA hard disk backboard as the front 2 ports or the rear 2 ports. Then, the hard disk areas of the front 2 ports and the rear 2 ports can be staggered or randomly arranged in the position of the rear window.

[0062] Figure 2C A schematic diagram of an electronic device according to yet another embodiment of the application is shown.

[0063] According to an embodiment of the application, the hard disk backboards connected with the first port of the first storage controller and the hard disk backboards connected with the second port of the first storage controller are alternately arranged on the case of the electronic device. The first storage controller can be a redundant array of independent disks (RAID) controller. As shown in Figure 2C The RAID controller R includes a first port and a second port. The first port of the RAID controller R is connected with the first hard disk backboard B0 and the third hard disk backboard B2. The second port of the RAID controller R is connected with the second hard disk backboard B1 and the fourth hard disk backboard B3.

[0064] According to an embodiment of the present application, the plurality of hard disk backplanes are arranged in a plurality of positions in sequence, the first storage controller is connected with the hard disk backplanes in any odd position and any even position, wherein the first storage controller further has a serial general purpose input / output (SGPIO) interface, the serial general purpose input / output (SGPIO) interface of the first storage controller is connected with the complex programmable logic device (CPLD) of the hard disk backplane in the odd position and the complex programmable logic device (CPLD) of the hard disk backplane in the even position, the first port of the first storage controller is connected with the plurality of hard disk connectors of the hard disk backplane in the odd position, and the second port of the first storage controller is connected with the plurality of hard disk connectors of the hard disk backplane in the even position.

[0065] As shown in Figure 2C the RAID controller R includes a SGPIO interface. The SGPIO interface of the RAID controller R can be connected with the CPLD 203 of the first hard disk backplane B0 (odd position), the second hard disk backplane B1 (even position), the third hard disk backplane B2 (odd position) and the fourth hard disk backplane B3 (even position). The first port of the RAID controller R can be connected with two hard disk connectors on the first hard disk backplane B0 (odd position) through the interface of the SAS / SATA 320 of the first hard disk backplane B0 (odd position), and then connected to two hard disks 310 accessed on the first hard disk backplane B0 (odd position). Similarly, the first port of the RAID controller R can be connected with two hard disks 310 accessed on the third hard disk backplane B2 (odd position) through the interface of the SAS / SATA 320 on the third hard disk backplane B2 (odd position). The second port of the RAID controller R can be connected with two hard disks 310 accessed on the second hard disk backplane B1 (even position) through the interface of the SAS / SATA 320 on the second hard disk backplane B1 (even position). The second port of the RAID controller R can be connected with two hard disks 310 accessed on the fourth hard disk backplane B3 (even position) through the interface of the SAS / SATA 320 on the fourth hard disk backplane B3 (even position).

[0066] It should be noted that for one SGPIO signal to control four hard disks, it can also be four hard disks on the first hard disk backplane B0 (odd position) connected with the first port of the RAID controller R and the fourth hard disk backplane B3 (even position) connected with the second port of the RAID controller R.

[0067] The following further explains the dip value issuing scheme for the SAS / SATA hard disk backplane in the system diagnosis program running before factory.

[0068] In a system diagnosis program running before factory shipment, the CPLD on the backboard can be accessed by the BIOS (Basic Input / Output System) through the I2C link to obtain the type of hard disk slot support on the backboard, and the hard disk slot on the backboard supports SAS / SATA hard disks, so as to determine that the hard disk backboard is a SAS / SATA hard disk backboard.

[0069] In a system diagnosis program running before factory shipment, a one-key dialing instruction is issued to the BMC to trigger the BMC dialing. After receiving the one-key dialing instruction, the BMC can issue a predetermined dialing value to the CPLD according to the mapping table of the I2C channel (second column in Table 1) and the first dialing value and the second dialing value (fourth column in Table 1), and the CPLD stores the first dialing value and the second dialing value to the UFM area on the CPLD to realize the dialing value setting of the SAS / SATA hard disk backboard.

[0070] According to an embodiment of the present application, the first storage controller is further connected with the backboard controller, and the first storage controller is further configured to send a lighting signal to the backboard controller in response to the lighting instruction, and the backboard controller is further configured to determine a target indicator light among the plurality of indicator lights based on the lighting signal and the dialing value, and light up the target indicator light.

[0071] Figure 3 A schematic diagram of a first type of hard disk backboard according to an embodiment of the present application is shown.

[0072] As shown in Figure 3 , the electronic device includes a mainboard 111 and a SATA hard disk backboard 410. The SATA hard disk backboard 410 is a first type of hard disk backboard. The first storage controller can be a PCIe storage card 131, and can also be a RAID controller.

[0073] As shown in Figure 3 , the PCIe storage card 131 can be used to send SAS / SATA signals and SGPIO signals to the SATA hard disk backboard 410. The SAS / SATA signals and the SGPIO signals can share a cable (not shown in the figure), and the SAS / SATA signals can access the SAS / SATA uplink interface 403 on the SATA hard disk backboard 410 through the SAS / SATA data channel, and the SGPIO signals can access the SGPIO management interface 402 on the SATA hard disk backboard 410 through the SGPIO management channel (lighting instruction channel).

[0074] The CPU 201 can send a lighting instruction to the PCIe storage card 131 through the PCIe data bus. The PCIe storage card 131 can parse the lighting instruction and send the SGPIO signal, which can be used for low-speed control instruction transmission related to hard disk lighting.

[0075] The first hard disk connector L0 and the second hard disk connector L1 can be directly connected to the SAS / SATA uplink interface 403 through the circuit board trace. The first hard disk Y0 can be connected to the PCIe storage card 131 through the first hard disk connector L0. The second hard disk Y1 can be connected to the PCIe storage card 131 through the second hard disk connector L1. The SAS / SATA signal can be used for high-speed data read and write between the first hard disk Y0 and the PCIe storage card 131, between the second hard disk Y1 and the PCIe storage card 131, such as distributed storage of data in a RAID array, real-time access of business data, etc.

[0076] The CPLD 203 can receive the SGPIO signal through the SGPIO management interface 402. The CPLD 203 is connected to the positioning / fault indicator light 1431 and the activity indicator light 1432 of the first hard disk slot C0 and the second hard disk slot C1 respectively, and the CPLD 203 can control the positioning / fault indicator light 1431 and the activity indicator light 1432 according to the instruction of the SGPIO signal. The SGPIO management interface 402 includes Sclock (clock line), SLoad (latch signal line), SDataOut (data output line). In the initialization stage, the PCIe storage card 131 or the RAID controller configures the transmission timing of the SGPIO signal, and the CPLD 203 performs the analysis preparation work of the SGPIO signal, and at the same time, the mapping relationship between each group of SGPIO signal and the corresponding positioning / fault indicator light 1431 and activity indicator light 1432 is determined.

[0077] The CPU 201 can issue a lighting instruction through the serial bus arbitrator 112 and the serial bus hub 113 to directly control the SATA hard disk backboard 410. The BMC 202 can also issue a lighting signal through the serial bus arbitrator 112 and the serial bus hub 113 to manage the SATA hard disk backboard. The serial bus hub 113 can also be replaced by an I2C bus or an SMBus (System Management Bus) bus, and the lighting instruction is input to the I2C / SMBus interface 401 on the SATA hard disk backboard 410 through the sensor or configuration channel of the I2C bus or the SMBus bus. The CPLD 203 can receive the lighting instruction or the BMC management from the I2C / SMBus interface 401. The CPLD 203 can send a monitoring in-place signal to the first hard disk connector L0 and the second hard disk connector L1 to monitor the state of the first hard disk Y0 and the second hard disk Y1.

[0078] The hard disk backboard is a second type of hard disk backboard. The processor and the management controller are connected to the backboard controller on the hard disk backboard through a first bus link; the processor is connected to the hard disk connector on the hard disk backboard through a second bus link.

[0079] Figure 4A A schematic diagram of a NVMe hard disk backboard directly connected to a CPU according to an embodiment of the present application is shown. Figure 4B A schematic diagram of a NVMe hard disk backboard not directly connected to a CPU according to an embodiment of the present application is shown.

[0080] The management controller can be a baseboard management controller (BMC), and the backboard controller is a complex programmable logic device (CPLD). The second type of hard disk backboard is a hard disk backboard supporting a non-volatile memory express (NVMe) protocol, such as a NVMe hard disk backboard. The second storage controller can be a triple-mode disk redundant array controller (Trimode). The Trimode card can be compatible with SAS, SATA, and NVMe protocols.

[0081] According to an embodiment of the present application, the first bus is an internal integrated circuit bus, and the second bus is a peripheral component interconnect express (PCIe) bus.

[0082] According to an embodiment of the present application, in the case that the hard disk connector on the hard disk backboard is directly connected to the processor, a plurality of second bus ports of the processor are respectively connected to a plurality of hard disk connectors on the hard disk backboard. As shown in Figure 4A In the case that the hard disk connector 142 is directly connected to the CPU 201, a plurality of second bus (PCIe) ports of the CPU 201 are respectively connected to a plurality of hard disk connectors 142 on the NVMe hard disk backboard Me.

[0083] As shown in Figure 4B In the case that the hard disk connector 142 is not directly connected to the CPU 201, a plurality of hard disk connectors 142 on the NVMe hard disk backboard Me are connected to the CPU 201 through the Trimode card 132.

[0084] According to an embodiment of the present application, the number of hard disk backboards is a plurality, and the mainboard further comprises a serial bus arbitrator and a serial bus hub. The processor and the management controller are connected to an upstream port of the serial bus hub through the serial bus arbitrator. A plurality of downstream ports of the serial bus hub are respectively connected to backboard controllers of the plurality of hard disk backboards. The serial bus arbitrator is configured to connect one of the processor and the management controller to the upstream port of the serial bus hub in communication according to a preset arbitration strategy. As shown in Figure 4A and Figure 4BAs shown, CPU 201 and BMC 202 are connected to serial bus arbiter 112 via an I2C bus. Serial bus arbiter 112 can be connected to at least one serial bus hub 113. CPU 201 and BMC 202 are connected to the upstream port of serial bus hub 113 via serial bus arbiter 112. The first downstream port S0 of serial bus hub 113 is connected to the NVMe hard drive backplane Me. The second downstream port S1 of serial bus hub 113 and the first downstream port S0 and second downstream port S1 of other serial bus hubs 113 can also be connected to the NVMe hard drive backplane Me.

[0085] The serial bus arbiter 112 enables the CPU 201 and BMC 202 to access the same I2C channel mutually exclusively. The serial bus hub can isolate devices with the same I2C address on the same I2C channel, thus avoiding I2C address conflicts.

[0086] The processor is configured to, upon power-up, obtain a slot-to-hard drive address mapping table from the backplane controller of the hard drive backplane via a first bus link, and obtain hard drive identifiers from each hard drive connector on the hard drive backplane via a second bus link, thus obtaining a hard drive identifier-to-second bus port mapping table. Based on the slot-to-hard drive address mapping table, the hard drive identifier-to-second bus port mapping table, and the pre-stored hard drive address-to-second bus port mapping table, it determines whether the hard drive on the hard drive backplane is directly connected to the processor. If it is directly connected, it sends a third DIP switch value to the backplane controller via the first bus link. The management controller is configured to, in response to a DIP switch command, perform a DIP switch value write operation to the backplane controller via the first bus link. The DIP switch value write operation includes: if the backplane controller has been assigned a third DIP switch value, controlling the backplane controller to store the third DIP switch value as the DIP switch value for the hard drive backplane; otherwise, controlling the backplane controller to store a fourth DIP switch value as the DIP switch value for the hard drive backplane.

[0087] For the LED operation of NVMe hard drives, it is necessary to first determine whether the hard drive on the NVMe hard drive backplane is directly connected to the CPU. Therefore, two DIP switch values ​​are set for the two cases of whether it is directly connected to the CPU. Before issuing the DIP switch values, it is also necessary to first determine whether the hard drive on the NVMe hard drive backplane is directly connected to the CPU.

[0088] like Figure 4A As shown, the first bus link can be a link established by the CPU 201 via the I2C bus through the serial bus arbiter 112 and the serial bus hub 113 with the CPLD 203 of the NVMe hard drive backplane Me. The second bus link can be a link established by the CPU 201 via the PCIe data bus through the PCIe MCIO (Mini Cool Edge I / O) connector M with each hard drive connector 142 of the NVMe hard drive backplane Me.

[0089] The mainboard 111 can set a state value of a configuration strap group (Strap) of a respective virtual pin port (VPP) for each second bus port (PCIe Port), and the state value can be represented by [0:3], as shown in Table 2. The hard disk address can be represented by VPP ADDR (Virtual Pin Port Address). Each second bus port (PCIe Port) on the mainboard 111 is connected to each slot through a cable corresponding to each second bus port. Therefore, the state value of each slot is consistent with the state value of each second bus port. On the hardware of the NVMe hard disk backplane Me, each slot is directly connected to a GPIO (General Purpose Input / Output) pin of the CPLD 203. Therefore, the state value of the GPIO pin of the CPLD 203 is consistent with the state value of each second bus port. The CPLD 203 can obtain the mapping table of each slot and the hard disk address (VPP ADDR) by obtaining the state value of the GPIO pin. The CPU 201 reads the hard disk address (VPP ADDR) of each slot recorded by the CPLD 203 through the I2C (first bus link).

[0090] The CPU 201 obtains the mapping table of the slot and the hard disk address (VPP ADDR) from the CPLD 203 of the NVMe hard disk backplane Me through the first bus link when powered on. The hard disk identifier is obtained from each hard disk connector 142 of the NVMe hard disk backplane Me through the second bus link to obtain the mapping table of the hard disk identifier and the second bus port (PCIe Port).

[0091] Based on the mapping table of the slot and the hard disk address (VPP ADDR), the mapping table of the hard disk identifier and the second bus port (PCIe Port), and the pre-stored mapping table of the hard disk address and the second bus port (PCIe Port) (as shown in Table 2), it is determined whether the hard disk on the NVMe hard disk backplane Me is directly connected to the CPU 201.

[0092] Table 2

[0093]

[0094] Figure 5 A schematic diagram of a second type of hard disk backplane according to an embodiment of the application is shown.

[0095] The following will be described in combination with Figure 5The dip value assignment scheme for the NVMe hard disk backplane 420 in the system diagnostic program running before factory shipment is further explained. The dip value assignment scheme for the NVMe hard disk backplane 420 includes two main steps.

[0096] The first main step is to determine whether the hard disk on the NVMe hard disk backplane 420 is directly connected to the CPU 201.

[0097] The system diagnostic program running before factory shipment can access the CPLD 203 through the first bus link by the BIOS 404 to obtain the slot and hard disk address mapping table. The BIOS 404 can obtain the hard disk identification from each hard disk connector 142 of the NVMe hard disk backplane 420 through the second bus link to obtain the hard disk identification and the second bus port mapping table.

[0098] The BIOS 404 obtains the code of the second bus port (PCIe Port) through the first path. The first path is NVMe hard disk backplane X-global address X-hard disk address (VPP ADDR)-second bus port (PCIe Port).

[0099] The BIOS 404 can access the NVMe hard disk backplane through the I2C bus, and by giving the virtual port address special configuration pin (VPP Strap Pin) to the GPIO pin of the CPLD 203, the BIOS 404 can read the configuration pin group information of the virtual port address corresponding to the hard disk slot in the CPLD 203 to obtain the slot and hard disk address mapping table. Based on the slot and hard disk address (VPP ADDR) mapping table and the pre-stored hard disk address and second bus port (PCIe Port) mapping table (as shown in Table 2), the BIOS 404 can obtain the code of the second bus port (PCIe Port).

[0100] The special configuration pin of the virtual port address of the first hard disk connector L0 and the second hard disk connector L1 is the unique hard disk address allocated to the NVMe hard disk with a PCIe interface in the server. The first hard disk connector L0 and the second hard disk connector L1 both correspond to a configuration pin group of a virtual port address, and the configuration pin group of the virtual port address stores the virtual port address of the corresponding slot through high and low level combination. When the first hard disk Y0 is inserted into the first hard disk connector L0, a group of virtual port address configuration pins of the first hard disk connector L0 will directly transmit the level signal to the GPIO pin reserved in the CPLD 203. The CPLD 203 internally pre-stores a mapping table of the GPIO pin (corresponding to the slot) and the hard disk address, for example, different level combinations of the bit0-bit3 pins of the GPIO correspond to different hard disk address codes.

[0101] In the case of direct connection between the hard disk on the NVMe hard disk backplane and the CPU, the BIOS 404 can identify the first hard disk Y0 and the second hard disk Y1 through the PCIe Port scanning through the second bus link and assign the BDF value. The BIOS 404 obtains the BDF value of the first hard disk Y0 and the second hard disk Y1 according to the encoding of the second bus port (PCIe Port), and can obtain the relationship between the slot and the hard disk identifier, that is, the direct connection between the hard disk on the NVMe hard disk backplane and the CPU 201 can be identified. The BDF value of the hard disk is the combination of the bus (Bus) number, device (Device) number and function (Function) number of the PCIe device. The bus number is a unique number that identifies the PCIe bus and is used to distinguish different PCIe transmission channels. The device number is used to identify independent devices on the same PCIe bus, and multiple hard disks on the same hard disk backplane or multiple hard disk interfaces on the same PCIe expansion card are distinguished by different device numbers. The function number is used to identify independent functional modules within the same device.

[0102] The BIOS 404 obtains the BDF value of the first hard disk Y0 and the second hard disk Y1 through the second path. The second path is direct connection NVMe hard disk backplane X-second bus port (PCIe Port)-BDF value. Through the management of the second bus port (PCIe Port), NVMe hard disk backplane X-global address X-hard disk address (VPP ADDR)-second bus port (PCIe Port)-NVMe hard disk backplane X-BDF value can be obtained. The BIOS 404 can determine whether the hard disk connected to the NVMe hard disk backplane X-global address X is a direct connection CPU NVMe hard disk.

[0103] To realize the two modes of CPU direct connection and Trimode card connection compatible with NVMe hard disk backplane, the connector of the NVMe hard disk backplane will multiplex the pin corresponding to the hard disk address (VPP ADDR) with the I2C signal pin required by the Trimode card. Each PCIe port connector of the Trimode card 132 has a dedicated I2C signal, and each I2C signal pin corresponds to a corresponding hard disk one by one, without the need for hard disk address (VPP ADDR) to distinguish different PCIe ports. At this time, the positioning of the PCIe port relies on the PCIe Switch expansion logic built-in the Trimode card and the BDF value assigned by the system to realize, and the port distinguishing function of the hard disk address (VPP ADDR) is invalid.

[0104] In the case of hard disks on the NVMe hard disk backplane and connecting the Trimode card 132, the original pin corresponding to the hard disk address (VPPADDR) is used for the I2C signal required by the Trimode card. Then, the configuration pin group information of the virtual port address obtained from the GPIO pin of the CPLD 203 may not match the slot information, and the wrong slot and hard disk address mapping table is obtained.

[0105] The BIOS 404 reads the wrong slot and hard disk address mapping table in the CPLD 203. The BIOS 404 scans and identifies the first hard disk Y0 and the second hard disk Y1 according to the second bus port (PCIe Port), and assigns the BDF value. The BIOS 404 obtains the wrong encoding of the second bus port (PCIe Port) based on the wrong slot and hard disk address mapping table and the pre-stored hard disk address and second bus port (PCIe Port) mapping table (as shown in Table 2), and the BIOS 404 obtains the BDF value of the first hard disk Y0 and the second hard disk Y1 according to the wrong encoding of the second bus port (PCIe Port). The slot and hard disk identification obtained do not match, and it can be determined that the hard disk on the NVMe hard disk backplane is connected to the Trimode card.

[0106] The second main step is the third dial value or the fourth dial value.

[0107] After determining that the hard disk on the NVMe hard disk backplane 420 is connected to the CPU 201, the BIOS 404 issues the third dial value to the NVMe hard disk backplane 420. The third dial value can be 0x00 (0), as shown in Table 1. The third dial value can represent that the NVMe hard disk is directly connected to the CPU.

[0108] If the CPLD 203 receives the third dial value issued by the BIOS 404, a one-key dial instruction is issued to the BMC 202 in the system diagnostic program running before shipment, triggering the BMC 202 to dial. After the BMC 202 receives the one-key dial instruction, it can issue the predetermined dial value to the CPLD 203 according to the I2C channel (second column in Table 1) and third dial value (sixth column in Table 1) mapping table shown in Table 1, and the CPLD 203 stores the third dial value to the UFM 204 area on the CPLD 203, realizing the direct connection CPU dial value setting.

[0109] It should be noted that the UFM area on the CPLD has a read-write number display. Based on the fact that the BIOS will start to judge whether it is directly connected and issue the third dial code value in the case of direct connection every time the machine is started, the third dial code value issued by the BIOS to the CPLD will be temporarily stored on the CPLD. In this way, the UFM area on the CPLD will not be read and written multiple times during multiple restarts. During the process of running the system diagnosis program before shipment and in the case of user updates, the BMC will issue the third dial code value to the UFM area on the CPLD.

[0110] After determining that the hard disk is connected to the Trimode card 132 on the NVMe hard disk backboard 420, and the CPLD 203 does not receive the third dial code value issued by the BIOS 404, a one-key dial code instruction is issued to the BMC 202 in the system diagnosis program running before shipment, triggering the BMC dial code. After receiving the one-key dial code instruction, the BMC 202 can issue the given dial code value to the CPLD 203 according to the mapping table of the I2C channel (second column in Table 1) and the fourth dial code value (fifth column in Table 1), and the CPLD 203 stores the fourth dial code value to the UFM 204 area on the CPLD 203, realizing the Trimode card dial code value setting.

[0111] It should be noted that the fourth dial code value corresponding to the fifth column in Table 1 can be 1 or 2. For example, the BMC 202 can issue 1 to the UFM 204 area on the CPLD 203.

[0112] Since the physical dial switch or the instruction dial code needs to distinguish the hard disk backboard light type by physical dialing or instruction dialing according to the material, hundreds of dial code values caused by different projects, different topologies, and different materials require development. The SAS / SATA hard disk backboard and the NVMe hard disk backboard dial code instruction are incompatible, and need to be identified and distinguished between the two types of backboards. Moreover, the hard disk backboard light type depends on the topology and the material for scheme development.

[0113] The electronic device of the embodiment of the present application adopts an automatic hard disk backboard dial code value issuing scheme. The BIOS automatically identifies whether the CPU is directly connected to the NVMe hard disk and issues the NVMe hard disk backboard dial code value. Through the factory system diagnosis process, the BMC triggers the automatic issuance of the third dial code value or the fourth dial code value to the hard disk backboard CPLD according to the channel dial code value list (such as Table 1) and stores it to the UFM non-volatile storage space of the CPLD. This can automatically, efficiently, and at low cost distinguish the hard disk backboard light type, which is conducive to more effectively solving the problem of distinguishing the hard disk backboard light type and avoiding physical dialing or instruction dialing according to the material number, topology, and other information.

[0114] After setting the dial code value of the NVMe hard disk backboard in the system diagnosis process before leaving the factory, the subsequent server application process can be based on the preset dial code value to perform the lighting operation of the NVMe hard disk backboard.

[0115] In the case that the hard disk on the NVMe hard disk backboard is directly connected with the CPU, the processor is further configured to, in response to the lighting instruction, issue a lighting signal to the backboard controller through the first bus link, and the backboard controller is further configured to determine a target indicator light among the plurality of indicator lights based on the lighting signal and the dial code value, and light up the target indicator light.

[0116] The processor can also transmit the lighting instruction to the management controller, and the management controller issues a lighting signal to the backboard controller through the first bus link in response to the lighting instruction, and the backboard controller is further configured to determine a target indicator light among the plurality of indicator lights based on the lighting signal and the dial code value, and light up the target indicator light.

[0117] According to an embodiment of the present application, the second storage controller is also connected with the backboard controller, and the second storage controller is further configured to, in response to the lighting instruction, send a lighting signal to the backboard controller, and the backboard controller is further configured to determine a target indicator light among the plurality of indicator lights based on the lighting signal and the dial code value, and light up the target indicator light.

[0118] As shown in Figure 5 The second storage card can be a Trimode card 132. The CPU 201 can connect the Trimode card 132 through the PCIe data bus, and the Trimode card 132 can connect the PCIe uplink interface 405 on the NVMe hard disk backboard 420 through the PCIe data channel (high-speed data channel). The PCIe uplink interface 405 can be directly connected with the first hard disk connector L0 and the second hard disk connector L1 through the circuit board wiring.

[0119] The controller chip of the Trimode card 132 has a hard disk management function, and the Trimode card 132 is connected to the CPLD 203 through the SGPIO interface of the controller chip, and can control the lighting of the SATA hard disk backboard (not shown in the figure). The Trimode card 132 can also control the CPLD to realize the lighting of the NVMe hard disk backboard 420 (not shown in the figure) through the I2C interface (multiplexed with VPP) on the card. In the initialization stage, the Trimode card 132 configures the transmission timing of the SGPIO signal, and the CPLD 203 performs the analysis preparation work of the SGPIO signal, and at the same time, the mapping relationship between each group of SGPIO signal and the corresponding positioning / fault indicator light and the active indicator light is determined.

[0120] The trimode card 132 is connected with the CPLD 203. The trimode card 132 sends a lighting signal to the CPLD 203 in response to a lighting instruction, and the CPLD 203 determines a target indicator light among the plurality of indicator lights based on the lighting signal and the dial value, and lights up the target indicator light. The CPLD 203 is connected with the positioning / fault indicator light 1431 and the activity indicator light 1432 of the first hard disk slot C0 and the second hard disk slot C1 respectively, and can control the positioning / fault indicator light 1431 and the activity indicator light 1432 according to the lighting signal and the dial value.

[0121] The CPU 201 can also be directly connected with the first hard disk connector L0 and the second hard disk connector L1 through the PCIe data channel (high-speed data channel), that is, the second bus link.

[0122] The CPU 201 can also send a lighting instruction to the NVMe hard disk backboard 420 through the serial bus arbitrator 112 and the serial bus hub 113, that is, the first bus link.

[0123] The BMC 202 can also send a lighting signal to the NVMe hard disk backboard 420 through the serial bus arbitrator 112 and the serial bus hub 113, that is, the first bus link.

[0124] Figure 6 A schematic diagram of an electronic device according to a second embodiment of the application is shown.

[0125] As shown in Figure 6 The electronic device includes a processor 110, a management controller 120, a first storage controller 611, a second storage controller 612, a serial bus hub 113, and a plurality of hard disk backboards, wherein the hard disk backboard is provided with a backboard controller 141, a plurality of hard disk connectors 142, and a plurality of indicator lights 143 corresponding to the plurality of hard disk connectors, and the processor 110 and the management controller 120 are connected with the backboard controller 141 of the plurality of hard disk backboards through the serial bus hub 113.

[0126] The plurality of hard disk backboards includes a first type hard disk backboard 614 and a second type hard disk backboard 613, the plurality of hard disk connectors 142 on the first type hard disk backboard 614 are connected with the processor 110 through the first storage controller 611, and the plurality of hard disk connectors 142 on the second type hard disk backboard 613 are connected with the processor 110 through the second storage controller 612 or directly connected with the processor 110.

[0127] The processor is configured to determine whether the hard disk backboard is a first type hard disk backboard or a second type hard disk backboard for each hard disk backboard in the plurality of hard disk backboards, and if it is a first type hard disk backboard, enter a first mode, and if it is a second type hard disk backboard, enter a second mode.

[0128] In the first mode, the management controller is configured to control the backplane controller to set the dip value of the hard disk backplane to a first dip value or a second dip value according to whether the plurality of hard disk connectors of the hard disk backplane are connected to the first port or the second port of the storage controller in response to a dip instruction. In the second mode, the processor is configured to determine whether the processor is directly connected to the plurality of hard disk connectors on the hard disk backplane, and if so, assign a third dip value to the backplane controller. The management controller is configured to set the dip value of the hard disk backplane to the third dip value or a fourth dip value according to whether the backplane controller is assigned the third dip value in response to a dip instruction, the dip value of the hard disk backplane being used for lighting control of the indicator light on the hard disk backplane.

[0129] According to embodiments of the present application, different dip values are issued to the backplane controller of the hard disk backplane according to the type of the hard disk backplane and whether the second type hard disk backplane is directly connected to the processor, so that the global address of the hard disk connector on the uplink hard disk backplane can be informed in the lighting program of the hard disk backplane, while being compatible with SAS / SATA hard disks and NVMe hard disks, and realizing a unified dip scheme. By accurately issuing the dip value according to the preset logic, the global address parameter of the hard disk is directly corresponded, which can ensure that the lighting program can accurately identify the hard disk position, reduce the address matching deviation and lighting abnormality caused by human operation errors, and provide reliable address guidance for subsequent hard disk positioning and maintenance.

[0130] The present application also provides a lighting control method, which can be executed by the electronic device of the embodiments of the present application.

[0131] Figure 7 An operation flowchart of the lighting control method according to embodiments of the present application is shown.

[0132] As shown in Figure 7 The lighting control method includes operations S710-S720.

[0133] In operation S710, in the case where the hard disk backplane is a first type hard disk backplane, the management controller controls the backplane controller to set the dip value of the hard disk backplane to a first dip value or a second dip value according to whether the plurality of hard disk connectors of the hard disk backplane are connected to the first port or the second port of the first storage controller in response to a dip instruction, the dip value of the hard disk backplane being used for lighting control of the indicator light on the hard disk backplane.

[0134] In operation S720, in the case where the hard disk backboard is a second type of hard disk backboard, the processor detects whether the processor is directly connected with the plurality of hard disk connectors on the hard disk backboard, and if so, assigns a third dial code value to the backboard controller; the management controller responds to the dial code instruction and sets the dial code value of the hard disk backboard to the third dial code value or the fourth dial code value according to whether the backboard controller is assigned the third dial code value.

[0135] According to the embodiments of the present application, different dial code values are issued to the backboard controller of the hard disk backboard according to the type of the hard disk backboard and whether the second type of hard disk backboard is directly connected with the processor, so that the global address of the hard disk connector on the uplink hard disk backboard can be informed in the lighting program of the hard disk backboard, and SAS / SATA hard disks and NVMe hard disks are compatible, and a unified dial code scheme is realized. By accurately issuing the dial code value according to the preset logic, the global address parameter of the hard disk is directly corresponded, so that the lighting program can accurately identify the position of the hard disk, reduce the address matching deviation and lighting abnormality caused by human operation errors, and provide reliable address guidance for subsequent hard disk positioning and maintenance.

[0136] Figure 8 A schematic diagram of a backboard automatic dialing process according to an embodiment of the present application is shown.

[0137] As shown in Figure 8 , the backboard automatic dialing process includes operations S801-S814.

[0138] The SAS / SATA hard disk backboard hardware design topology (such as Figure 2A ) of the electronic device according to the embodiments of the present application, the NVMe hard disk backboard hardware design topology (such as Figure 4A ), the system topology rule, the hard disk backboard automatic dialing value list (such as Table 1), and the PCIe Port mapping table (such as Table 2) are combined to design the hardware and system. Figure 8 The backboard CPLD, BIOS, and BMC are developed according to the backboard automatic dialing process (such as

[0139] In operation S801, the backboard CPLD obtains the PCIe Port code of the NVMe hard disk. If the hard disk backboard is an NVMe hard disk backboard, the hard disk backboard CPLD obtains the VPP ADDR of each hard disk slot through the GPIO pin representing the VPP ADDR, and maps to the PCIe Port code according to Table 2.

[0140] In operation S802, the backboard CPLD sets the slot to SAS / SATA / NVMe. The hard disk backboard CPLD sets the slot to SAS / SATA / NVMe according to the type of the hard disk backboard.

[0141] In operation S803, the BIOS identifies and assigns a BDF value of the server NVMe hard disk. The BIOS identifies and assigns the BDF value of the CPU direct connection NVMe disk according to PCIe Port scanning.

[0142] In operation S804, the BIOS accesses the backplane CPLD to obtain the hard disk slot support type. The BIOS can access the backplane CPLD through I2C to obtain the hard disk backplane support type. If it is an NVMe backplane, the hard disk backplane CPLD obtains the VPP ADDR value corresponding to each slot according to the scheme, which can be mapped to the PCIe Port code according to Table 2.

[0143] In operation S805, the BIOS accesses the backplane CPLD supporting the NVMe slot category to obtain the PCIe Port code value corresponding to the hard disk slot.

[0144] In operation S806, the BIOS obtains the BDF value according to the PCIe Port code value mapping, and further obtains the NVMe hard disk and NVMe slot relationship. According to the NVMe hard disk and NVMe slot relationship, the corresponding NVMe hard disk can be identified as being directly connected to the CPU rather than a Trimode card.

[0145] In operation S807, the BIOS issues the dial code value 0x00 to the backplane CPLD corresponding to the NVMe slot directly connected to the CPU.

[0146] In operation S808, it is judged whether the backplane CPLD receives the dial code value issued by the BIOS.

[0147] If yes, operations S809-S811 are performed.

[0148] In operation S809, the factory system diagnosis issues a one-key dialing instruction to the BMC.

[0149] In operation S810, after the BMC receives the one-key dialing instruction, the predetermined dialing value is issued to the backplane CPLD according to the I2C channel-dialing value mapping table.

[0150] In operation S811, the backplane CPLD stores the BIOS dialing value to the CPLD UFM area.

[0151] If the hard disk backplane CPLD receives the dialing value issued by the BIOS, the factory system diagnosis issues a one-key dialing instruction to the BMC, triggers the BMC dialing, and the BMC receives the one-key dialing instruction. After the instruction, the predetermined dialing value is issued to the backplane CPLD according to the I2C channel-dialing value mapping table in Table 1, and the backplane CPLD stores the BIOS dialing value to the backplane CPLD UFM area.

[0152] If no, operations S812-S814 are performed.

[0153] In operation S812, the factory system diagnosis issues a one-key dialing instruction to the BMC.

[0154] In operation S813, after the BMC accepts the one-key dialing instruction, the BMC issues the determined dialing value to the backplane CPLD according to the I2C channel-dialing value mapping table.

[0155] In operation S814, the backplane CPLD stores the BMC dialing value to the CPLD UFM area.

[0156] If the hard disk backplane CPLD does not receive the dialing value issued by the BIOS, the factory system diagnosis issues a one-key dialing instruction to the BMC, triggers the BMC dialing, and after the BMC accepts the one-key dialing instruction, the BMC issues the determined dialing value to the backplane CPLD according to the I2C channel-dialing value mapping table in Table 1, and the backplane CPLD stores the BMC dialing value to the backplane CPLD UFM area.

[0157] Until the backplane CPLD identifies the front 2 ports of the 2-port SAS\SATA backplane or the rear 2 ports of the backplane, and identifies whether the NVMe hard disk is directly connected to the CPU or the Trimode card.

[0158] The electronic device of the embodiments of the present application adopts the dialing value issuing mode of the factory diagnosis program, which can directly cancel the physical dialing switch component, not only saving the valuable space on the backplane and reserving space for the layout of other core devices, but also reducing the hardware material cost, simplifying the hardware design and wiring of the backplane, and reducing the potential risk of hardware failure. It can also effectively solve the difficulties of dialing scheme transmission and dialing instruction maintenance adaptation caused by material and topology changes, effectively solve the problem of production rate decline and production cost increase caused by factory changes.

[0159] The electronic device of the embodiment of the present application adopts BIOS to automatically identify the directly connected NVMe hard disk and the BMC to automatically issue the dial code value to the hard disk backplane CPLD in the channel dial code value list mode, so as to realize automatic dial code to distinguish the hard disk backplane light type. Through the dial code value issuing mode of the factory diagnosis program, cooperating with the baseboard management controller (BMC) and other modules, a remote communication link can be constructed. The staff does not need to operate on site, but can remotely query whether the current dial code configuration matches the hard disk global address, and if the light is abnormal or the address recognition is wrong, the dial code value can also be remotely reissued for debugging, reducing the difficulty and cost of equipment operation and maintenance. The dial code value parameters of the factory diagnosis program can be uniformly managed, and all hard disk backplanes are issued according to the same standard configuration, which ensures the consistency of the configuration of the same batch or even different batches of products, and avoids the configuration confusion caused by manual operation differences. In addition, the program can record the time, parameters and other log information of each dial code value issuing, and if subsequent hard disk address or light related problems occur, the configuration process can be traced through the log to quickly locate the problem source and improve the problem troubleshooting efficiency.

[0160] The dial code value issuing scheme of the embodiment of the present application is compatible with SAS / SATA hard disks and NVMe hard disks, realizes a unified dial code scheme, and does not need to identify the hard disk material category to execute different dial codes.

[0161] Those skilled in the art can understand that the features described in various embodiments of the present application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present application. In particular, the features described in various embodiments of the present application can be combined and / or combined in various ways without departing from the spirit and teachings of the present application. All these combinations and / or combinations fall within the scope of the present application.

[0162] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. Although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present application, those skilled in the art can make various alternatives and modifications, which should fall within the scope of the present application.

Claims

1. An electronic device, comprising: The electronic device comprises a processor, a storage controller, a management controller and a hard disk backboard, the hard disk backboard is provided with a backboard controller, a plurality of hard disk connectors and a plurality of indicator lamps corresponding to the plurality of hard disk connectors, the backboard controller is connected with the plurality of hard disk connectors and the plurality of indicator lamps, and the management controller is connected with the backboard controller. Wherein: The hard disk backboard is a first type hard disk backboard, the processor is connected with the plurality of hard disk connectors through a first storage controller, the first storage controller has a first port and a second port, the management controller is configured to judge whether the hard disk backboard is connected with the first port or the second port of the first storage controller in response to a dial code instruction, if the plurality of hard disk connectors of the hard disk backboard are connected with the first port of the first storage controller, the backboard controller is controlled to set a dial code value of the hard disk backboard as a first dial code value, if the plurality of hard disk connectors of the hard disk backboard are connected with the second port of the first storage controller, the backboard controller is controlled to set the dial code value of the hard disk backboard as a second dial code value, and the dial code value of the hard disk backboard is used for lighting control of the indicator lamps on the hard disk backboard; or The hard disk backboard is a second type hard disk backboard, the processor is connected with the plurality of hard disk connectors through a second storage controller or directly connected with the plurality of hard disk connectors, the processor is configured to detect whether the processor is directly connected with the plurality of hard disk connectors on the hard disk backboard, if yes, a third dial code value is allocated to the backboard controller, the management controller is configured to set a dial code value of the hard disk backboard as a third dial code value or a fourth dial code value in response to a dial code instruction according to whether the backboard controller is allocated with the third dial code value, if the backboard controller is allocated with the third dial code value, the backboard controller is controlled to store the third dial code value as the dial code value of the hard disk backboard, otherwise, the backboard controller is controlled to store the fourth dial code value as the dial code value of the hard disk backboard.

2. The electronic device of claim 1, wherein, The number of hard disk backboards is multiple, the electronic device is further provided with a serial bus arbitrator and a serial bus hub, the processor and the management controller are connected to an upstream port of the serial bus hub through the serial bus arbitrator, a plurality of downstream ports of the serial bus hub are connected with the backboard controllers of the plurality of hard disk backboards respectively, and the serial bus arbitrator is configured to communicate and connect one of the processor and the management controller with the upstream port of the serial bus hub according to a preset arbitration strategy.

3. The electronic device of claim 2, wherein, The hard disk backboards connected with the first port of the first storage controller and the hard disk backboards connected with the second port of the first storage controller are alternately arranged on a case of the electronic device.

4. The electronic device of claim 3, wherein, The plurality of hard disk backboards are arranged in a plurality of positions arranged in sequence, the first storage controller is connected with the hard disk backboards in any odd position and any even position, the first storage controller further has a serial universal input / output interface, the serial universal input / output interface of the first storage controller is connected with the backboard controllers of the hard disk backboards in the odd position and the even position, the first port of the first storage controller is connected with the plurality of hard disk connectors of the hard disk backboards in the odd position, and the second port of the first storage controller is connected with the plurality of hard disk connectors of the hard disk backboards in the even position.

5. The electronic device of claim 1, wherein, The first storage controller is further connected with the backboard controller, and the first storage controller is further configured to send a lighting signal to the backboard controller in response to the lighting instruction, and the backboard controller is further configured to determine a target indicator light from the plurality of indicator lights based on the lighting signal and the dial value, and light up the target indicator light.

6. The electronic device of claim 1, wherein, The first port and the second port are serial advanced technology attachment interfaces.

7. The electronic device of claim 1, wherein, The first storage controller is a redundant array of independent disks controller.

8. The electronic device of claim 1, wherein, The hard disk backboard is a second type of hard disk backboard. The processor and the management controller are connected with the backboard controller on the hard disk backboard through a first bus link; and the processor is connected with the hard disk connector on the hard disk backboard through a second bus link. The processor is configured to obtain a slot and hard disk address mapping table from the backboard controller of the hard disk backboard through the first bus link when powered on, obtain hard disk identifiers from each hard disk connector of the hard disk backboard through the second bus link, obtain a hard disk identifier and second bus port mapping table, determine whether the hard disks on the hard disk backboard are directly connected with the processor based on the slot and hard disk address mapping table, the hard disk identifier and the second bus port mapping table, and a pre-stored hard disk address and second bus port mapping table, and if the hard disks are directly connected with the processor, send a third dial value to the backboard controller through the first bus link. The management controller is configured to execute the following on the backboard controller through the first bus link in response to the dial instruction: if the backboard controller is assigned the third dial value, control the backboard controller to store the third dial value as the dial value of the hard disk backboard, otherwise control the backboard controller to store a fourth dial value as the dial value of the hard disk backboard.

9. The electronic device of claim 8, wherein, The first bus link is an internal integrated circuit bus link, and the second bus link is a peripheral component interconnect express standard bus link.

10. The electronic device of claim 8, wherein, In the case that the hard disk connector on the hard disk backboard is directly connected with the processor, the plurality of second bus ports of the processor are connected with the plurality of hard disk connectors on the hard disk backboard.

11. The electronic device of claim 8, wherein, The processor is further configured to send a lighting signal to the backboard controller through the first bus link in response to the lighting instruction, and the backboard controller is further configured to determine a target indicator light from the plurality of indicator lights based on the lighting signal and the dial value, and light up the target indicator light.

12. The electronic device of claim 8, wherein, The second storage controller is further connected with the backboard controller, and the second storage controller is further configured to send a lighting signal to the backboard controller in response to the lighting instruction, and the backboard controller is further configured to determine a target indicator light from the plurality of indicator lights based on the lighting signal and the dial value, and light up the target indicator light.

13. The electronic device of claim 8, wherein, The number of hard disk backboards is a plurality, and the mainboard is further provided with a serial bus arbitrator and a serial bus hub, the processor and the management controller are connected to an upstream port of the serial bus hub through the serial bus arbitrator, a plurality of downstream ports of the serial bus hub are connected with the backboard controllers of the plurality of hard disk backboards, and the serial bus arbitrator is configured to communicate and connect one of the processor and the management controller with the upstream port of the serial bus hub according to a preset arbitration strategy.

14. The electronic device of claim 1, wherein, The second type of hard disk backboard is a hard disk backboard supporting a non-volatile memory express channel.

15. The electronic device of claim 1, wherein, The second storage controller is a three-mode redundant array of independent disks controller.

16. The electronic device of any of claims 1-15, wherein, The dial code is based on user-provided or generated during a pre-shipment system diagnostic procedure.

17. The electronic device of any of claims 1-15, wherein, The management controller is a baseboard management controller, and the backplane controller is a complex programmable logic device.

18. An electronic device, comprising: The electronic device includes a processor, a management controller, a first storage controller, a second storage controller, a serial bus hub, and a plurality of hard disk backplanes, each of which is provided with a backplane controller, a plurality of hard disk connectors, and a plurality of indicator lights corresponding to the plurality of hard disk connectors, and the processor and the management controller are connected to the backplane controllers of the plurality of hard disk backplanes through the serial bus hub; The plurality of hard disk backplanes includes a first type of hard disk backplane and a second type of hard disk backplane, the plurality of hard disk connectors on the first type of hard disk backplane are connected to the processor through the first storage controller, and the plurality of hard disk connectors on the second type of hard disk backplane are connected to the processor through the second storage controller or directly connected to the processor; The processor is configured to determine, for each hard disk backplane in the plurality of hard disk backplanes, whether the hard disk backplane is a first type of hard disk backplane or a second type of hard disk backplane, and if it is a first type of hard disk backplane, enter a first mode, and if it is a second type of hard disk backplane, enter a second mode; In the first mode, the management controller is configured to respond to the dial code instruction to determine whether the hard disk backplane is connected to a first port or a second port of the first storage controller, and if the plurality of hard disk connectors of the hard disk backplane are connected to the first port of the first storage controller, control the backplane controller to set the dial code value of the hard disk backplane to a first dial code value, and if the plurality of hard disk connectors of the hard disk backplane are connected to the second port of the first storage controller, control the backplane controller to set the dial code value of the hard disk backplane to a second dial code value; In the second mode, the processor is configured to determine whether the processor is directly connected to the plurality of hard disk connectors on the hard disk backplane, and if it is directly connected, assign a third dial code value to the backplane controller; The management controller is configured to respond to the dial code instruction to set the dial code value of the hard disk backplane to a third dial code value or a fourth dial code value based on whether the backplane controller is assigned the third dial code value, wherein if the backplane controller is assigned the third dial code value, control the backplane controller to store the third dial code value as the dial code value of the hard disk backplane, otherwise control the backplane controller to store the fourth dial code value as the dial code value of the hard disk backplane, and the dial code value of the hard disk backplane is used for lighting control of the indicator lights on the hard disk backplane.

19. A lighting-up control method characterized by comprising: The lighting control method is performed by the electronic device of any one of claims 1 to 17, and the lighting control method comprises: In the case where the hard disk backplane is a first type of hard disk backplane, the management controller responds to the dial code instruction to control the backplane controller to set the dial code value of the hard disk backplane to a first dial code value or a second dial code value based on whether the plurality of hard disk connectors of the hard disk backplane are connected to a first port or a second port of the first storage controller, and the dial code value of the hard disk backplane is used for lighting control of the indicator lights on the hard disk backplane. In the case that the hard disk backboard is the second type hard disk backboard, the processor detects whether the processor is directly connected with the plurality of hard disk connectors on the hard disk backboard, and if yes, assigns a third dial code value to the backboard controller; the management controller sets the dial code value of the hard disk backboard as the third dial code value or a fourth dial code value according to whether the backboard controller is assigned the third dial code value in response to the dial code instruction.

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