Bus data transmission method, device and chip

Abstract

The application provides a bus data transmission method, device and chip. The method comprises the following steps: obtaining at least one data request from a high-level extensible interface bus; determining at least one data packeting strategy in a preset data packeting strategy set based on data access information of the data request; performing data merging on data in at least one first data packet in a pre-created first queue based on the at least one data packeting strategy to obtain merged data; in response to the merged data meeting a preset transmission condition, determining at least one data unpacking strategy in a preset data unpacking strategy set based on data transmission information of the merged data; performing data unpacking processing on the merged data based on the at least one data unpacking strategy to obtain at least one second data packet; and transmitting the second data packet to a data storage area to be accessed through an on-chip network bus. Through the application, the utilization rate of bus bandwidth can be improved.

Description

Technical Field

[0001] This application relates to data processing technology, and more particularly to a bus data transmission method, apparatus, and chip. Background Technology

[0002] In modern high-performance computing chips (such as AI computing chips), a wide-bit-width Network on-chip (NOC) bus is used internally to achieve high-throughput data exchange. At the same time, to ensure compatibility with external modules or standard interfaces, the chip also integrates a narrower-bit-width bus, such as the Advanced Scalable Interface (AXI) bus.

[0003] When faced with complex application scenarios, the types, sources, and access targets of data requests transmitted on the bus are often different and dynamically changing. Therefore, when faced with data requests of varying types, sources, and access targets, the utilization rate of bus bandwidth during data transmission is not high. Summary of the Invention

[0004] This application provides a bus data transmission method, apparatus, and chip that can improve the utilization rate of bus bandwidth.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a bus data transmission method, including:

[0007] Acquire at least one data request from the Advanced Extensible Interface Bus, wherein the transmission bit width of the first data packet corresponding to the data request is the same as the bit width of the Advanced Extensible Interface Bus.

[0008] Based on the data access information of the data request, at least one data packet consolidation strategy is determined from a preset set of data packet consolidation strategies.

[0009] Based on the at least one data packet concatenation strategy, the data in at least one first data packet is merged in a pre-created first queue to obtain merged data;

[0010] In response to the merged data meeting preset transmission conditions, at least one data unpacking strategy is determined from a preset set of data unpacking strategies based on the data transmission information of the merged data.

[0011] The merged data is depacketized based on the at least one data depacketization strategy to obtain at least one second data packet, wherein the transmission bit width of the second data packet is the same as the bit width of the on-chip network bus.

[0012] The second data packet is transmitted to the data storage area to be accessed via the on-chip network bus.

[0013] This application provides a bus data transmission device, including:

[0014] A request acquisition module is used to acquire at least one data request from an Advanced Expansion Interface Bus (AEP), wherein the transmission bit width of the first data packet corresponding to the data request is the same as the bit width of the AEP.

[0015] The data packet selection module is used to determine at least one data packet selection strategy from a preset set of data packet selection strategies based on the data access information of the data request.

[0016] The data packet assembly execution module is used to merge data from at least one first data packet in a pre-created first queue based on the at least one data packet assembly strategy to obtain merged data.

[0017] The unpacking strategy selection module is used to determine at least one data unpacking strategy from a preset data unpacking strategy set based on the data transmission information of the merged data in response to the merged data meeting preset transmission conditions.

[0018] The data unpacking execution module is used to perform data unpacking processing on the merged data based on the at least one data unpacking strategy to obtain at least one second data packet, wherein the transmission bit width of the second data packet is the same as the bit width of the on-chip network bus.

[0019] The data transmission module is used to transmit the second data packet to the data storage area to be accessed via the on-chip network bus.

[0020] This application provides a chip that includes the bus data transmission device described above.

[0021] The embodiments of this application have the following beneficial effects: First, after obtaining at least one data request from the Advanced Scalable Interface Bus (ASME), at least one data packet assembly strategy can be determined from a preset data packet assembly strategy set based on the data access information of the data request. Then, based on the data packet assembly strategy, the data in the first data packet is merged to obtain merged data. Next, when the merged data meets the transmission conditions, at least one data unpacking strategy can be determined from a preset data unpacking strategy set based on the data transmission information of the merged data itself. The merged data is then unpacked based on the data unpacking strategy to obtain a second data packet suitable for transmission on the on-chip network bus. Finally, the second data packet is transmitted through the on-chip network bus. Through the above embodiments, it is equivalent to setting two adaptation mechanisms. The first adaptation mechanism dynamically selects the merging strategy based on the data request characteristics on the narrow bus (ASME), and the second adaptation mechanism dynamically selects the unpacking strategy based on the characteristics of the merged data to generate a data packet adapted to the backend wide bus (on-chip network bus). This allows the packet assembly and disassembly methods of this application embodiment to be adjusted according to the different characteristics of the data request (stream) (e.g., different access sources and access targets) during the data conversion process from a narrow-width bus to a wide-width bus. Therefore, when facing data requests with varying access sources and targets, involving data transmission across multiple buses, the utilization rate of bus bandwidth is effectively improved. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of the structure of a bus data transmission device provided in an embodiment of this application;

[0024] Figure 3 This is a schematic flowchart of a bus data transmission method provided in an embodiment of this application;

[0025] Figure 4 This is a first application scenario example diagram of the bus data transmission method provided in the embodiments of this application;

[0026] Figure 5 This is a second application scenario example diagram of the bus data transmission method provided in the embodiments of this application;

[0027] Figure 6 This is a third application scenario example diagram of the bus data transmission method provided in the embodiments of this application;

[0028] Figure 7 This is a fourth application scenario example diagram of the bus data transmission method provided in the embodiments of this application;

[0029] Figure 8 This is a fifth application scenario example diagram of the bus data transmission method provided in the embodiments of this application;

[0030] Figure 9 This is a sixth application scenario example diagram of the bus data transmission method provided in the embodiments of this application.

[0031] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In the following description, the term "some embodiments" refers to a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subset of all possible embodiments and may be combined with each other without conflict.

[0034] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0036] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0037] 1) Advanced Xtensible Interface (AXI): A high-performance, high-bandwidth bus protocol standard for communication between components within a chip. In this embodiment, it is the source bus for data transmission. The execution entity (chip) obtains data requests (first data packets) from the Host (accessed directly by the host computer through the CPU chip), Host DMA (accessed by the host computer through the Direct Memory Access Engine), or SDMA engine (System Direct Memory Access Engine) through the AXI interface. Its bit width is set to 512 bits.

[0038] 2) Network-on-Chip (NOC): A communication subsystem that connects multiple processing cores on a single chip, offering higher bandwidth and more flexible routing capabilities than traditional buses. In this embodiment, the target bus for data transmission is used. The second data packet, generated after packet assembly and disassembly, is transmitted through this bus to the data storage area to be accessed (e.g., DRAM, Dynamic Random Access Memory), with a bit width set to 4096 bits.

[0039] 3) Initiator ID: In bus protocols such as AXI, this is an identifier used to uniquely identify a transaction initiator (e.g., CPU core, DMA engine, etc.). In this embodiment, the Initiator ID is part of the metadata information and is used to identify whether the source of the data request is direct access from the Host, Host DMA access, or SDMA engine access. It is one of the bases for selecting the data packet concatenation strategy.

[0040] 4) Data Packing Strategy: This refers to the rules used to merge multiple smaller data requests into a larger logical data set. In this embodiment, the executing entity selects one or more strategies from a preset strategy set to guide the data merging process based on the access information of the data requests (e.g., request source, address, length, etc.). The strategies include contiguous address pattern strategy, configuration granularity packing strategy, aging timeout packing strategy, and packet tail packing strategy.

[0041] 5) Data Unpacking Strategy: This refers to the rules used to split a large, merged logical data into one or more data packets suitable for transmission on the on-chip network bus. In this embodiment, the executing entity determines which unpacking strategy to use, such as a cross-page splitting strategy or a non-cross-page splitting strategy, based on whether the attributes of the merged data (e.g., starting address, total length) cross the address boundary of the NOC.

[0042] 6) Content Addressable Memory (CAM): This is a type of memory that works by inputting data, then searching in parallel for identical data in the memory, and returning the address of the matching item. In this embodiment, CAM is used as a method to quickly determine a data packet concatenation strategy. By inputting a matching vector composed of data request information (e.g., request source, operation type) into CAM, the corresponding concatenation strategy identifier can be found in parallel, thereby improving the speed of strategy selection.

[0043] 7) Merged Data: This refers to a larger, contiguous memory access entity formed by logically aggregating one or more original AXI requests (first data packets) in the first queue according to the selected data packet assembly strategy. In this embodiment, this merged data is the input object for data unpacking processing.

[0044] 8) End-of-Packet Flag Information: This is a special signal or flag used to mark the end of a transaction stream or a logical data block during data transmission. In this embodiment, when a first data packet carries end-of-packet flag information, the end-of-packet reassembly strategy is triggered, immediately marking the first queue it belongs to as full and preparing for packet unpacking and transmission, even if its data volume has not reached the threshold of other strategies.

[0045] 9) Address Boundary Width: This refers to the block size used to divide the physical address space, and is the same as the physical bit width of the underlying hardware bus. In this embodiment, it is the same as the bit width of the NOC bus (4096 bits, i.e., 512 bytes), used to determine whether the start and end addresses of the merged data fall within the same 512-byte aligned address block (address space), thereby deciding whether to adopt a page-crossing or non-page-crossing unpacking strategy.

[0046] 10) Byte Enable Signal: In bus write operations, this signal specifies which bytes are valid data during the write operation. In this embodiment, for unaligned write operations, the generated second data packet contains byte enable mask information to ensure that the target memory area only updates valid bytes of data and does not incorrectly overwrite other data.

[0047] The related technologies have the following limitations:

[0048] Modern AI chips (such as GPUs, NPUs, TPUs, etc.) have highly parallelized internal structures to handle massive parallel computing tasks (such as matrix multiplication and convolution in neural networks).

[0049] The NOC (Network Controller) connects various functional units such as computing cores, memory controllers, and I / O interfaces, transmitting data for AI computing. In other words, the core of AI computing is data transfer. A wide-band NOC bus system ensures that data transfer between computing cores, or from on-chip cache to computing cores, can be performed in large blocks. The utilization rate of bus bandwidth is related to both the bus width and the data transfer width. With a fixed bus width, ensuring that the data transfer width is close to the bus width can effectively improve bandwidth utilization.

[0050] AXI is a standard bus protocol used to connect internal and external devices (such as the host CPU, external DRAM, and other chips), serving as the channel for data transmission between the chip and the outside world. However, the number of physical pins on a chip is limited and expensive. A 4096-bit interface requires a large number of pins, increasing the chip's packaging cost and PCB board complexity. Therefore, unlike NOC, AXI typically uses a smaller bit width (e.g., 128 / 256 / 512 bits).

[0051] In the actual operation of AI chips, the data transfer process on the bus is not limited to one type of access. At any given moment, depending on the different processing stages of the chip and the data transfer task requirements, any one of the following three scenarios, or a combination of scenario 1 and scenario 2, may exist on the bus:

[0052] Scenario 1, Host direct access: A single, small read / write request issued by the CPU for debugging or reading the status register.

[0053] Scenario 2, Host DMA access: The DMA engine sends out a large, contiguous stream of requests with extremely high throughput requirements in order to move model weights or input data.

[0054] Scenario 3, SDMA access: The SDMA engine inside the chip sends out a request stream with clear boundaries (with a beginning and an end) in order to perform cross-chip communication.

[0055] For example, in the mode of data interaction between the chip and the host computer, Scenario 1 and Scenario 2 may coexist. That is, the host CPU may initiate a small direct access request (corresponding to Scenario 1) to perform status monitoring, read registers, or issue control instructions; and the host may initiate a large, contiguous data request stream (corresponding to Scenario 2) through its DMA engine to provide model weights and input data for computation tasks. Scenario 1 and Scenario 2 may occur simultaneously, forming a hybrid access mode. Conversely, in the mode of multi-chip collaborative computing between chips, data interaction is mainly completed through the SDMA engine (corresponding to Scenario 3). In this mode, it does not occur simultaneously with direct access or DMA access from the host (i.e., Scenario 1 and Scenario 2).

[0056] The relevant technologies do not provide a method for flexible data transfer based on data requests to cope with the complex and changing scenarios that truly exist in AI chips (which may switch to one of scenario 1, scenario 2, and scenario 3 at any time depending on the different processing stages and data transfer task requirements of the chip). The applicant found that the relevant technologies lack a way to dynamically organize data transfer based on the size and type of the requested data, thus failing to cope with the complex scenarios of mixed access in AI chips. Specifically, when a request with a data transfer size (bit width) much smaller than the physical bit width of the AXI bus and the NOC bus, such as a small single access initiated by the host CPU to read a 32-bit or 64-bit status register, coexists with a large data transfer request that requires the DMA engine, the method of transferring one request per clock cycle leads to bandwidth waste. In order to transfer this only 64 bits of valid data, the entire 512-bit or 4096-bit bus is monopolized in one clock cycle, resulting in most of the bus's physical transmission capacity not being utilized in the clock cycle (4096 bits only occupy 64 bits of transmission), thus leading to low bus bandwidth utilization.

[0057] This application provides a bus data transmission method, apparatus, chip, computer-readable storage medium, and computer program product, which can effectively improve the utilization of bus bandwidth when facing data requests with varying access sources and access targets, involving data transmission across multiple buses.

[0058] See Figure 1 , Figure 1 This is a schematic diagram of the structure of the chip 100 provided in the embodiments of this application. Figure 1The chip 100 shown includes a bus data transmission device 110. The chip 100 is connected to an Advanced Scalable Interface (AMI) bus 200 and an on-chip network bus 300. The chip 100 is configured in a host computer and is connected to the host computer's CPU chip (or SDMA engine chip, DMA engine chip) via an AMI bus 200 power-on signal. It receives requests from the AMI bus 200. The bus data transmission device 110 executes a bus data transmission method provided in this embodiment, processing the first data packet corresponding to the data request to obtain a second data packet, and then sending the second data packet through the on-chip network bus 300.

[0059] In other embodiments, reference is made to Figure 2 The device provided in this application embodiment is implemented in hardware, such as... Figure 2 As shown, the bus data transmission device provided in this application embodiment can be a processor in the form of a hardware decoding processor, including the following hardware modules: a request acquisition module 1101, a packet assembly strategy selection module 1102, a data packet assembly execution module 1103, a packet disassembly strategy selection module 1104, a data packet disassembly execution module 1105, and a data transmission module 1106. It is programmed to execute a bus data transmission method provided in this application embodiment. For example, the processor in the form of a hardware decoding processor can employ one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0060] In a bus data transmission device provided in this application embodiment, the request acquisition module 1101 is used to acquire at least one data request from the Advanced Scalable Interface Bus. The request acquisition module 1101 is electrically connected to the packet concatenation strategy selection module 1102 and the data packet concatenation execution module 1103 respectively.

[0061] The packet consolidation strategy selection module 1102 is used to determine at least one data consolidation strategy from a preset data consolidation strategy set based on the data access information of the data request. The packet consolidation strategy selection module 1102 is electrically connected to the data consolidation execution module 1103.

[0062] The data packet assembly execution module 1103 is used to merge data in at least one first data packet in a pre-created first queue based on the at least one data packet assembly strategy to obtain merged data. The data packet assembly execution module 1103 is electrically connected to the packet unpacking strategy selection module 1104.

[0063] The unpacking strategy selection module 1104 is used to determine at least one data unpacking strategy from a preset data unpacking strategy set based on the data transmission information of the merged data in response to the merged data meeting the preset transmission conditions. The unpacking strategy selection module 1104 is electrically connected to the data unpacking execution module 1105.

[0064] The data unpacking execution module 1105 is used to perform data unpacking processing on the merged data based on the at least one data unpacking strategy to obtain at least one second data packet. The data unpacking execution module 1105 is electrically connected to the data transmission module 1106.

[0065] The data transmission module 1106 is used to transmit the second data packet to the data storage area to be accessed through the on-chip network bus, and the data transmission module 1106 is electrically connected to the on-chip network bus 300.

[0066] The present application will describe a method for bus data transmission based on exemplary applications and implementations of the chips provided in the embodiments of this application.

[0067] See Figure 3 , Figure 3 This is a flowchart illustrating the bus data transmission method provided in an embodiment of this application, which will be combined with... Figure 3 The steps shown are explained below. The execution subject in this application embodiment is a bus data transmission device provided in the above embodiments.

[0068] In step 101, at least one data request is obtained from the Advanced Extensible Interface Bus.

[0069] The transmission bit width of the first data packet corresponding to the data request is the same as the bit width of the advanced scalable interface bus.

[0070] It should be noted that a data request refers to a transaction conforming to the Advanced Extensible Interface (AXI) protocol standard. For a data request, both the data itself and metadata information need to be transmitted on the bus. For example, for a write request transmitted via the bus, the metadata information includes address, length, access target identifier, initiator identifier, etc., while the data itself is the actual data corresponding to this read or write operation. In this embodiment, the initiator identifier in the metadata information can be used to identify the request source (e.g., direct access from the host, host DMA access, or SDMA engine access). In this embodiment, the first data packet refers to the smallest data unit transmitted on the AXI bus that conforms to the AXI protocol definition. In this embodiment, it is assumed that the AXI bus width is set to 512 bits (i.e., 64 bytes), therefore the size of a first data packet is 512 bits. For an AXI request, both the data itself and metadata information are transmitted via the bus. The metadata information is transmitted in the first clock cycle, and each subsequent clock cycle can transmit one 512-bit first data packet, i.e., the data itself. The transmission bit width of the first data packet is the same as the bit width of the Advanced Scalable Interface (AXI) bus. This means that the output data unit size (4096 bits) of the first data packet in this embodiment of the application is completely matched with the physical data path width of the AXI bus. It also means that the data transmission outlet of the first data packet with a transmission bit width of 512 bits corresponding to the data request in this embodiment of the application is directly connected to a 512-bit physical bit width AXI bus inlet.

[0071] As an example, suppose the host CPU directly accesses the data and needs to read a single 4-byte value at address 0xC0001A4C. In this case, the host CPU connected to the chip will initiate a data request via the AXI bus. In this embodiment, obtaining at least one data request from the Advanced Scalable Interface bus specifically includes the AXI detecting a new transaction on the AXI read address channel and latching metadata information, including: a write address of 0xC0001A4C, write length information indicating that 4 bytes need to be read, and a specific initiator identifier (ID), where ID 01 is predefined as representing direct access by the host CPU.

[0072] In step 102, based on the data access information of the data request, at least one data packetization strategy is determined from a preset set of data packetization strategies.

[0073] It should be noted that, in this embodiment, the data access information refers to the information parsed from the data request obtained in step 101, including at least: the request source (e.g., identifying whether it is a Host access, HostDMA engine, or SDMA engine by parsing the initiator identifier), the operation type (e.g., parsing the operation identifier to determine whether the data request is a read request or a write request), the access address (i.e., the starting address in the metadata information), and the data length. The preset data packet concatenation strategy set refers to a pre-configured set of packet concatenation rules. In this embodiment, the data packet concatenation strategy set includes at least the continuous address mode strategy (i.e., used to merge requests with consecutive addresses), the configuration granularity concatenation strategy (i.e., used to merge requests until a preset total data volume is reached), the aging timeout concatenation strategy (i.e., used to set a maximum waiting time for low-frequency requests to ensure latency), and the packet tail concatenation strategy (i.e., used to identify the end of the transaction flow and immediately package the data). The data concatenation strategy is one or more specific strategies selected from the data concatenation strategy set based on the current data access information.

[0074] As an example, continuing from step 101, after receiving a 4-byte read request from the Host CPU, the data access information is parsed to identify that the request originates from direct access by the Host. A characteristic of direct access by the Host is a small data volume. Based on this, an aging timeout packet consolidation strategy is selected from the preset data packet consolidation strategy set and applied.

[0075] In some embodiments, step 102 can be implemented as follows: combining the first key fields (including request source, operation type, etc.) of the data access information of the data request into a matching vector; inputting the matching vector into the content addressing memory for parallel lookup; and, when the content addressing memory successfully matches, obtaining one or more pre-encoded packet-combining strategy identifiers corresponding to the data access information. Utilizing the parallel lookup characteristics of CAM (Content Addressing Memory), the entire strategy selection process can be completed in fewer clock cycles, improving the speed of the strategy selection process.

[0076] In other embodiments, step 102 can be implemented as follows: for each strategy in the preset data packet assembly strategy set, configure one or more associated activation conditions and priority values; when a data request is received, determine whether the activation conditions of each strategy are satisfied by the current data access information; and, if the activation conditions of multiple strategies are satisfied simultaneously, select one or more strategies with priority values ​​greater than a first threshold as the determined data packet assembly strategy. This approach is highly flexible, and the priority relationship of strategies in different scenarios can be adjusted through software programming.

[0077] In other embodiments, step 102 can be implemented as follows: parsing the data request to obtain the request source and operation type; determining a first keyword based on the request source and operation type; comparing the first keyword with a second keyword corresponding to each data merging strategy in the preset data merging strategy set; and, in response to the comparison result indicating that the first keyword and the second keyword are the same, determining at least one data merging strategy associated with the second keyword from the data merging strategy set. Here, by parsing the data request to obtain the request source and operation type, and determining the first keyword based on this, and then comparing the first keyword with the second keyword corresponding to the data merging strategy, the most suitable data merging strategy is automatically determined according to the specific characteristics of the data request (request source and operation type), improving the accuracy of merging strategy selection.

[0078] For example, before an AI inference task begins, the Host CPU configures a DMA engine (request source) to read a 2MB model weight file from external DRAM. After the DMA engine starts, it generates a series of consecutive AXI read requests. The first data request arrives at the chip's AXI bus interface. The metadata information of this request is captured and parsed. By parsing the initiator identifier ARID in the request header, for example, ARID 0b1010, the initiator of the request is identified as the Host DMA engine (request source) according to the preset ID mapping relationship. Since the request appears on the AXI read address channel, it is determined to be a read request (operation type). The two pieces of information are combined to generate a temporary keyword for this query, i.e., the first keyword, for example, 0b1010-01. Then, based on the first keyword 0b1010-01, the preset keyword-policy association table is queried in parallel.

[0079] The comparison process is as follows: It compares with the second keyword (0b1010-00) of sequence number 1, and the result is a mismatch. It then compares with the second keyword (0b1010-01) of sequence number 2, and the result is a complete match, and so on, until all matches are completed, at which point a completely matching second keyword is obtained. Since a completely matching second keyword is found in sequence number 2, the data packet concatenation strategy associated with the second keyword is latched. The final set of data packet concatenation strategies determined for this DMA read request stream is: contiguous address mode strategy, configuration granularity concatenation strategy, and aging timeout concatenation strategy.

[0080] In step 103, based on the at least one data packet concatenation strategy, the data in at least one first data packet is merged in a pre-created first queue to obtain merged data.

[0081] It should be noted that the first queue refers to one of multiple cache queues used to aggregate AXI requests. In this embodiment, the first queue is a stateful logical container, and each first queue corresponds to a set of metadata information to describe the logical data currently being constructed. For example, the metadata information includes the starting address of the first queue, the cumulative total length, the request source type, etc. The merged data refers to a larger, continuous memory access entity formed by logically aggregating multiple original AXI requests in the first queue after processing by one or more packet-merging strategies; that is, the complete logical data of the first queue.

[0082] As an example, based on the aging timeout packet consolidation strategy, a 4-byte read request is sent to a first queue dedicated to host access (e.g., read queue 0). At this point, data merging begins: the metadata information of read queue 0 is updated, the starting address of the logical data is 0xC0001A4C, and the cumulative total length is 4 bytes. Since no new requests arrive in a short period, read queue 0 does not continue to grow. Therefore, in this scenario, the final merged data is a single logical data entry containing only this one 4-byte read request.

[0083] In some embodiments, step 103 can be implemented as follows: encapsulate the first data packet corresponding to each arriving data request into a request descriptor containing all metadata and store it in the descriptor memory; in the first queue, only the pointers to the first request descriptor and the last request descriptor pointing to the current logical data are stored; when merging the first data packet corresponding to a new request, update the pointer of the last request descriptor based on the descriptor of the new request, until the first data packets corresponding to all data requests are merged.

[0084] In other embodiments, step 103 can be implemented as follows: for each first data packet, perform the following processing: obtain the current state information of the first queue; based on the current state information of the first queue and the at least one data packet concatenation strategy, merge the data in the first data packet in the first queue; in response to the fact that the data in each first data packet has been processed, use the data in the first queue as the merged data. Here, by obtaining the current state information of the first queue for each first data packet and merging the data based on the data packet concatenation strategy, this merging method based on the current state of the queue in this embodiment of the application ensures that each step of the data merging follows a preset strategy, thereby ensuring the accuracy of the final merged data.

[0085] It should be noted that the current status information of the first queue in this embodiment refers to the metadata information of the first queue.

[0086] Specifically, based on the current state information of the first queue and the at least one data packet merging strategy, the data in the first data packet is merged in the first queue, which can be achieved through one or more of the following methods one to four:

[0087] Method 1: The current status information includes the queue start address of the first queue, the total length of data in the first queue, and the capacity status of the first queue;

[0088] When the data packet concatenation strategy is an address-contiguous concatenation strategy, the starting address of the data in the first data packet is obtained; based on the total length of the data in the first data packet and the starting address of the first queue, the ending address of the first queue is determined; in response to the starting address of the data in the first data packet being contiguous with the ending address of the first queue, the data in the first data packet is merged into the first queue; in response to the starting address of the data in the first data packet being discontiguous with the ending address of the first queue, the data in the first data packet is merged into an empty second queue, wherein the second queue is used as the first queue for the next merging of data in the first data packet when the capacity state of the first queue is full. Here, by determining whether the starting address of the data in the first data packet is contiguous with the ending address of the first queue, it is achieved that only data requests with contiguous addresses are merged. This can effectively aggregate continuous data streams into a large logical data, while ensuring the isolation between different data streams and the address continuity of the merged data by enabling a new second queue when the addresses are discontiguous.

[0089] For example, in an AI training task, the host CPU needs to write a batch of training sample data of 10KB (10240 bytes) to the DRAM of the AI ​​chip through the DMA engine (request source). The first 8KB (8192 bytes) of data is contiguous in address, but the last 2KB (2048 bytes) of data is stored in a different non-contiguous address due to memory fragmentation. The DMA engine is configured to generate an AXI write request of 256 bytes each time. During a gap in the host DMA transfer, an internal SDMA engine (another request source) also initiates a cross-chip write operation. The write operation has a packet tail identifier, the preset packet granularity threshold is 4096 bytes, and the preset aging timeout is 500 clock cycles. Initially, all first queues used for data merging are in an idle state.

[0090] For Method 1: The Host DMA engine begins transferring the first 8KB of continuous data. The first 256-byte write request (data request) arrives, with a starting address (the starting address of the data in the first data packet) of 0xA0000000. Since all queues are empty, the request is assigned to a new first queue, i.e., write queue 1. The current status information of write queue 1 is initialized as follows: queue starting address 0xA0000000, total data length 256 bytes, and capacity status "collecting". The Host DMA engine quickly issues a second write request, starting at address 0xA0000100 (i.e., 0xA00000000 plus 256). At this point, the control logic begins processing based on the current status information of write queue 1 and the address contiguous packet concatenation strategy. First, based on the queue starting address of write queue 1 (0xA0000000) and the total data length (256 bytes), the queue ending address is determined to be 0xA0000100. Next, it checks if the starting address of the new request (0xA0000100) is contiguous with the end address of write queue 1 (0xA0000100). The result is that they are contiguous. Therefore, in response to the address contiguousness, this new 256 bytes of data is merged into the first queue (write queue 1). The current status information of write queue 1 is updated to: the total length of the data is 512 bytes, and the queue end address is updated to 0xA0000200. The above process will continue to repeat. The starting addresses of the 3rd, 4th, and up to the 32nd requests issued by the DMA engine are all contiguous with the end addresses of the merged data in write queue 1. Therefore, all requests will be merged into write queue 1. The total length of the data in write queue 1 continues to accumulate, growing from 256 bytes to 8192 bytes. After completing the first 8KB of transfer, the DMA engine now needs to send the last 2KB of data, which starts at address 0xB000C000 and is not contiguous with the previous part. When a new request starting at address 0xB000C000 arrives, the control logic performs another check. At this point, the end address of write queue 1 is 0xA0000000, which, when added to 8192, equals 0xA0002000. The starting address of the new request (0xB000C000) is not contiguous with the end address of write queue 1 (0xA0002000). Due to this address discontinuity, the data from this new request will not be merged into write queue 1. Instead, the control logic selects an empty second queue, write queue 2, and merges the 256 bytes of data starting at address 0xB000C000 into this empty second queue (write queue 2). The current status information of write queue 2 is initialized. In this way, the two discontinuous data streams are isolated in two different queues, ensuring that the addresses of the merged data within each queue are strictly contiguous.

[0091] Method 2: The current status information includes the total length of data in the first queue and the capacity status of the first queue;

[0092] When the data packet concatenation strategy is a configured granularity concatenation strategy, a preset concatenation granularity threshold and the total length of data in the first data packet are obtained. The total length of data in the first data packet and the total length of data in the first data packet are accumulated to obtain the total length of data to be merged. The total length of data to be merged is compared with the preset concatenation granularity threshold to obtain a comparison result. In response to the comparison result indicating that the total length of data to be merged is less than or equal to the preset concatenation granularity threshold, the data in the first data packet is merged into the first queue. In response to the comparison result indicating that the total length of data to be merged is greater than the preset concatenation granularity threshold, the data in the first data packet is merged into an empty second queue. The second queue is used as the first queue for the next merging of data in the first data packet when the capacity of the first queue is full. Here, by comparing the total length of data to be merged with the preset concatenation granularity threshold, data merging with the configured concatenation granularity as the target is realized. This ensures that the generated merged data reaches or is close to an optimal size, thereby maximizing the data load capacity of the subsequently generated second data packet, improving the utilization rate of the on-chip network bus transmission bandwidth, and avoiding the waste of overhead caused by the transmission packet being too small.

[0093] For example, if the queue is continuously merging 256-byte write requests from Host DMA with consecutive addresses, the preset packet granularity threshold is 4096 bytes.

[0094] For Method 2: The first 256-byte request enters write queue 1, and the current status information shows a total data length of 256 bytes. When the second request arrives, the control logic processes it according to the configured granularity packet assembly strategy. The total length of the data in write queue 1 (256 bytes) and the total length of the new request's data (256 bytes) are obtained and summed, resulting in a total length of 512 bytes for the data to be merged. This total length (512 bytes) is compared with a preset packet assembly granularity threshold (4096 bytes). The comparison result shows that 512 is less than 4096. Therefore, in response to the total length of the data to be merged being less than or equal to the threshold, the data from the second request is merged into the first queue (write queue 1). The total length of the data in write queue 1 is updated to 512 bytes. This merging process continues. When the 15th request is merged, the total length of the data in write queue 1 reaches 15 times 256, which is 3840 bytes. At this point, the 16th request (256 bytes) arrives. The control logic recalculates the total length of the data to be merged: 3840 plus 256 equals 4096 bytes. The comparison shows that 4096 equals 4096. Therefore, the data from the 16th request is still merged into the first queue (write queue 1). The total length of the data in write queue 1 is updated to exactly 4096 bytes. At this point, the total length of the data in write queue 1 reaches the preset packet granularity threshold, and the capacity status of write queue 1 will be updated to full queue. Write queue 1 is scheduled to send data because it is full, then cleared and data reception resumes. If requests 17 to 31 are currently being merged, and the current total length of the data is 15 multiplied by 256, which is 3840 bytes, and if the DMA suddenly sends a large request of 1024 bytes, the control logic calculates the total length of the data to be merged: 3840 plus 1024 equals 4864 bytes. The total length of the data to be merged (4864 bytes) is compared with the preset packet granularity threshold (4096 bytes). The comparison shows that 4864 is greater than 4096. Since the total length of the data to be merged exceeds the threshold, this large request of 1024 bytes will not be merged into write queue 1, even if the addresses are contiguous. This request will be merged into an empty second queue (e.g., write queue 3). This avoids generating an unexpectedly large logical data set, which could negatively impact downstream buffer management or network scheduling. Write queue 1 continues to wait for the next (appropriately sized) request because its current length has not reached the threshold.

[0095] Method 3: The current status information includes the waiting time of the first queue and the capacity status of the first queue; the waiting time of the first queue is the time between the first moment and the second moment, the first moment is the moment when the data in the previous first data packet was merged into the first queue, and the second moment is the moment when the data in the first data packet is merged;

[0096] When the data packet consolidation strategy is an aging timeout consolidation strategy, a preset aging timeout duration is obtained; the waiting time of the first queue is compared with the preset aging timeout duration to obtain a comparison result; in response to the comparison result indicating that the waiting time of the first queue is less than or equal to the preset aging timeout duration, the data in the first data packet is merged into the first queue; in response to the comparison result indicating that the waiting time of the first queue is greater than the preset aging timeout duration, the data in the first data packet is merged into an empty second queue, wherein the second queue is used as the first queue for the next merging of data in the first data packet when the capacity state of the first queue is full. Here, by comparing the waiting time of the first queue with the preset aging timeout duration, a time constraint is introduced into the data merging process. This ensures that even when the data request volume is small, data already in the queue will not wait indefinitely, avoiding excessive delays caused by packet consolidation.

[0097] For example, if during a Host DMA transfer, the DMA data stream is suddenly interrupted due to a Host CPU scheduling issue. Before the interruption, write queue 2 (the queue used to process the second segment of discontinuous data) had already merged three 256-byte requests, and the total length of data in the current status information is 768 bytes.

[0098] For Method 3: The moment when the third request is merged into write queue 2 is considered the first moment. The control logic resets an internal aging counter for write queue 2. If no new data requests arrive in write queue 2, the aging counter continues to increment, recording the waiting time from the first moment to the present (the second moment). Write queue 2 remains in a waiting state because neither the address contiguous condition (no new requests to judge) nor the configuration granularity condition (768 bytes less than 4096 bytes) is met. When the value of the aging counter, i.e., the waiting time of the first queue, reaches the preset aging timeout duration (500 clock cycles), the aging timeout packet consolidation strategy is triggered. Assume a new write request arrives and needs to be merged. Before processing this new request, the status of the existing queues is checked. If the waiting time of write queue 2 is greater than or equal to the preset aging timeout duration, the new request will not be merged into write queue 2, and the capacity status of write queue 2 will be updated to full queue status.

[0099] Understandably, based on methods one through three above, the grouping strategy of method four can be combined for grouping:

[0100] Method 4: In response to the end-of-packet identifier information carried by the first data packet, the data in the first data packet is merged into the first queue, and the capacity status of the first queue is updated to full queue status. Here, by updating the capacity status of the first queue to full queue status in response to the end-of-packet identifier information carried by the first data packet, it is ensured that multiple data requests that logically belong to the same transaction can be completely merged together.

[0101] For example, during the interruption of the Host DMA data stream, the chip's internal SDMA engine initiates a cross-chip write operation, transferring a total of 512 bytes, divided into two 256-byte AXI write requests. Crucially, the second (and last) request carries a packet tail identifier. The first 256-byte SDMA write request arrives and is allocated to a dedicated first queue, write queue 5. The data is merged into write queue 5, bringing the total data length to 256 bytes. The second 256-byte SDMA write request arrives. The control logic detects that this first data packet carries a packet tail identifier. At this point, the packet tail concatenation strategy is triggered; in response to the detection of the packet tail identifier, this 256-byte data is merged into the first queue (write queue 5). The total length of data in write queue 5 is updated to 512 bytes. Simultaneously, the capacity status of write queue 5 is immediately updated to full queue. Although the total length of the data in write queue 5 (512 bytes) did not reach the threshold of the configured granular packet concatenation strategy (4096 bytes), nor was it far from the aging timeout period, the preset transmission conditions were forcibly triggered simply because a request with a packet tail identifier was received. This allowed the complete 512-byte SDMA transaction in write queue 5 to be sent as a whole. If subsequent requests from the same SDMA engine are received, they will be placed in a new queue.

[0102] In this embodiment of the invention, the capacity status of the first queue can be updated in real time. Specifically, in response to the data in the first queue meeting the dequeue conditions, the capacity status of the first queue is updated to a full queue state. The dequeue conditions include any one of the following: the total length of the data in the first queue reaches a preset packet-merging granularity threshold, or the waiting time of the first queue reaches a preset aging timeout period. Here, by updating the capacity status of the first queue to a full queue state when the total length of the data in the first queue reaches the packet-merging granularity threshold or the waiting time reaches the aging timeout period, the completion status of different packet-merging strategies is normalized into a unified full queue state, simplifying the logic for determining queue readiness in subsequent steps and improving the efficiency of the packet unpacking process.

[0103] In step 104, in response to the merged data meeting preset transmission conditions, at least one data unpacking strategy is determined from a preset set of data unpacking strategies based on the data transmission information of the merged data.

[0104] It should be noted that the preset transmission conditions refer to the conditions that trigger the transmission of complete logical data constructed in the first queue. In this embodiment, the preset transmission conditions may be that the cumulative length of the logical data reaches the threshold set by the configuration granularity packet assembly strategy, the time the queue waits for a new request reaches the threshold set by the aging timeout packet assembly strategy, or the packet tail identifier defined by the packet tail assembly strategy is received. Data transmission information refers to the attributes of the logical data that meet the transmission conditions, including the start address and total length. The preset data splitting strategy set is a rule base used to decompose logical data into NOC transmission packets, including cross-page splitting strategies (used to handle cases that cross NOC data block boundaries) and non-cross-page splitting strategies (used to handle cases where the start or end addresses are not aligned).

[0105] It is understandable that the reason for requiring pre-set transmission conditions to de-packetize is that packet assembly is essentially a process of continuously accumulating data until certain conditions are triggered. If every AXI request is immediately de-packetized and sent, the NOC bus utilization cannot be effectively improved. In this embodiment, packet assembly is only performed in response to pre-set transmission conditions, ensuring that requests in the queue are accumulated to an optimal point where they are large enough (meeting granularity), long enough (meeting timeout), or logically complete (meeting packet tail) before being sent to the next stage for de-packetizing.

[0106] As an example, small logical data in read queue 0, due to a long period without new requests, causes the aging counter associated with read queue 0 to reach a preset aging threshold (e.g., 100 clock cycles). At this point, the preset transmission condition of aging timeout is met, and the logical data is sent to the next stage for unpacking.

[0107] In some embodiments, step 104 can be implemented as follows: a mapping table is pre-configured, the index of which is composed of the attributes of the merged data (including request source, operation type, alignment status, etc.), and the index of the mapping table is the corresponding packet splitting strategy identifier. After the transmission conditions are met, the attributes of the merged data are extracted as the index to query the mapping table; and the packet splitting strategy identifier obtained by querying the mapping table is used for subsequent packet splitting processing.

[0108] In other embodiments, the preset transmission condition is that the capacity state of the first queue is a full queue state; step 104 can be implemented as follows: obtain the address boundary bit width of the on-chip network bus; determine the first address space to which the data start address of the merged data belongs based on the data start address of the merged data and the address boundary bit width; determine the data end address of the merged data based on the data start address of the merged data and the total data length of the merged data; determine the second address space to which the data end address of the first data packet belongs based on the data end address of the merged data and the address boundary bit width; determine at least one data splitting strategy from a preset set of data splitting strategies based on the judgment result of whether the first address space and the second address space are the same address space. Here, by judging whether the data start address and data end address of the merged data belong to the same address space, it is identified whether the merged data crosses the address boundary of the on-chip network bus. This provides a decisive basis for subsequently selecting the correct data splitting strategy, ensuring that the data is split and processed without omission regardless of whether the data crosses the address boundary, thus guaranteeing the integrity of data transmission.

[0109] For example, after the merge is complete, the metadata information for write queue 1 is updated: the total length of the data becomes 4096 bytes, and the starting address of the data is 0xA00001A2. Adding 4096 bytes to the starting address 0xA00001A2 gives the ending address 0xA00011A1 (Note: the data range is from 0xA00001A2 to 0xA00011A1, a total of 4096 bytes). For the NOC bus, which has a width of 4096 bits (512 bytes), the corresponding physical blocks start from 0x00000000, with each block (address space) consisting of 4096 bits (512 bytes). Then, the physical block between the two addresses 0xA00001A2 (the first address space) and 0xA0000000 (the second address space) can be determined, and the physical block between the two addresses 0xA00011A1 (the third address space) and 0xA0001000 (the fourth address space) can be determined. Based on the comparison between the first and second address spaces, the unpacking strategy can be determined. If they are in the same address space, a non-page-crossing unpacking strategy can be used, and if they are not in the same address space, a page-crossing unpacking strategy can be used.

[0110] In step 105, the merged data is depacketized based on the at least one data depacketization strategy to obtain at least one second data packet, wherein the transmission bit width of the second data packet is the same as the bit width of the on-chip network bus.

[0111] It should be noted that the second data packet refers to the transmission packet generated after unpacking and processing, conforming to the Network on-Chip (NOC) protocol. In this embodiment, the NOC bus width is 4096 bits (512 bytes), therefore the data payload size of each second data packet is 4096 bits. The transmission width of the second data packet is the same as the width of the NOC bus, meaning that the output data unit size (4096 bits) of the second data packet at the hardware level in this embodiment perfectly matches the physical data path width of the NOC bus.

[0112] As an example, data splitting is performed based on a non-page-splitting strategy. Since the merged data is only 4 bytes and not aligned, the processing involves generating a second data packet (i.e., a NOC read request packet) based on the merged data. The destination address of the second data packet is set to the starting address of a 4096-bit aligned address block containing the original address 0xC0001A4C, i.e., 0xC0001A00. The intent of the NOC request is to read the entire 512-byte data block starting at 0xC0001A00. Simultaneously, the precise information of the original request (starting address 0xC0001A4C, length 4 bytes) is temporarily stored for accurate retrieval when subsequent data is returned.

[0113] In some embodiments, step 105 can be implemented as follows: In response to the judgment result indicating that the first address space and the second address space are the same address space, and the data unpacking strategy is a non-cross-page unpacking strategy, the merged data is encapsulated into a second data packet; In response to the judgment result indicating that the first address space and the second address space are not the same address space, and the data unpacking strategy is a cross-page unpacking strategy, a preset unpacking granularity threshold is obtained; Based on the data starting address of the merged data and the address at the connection between the first address space and the third address space, the merged data is segmented to obtain the data in the first data block; Based on the total length of the merged data and the total length of the data in the first data block, the remaining data length of the merged data is determined. Starting from the beginning address of the third address space, the remaining data corresponding to the remaining data length is sequentially segmented based on the unpacking granularity threshold to obtain data in at least one intermediate data block. Based on the beginning address of the second address space and the end address of the merged data, the remaining data corresponding to the remaining data length is segmented to obtain data in the tail data block. The data in the first data block, the data in the at least one intermediate data block, and the data in the tail data block are each encapsulated into a second data packet. Here, by segmenting the merged data across boundaries into a first data block, at least one intermediate data block, and a tail data block, and encapsulating them into second data packets respectively, it is ensured that even merged data with arbitrary starting addresses and lengths can be seamlessly converted into standard data packets that meet the transmission requirements of the on-chip network bus. Furthermore, by making the total length of the data in the intermediate data blocks equal to the unpacking granularity threshold, the data ratio during cross-page transmission is maximized, improving the bus transmission efficiency.

[0114] For example, the on-chip network bus has a width of 4096 bits (512 bytes). The address boundary width is also 512 bytes. The address space is divided into contiguous 512-byte blocks, for example: address space 0: 0x00000000 to 0x000001FF; address space 1: 0x00000200 to 0x000003FF; address space 2: 0x00000400 to 0x000005FF; and so on. The default unpacking granularity threshold is 512 bytes (equal to the NOC's width).

[0115] For example, in a merged data set starting at address 0xA00001A2 with a total length of 4096 bytes, a cross-page splitting strategy is used because it crosses address boundaries. Assume the preset splitting granularity threshold is 512 bytes. First, based on the starting address 0xA00001A2 of the merged data and the ending address 0xA00001FF of its first address space, the merged data is segmented to obtain a first data block with a total length of 94 bytes. Next, based on the total length of the merged data (4096 bytes) and the total length of the first data block (94 bytes), the remaining data length of the merged data is determined to be 4002 bytes. Then, based on a 512-byte unpacking granularity threshold, starting from the starting address 0xA0000200 of the third address space, the remaining 4002 bytes are segmented sequentially to obtain seven intermediate data blocks, each with a total length of 512 bytes. Finally, based on the starting address 0xA0001000 of the second address space and the ending address 0xA00011A1 of the merged data, the remaining data is segmented to obtain a tail data block with a total length of 418 bytes. Ultimately, the 94-byte initial data block, seven 512-byte intermediate data blocks, and the 418-byte tail data block are encapsulated into a total of nine second data packets for transmission. Understandably, the intermediate data blocks are fully loaded, improving bus transmission efficiency.

[0116] In some embodiments, if the second address space and the first address space are contiguous address spaces, the merged data is segmented based on the address connection points of the second address space and the first address space to obtain the first data block and the tail data block.

[0117] Understandably, the starting and ending addresses of the merged data belong to contiguous address spaces, and there will be no multiple intermediate data blocks. Therefore, it is directly divided into a header data block and a tail data block.

[0118] In step 106, the second data packet is transmitted to the data storage area to be accessed via the on-chip network bus.

[0119] It should be noted that the data storage area to be accessed refers to the target storage area in the NOC network that serves as the endpoint for this data access. In this embodiment, the target storage area can be DRAM connected externally to the chip (managed by the on-chip DRAM controller), or it can be on-chip shared high-speed SRAM, or, in a distributed computing scenario, DRAM on another AI chip connected via the NOC.

[0120] For example, suppose an 8192-byte logical data packet, after being depacketized, results in 16 consecutive second data packets. The NOC transmitting interface then sequentially transmits these 16 second data packets into the NOC bus network. The NOC router routes each packet to the corresponding DRAM controller in the address space based on the destination address in the packet header (starting from 0xB0008000). The DRAM controller is the data storage area to be accessed. Upon receiving these NOC requests, the DRAM controller writes the corresponding data into the DRAM.

[0121] The following will describe exemplary applications of the embodiments of this application in real-world application scenarios.

[0122] The bus data transmission method proposed in this application can adapt to the dual-bus transmission requirements in multiple scenarios. For example, with a fixed NOC bit width (4096 bits) and AXI bit width (512 bits), it provides a flexible method for assembling and disassembling read and write requests for the three main scenarios of Host direct access, Host DMA access, and SDMA access, effectively improving bus utilization. Specific application scenarios one through three are given below.

[0123] It should be noted that for a 4096-bit bus, each physical block is 512 bytes in size. This is represented as 0x200 in hexadecimal. The entire memory address space is then divided into contiguous, non-overlapping 512-byte physical blocks, for example, 0x00000000 to 0x000001FF, which are bytes 0 to 511.

[0124] Scenario 1: Direct access by the host, reading / writing data.

[0125] (1) Obtain at least one data request from the AXI bus. Specifically, obtain a read data request initiated by the Host CPU. The data request corresponds to a first data packet, and the transmission bit width of the first data packet is the same as the bit width of the AXI bus. The data access information of the data request includes: the data start address is 0xC0001A4C, and the total data length is 4 bytes.

[0126] (2) Based on the data access information of the data request, determine at least one data concatenation strategy from the preset data concatenation strategy set. The data concatenation strategy associated with the first keyword is determined to be the address contiguous concatenation strategy, the configuration granularity concatenation strategy, and the aging timeout concatenation strategy.

[0127] (3) Based on at least one data packet concatenation strategy, the data in at least one first data packet is merged in a pre-created first queue to obtain merged data.

[0128] Reference Figure 4 Processing is based on a configuration-granularity packet assembly strategy: Figure 4 This demonstrates the process of data accumulation in a queue (or congestion queue) based on configured granularity. The queue is logically divided into multiple 4096-bit blocks (e.g., 4096-bit_0, 4096-bit_1, etc.), each block consisting of multiple 512-bit data packets received from the AXI bus. The packet assembly logic continuously fills the queue with 512-bit data packets until the configured packet assembly granularity threshold is reached.

[0129] Reference Figure 5 The process is handled based on the aging timeout repackaging strategy: Figure 5 It demonstrates how data transmission can be triggered when there is insufficient data but the waiting time is too long. Figure 5 The aging counter (age_cnt) below keeps counting. When the aging counter count reaches the preset threshold N, the timeout condition is triggered.

[0130] (4) In response to the merged data meeting the preset transmission conditions, the capacity status of the first queue is updated to full queue status (i.e., ready status). In this embodiment, since there are no new requests in a short period of time, the preset transmission condition is that the waiting time of the first queue reaches the preset aging timeout period. At this time, the data in the first queue is the merged data, and the data transmission information is: data start address 0xC0001A4C, total data length 4 bytes.

[0131] (5) Based on the data transmission information of the merged data, at least one data splitting strategy is determined from the preset data splitting strategy set. It is determined that the data is located within the same address space, therefore the data splitting strategy is determined to be a non-page-crossing splitting strategy.

[0132] (6) Perform data unpacking processing on the merged data based on at least one data unpacking strategy to obtain at least one second data packet. If the start and end addresses of the merged data are not in the same address space, then refer to... Figure 6 Cross-page unpacking will be performed. Figure 6 The upper part displays the merged data (512 bits _0) to be processed in the queue. Figure 6 The lower half shows the unpacking process. The original data crossed the boundary at address 4096*(N+1), so it was split into two second data packets. Figure 6 The 512-bit frames in both second data packets contain both regions without shading (invalid data) and regions with shading (valid data). This means that the starting address of the merged 512-bit data block in the queue is not 4096-bit aligned. Therefore, in the first second data packet, only the portion from the starting address to the junction of the first and second address spaces is valid data; the rest is invalid padding data.

[0133] (7) Transmit the second data packet (generated after the timeout of scenario one) to the data storage area (DRAM) to be accessed via the NOC bus.

[0134] Scenario 2: Host DMA access scenario, specifically reading / writing data.

[0135] (1) Obtain a series of consecutive data requests from the AXI bus. The data access information for the first data request is: operation type is write, data start address is 0xA00001A2, and total data length is 256 bytes.

[0136] (2) Based on the data access information of the data request, the data packet concatenation strategy is determined to be the address contiguous packet concatenation strategy and the configuration granularity packet concatenation strategy.

[0137] (3) Based on the determined data packetization strategy, data is merged in the pre-created first queue.

[0138] (4) When the total length of the data in the first queue reaches the preset packet granularity threshold of 2048 bytes, the merging is completed. The data transmission information of the merged data is as follows: data start address 0xA00001A2, total data length 2048 bytes.

[0139] (5) Based on the data transmission information of the merged data, the data unpacking strategy is determined to be a cross-page unpacking strategy.

[0140] (6) Reference Figure 7 Based on the cross-page unpacking strategy, the merged data is unpacked to obtain multiple second data packets. Figure 7 The upper part shows that four 4096-bit data blocks, totaling 2048 bytes, have been merged in the queue. Figure 7 The lower half shows the packet unpacking results. Due to the unaligned start address 0xA00001A2, the 2048 bytes of data were split into four NOC packets, i.e., the second packet. The first packet (indicating partial data validity): Due to the unaligned start address, only the beginning portion of the last 512-bit block of this packet is valid. Figure 7 Within a 512-bit box, a shaded diagonal line indicates that this portion is valid. Intermediate data packets (all data is valid): The data in these packets falls entirely within the valid data range; therefore, their internal 512-bit blocks represent completely valid data without any invalid padding. Figure 7 In bold, each 512-bit block indicates that all data is valid. Tail packet (indicating partial validity): Due to misalignment of the end address, the last 512-bit block of this packet contains a valid portion at the end. Figure 7The shaded diagonal line within the 512-bit box indicates that this part is valid.

[0141] (7) Transmit these four second data packets sequentially to the data storage area (DRAM) to be accessed via the NOC bus.

[0142] Scenario 3: Accessing remote DRAM via SDMA for reading / writing data.

[0143] (1) Obtain a series of consecutive data requests from the AXI bus, which are initiated by the SDMA engine, and the last request carries packet tail identifier information.

[0144] (2) Based on the data access information of the data request, the data packet concatenation strategy is determined to be the address contiguous concatenation strategy and the packet tail concatenation strategy.

[0145] (3) Reference Figure 8 Based on a defined data packet assembly strategy, data is merged in a pre-created first queue. Data is continuously added to the queue as shown in the diagram. When a data block marked as the end of the packet is received, it indicates that the end of the packet has arrived, and packet assembly is immediately completed.

[0146] (4) Upon receiving the first data packet carrying the packet tail identifier information, immediately update the capacity status of the first queue to full queue status. The data transmission information of the merged data is: data start address 0xD200_0000, total data length 2048 bytes.

[0147] (5) Based on the data transmission information of the merged data, the data unpacking strategy is determined to be a cross-page unpacking strategy.

[0148] (6) Reference Figure 9 The merged data is split into multiple data packets based on a cross-page splitting strategy. Figure 9 The upper part displays the 2048 bytes of data that have been merged in the queue. Figure 9 The lower part illustrates the packet unpacking process. Because the data starting address 0xD2000000 is aligned, and the total length of 2048 bytes is an integer multiple of the NOC packet size (512 bytes), the four resulting second data packets are all fully loaded with data. For example... Figure 9 As shown, the 512-bit blocks in all data packets are highlighted with bold black boxes, indicating that each NOC packet is completely filled with valid data, maximizing bus utilization. Partial data in the first and last packets is valid; please refer to [reference needed]. Figure 7 The explanation is omitted here.

[0149] (7) These second data packets are transmitted sequentially through the NOC bus to the data storage area (DRAM) to be accessed by the remote chip.

[0150] It is understood that in the embodiments of this application, data such as user information are involved. When the embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0151] The following description continues to illustrate the exemplary structure of the bus data transmission device 110 provided in the embodiments of this application as a software module. In some embodiments, such as Figure 2 As shown, the hardware module in the bus data transmission device 110 provided in this application embodiment may include:

[0152] The request acquisition module 1101 is used to acquire at least one data request from the Advanced Expansion Interface Bus, wherein the transmission bit width of the first data packet corresponding to the data request is the same as the bit width of the Advanced Expansion Interface Bus.

[0153] The packet consolidation strategy selection module 1102 is used to determine at least one data consolidation strategy from a preset set of data consolidation strategies based on the data access information of the data request.

[0154] The data packet assembly execution module 1103 is used to merge data in at least one first data packet in a pre-created first queue based on the at least one data packet assembly strategy to obtain merged data;

[0155] The unpacking strategy selection module 1104 is used to determine at least one data unpacking strategy from a preset data unpacking strategy set based on the data transmission information of the merged data in response to the merged data meeting preset transmission conditions.

[0156] The data unpacking execution module 1105 is used to perform data unpacking processing on the merged data based on the at least one data unpacking strategy to obtain at least one second data packet, wherein the transmission bit width of the second data packet is the same as the bit width of the on-chip network bus.

[0157] The data transmission module 1106 is used to transmit the second data packet to the data storage area to be accessed via the on-chip network bus.

[0158] In some embodiments, the data packet selection module 1102 is further configured to parse the data request to obtain the request source and operation type of the data request; determine a first keyword based on the request source and the operation type; compare the first keyword with a second keyword corresponding to each data packet strategy in the preset data packet strategy set; and, in response to the comparison result indicating that the first keyword and the second keyword are the same, determine at least one data packet strategy associated with the second keyword from the data packet strategy set.

[0159] In some embodiments, the data packet assembly execution module 1103 is further configured to perform the following processing for each of the first data packets: obtain the current status information of the first queue; merge the data in the first data packets in the first queue based on the current status information of the first queue and the at least one data packet assembly strategy; and, in response to the fact that the data in each of the first data packets has been processed, use the data in the first queue as the merged data.

[0160] In some embodiments, the current status information includes the queue start address of the first queue, the total length of the data in the first queue, and the capacity status of the first queue; the data packet assembly execution module 1103 is further configured to, when the data packet assembly strategy is an address contiguous assembly strategy, obtain the start address of the data in the first data packet; determine the queue end address of the first queue based on the total length of the data in the first data packet and the queue start address of the first queue; in response to the start address of the data in the first data packet being contiguous with the queue end address of the first queue, merge the data in the first data packet into the first queue; in response to the start address of the data in the first data packet being discontinuous with the queue end address of the first queue, merge the data in the first data packet into an empty second queue, wherein the second queue is used as the first queue for the next merging of the data in the first data packet when the capacity status of the first queue is a full queue state.

[0161] In some embodiments, the current status information includes the total length of the data in the first queue and the capacity status of the first queue; the data packet assembly execution module 1103 is further configured to, when the data packet assembly strategy is a configured granularity packet assembly strategy, obtain a preset packet assembly granularity threshold and the total length of the data in the first data packet; accumulate the total length of the data in the first data packet and the total length of the data in the first data packet to obtain the total length of the data to be merged; compare the total length of the data to be merged with the preset packet assembly granularity threshold to obtain a comparison result; in response to the comparison result indicating that the total length of the data to be merged is less than or equal to the preset packet assembly granularity threshold, merge the data in the first data packet into the first queue; in response to the comparison result indicating that the total length of the data to be merged is greater than the preset packet assembly granularity threshold, merge the data in the first data packet into an empty second queue, wherein the second queue is used as the first queue for the next merging of the data in the first data packet when the capacity status of the first queue is a full queue state.

[0162] In some embodiments, the current status information includes the waiting time of the first queue and the capacity status of the first queue; the waiting time of the first queue is the duration between a first moment and a second moment, where the first moment is the moment when the data in the previous first data packet was merged into the first queue, and the second moment is the moment when the data in the first data packet is merged; the data packet assembly execution module 1103 is further configured to, when the data packet assembly strategy is an aging timeout assembly strategy, obtain a preset aging timeout duration; compare the waiting time of the first queue with the preset aging timeout duration to obtain a comparison result; in response to the comparison result indicating that the waiting time of the first queue is less than or equal to the preset aging timeout duration, merge the data in the first data packet into the first queue; in response to the comparison result indicating that the waiting time of the first queue is greater than the preset aging timeout duration, merge the data in the first data packet into an empty second queue, wherein the second queue is used as the first queue for the next merging of the data in the first data packet when the capacity status of the first queue is a full queue state.

[0163] In some embodiments, the current status information includes the capacity status of the first queue; the above apparatus further includes a queue capacity update module, which is configured to, in response to the first data packet carrying packet tail identifier information, merge the data in the first data packet into the first queue, and update the capacity status of the first queue to a full queue status.

[0164] In some embodiments, the queue capacity update module is further configured to update the capacity status of the first queue to full queue status in response to the data in the first queue meeting the dequeue conditions, wherein the dequeue conditions include any one of the following: the total length of the data in the first queue reaches a preset packet granularity threshold, or the waiting time of the first queue reaches a preset aging timeout period.

[0165] In some embodiments, the preset transmission condition is that the capacity state of the first queue is a full queue state; the data transmission information of the merged data includes the data start address of the merged data and the total data length of the merged data; the packet splitting strategy selection module 1104 is further used to obtain the address boundary bit width of the on-chip network bus, wherein the address boundary bit width is the same as the data transmission bit width of the on-chip network bus, and the address boundary bit width is used to divide the address space; based on the data start address of the merged data and the address boundary bit width, the first address space to which the data start address of the merged data belongs is determined; based on the data start address of the merged data and the total data length of the merged data, the data end address of the merged data is determined; based on the data end address of the merged data and the address boundary bit width, the second address space to which the data end address of the first data packet belongs is determined; based on the judgment result of whether the first address space and the second address space are the same address space, at least one data splitting strategy is determined from the preset data splitting strategy set.

[0166] In some embodiments, the data unpacking execution module 1105 is further configured to: respond to the judgment result indicating that the first address space and the second address space are the same address space and the data unpacking strategy is a non-page-crossing unpacking strategy, encapsulate the merged data into a second data packet, wherein the total length of the merged data is the same as the total length of the second data packet; respond to the judgment result indicating that the first address space and the second address space are not the same address space and the data unpacking strategy is a page-crossing unpacking strategy, obtain a preset unpacking granularity threshold; based on the data starting address of the merged data and the address at the connection between the first address space and the third address space, segment the merged data to obtain data in the first data block, wherein the starting address of the third address space is continuous with the address of the first address space; based on the total length of the merged data and the address at the connection between the first address space and the third address space, segment the merged data to obtain data in the first data block, wherein the starting address of the third address space is continuous with the address of the first address space; based on the total length of the merged data and the address at the connection between the first address space and the third address space, segment the merged data to obtain data in the first data block. The total length of the data in the first data block is used to determine the remaining data length of the merged data. Based on the unpacking granularity threshold, the remaining data corresponding to the remaining data length is sequentially segmented starting from the starting address of the third address space to obtain data in at least one intermediate data block, wherein the data termination address of the last intermediate data block is continuous with the starting address of the second address space. Based on the starting address of the second address space and the data termination address of the merged data, the remaining data corresponding to the remaining data length is segmented to obtain data in the tail data block. The data in the first data block, the data in the at least one intermediate data block, and the data in the tail data block are encapsulated into a second data packet, wherein the total data length of the intermediate data block is equal to the unpacking granularity threshold, and the total data length of the tail data block is less than the unpacking granularity threshold.

[0167] This application provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the bus data transmission method described above in this application.

[0168] This application provides a computer-readable storage medium storing executable instructions. When these executable instructions are executed by a processor, they cause the processor to perform the method provided in this application, for example... Figure 2 The bus data transmission method is shown.

[0169] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0170] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0171] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0172] In summary, through the embodiments of this application, after obtaining at least one data request from the Advanced Scalable Interface Bus (ASME), at least one data packet assembly strategy can be determined from a preset set of data packet assembly strategies based on the data access information of the data request. The data in the first data packet is then merged based on the data packet assembly strategy to obtain merged data. Next, when the merged data meets the transmission conditions, at least one data unpacking strategy can be determined from a preset set of data unpacking strategies based on the data transmission information of the merged data itself. The merged data is then unpacked based on the data unpacking strategy to obtain a second data packet suitable for transmission on the on-chip network bus. Finally, the second data packet is transmitted through the on-chip network bus. Through the above embodiments, two adaptation mechanisms are essentially set up: the first adaptation mechanism dynamically selects the merging strategy based on the data request characteristics on the narrow bus (ASME), and the second adaptation mechanism dynamically selects the unpacking strategy based on the characteristics of the merged data to generate a data packet adapted to the backend wide bus (on-chip network bus). This allows the packet assembly and disassembly methods in this embodiment to be adjusted according to the different characteristics of the data request (stream) (e.g., different access sources and access targets) during the data conversion process from a narrow-width bus to a wide-width bus. Therefore, when facing data requests with varying access sources and targets, involving data transmission across multiple buses, the utilization rate of bus bandwidth is effectively improved.

[0173] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method of bus data transmission, characterized by, The method comprises: acquiring at least one data request from a high-level expandable interface bus, wherein a transmission bit width of a first data packet corresponding to the data request is the same as a bit width of the high-level expandable interface bus; determining at least one data packet strategy in a preset data packet strategy set based on data access information of the data request; for each first data packet, performing the following processing: acquiring current state information of a first queue; based on the current state information of the first queue and the at least one data packet strategy, merging data in the first data packet in the first queue; in response to data of each first data packet being processed, taking data in the first queue as merged data; when the current state information comprises a total length of data in the first queue and a capacity state of the first queue, the merging of the data in the first data packet in the first queue based on the current state information of the first queue and the at least one data packet strategy comprises: in a case where the data packet strategy is a configuration granularity packet strategy, acquiring a preset packet granularity threshold and the total length of data in the first data packet; accumulating the total length of data in the first data packet and the total length of data in the first data packet to obtain a total length of to-be-merged data; comparing the total length of to-be-merged data with the preset packet granularity threshold to obtain a comparison result; in response to the comparison result representing that the total length of to-be-merged data is less than or equal to the preset packet granularity threshold, merging the data in the first data packet to the first queue; in response to the comparison result representing that the total length of to-be-merged data is greater than the preset packet granularity threshold, merging the data in the first data packet to an empty second queue, wherein the second queue is used as the first queue when next time the data in the first data packet is merged, in a case where the capacity state of the first queue is a full queue state; in response to the merged data meeting a preset transmission condition, determining at least one data unpacking strategy in a preset data unpacking strategy set based on data transmission information of the merged data; based on the at least one data unpacking strategy, performing data unpacking processing on the merged data to obtain at least one second data packet, wherein a transmission bit width of the second data packet is the same as a bit width of a network-on-chip bus; transmitting the second data packet to a data storage area to be accessed through the network-on-chip bus.

2. The method of claim 1, wherein, The determining of the at least one data packet strategy in the preset data packet strategy set based on the data access information of the data request comprises: parsing the data request to obtain a request source and an operation type of the data request; determining a first keyword based on the request source and the operation type; comparing the first keyword with a second keyword corresponding to each data packet strategy in the preset data packet strategy set; In response to the comparison result indicating that the first keyword is the same as the second keyword, determining at least one data packet assembly strategy associated with the second keyword from the set of data packet assembly strategies.

3. The method of claim 1, wherein, When the current state information comprises a queue start address of the first queue, a total length of data in the first queue, and a capacity state of the first queue, the merging of the data in the first data packet into the first queue based on the current state information of the first queue and the at least one data packet assembly strategy comprises: in a case where the data packet assembly strategy is an address continuous assembly strategy, obtaining a start address of the data in the first data packet; determining a queue end address of the first queue based on the total length of the data in the first data packet and the queue start address of the first queue; in response to the start address of the data in the first data packet being continuous with the queue end address of the first queue, merging the data in the first data packet into the first queue; in response to the start address of the data in the first data packet being discontinuous with the queue end address of the first queue, merging the data in the first data packet into an empty second queue, wherein the second queue is used as the first queue when next time the data in the first data packet is merged.

4. The method of claim 1, wherein, When the current state information comprises a waiting duration of the first queue and a capacity state of the first queue, the waiting duration of the first queue is a duration between a first time and a second time, the first time being a time when last time the data in the first data packet is merged into the first queue, and the second time being a time when the data in the first data packet is merged; the merging of the data in the first data packet into the first queue based on the current state information of the first queue and the at least one data packet assembly strategy comprises: in a case where the data packet assembly strategy is an aging timeout assembly strategy, obtaining a preset aging timeout duration; comparing the waiting duration of the first queue with the preset aging timeout duration to obtain a comparison result; in response to the comparison result indicating that the waiting duration of the first queue is less than or equal to the preset aging timeout duration, merging the data in the first data packet into the first queue; in response to the comparison result indicating that the waiting duration of the first queue is greater than the preset aging timeout duration, merging the data in the first data packet into an empty second queue, wherein the second queue is used as the first queue when next time the data in the first data packet is merged.

5. The method according to claim 3 or 4, characterized in that, When the current state information comprises the capacity state of the first queue, the method further comprises: in response to the first data packet carrying tail identifier information, merging the data in the first data packet into the first queue, and updating the capacity state of the first queue to a full queue state.

6. The method of claim 5, wherein, the method further comprises: updating, in response to the data in the first queue meeting a dequeue condition, a capacity state of the first queue as a full queue state, wherein the dequeue condition comprises any one of: a total length of the data in the first queue reaching a preset packetization granularity threshold, a waiting duration of the first queue reaching a preset aging timeout duration.

7. The method of claim 6, wherein, The preset transmission condition is that the capacity state of the first queue is a full queue state; and the data transmission information of the merged data comprises a data start address of the merged data and a total data length of the merged data. The determining, based on the data transmission information of the merged data, at least one data unpacking strategy from a preset data unpacking strategy set comprises: obtaining an address boundary bit width of the network-on-chip bus, wherein the address boundary bit width is the same as a data transmission bit width of the network-on-chip bus, and the address boundary bit width is used to divide an address space; determining, based on the data start address of the merged data and the address boundary bit width, a first address space to which the data start address of the merged data belongs; determining, based on the data start address of the merged data and the total data length of the merged data, a data end address of the merged data; determining, based on the data end address of the merged data and the address boundary bit width, a second address space to which the data end address of the first data packet belongs; determining, based on a result of judging whether the first address space and the second address space are the same address space, at least one data unpacking strategy from a preset data unpacking strategy set.

8. The method of claim 7, wherein, The data unpacking processing, based on the at least one data unpacking strategy, on the merged data to obtain at least one second data packet comprises: in response to the result indicating that the first address space and the second address space are the same address space and the data unpacking strategy is a non-cross-page unpacking strategy, encapsulating the merged data as a second data packet, wherein a total data length of the merged data is the same as a total data length of the second data packet; in response to the result indicating that the first address space and the second address space are not the same address space and the data unpacking strategy is a cross-page unpacking strategy, obtaining a preset unpacking granularity threshold; based on the data start address of the merged data and an address at a connection between the first address space and a third address space, cutting the merged data to obtain data in a first data block, wherein a start address of the third address space is continuous with an address of the first address space; based on the total data length of the merged data and a total data length of the data in the first data block, determining a remaining data length of the merged data; based on the unpacking granularity threshold, cutting, from the start address of the third address space, the remaining data corresponding to the remaining data length in sequence to obtain data in at least one intermediate data block, wherein a data end address of data in a last intermediate data block is continuous with a start address of the second address space; and based on the data transmission information of the merged data, determining at least one data unpacking strategy from a preset data unpacking strategy set. split the remaining data corresponding to the remaining data length based on a start address of the second address space and a data end address of the merged data to obtain tail data in a tail data block; encapsulate the data in the first data block, the data in the at least one intermediate data block and the data in the tail data block into second data packets respectively; wherein a total data length of the data in the intermediate data block is equal to the packetization granularity threshold, and a total data length of the data in the tail data block is less than the packetization granularity threshold.

9. A bus data transmission apparatus, characterized by The apparatus comprises: a request acquisition module configured to acquire at least one data request from an advanced extensible interface bus, wherein a transmission bit width of a first data packet corresponding to the data request is the same as a bit width of the advanced extensible interface bus; a packetization strategy selection module configured to determine at least one data packetization strategy from a preset data packetization strategy set based on data access information of the data request; a data packetization execution module configured to, for each first data packet, perform the following processing: acquire current state information of a first queue; based on the current state information of the first queue and the at least one data packetization strategy, merge data in the first data packet in the first queue; in response to the data of each first data packet being processed, take the data in the first queue as merged data; when the current state information comprises a total length of data in the first queue and a capacity state of the first queue, the merging of the data in the first data packet in the first queue based on the current state information of the first queue and the at least one data packetization strategy comprises: in a case where the data packetization strategy is a configuration granularity packetization strategy, acquiring a preset packetization granularity threshold and a total length of data in the first data packet; accumulating the total length of data in the first data packet and the total length of data in the first data packet to obtain a total length of to-be-merged data; comparing the total length of to-be-merged data with the preset packetization granularity threshold to obtain a comparison result; in response to the comparison result representing that the total length of to-be-merged data is less than or equal to the preset packetization granularity threshold, merging the data in the first data packet to the first queue; in response to the comparison result representing that the total length of to-be-merged data is greater than the preset packetization granularity threshold, merging the data in the first data packet to an empty second queue, wherein the second queue is used as a first queue when next merging the data in the first data packet, in a case where the capacity state of the first queue is a full queue state; a packetization strategy selection module configured to, in response to the merged data meeting a preset transmission condition, determine at least one data packetization strategy from a preset data packetization strategy set based on data transmission information of the merged data; The data unpacking execution module is configured to perform data unpacking processing on the merged data based on the at least one data unpacking strategy, to obtain at least one second data packet, wherein a transmission bit width of the second data packet is the same as a bit width of the network-on-chip bus. The data transmission module is configured to transmit the second data packet to the data storage area to be accessed through the network-on-chip bus.

10. A chip, characterized by The chip comprises the device as claimed in claim 9.

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