Display substrate, driving method thereof and display device

Abstract

The embodiment of the invention provides a display substrate, a driving method thereof and a display device, relates to the technical field of display, and aims to solve the problem of display residue of the display substrate. The display substrate comprises a plurality of input signal lines, a plurality of columns of pixel circuits, a plurality of first signal line groups, a plurality of first multiplexing circuits and a plurality of second multiplexing circuits. The first signal line group comprises at least two first signal lines, and one first signal line is electrically connected with one column of pixel circuits. The first multiplexing circuit is electrically connected with one input signal line and a first signal line of the first signal line group. The second multiplexing circuit is electrically connected with one input signal line and the first signal line of one first signal line group. The input signal line is electrically connected with one first multiplexing circuit and one second multiplexing circuit respectively, and the first signal lines of the first signal line group are electrically connected with one first multiplexing circuit and one second multiplexing circuit respectively. The display substrate is used for displaying images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and its driving method, and a display device. Background Technology

[0002] Touch and Display Driver Integration (TDDI) display products are one of the mainstream screen display technologies today. TDDI products are widely used in various display products due to their more sensitive touch technology, lighter and thinner appearance, and lower cost advantages. Summary of the Invention

[0003] The purpose of the embodiments of this disclosure is to provide a display substrate and its driving method and display device, for reducing the risk of right drift of transistors in multiplexed circuits, and reducing or completely eliminating the problem of display residue on the display substrate.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display substrate is provided. The display substrate includes multiple input signal lines, multiple columns of pixel circuits, and multiple first signal line groups. Each first signal line group includes at least two first signal lines, and one first signal line is electrically connected to one column of the pixel circuits. The display substrate also includes multiple first multiplexing circuits and multiple second multiplexing circuits. Each first multiplexing circuit is electrically connected to one input signal line and the at least two first signal lines of one first signal line group, and controls the electrical connection between the input signal line and one first signal line at the same time period. Each second multiplexing circuit is electrically connected to one input signal line and the at least two first signal lines of one first signal line group, and controls the electrical connection between the input signal line and at least one first signal line at the same time period. Specifically, one input signal line is electrically connected to one first multiplexing circuit and one second multiplexing circuit, and the at least two first signal lines of one first signal line group are electrically connected to one first multiplexing circuit and one second multiplexing circuit, respectively.

[0006] The display substrate provided in the embodiments of this disclosure has an input signal line electrically connected to a first multiplexer circuit and a second multiplexer circuit, respectively, and at least two first signal lines of a first signal line group are electrically connected to a first multiplexer circuit and a second multiplexer circuit, respectively. The input signal line can transmit control signals to the first signal lines of the same first signal line group through the first multiplexer circuit and the second multiplexer circuit, respectively. In this way, various different driving methods can be used to drive the display substrate to operate at different times, selecting one of the first multiplexer circuit and the second multiplexer circuit to operate. On the one hand, this helps to reduce the operating time of the first multiplexer circuit and the second multiplexer circuit, reduces the risk of right-hand drift of the transistors in the first multiplexer circuit and the second multiplexer circuit, and reduces or completely eliminates the problem of display residue on the display substrate.

[0007] In some embodiments, the first signal line group includes M first signal lines, and both the first multiplexing circuit and the second multiplexing circuit are electrically connected to the M first signal lines, where M ≥ 2. The display substrate further includes N second signal line groups. Each second signal line group includes M second signal lines, and the M second signal lines of each second signal line group are electrically connected to one of the first multiplexing circuits. Each second signal line controls the electrical connection between one first signal line and the input signal line; N ≥ 2. The plurality of first multiplexing circuits are alternately connected to the N second signal line groups.

[0008] In some embodiments, the display substrate further includes P third signal line groups. Each third signal line group includes M third signal lines, and the M third signal lines of the third signal line group are electrically connected to a second multiplexing circuit, and one of the third signal lines controls the electrical connection between the input signal line and a first signal line; P ≥ 1.

[0009] In some embodiments, the number of the second signal line groups is the same as the number of the third signal line groups, and the plurality of second multiplexing circuits are alternately electrically connected to P of the third signal line groups.

[0010] In some embodiments, the display substrate includes one of the third signal line groups, and the plurality of second multiplexing circuits are all electrically connected to the third signal line group.

[0011] In some embodiments, the display substrate further includes a third signal line. The third signal line is electrically connected to the second multiplexing circuit, and the third signal line controls the electrical connection between the input signal line and the M first signal lines that are electrically connected to the same second multiplexing circuit at the same time.

[0012] In some embodiments, both the first multiplexing circuit and the second multiplexing circuit include a plurality of first thin-film transistors. One of the source and drain of the first thin-film transistor is electrically connected to the input signal line, and the other is electrically connected to the first signal line; at least one of the first thin-film transistors has a width-to-length ratio greater than or equal to 200 μm / 3.5 μm.

[0013] In some embodiments, both the first multiplexing circuit and the second multiplexing circuit include a plurality of first thin-film transistors. One of the source and drain of the first thin-film transistor is electrically connected to the input signal line, and the other is electrically connected to the first signal line; at least one of the first thin-film transistors has a width and length of 320 μm / 3.5 μm.

[0014] In some embodiments, the plurality of first thin-film transistors are arranged in multiple rows along a first direction, with at least two adjacent rows of first thin-film transistors partially overlapping in the first direction, and adjacent first thin-film transistors belonging to two adjacent rows being staggered in a second direction. The first direction is the arrangement direction of a single column of the pixel circuits, and the second direction is the arrangement direction of multiple columns of the pixel circuits.

[0015] In some embodiments, the display substrate includes a plurality of gate lines. Each gate line includes a body portion and a gate portion alternately connected along a second direction. Along the first direction, one end of the gate portion is flush with one end of the body portion, and the other end of the gate portion protrudes beyond the edge of the body portion. One gate line is connected to a row of first thin-film transistors, and one gate portion forms the gate of one first thin-film transistor. The gate portions of two adjacent gate lines protrude to opposite sides relative to the body portion in the first direction. The plurality of gate lines are divided into multiple pairs, each pair comprising two adjacent gate lines, with the gate portions of the two gate lines in a pair protruding towards each other. Two rows of first thin-film transistors connected to a pair of gate lines partially overlap in the first direction, while two rows of first thin-film transistors connected to two adjacent pairs of adjacent gate lines do not overlap in the first direction.

[0016] In some embodiments, the first multiplexing circuit includes two of the first thin-film transistors; and / or, the second multiplexing circuit includes two of the first thin-film transistors.

[0017] In some embodiments, the input signal line is configured to be electrically connected to a driver chip. And / or, at least one of the pixel circuit, the first multiplexing circuit, and the second multiplexing circuit includes an oxide thin-film transistor.

[0018] On the other hand, a driving method for a display substrate is provided for driving the display substrate described in any of the above embodiments. The driving method includes: in the on-screen display mode, a first multiplexing circuit controls the electrical connection between an input signal line and a first signal line during the same time period. In the off-screen wake-up mode, a second multiplexing circuit controls the electrical connection between the input signal line and at least one of the first signal lines during the same time period.

[0019] In some embodiments, the first signal line group includes M first signal lines, and the second multiplexing circuit is electrically connected to the M first signal lines, where M ≥ 2. The display substrate further includes P third signal line groups, each comprising M third signal lines. The second multiplexing circuit is electrically connected to the M third signal lines of the third signal line group; P ≥ 1. The driving method includes: in the screen-off wake-up mode, the second multiplexing circuit controls the electrical connection between the input signal line and one of the first signal lines during the same time period.

[0020] In some embodiments, the driving method further includes: in the on-screen display mode, the first multiplexing circuit and the second multiplexing circuit alternately control the electrical connection between the input signal line and one of the first signal lines in different display frames.

[0021] In some embodiments, the driving method further includes: in the always-on wake-up mode, both the first multiplexing circuit and the second multiplexing circuit control the electrical connection of the same input signal line with the same first signal line during the same time period, and the first multiplexing circuit and the second multiplexing circuit control the electrical connection of the same input signal line with different first signal lines during different time periods of a frame period.

[0022] In some embodiments, the first signal line group includes M first signal lines, and the second multiplexing circuit is electrically connected to the M first signal lines, where M ≥ 2; the display substrate includes a third signal line, and the third signal line is electrically connected to the second multiplexing circuit. The driving method further includes: in the screen-on display mode, the second multiplexing circuit controls the circuit between the input signal line and at least two first signal lines of the signal line group to be cut off; in the screen-off wake-up mode, the second multiplexing circuit controls the electrical connection of the input signal line and at least two first signal lines of the signal line group during the same time period.

[0023] In another aspect, a display device is provided. The display device includes a driver chip and a display substrate as described in any of the above embodiments. The driver chip is electrically connected to the input signal line of the display substrate and is configured to transmit data signals to the data signal terminal.

[0024] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0028] Figure 2 This is a structural diagram of a display device according to some embodiments;

[0029] Figure 3 This refers to a display substrate with residual display image in a related technology;

[0030] Figure 4 This is a schematic diagram illustrating the principle of display residual images on display substrates in related technologies.

[0031] Figure 5 This is a structural diagram of a display substrate according to some embodiments;

[0032] Figure 6 This is an equivalent circuit diagram of a display substrate according to some embodiments;

[0033] Figure 7 This is another equivalent circuit diagram of a display substrate according to some embodiments;

[0034] Figure 8 This is yet another equivalent circuit diagram of a display substrate according to some embodiments;

[0035] Figure 9 This is a structural diagram of a display substrate according to some embodiments;

[0036] Figure 10 for Figure 9 A magnified view of a portion of region A in the middle;

[0037] Figure 11 The study describes the mobility, positive and negative threshold voltage drift of transistors with high-mobility oxide materials in the semiconductor layer at different thicknesses. Detailed Implementation

[0038] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0039] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0040] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0041] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0042] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0043] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0045] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0046] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0047] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0048] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0049] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0050] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] See Figure 1 Embodiments of this disclosure provide a display device 1000, which is a product with image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0052] In some embodiments, the display device described above may be an augmented reality (AR) device, a virtual reality (VR) device, or a mixed reality (MR) device. Alternatively, in other embodiments, the display device may also be a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, camera view display (e.g., a rearview camera display in a vehicle), wearable device, in-vehicle display, flight display, or any other product or component with display functionality.

[0053] In some embodiments, regarding the type of light emission of the display device 1000, the display device 1000 may be a liquid crystal display (LCD), or it may be an organic light-emitting diode (OLED) display or a quantum dot light-emitting diode (QLED) display, etc. Regarding the shape of the display device 1000, it may be a flat panel display or a curved display, etc. Regarding the shape of the display device 1000, it may be rectangular or circular, etc. The following uses a rectangular, flat liquid crystal display as an example to illustrate some embodiments of this disclosure; however, the embodiments of this disclosure are not limited to this, and any other display device can be considered, as long as the same technical concept is applied.

[0054] In some embodiments, see Figure 2 The display device 1000 may include a display substrate 1100 and a driver chip 1200. Of course, the structure of the display device 1000 is not limited to this, and will not be listed here; for example, the display device 1000 may also include a camera and a fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as taking pictures, recording videos or fingerprint recognition.

[0055] The display substrate 1100 includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA refers to the region in the display substrate 1100 used for displaying images, and includes multiple sub-pixels P, where each sub-pixel P is the smallest light-emitting unit in the display substrate 1100. The peripheral area BB can be used to house signal traces (such as power signal lines, clock signal lines, etc.), driving circuits (such as gate driving circuits), and bonding parts, etc. Of course, the structure and function of the peripheral area BB are not limited to these, and will not be listed here. The driving chip 1200 can be disposed in the peripheral area of ​​the display substrate 1100 and bonded to the display substrate 1100.

[0056] The aforementioned plurality of sub-pixels P may include at least two types of sub-pixels that emit light of different colors, which is beneficial for the display substrate to achieve color display. In one example, the plurality of sub-pixels P may include a red light sub-pixel that emits red light, a green light sub-pixel that emits green light, and a blue light sub-pixel that emits blue light. The sub-pixel P may include a pixel circuit 100, and the display substrate 1100 includes a plurality of pixel circuits 100, each pixel circuit 100 being configured to drive one sub-pixel P to emit light.

[0057] Continue reading Figure 2 Multiple pixel circuits 100 are arranged in columns along a first direction Y, and the display substrate 1100 includes multiple columns of pixel circuits 100, which are arranged at intervals along a second direction X. That is, the first direction Y refers to the arrangement direction of a column of pixel circuits, and the second direction X refers to the arrangement direction of multiple columns of pixel circuits; wherein, the first direction Y and the second direction X intersect, for example, the first direction Y and the second direction X are perpendicular to each other.

[0058] like Figure 2 As shown, the display substrate 1100 also includes a plurality of first signal line groups 10, and each first signal line group 10 includes at least two first signal lines 11. Figure 2 (Taking two examples as an illustration), one first signal line 11 is electrically connected to a column of pixel circuits 100.

[0059] Among them, at least two first signal lines 11 of the first signal line group 10 can be arranged adjacent to each other (e.g., Figure 6 As shown), that is, at least two first signal lines 11 of a signal line group 10 can be electrically connected to at least two adjacent column pixel circuits; or at least two first signal lines 11 of the first signal line group 10 can be spaced apart (e.g., Figure 7 As shown), at least two first signal lines 11 of a signal line group 10 can be electrically connected to at least two columns of pixel circuits arranged at intervals.

[0060] In some embodiments, at least a portion of a plurality of first signal line groups 10 are disposed within the display area AA, and the first signal line 11 may be, for example, a data signal line, used to transmit data signals to a column of pixel circuits 100. Hereinafter, embodiments of the present disclosure will be described by way of example, with the first signal line 11 being a data signal line.

[0061] In some embodiments, such as Figure 2 As shown, the pixel circuit 100 may include a second thin-film transistor T20. The control electrode of the second thin-film transistor T20 is electrically connected to the scan signal line 12, one of its source and drain electrodes is electrically connected to the first signal line 11, and the other is electrically connected to the pixel electrode.

[0062] In some embodiments, when the display substrate is a liquid crystal display substrate, the pixel circuit 100 may further include a common electrode, and a capacitor may be formed between the pixel electrode and the common electrode. During the display substrate's image display process, a capacitor may be generated between the pixel electrode and the common electrode. This electric field may drive the liquid crystal molecules of the liquid crystal layer to deflect, thereby adjusting the light transmittance of each sub-pixel and thus displaying the image.

[0063] The pixel circuit 100 may include an oxide thin-film transistor (OTFT), for example, the second thin-film transistor T20 may be an oxide thin-film transistor. OTFTs have the characteristic of low leakage current, which helps to reduce the leakage current of the pixel circuit 100, thereby simplifying the circuit structure of the pixel circuit 100, thereby increasing the aperture ratio of the array substrate and improving the light transmittance of the display substrate.

[0064] In some embodiments, the aforementioned driver chip 1200 may be a source driver IC, which refers to a chip used to transmit data signals to multiple first signal lines 11 of multiple first signal line groups 10. To reduce the cost of the driver chip 1200, a multiplexer (MUX) circuit may be provided within the peripheral area BB and between the driver chip 1200 and the display area AA to reduce the number of signals (such as data signals) output by the driver chip 1200 (at the same time), thereby reducing the cost of the driver chip 1200 and the manufacturing cost of the display substrate 1100.

[0065] In some embodiments, the driving chip 1200 may also be a touch and display driver integrated chip (TDDI chip). In this case, the display substrate 1100 may be a display substrate with touch functionality, and the display substrate may also be referred to as a TDDI display substrate. For example, when the display substrate 1100 is a liquid crystal display substrate, the display substrate 1100 may include an array substrate and a color filter substrate (which may also be called opposing substrates) disposed opposite each other, and a liquid crystal layer and a touch structure (In-cell) disposed between the array substrate and the color filter substrate. For example, the touch structure may be disposed on the array substrate, that is, the touch structure is located between the array substrate and the liquid crystal layer.

[0066] When the driver chip 1200 is a TDDI chip, it can be used to transmit data signals to multiple first signal lines 11 included in multiple first signal line groups 10, and also to transmit touch signals to the touch structure. To reduce the cost of the driver chip 1200, a multiplexer (MUX) circuit can be provided in the peripheral area BB and between the driver chip 1200 and the display area AA to reduce the number of signals (such as data signals) output by the driver chip 1200 (at the same time), thereby reducing the cost of the driver chip 1200 and the manufacturing cost of the display substrate 1100.

[0067] In some embodiments, when the display substrate 1100 includes touch functionality, the display substrate 1100 may have a Low Power wake-up Gesture (LPWG). The Low Power wake-up Gesture is a unique feature of TDDI display substrates. This feature allows for screen swiping operations even when the display substrate is in standby mode (sleep in). For example, users can directly wake up certain functions or corresponding software of the display substrate through preset gestures. However, even when the display substrate is not in use (in standby mode with a black screen), the screen-off wake-up function still consumes a certain amount of power. In order to retain the screen-off wake-up function while saving power, in screen-off wake-up mode, touch signals are continuously supplied to the touch electrodes in the TDDI display substrate. At the same time, the display function and the charge pump module of the driver chip 1200 are turned off. This reduces the power consumption of the TDDI display substrate. In screen-off wake-up mode, the touch structure is driven by the voltage of the external power supply. The highest voltage of the driver chip 1200 is the VSP voltage of the front-end input (e.g., +6V), and the lowest voltage is the VSN voltage of the front-end input (e.g., -6V).

[0068] Currently, related display products (TDDI display substrates) exhibit large-area display residue after reliability testing and in screen-off / wake-up mode (e.g. Figure 3(As shown), and the longer the screen remains in wake-up mode, the more severe the residue becomes. The inventors discovered that a key reason for this residue problem is: ... Figure 4 As shown, after the display substrate undergoes reliability testing, the transistors in the multiplexing circuit MUX experience right drift (the transistor's on-state voltage increases and its on-state current decreases) due to prolonged operation. Therefore, when the display substrate is in a screen-off wake-up mode, the transistors in the multiplexing circuit MUX cannot be fully turned on. Consequently, when the driver chip 1200 transmits data signals to the first signal line 11, the data signals on the input signal line 41 cannot be fully loaded (transmitted) onto the first signal line 11, resulting in significant distortion of the data signals received on the first signal line 11. Consequently, the data signals transmitted to the pixel circuit are also distorted, leading to a voltage difference between the pixel electrode and the common electrode. This voltage difference causes the liquid crystal in the liquid crystal layer to deflect, resulting in light leakage in the black screen mode and causing the aforementioned residual problem.

[0069] See Figure 5 In order to solve the above-mentioned technical problems, the display substrate 1100 provided in the embodiments of this disclosure further includes multiple input signal lines 41, multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2.

[0070] A first multiplexing circuit MUX 1 is electrically connected to an input signal line 41 and at least two (all) of the first signal lines 11 of a first signal line group 10. The first multiplexing circuit MUX 1 controls the electrical connection between the input signal line 41 and one of the first signal lines 11 at the same time; in other words, the first multiplexing circuit MUX 1 can only conduct one of the first signal lines 11 in the input signal line 41 and the first signal line group 10 at the same time, so that the input signal line 41 can transmit data signals to each of the first signal lines 11 individually.

[0071] For example, the number of first multiplexing circuits MUX 1, the number of input signal lines 41, and the number of first signal line groups 10 are equal. One input signal line 41 is electrically connected to one first multiplexing circuit MUX 1, and different input signal lines 41 are electrically connected to different first multiplexing circuits MUX 1. One first multiplexing circuit MUX 1 is electrically connected to one first signal line group 10, and different first multiplexing circuits MUX 1 are electrically connected to different first signal line groups 10.

[0072] A second multiplexing circuit MUX 2 is electrically connected to an input signal line 41 and at least two (all) of the first signal lines 11 of a first signal line group 10. The second multiplexing circuit MUX 2 controls the electrical connection between the input signal line 41 and at least one of the first signal lines 11 at the same time. In other words, the first multiplexing circuit MUX 1 can conduct the input signal line 41 and at least one of the first signal lines 11 in the first signal line group 10 at the same time, so that the input signal line 41 can transmit data signals to each first signal line 11 individually, or transmit data signals to multiple first signal lines 11 simultaneously.

[0073] For example, the number of second multiplexing circuits MUX 2, the number of input signal lines 41, and the number of first signal line groups 10 are equal. One input signal line 41 is electrically connected to one second multiplexing circuit MUX 2, and different input signal lines 41 are electrically connected to different second multiplexing circuits MUX 2. One second multiplexing circuit MUX 2 is electrically connected to one first signal line group 10, and different second multiplexing circuits MUX 2 are electrically connected to different first signal line groups 10.

[0074] Continue reading Figure 5 An input signal line 41 is electrically connected to a first multiplexer circuit MUX 1 and a second multiplexer circuit MUX 2, respectively. At least two first signal lines 11 of a first signal line group 10 are electrically connected to a first multiplexer circuit MUX 1 and a second multiplexer circuit MUX 2, respectively. The input signal line 41 can transmit control signals to the first signal lines 11 of the same first signal line group 10 through the first multiplexer circuit MUX 1 and the second multiplexer circuit MUX 2, respectively. In this way, various different driving methods can be used to drive the display substrate 1100 to select one of the first multiplexer circuit MUX 1 and the second multiplexer circuit MUX 2 to operate at different times. On the one hand, this helps to reduce the operating time of the first multiplexer circuit MUX 1 and the second multiplexer circuit MUX 2, reduce the risk of right drift of the transistors of the first multiplexer circuit MUX 1 and the second multiplexer circuit MUX 2, and reduce or completely eliminate the problem of display residue on the display substrate 1100.

[0075] In some embodiments of this disclosure, for the sake of simplicity, the electrical connection between the control input signal line 41 of the first multiplexing circuit MUX 1 and / or the second multiplexing circuit MUX 2 and the first signal line 11 is described as the operation of the first multiplexing circuit MUX 1 and / or the second multiplexing circuit MUX 2.

[0076] For example, the display substrate 1100 may include a screen-on display mode and a screen-off wake-up mode.

[0077] When the second multiplexing circuit MUX 2 controls the electrical connection between the input signal line 41 and a first signal line 11 during the same time period, either the first multiplexing circuit MUX 1 or the second multiplexing circuit MUX 2 can be used in the on-screen display mode and the off-screen wake-up mode, respectively. For example, in the on-screen display mode, the first multiplexing circuit MUX 1 controls the electrical connection between the input signal line 41 and a first signal line 11 during the same time period, and in the off-screen wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection between the input signal line 41 and a first signal line 11 during the same time period.

[0078] Since all sub-pixels display the same grayscale in the screen-off wake-up mode (0 grayscale in the screen-off state), the same data signal size can be transmitted to all pixel circuits 100. Based on this, the second multiplexing circuit MUX 2 can control the electrical connection between the input signal line 41 and at least two first signal lines 11 during the same period. In this case, in the screen-on display mode, the first multiplexing circuit MUX 1 can control the electrical connection between the input signal line 41 and one first signal line 11 during the same period, and in the screen-off wake-up mode, the second multiplexing circuit MUX 2 can control the electrical connection between the input signal line 41 and one first signal line 11 during the same period.

[0079] It should be noted that the driving method of the display substrate 1100 is not limited to the two specific embodiments described above. As long as the same technical concept is adopted, it is acceptable. The embodiments disclosed herein will not be listed one by one.

[0080] In some embodiments, see Figures 5-8 The first signal line group 10 includes M first signal lines 11. The first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 are both electrically connected to the M first signal lines 11 included in the first signal line group 10. That is, the ratio of the first multiplexing circuit MUX 1 to the second multiplexing circuit MUX 2 is 1:M; where M ≥ 2. Exemplarily, the value of M can be 2, 3, 4, or 6, etc., and these will not be listed individually in the embodiments of this disclosure. This reduces the number of data signals output by the driver chip 1200 (at the same time), thereby reducing the cost of the driver chip 1200 and the manufacturing cost of the display substrate. Furthermore, as the value of M increases, the number of data signals output by the driver chip 1200 (at the same time) decreases accordingly.

[0081] Among them, see Figures 5-8In the accompanying drawings provided with the embodiments of this disclosure, the value of M is 2 for illustrative purposes. However, the embodiments of this disclosure are not limited thereto, and the value of M can be arbitrarily set as needed. The embodiments of this disclosure are described below with the value of M being 2.

[0082] In some embodiments, see Figure 6 Both the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 include M (2) first thin-film transistors T10. One of the source and drain of each first thin-film transistor T10 is electrically connected to the input signal line 41, and the other is electrically connected to a first signal line 11. The first thin-film transistor T10 can control the electrical connection between the input signal line 41 and the first signal line 11.

[0083] In some embodiments, the first multiplexing circuit MUX 1 includes two first thin-film transistors T10. And / or, the second multiplexing circuit MUX 2 includes two first thin-film transistors T10.

[0084] In some embodiments, at least one of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 includes an oxide thin-film transistor (OST). Exemplarily, the first thin-film transistors T10 included in both the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 are oxide thin-film transistors. Oxide thin-film transistors are characterized by low leakage current, which helps to reduce the leakage current of the first thin-film transistor T10.

[0085] See Figure 6 The display substrate 1100 further includes N second signal line groups 20. Each second signal line group 20 includes M second signal lines 21, and the M second signal lines 21 of each second signal line group 20 are electrically connected to a first multiplexing circuit MUX 1. Each second signal line 21 controls the electrical connection between a first signal line 11 and an input signal line 41. Wherein, N ≥ 2; exemplarily, the value of N can be 2, 3, or 4, etc., and these are not listed individually in the embodiments of this disclosure. Multiple first multiplexing circuits MUX 1 are alternately electrically connected to the N second signal line groups 20. This helps to reduce the load on each second signal line group 20 and reduce the voltage drop on the second signal lines 21.

[0086] For example, the second signal line 21 can be a gate line, configured to control the electrical connection between the input signal line 41 and the first signal line 11. For instance, the second signal line 21 can be configured to form the gate (control electrode) of the first thin-film transistor T10, thereby controlling the on and off states of the first thin-film transistor T10.

[0087] The M second signal lines 21 of the second signal line group 20 correspond to the M first thin-film transistors T10 of the first multiplexing circuit MUX 1, and one second signal line 21 is used to form the gate of one first thin-film transistor T10. Figure 6 As shown, when M is 2, a second signal line group 20 includes two second signal lines 21, and the two second signal lines 21 are respectively connected to the gates of the two first thin film transistors T10 of the first multiplexing circuit MUX 1.

[0088] For example, N can be 2, meaning the display substrate 1100 includes two second signal line groups 20, and multiple first multiplexing circuits MUX 1 are alternately electrically connected to N second signal line groups 20. This can be achieved by alternating between each first multiplexing circuit MUX 1 once. For instance, from left to right, the odd-numbered (or even-numbered) first multiplexing circuit MUX 1 is electrically connected to a second signal line group 20 closer to the display area, and the even-numbered (or odd-numbered) first multiplexing circuit MUX 1 is electrically connected to a second signal line group 20 farther from the display area. Alternatively, each set of multiple (e.g., every 2, 3, 4, or other numbers) first multiplexing circuits MUX 1 can alternate once.

[0089] In some embodiments, in the bright screen display mode, a first multiplexing circuit MUX 1 can be used to transmit data signals to the first signal line 11. Using N second signal line groups 20 to control the first multiplexing circuit MUX 1 can reduce the load on the second signal line group 20 and reduce the voltage drop on the second signal line 21, thereby fully opening the first thin film transistor T10 included in the first multiplexing circuit MUX 1, which is beneficial for the data signals transmitted on the input signal line 41 to be fully written onto the first signal line 11.

[0090] In some embodiments, see Figure 6 and Figure 7 The display substrate 1100 further includes P third signal line groups 30. Each third signal line group 30 includes M third signal lines 31. The M third signal lines 31 of the third signal line group 30 are electrically connected to a second multiplexing circuit MUX 2, and one third signal line 31 controls the electrical connection between an input signal line 41 and a first signal line 11. Wherein, P ≥ 1. Exemplarily, the value of P can be 1, 2, or 3, etc., and the embodiments of this disclosure will not be listed one by one.

[0091] For example, the third signal line 31 can be a gate line, configured to control the electrical connection between the input signal line 41 and the first signal line 11. For instance, the third signal line 31 is configured to form the gate (control electrode) of the first thin-film transistor T10 of the second multiplexing circuit MUX 2, thereby controlling the on and off states of the first thin-film transistor T10.

[0092] The M third signal lines 31 of the third signal line group 30 correspond to the M first thin-film transistors T10 of the second multiplexing circuit MUX 2, and one third signal line 31 is used to form the gate of one first thin-film transistor T10. Figure 6 and Figure 7 As shown, when M is 2, a third signal line group 30 includes two third signal lines 31, and the two third signal lines 31 are respectively connected to the gates of the two first thin-film transistors T10 of the second multiplexing circuit MUX 2.

[0093] like Figure 7 As shown, when P is 1, the display substrate 1100 includes one third signal line group 30, and multiple second multiplexing circuits MUX 2 are electrically connected to M third signal lines 31 of the third signal line group 30. This reduces the number of third signal line groups 30, simplifies the control of the driver chip, simplifies the structure of the display substrate 1100, and reduces the width of the peripheral area.

[0094] When the value of P is greater than 1, for example, the value of P can be 2 or 3, that is, the display substrate 1100 includes a plurality of third signal line groups 30. A plurality of second multiplexing circuits MUX 2 are alternately electrically connected to P third signal line groups 30. This helps to reduce the load on each second signal line group 20 and reduce the voltage drop on the second signal line 21.

[0095] In one example, such as Figure 6As shown, the value of P can be 2, meaning that the display substrate 1100 includes two third signal line groups 30. Multiple second multiplexing circuits MUX 2 are alternately electrically connected to the two third signal line groups 30. This can be done by alternating between each first multiplexing circuit MUX 1 once. For example, along the second direction X, the odd-numbered (or even-numbered) second multiplexing circuits MUX 2 are connected to the first (closest to the display area AA) third signal line group 30, and the even-numbered (or odd-numbered) second multiplexing circuits MUX 2 are connected to the second (farthest from the display area AA) third signal line group 30. This helps reduce the load on each second signal line group 20 and reduces the voltage drop on the second signal line 21. Alternatively, multiple (e.g., every 2, 3, 4, or other numbers) second multiplexing circuits MUX 2 can alternate once.

[0096] In some embodiments, when the value of P is greater than 1, the display substrate 1100 includes a plurality of third signal line groups 30. In this case, the number of third signal line groups 30 can be equal to the number of second signal line groups 20 (e.g., ...). Figure 6 As shown), multiple second multiplexing circuits MUX 2 are alternately electrically connected to P third signal line groups 30. In this way, the connection methods of multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 are exactly the same, and the multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 are redundantly configured.

[0097] In some embodiments, when the value of P is greater than 1, that is, the display substrate 1100 includes a plurality of third signal line groups 30, the number of third signal line groups 30 may not be equal to the number of second signal line groups 20 (not shown in the figure), for example, the number of third signal line groups 30 may be greater than the number of second signal line groups 20; or, the number of third signal line groups 30 may be less than the number of second signal line groups 20.

[0098] When the value of P is greater than 1, that is, when the display substrate 1100 includes multiple third signal line groups 30, the multiple first multiplexing circuits MUX 1 and the multiple second multiplexing circuits MUX 2 can operate in any display mode in a selective manner, or the multiple first multiplexing circuits MUX 1 and the multiple second multiplexing circuits MUX 2 can operate alternately in any display mode.

[0099] For example, in the on-screen display mode, one of the multiple first multiplexing circuits MUX 1 and the multiple second multiplexing circuits MUX 2 operates; in the off-screen wake-up mode, the other of the multiple first multiplexing circuits MUX 1 and the multiple second multiplexing circuits MUX 2 operates. That is, in the same display mode, one of the multiple first multiplexing circuits MUX 1 and the multiple second multiplexing circuits MUX 2 operates selectively, and in different display modes, the multiple first multiplexing circuits MUX 1 and the multiple second multiplexing circuits MUX 2 operate alternately. In this way, screen residue can be avoided when switching modes.

[0100] For example, in any mode, multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 can operate alternately. For instance, in the on-screen display mode, multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 alternately transmit the data signals required for at least one frame of the image; for example, multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 can operate alternately every 1 frame (or 2 frames, 3 frames, 4 frames, 60 frames, etc., as needed). In this way, the operating time of multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 can be reduced, the turn-on time of the first thin-film transistor T10 can be reduced, and the risk of drift of the first thin-film transistor T10 can be effectively reduced.

[0101] It is understood that the driving method for the display substrate provided in this embodiment is not limited to this, as long as the same technical concept is used.

[0102] In some embodiments, see Figure 8 The display substrate 1100 includes a third signal line 31, which is electrically connected to all the second multiplexing circuits MUX 2. The third signal line 31 controls the electrical connection between the input signal line 41, which is electrically connected to the same second multiplexing circuit MUX 2, and the M first signal lines 11 included in the first signal line group 10 at the same time. That is, the third signal line 31 simultaneously connects or disconnects the input signal line 41 from the M first signal lines 11.

[0103] For example, such as Figure 8As shown, the third signal line 31 can be a gate line, configured to control the electrical connection between the input signal line 41 and all the first signal lines 11 of a first signal line group 10. Exemplarily, the third signal line 31 is configured to form the gate (control electrode) of all the first thin-film transistors T10 in the second multiplexing circuit MUX 2, thereby controlling the on and off states of all the first thin-film transistors T10. For example, one third signal line 31 can be used to form the gates of M first thin-film transistors T10. This significantly reduces the number of third signal line groups 30, reduces the control complexity of the driver chip, simplifies the structure of the display substrate 1100, and helps reduce the width of the peripheral area.

[0104] For example, when the display substrate 1100 includes a third signal line 31, multiple second multiplexing circuits MUX 2 can operate in the screen-off wake-up mode. At this time, all pixel circuits 100 in the display area AA display the same gray level (0 gray level) and can synchronously transmit data signals of the same size to the pixel circuits 100. Therefore, all the first thin film transistors T10 of the second multiplexing circuit MUX 2 can be turned on synchronously. Based on this, multiple second multiplexing circuits MUX 2 can be controlled by a third signal line 31.

[0105] In some embodiments, see Figure 9 and Figure 10 In the case where multiple first multiplexing circuits MUX 1 and multiple second multiplexing circuits MUX 2 each include multiple first thin-film transistors T10, the aspect ratio (W / L) of the first thin-film transistor T10 is greater than or equal to 200μm / 3.5μm, that is, the aspect ratio of the channel structure of the first thin-film transistor T10 is greater than or equal to 200μm / 3.5μm. This is beneficial for improving the charging capability of the first thin-film transistor T10, i.e., improving the current gain of the first thin-film transistor T10, and also beneficial for reducing the signal transmission delay of the first multiplexing circuit MUX 1 and multiple second multiplexing circuits MUX 2. For example, the aspect ratio of the first thin-film transistor T10 can be 200μm / 3.5μm, 250μm / 3.5μm, 300μm / 3.5μm, 320μm / 3.5μm, or 350μm / 3.5μm, etc., and the embodiments of this disclosure will not be listed one by one.

[0106] In some embodiments, the aspect ratio of the first thin-film transistor T10 can be 320 μm / 3.5 μm. In this case, the charging capability of the first thin-film transistor T10 can be greatly improved, and the risk of drift of the first thin-film transistor T10 can be reduced.

[0107] For example, such as Figure 9 As shown and Figure 10 The display substrate 1100 may include multiple gate lines GL, wherein the multiple gate lines GL may include second signal lines 21 and third signal lines 31; in other words, both the second signal lines 21 and the third signal lines 31 may be gate lines GL. Furthermore, each gate line GL includes a body portion 42 and a gate portion 43 alternately connected along a second direction X. One gate portion 43 is configured to form the gate of a first thin-film transistor T10.

[0108] The display substrate 1100 also includes a substrate, see below. Figure 10 The first thin-film transistor T10 also includes a semiconductor pattern 44 disposed on the side of the gate portion 43 near the substrate. The orthographic projection of the gate portion 43 on the substrate and the orthographic projection of the semiconductor pattern 44 on the substrate partially coincide. In the semiconductor pattern 44, the portion on the substrate that coincides with the orthographic projection of the gate portion 43 on the substrate forms a channel structure 441. The dimension of the channel structure 441 in the first direction Y is the width W of the first thin-film transistor T10, and the dimension of the channel structure 441 in the second direction X is the length L of the first thin-film transistor T10. The width-to-length ratio W / L of the first thin-film transistor T10 refers to the ratio between the width W and the length L of the channel structure 441.

[0109] The semiconductor pattern 44 can be continuous in the first direction Y, or the semiconductor pattern 44 can include multiple sub-patterns 442 spaced apart along the first direction Y (e.g., ...). Figure 10 The two sub-patterns 442 shown can be used to illustrate the case where the semiconductor pattern 44 includes multiple sub-patterns 442. In this case, the size of the semiconductor pattern 44 along the first direction Y can be the sum of the sizes W' of the multiple sub-patterns 442 along the first direction Y.

[0110] For example, see Figure 10 The gate portion 43 may include a plurality of sub-portions 431 spaced apart along the second direction X. The plurality of sub-portions 431 extend along the first direction Y. The orthographic projection of a sub-portion 431 on the substrate and the orthographic projection of the semiconductor pattern 44 on the substrate form a channel structure 441. The length L of the channel structure 441 refers to the size of the portion of each semiconductor pattern 44 that coincides with the orthographic projection of a sub-portion 431 along the second direction X, that is, the individual size of each channel structure 441.

[0111] like Figure 10 As shown, multiple sub-sections 431 are connected end-to-end to form an S-shaped structure, and a slit 433 with an opening 432 can be formed between two adjacent sub-sections 431. The openings 432 of two adjacent slits 433 face opposite directions. The first thin-film transistor T10 also includes a source and a drain located in the middle of the slit 433, and the source and drain are connected to the semiconductor pattern 44 through the slit 433.

[0112] In some embodiments, see Figure 9 and Figure 10 Along the first direction Y, the size D1 of the main body portion 42 is smaller than the size D2 of the gate portion 43. This is beneficial to increase the size of the gate portion 43 in the first direction Y, thereby increasing the aspect ratio of the first thin film transistor T10, improving the charging capability of the first thin film transistor T10, that is, increasing the on-state current of the first thin film transistor T10, and reducing the risk of drift of the first thin film transistor T10.

[0113] like Figure 9 As shown, multiple first thin-film transistors (TFTs) T10 are arranged in multiple rows along the first direction Y. A gate line GL is electrically connected to a row of TFTs T10, or in other words, multiple TFTs T10 electrically connected to the same gate line GL form a row of TFTs T10. At least two adjacent rows of TFTs T10 partially overlap in the first direction Y. That is, at least two rows of TFTs T10 in the multiple rows of TFTs T10 partially overlap in the first direction Y. This can greatly reduce the space occupied by the multiple rows of TFTs T10 in the first direction Y, which is beneficial for reducing the size of the bezel area and realizing a narrow bezel of the display substrate 1100.

[0114] In this application, the partial overlap of two adjacent rows of first thin-film transistors T10 in the first direction Y means that the two adjacent rows of first thin-film transistors T10 jointly occupy the same portion of space along the first direction Y of the display substrate 1100, or that the projection portions of the two adjacent rows of first thin-film transistors T10 in the second direction X overlap. For example, Figure 9 The first thin-film transistors T10 in the first and second rows, as well as the third and fourth rows, are considered to be partially overlapping in the first direction Y, while the first thin-film transistors T10 in the second and third rows are considered to be non-overlapping in the first direction Y.

[0115] Continue reading Figure 9 The two adjacent first thin-film transistors T10 belonging to the two adjacent rows are staggered in the second direction X. This helps to optimize the arrangement space of the first thin-film transistors T10, increase the arrangement density of the first thin-film transistors T10, and greatly reduce the space occupied by the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 in the peripheral area, thereby reducing the width of the peripheral area and helping the display substrate 1100 to achieve a narrow bezel.

[0116] In some embodiments, such as Figure 9As shown, the main body portion 42 and the gate portion 43 are flush at one end in the first direction Y, and the other end of the gate portion 43 protrudes (extends) from the edge of the main body portion 42. The gate portions 43 of two adjacent gate lines GL protrude to the opposite sides of the main body portion 42 in the first direction Y. The multiple gate lines GL are divided into multiple pairs, with each pair consisting of two adjacent gate lines GL, and the gate portions 43 of the two gate lines GL in a pair protruding in a direction that approaches each other. The two rows of first thin-film transistors T10 connected to a pair of gate lines GL partially overlap in the first direction Y, while the two rows of first thin-film transistors T10 connected to two adjacent pairs of adjacent gate lines GL do not overlap in the first direction Y. This is beneficial for optimizing the arrangement space of the first thin-film transistors T10, increasing the arrangement density of the first thin-film transistors T10, and greatly reducing the space occupied by the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 in the peripheral area, thereby reducing the width of the peripheral area and facilitating the realization of a narrow bezel on the display substrate.

[0117] For example, such as Figure 9 As shown, the four gate lines GL are sequentially divided into the first gate line, the second gate line, the third gate line, and the fourth gate line from top to bottom. The four gate lines GL are divided into two groups: the first and second gate lines form one group, and the third and fourth gate lines form another group. Specifically, the gate portion 43 of the first gate line protrudes downwards relative to the main body portion 42 along the first direction Y, while the gate portion 43 of the second gate line protrudes upwards relative to the main body portion 42 along the first direction Y. The two rows of first thin-film transistors T10 connected to the first and second gate lines partially overlap in the first direction Y. The two rows of first thin-film transistors T10 connected to the second and third gate lines do not overlap in the first direction Y.

[0118] In some embodiments, the semiconductor pattern 44 can be made of a high-mobility metal-oxide-semiconductor (HMOS) material, which is beneficial for improving the electron mobility of the semiconductor pattern 44 and increasing the on-state current of the first thin-film transistor T10. Furthermore, high-mobility metal-oxide-semiconductor materials also possess good light-induced stability, which is beneficial for improving the light-induced stability of the first thin-film transistor T10. High-mobility metal-oxide-semiconductor materials include, but are not limited to, rare-earth-doped IZO and IGZO, with the rare-earth doping concentration ranging from 0.1% to 2%. However, due to the small optical bandgap Eg of high-mobility oxide-semiconductor materials, electrons in these materials can absorb some visible light and undergo electron transitions, causing the transistor to turn on prematurely after backlighting and increasing the number of new defects under illumination. Figure 11 As shown, applying a positive voltage to the transistor for an extended period of time (such as...) Figure 11The PBTS shown causes a positive shift in the threshold voltage, and applying a negative voltage to the transistor for an extended period of time (such as...) Figure 11 The residual problem (NBTS) caused by the high mobility leads to a negative shift in the threshold voltage, and the higher the mobility, the more severe the negative shift, which greatly limits the application of high-mobility oxide semiconductor materials. Since the technical solutions provided in the embodiments of this disclosure can improve or even completely eliminate the residual problem, it is beneficial to achieve the widespread application of high mobility.

[0119] Some embodiments of this disclosure also provide a driving method for a display substrate 1100, used to drive the display substrate described in any of the above embodiments. The display substrate includes a screen-on display mode and a screen-off wake-up mode. Of course, the display substrate may also include other display modes, which will not be listed here.

[0120] The driving method for the display substrate 1100 includes:

[0121] In the on-screen display mode, the first multiplexing circuit MUX 1 controls the electrical connection between the input signal line 41 and a first signal line at the same time.

[0122] In the screen-off wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection between the input signal line and at least one first signal line during the same period.

[0123] Based on the above driving method, the display substrate 1100 can use a first multiplexer circuit MUX 1 and a second multiplexer circuit MUX 2 to control the electrical connection between the input signal line 41 and the first signal line 11 during the same period in different display modes. Thus, even if the display substrate has undergone prolonged screen-on display (e.g., after a reliability test), and the first thin-film transistor T10 of the first multiplexer circuit MUX 1 drifts (e.g., drifts to the right), after switching to the screen-off wake-up mode, since the first multiplexer circuit MUX 1 is no longer used, and instead the second multiplexer circuit MUX 2 is used to control the electrical connection between the input signal line 41 and the first signal line 11 during the same period, the drift of the first thin-film transistor T10 of the first multiplexer circuit MUX 1 will not affect the electrical connection between the input signal line 41 and the first signal line 11. That is, it will not cause data signal distortion during the passage of the second multiplexer circuit MUX 2, thereby reducing the risk of residual data on the display substrate.

[0124] In some embodiments, see Figure 6 and Figure 7The first signal line group 10 includes M first signal lines 11, and a second multiplexing circuit MUX 2 is electrically connected to the M first signal lines, where M ≥ 2. The display substrate 1100 also includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and a second multiplexing circuit MUX 2 is electrically connected to the M third signal lines 31 of the third signal line group 30; wherein, P ≥ 1.

[0125] At this time, the driving method for the display substrate also includes:

[0126] In the screen-off wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection between the input signal line 41 and one first signal line 11 during the same period. That is, the second multiplexing circuit MUX 2 is only used to connect the input signal line 41 to one first signal line 11 in a first signal line group 10 during the same period.

[0127] In some embodiments, see Figure 6 and Figure 7 The first signal line group 10 includes M first signal lines 11, and a second multiplexing circuit MUX 2 is electrically connected to the M first signal lines, where M ≥ 2. The display substrate 1100 also includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and a second multiplexing circuit MUX 2 is electrically connected to the M third signal lines 31 of the third signal line group 30; wherein, P ≥ 1.

[0128] At this time, the driving method for the display substrate also includes:

[0129] In the bright-screen display mode, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 alternately connect the input signal line 41 to a first signal line 11 in different display frames. This reduces the total number of times and the total duration that the first thin-film transistor T10 of the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 is turned on in the bright-screen display mode, thereby reducing the risk of drift of the first thin-film transistor T10, improving the accuracy of data signal transmission in the bright-screen display mode, and ensuring that the image displayed on the display substrate does not become distorted during prolonged bright-screen display.

[0130] In other embodiments, see Figure 6 and Figure 7 The first signal line group 10 includes M first signal lines 11, and a second multiplexing circuit MUX 2 is electrically connected to the M first signal lines, where M ≥ 2. The display substrate 1100 also includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and a second multiplexing circuit MUX 2 is electrically connected to the M third signal lines 31 of the third signal line group 30; wherein, P ≥ 1.

[0131] At this time, the driving method for the display substrate also includes:

[0132] In the screen-off wake-up mode, both the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 control the electrical connection between the same input signal line 41 and the same first signal line 11 during the same time period. Furthermore, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 control the electrical connection between the same input signal line and different first signal lines at different time periods within a frame cycle.

[0133] In other words, the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 operate simultaneously. The two first thin-film transistors T10 belonging to the first multiplexing circuit MUX 1 and the second multiplexing circuit MUX 2 are connected in parallel. At this time, it is beneficial to increase the on-state current of the two first thin-film transistors T10, which helps to reduce the risk of data signal distortion during the process of passing through the two first thin-film transistors T10 and reduces the risk of residue on the display substrate.

[0134] In some embodiments, see Figure 8 The first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX 2 is electrically connected to the M first signal lines 11, where M ≥ 2. The display substrate 1100 includes a third signal line 31, which is electrically connected to the second multiplexing circuit MUX 2.

[0135] At this time, the driving method for the display substrate also includes:

[0136] In the on-screen display mode, the control input signal line 41 of the second multiplexing circuit MUX 2 and all the first signal lines 11 of the first signal line group 10 are not connected.

[0137] In the screen-off wake-up mode, the second multiplexing circuit MUX 2 controls the electrical connection between the input signal line 41 and at least two first signal lines during the same period.

[0138] In other words, when the display substrate 1100 includes only one third signal line 31, and in the on-screen display mode, the second multiplexing circuit MUX 2 is not working, and the electrical connection between the input signal line 41 and the first signal line 11 is controlled by the first multiplexing circuit MUX 1. Furthermore, in the off-screen wake-up mode, the second multiplexing circuit MUX 2 simultaneously connects the input signal line 41 and all the first signal lines 11 of a signal line group 10. This significantly reduces the number of third signal line groups 30, simplifies the control complexity of the driver chip, and streamlines the structure of the display substrate 1100, while also reducing the width of the peripheral area.

[0139] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any combination or substitution between embodiments, as well as changes or substitutions of technical features, that can be conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, characterized by, The display substrate comprises: a plurality of input signal lines, a plurality of pixel circuits, and a plurality of first signal line groups, one of the first signal line groups comprises at least two first signal lines, one of the first signal lines is electrically connected to one of the pixel circuits; a plurality of first multiplexing circuits, each of the first multiplexing circuits is electrically connected to one of the input signal lines and the at least two first signal lines of one of the first signal line groups, and each of the first multiplexing circuits controls electrical connection between the input signal line and one of the first signal lines in the same time period; a plurality of second multiplexing circuits, each of the second multiplexing circuits is electrically connected to one of the input signal lines and the at least two first signal lines of one of the first signal line groups, and each of the second multiplexing circuits controls electrical connection between the input signal line and at least one of the first signal lines in the same time period; wherein one of the input signal lines is electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits respectively, and the at least two first signal lines of one of the first signal line groups are electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits respectively.

2. The display substrate according to claim 1, wherein: the first signal line group comprises M first signal lines, and each of the first multiplexing circuits and the second multiplexing circuits is electrically connected to the M first signal lines, and M is greater than or equal to 2; the display substrate further comprises N second signal line groups, each of the second signal line groups comprises M second signal lines, the M second signal lines of each of the second signal line groups are electrically connected to one of the first multiplexing circuits, and one of the second signal lines controls electrical connection between one of the first signal lines and the input signal line, and N is greater than or equal to 2; wherein the plurality of first multiplexing circuits are alternately connected to the N second signal line groups. The display substrate further comprises: 3.The display substrate of claim 2, wherein, P third signal line groups, each of the third signal line groups comprises M third signal lines, the M third signal lines of each of the third signal line groups are electrically connected to one of the second multiplexing circuits, and one of the third signal lines controls electrical connection between the input signal line and one of the first signal lines, and P is greater than or equal to 1.

4. The display substrate according to claim 3, wherein: the number of the second signal line groups is the same as the number of the third signal line groups, and the plurality of second multiplexing circuits are alternately electrically connected to the P third signal line groups.

5. The display substrate according to claim 3, wherein: the display substrate comprises one of the third signal line groups, and each of the plurality of second multiplexing circuits is electrically connected to the third signal line group. The display substrate further comprises: 6.The display substrate of claim 2, wherein, one third signal line, the third signal line is electrically connected to the second multiplexing circuit, and the third signal line controls electrical connection between the input signal line and the M first signal lines electrically connected to the same second multiplexing circuit in the same time period.

7. The display substrate according to any one of claims 1 to 6, wherein: ​ The first multiplexing circuit and the second multiplexing circuit each include a plurality of first thin film transistors, one of the source and the drain of the first thin film transistor is electrically connected with the input signal line, and the other is electrically connected with the first signal line; the width-length ratio of at least one of the first thin film transistors is greater than or equal to 200μm / 3.5μm.

8. The display substrate according to any one of claims 1-6, wherein, The first multiplexing circuit and the second multiplexing circuit each include a plurality of first thin film transistors, one of the source and the drain of the first thin film transistor is electrically connected with the input signal line, and the other is electrically connected with the first signal line; the width-length ratio of at least one of the first thin film transistors is greater than or equal to 200μm / 3.5μm.

9. The display substrate according to claim 7, wherein, The plurality of first thin film transistors are arranged in multiple rows along a first direction, at least two adjacent rows of the first thin film transistors partially overlap in the first direction, and adjacent two first thin film transistors belonging to the adjacent two rows are arranged staggered in a second direction; the first direction is the arrangement direction of a column of the pixel circuits, and the second direction is the arrangement direction of multiple columns of the pixel circuits.

10. The display substrate according to claim 9, wherein, The display substrate includes a plurality of gate lines, the gate line includes a main body portion and a gate portion alternately connected along the second direction, along the first direction, the gate portion is flush with one end of the main body portion, and the other end of the gate portion protrudes from the edge of the main body portion; one of the gate lines is connected with one row of the first thin film transistors, and one of the gate portions forms a gate of one of the first thin film transistors; The gate portions of the adjacent two gate lines protrude from the two sides of the main body portion opposite to the first direction; the plurality of gate lines are divided into multiple pairs, one pair includes two adjacent gate lines, and the gate portions of the two gate lines of one pair protrude in a direction close to each other; The two rows of the first thin film transistors connected with one pair of the gate lines partially overlap in the first direction, and the two rows of the first thin film transistors connected with adjacent two pairs of the adjacent two gate lines do not overlap in the first direction. 11.The display substrate of claim 7, wherein, The first multiplexing circuit includes two of the first thin film transistors; and / or, the second multiplexing circuit includes two of the first thin film transistors.

12. The display substrate according to claim 1, wherein, The input signal line is configured to be electrically connected with a driving chip; and / or, At least one of the pixel circuit, the first multiplexing circuit and the second multiplexing circuit includes an oxide thin film transistor.

13. A method for driving a display substrate according to any one of claims 1 to 12, characterized by, The display substrate includes a bright screen display mode and an off-screen wake-up mode; the driving method includes: In the bright screen display mode, the first multiplexing circuit controls the electrical connection between the input signal line and one of the first signal lines in the same period; In the off-screen wake-up mode, the second multiplexing circuit controls the electrical connection between the input signal line and at least one of the first signal lines in the same period.

14. The driving method according to claim 13, wherein, the first signal line group comprises M first signal lines, the second multiplexing circuit is electrically connected with the M first signal lines, and M is greater than or equal to 2; the display substrate further comprises a third signal line group, the third signal line group comprises M third signal lines, and the second multiplexing circuit is electrically connected with the M third signal lines of the third signal line group; and P is greater than or equal to 1; the driving method comprises: in the screen-off wake-up mode, the second multiplexing circuit controls electrical connection between the input signal line and one first signal line in the same time period.

15. The driving method according to claim 14, wherein the driving method further comprises: in the screen-on display mode, the first multiplexing circuit and the second multiplexing circuit alternately control electrical connection between the input signal line and one first signal line in different display frames.

16. The driving method according to claim 14 or 15, wherein the driving method further comprises: in the screen-off wake-up mode, the first multiplexing circuit and the second multiplexing circuit both control electrical connection between the same input signal line and the same first signal line in the same time period, and the first multiplexing circuit and the second multiplexing circuit control electrical connection between the same input signal line and different first signal lines in different time periods in one frame period.

17. The driving method according to claim 13, wherein, the first signal line group comprises M first signal lines, the second multiplexing circuit is electrically connected with the M first signal lines, and M is greater than or equal to 2; and the display substrate comprises one third signal line, and the third signal line is electrically connected with the second multiplexing circuit; the driving method further comprises: in the screen-on display mode, the second multiplexing circuit controls electrical circuit cutoff between the input signal line and the at least two first signal lines of one signal line group; in the screen-off wake-up mode, the second multiplexing circuit controls electrical connection between the input signal line and the at least two first signal lines of one signal line group in the same time period.

18. A display device comprising: comprises: the display substrate according to any one of claims 1 to 12; a driving chip, which is electrically connected with the input signal line of the display substrate and is configured to transmit a data signal to the data signal end.

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