Device and method for logic calculation in MRAM (Magnetic Random Access Memory)
By using two memory arrays and write pulses in MRAM in-memory computing, the wiring structure is simplified, the accuracy and flexibility of logic operations are improved, and the complexity and scalability issues of existing MRAM in-memory computing devices are solved.
Patent Information
- Application Number
- CN202511237043.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-01
- Publication Date
- 2025-12-30
AI Technical Summary
Existing MRAM in-memory computing devices have complex wiring, limited scalability, and insufficient precision and flexibility in logic operations.
Two MRAM arrays are used, connected to source lines or bit lines via interconnect modules. The input and output units are selected by the control module, and logic operations are performed by writing pulses, avoiding the use of additional resistors and special pulses.
It simplifies the architecture of MRAM in-memory computing devices, improves the accuracy and flexibility of logic operations, and avoids voltage crosstalk during array cross-row or cross-column operations.
Smart Images
Figure CN121237147A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of in-memory computing technology, and in particular to an MRAM in-memory logic computing device and method. Background Technology
[0002] Magnetic random access memory (MRAM) is considered a strong candidate for next-generation general-purpose memory due to its non-volatility, high read / write speeds, high durability, and good compatibility with standard CMOS processes. However, in traditional computing architectures, MRAM, like other memories, primarily serves the function of data storage. When handling data-intensive computing tasks, the frequent data transfers between the processor and memory generate significant latency and power consumption, the so-called "memory wall" bottleneck.
[0003] To overcome the "memory wall," academia and industry have proposed the concept of in-memory computing, which embeds logic operation functions directly into the memory array. In existing technologies, in-memory computing solutions using MRAM typically require additional resistors, placeholder working cells, or special pulses, resulting in complex wiring and limited scalability of existing MRAM-based in-memory computing devices. Summary of the Invention
[0004] The MRAM in-memory logic computing device and method provided by the present invention effectively simplify the architecture for in-memory computing in MRAM.
[0005] In a first aspect, the present invention provides an MRAM in-memory logic computing device, comprising:
[0006] Two memory arrays, each of the memory arrays including a magnetic tunneling junction array, a column driving module for column gating of the magnetic tunneling junction array, and a row driving module for row gating of the magnetic tunneling junction array;
[0007] An interconnect module is provided for electrically connecting the source lines or bit lines of the two magnetic tunnel junction arrays.
[0008] The control module controls the column driving module and the row driving module to select an input unit storing target input data from one of the two magnetic tunnel junction arrays, and controls the column driving module and the row driving module to select an output unit for storing calculation results from the other of the two magnetic tunnel junction arrays.
[0009] Optionally, the in-memory array further includes a reading module. When the in-memory array has an input unit, the reading module is used to read the input data stored in the input unit to determine the accuracy of the input data.
[0010] Optionally, the in-memory array further includes a reading module. When the in-memory array has an output unit, the reading module is used to read the computation results stored in the output unit.
[0011] Optionally, the interconnect module is used to electrically connect all source lines or all bit lines of the two magnetic tunnel junction arrays.
[0012] Optionally, one of the two magnetic tunnel junction arrays is a first magnetic tunnel junction array and the other is a second magnetic tunnel junction array;
[0013] The first magnetic tunnel junction array includes multiple first subarrays, and each first subarray includes two or more columns of first storage cells.
[0014] The second magnetic tunnel junction array includes multiple second subarrays, each of which includes two or more columns of second memory cells;
[0015] The interconnect module includes multiple multiplexers, each multiplexer corresponding to a first subarray and a second subarray. The multiplexer is used to select one or more columns of first memory cells from the first subarray, select one column of second memory cells from the second subarray, and electrically connect the source lines or bit lines of the selected first and second memory cells.
[0016] Secondly, the present invention also provides an MRAM in-memory logic computation method, executed using the MRAM in-memory logic computation device described in any one of the preceding claims, the method comprising:
[0017] Based on the preset logical operation category, k first storage units are selected as input units in one magnetic tunnel junction array, and n second storage units are selected as output units in another magnetic tunnel junction array; where k≥1, n≥1;
[0018] Based on the input data required by the preset logical operation category, the input unit is written into the corresponding resistance state, and the preset resistance state is written into the output unit;
[0019] Configure the input unit and the output unit in a series connection.
[0020] According to the preset logic operation category, write pulses are input to the bit lines of the input unit or the bit lines of the output unit, so that the output unit conditionally flips according to the resistance state of the input unit and stores the operation result in the output unit.
[0021] Optionally, selecting k first memory cells as input cells from one of the magnetic tunnel junction arrays according to a preset logical operation category includes:
[0022] Based on the preset logical operation category, k first storage cells are selected as input cells in the same row or column of one of the magnetic tunnel junction arrays.
[0023] Optionally, after the step of inputting a write pulse to the bit line of the input unit or the bit line of the output unit according to a preset logic operation category, so that the output unit conditionally flips according to the resistance state of the input unit and stores the operation result in the output unit, the method further includes:
[0024] The steps of selecting the output unit from the previous operation as the input unit for the current operation, selecting the output unit for the current operation from another magnetic tunnel junction array, returning the input data required according to the preset logic operation category, writing the input unit to the corresponding resistance state, and writing the preset resistance state to the output unit are used to make the operation result of the previous operation participate in the current operation.
[0025] Optionally, after the step of inputting a write pulse to the bit line of the input unit or the bit line of the output unit according to a preset logic operation category, so that the output unit conditionally flips according to the resistance state of the input unit and stores the operation result in the output unit, the method further includes:
[0026] The output unit of the previous operation is selected as the output unit of the current operation. The input unit of the current operation is selected from another magnetic tunnel junction array. According to the input data required by the preset logic operation category, the input unit is written into the corresponding resistance state. Then, the step of setting the input unit and the output unit in series is returned so that the operation result of the previous operation is used as the preset resistance state in the current operation.
[0027] Optionally, setting the input unit and the output unit in a series connection includes:
[0028] The k input units are selected using row-driven and column-driven modules so that the k input units are connected in parallel.
[0029] Set the k input units and output units in parallel to be connected in series.
[0030] In the technical solution provided by this invention, only the source lines or bit lines of the two MRAM arrays need to be connected. Then, by pre-writing a preset resistance state to the output unit and writing input data to the input unit, conditional switching of the output unit can be achieved by applying a write pulse in a suitable direction. Therefore, in the technical solution provided by this invention, logic operations can be implemented without additional resistors, placeholder working units, or special pulses, thus effectively simplifying the architecture of the in-memory computing device in MRAM. Simultaneously, since one of the two magnetic tunnel junction arrays is used for input data and the other for storing the operation results, voltage crosstalk during array cross-row or cross-column operations can be effectively avoided, thus effectively improving the accuracy of logic operations. Furthermore, since the input and output units can be arbitrarily selected from the corresponding arrays, the flexibility of logic operations is effectively improved. Attached Figure Description
[0031] Figure 1 This is a schematic diagram of an MRAM in-memory logic computing device according to an embodiment of the present invention;
[0032] Figure 2 This is an exemplary source line electrical connection diagram of an MRAM in-memory logic computing device according to another embodiment of the present invention;
[0033] Figure 3 This is an exemplary source line electrical connection diagram of an MRAM in-memory logic computing device according to another embodiment of the present invention. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] This invention provides an MRAM in-memory logic computing device, comprising:
[0036] Two memory arrays, each of the memory arrays including a magnetic tunneling junction array, a column driving module for column gating of the magnetic tunneling junction array, and a row driving module for row gating of the magnetic tunneling junction array;
[0037] An interconnect module is provided for electrically connecting the source lines or bit lines of the two magnetic tunnel junction arrays.
[0038] The control module controls the column driving module and the row driving module to select an input unit storing target input data from one of the two magnetic tunnel junction arrays, and controls the column driving module and the row driving module to select an output unit for storing calculation results from the other of the two magnetic tunnel junction arrays.
[0039] In some embodiments, since the resistive state switching of a magnetic tunnel junction unit typically requires a write current exceeding the critical switching current, a temporary computation path can be formed by connecting one or more input units and one output unit in series. When a precisely calibrated write pulse is applied to this path, the total resistance in the path determines the actual current flowing through it. Based on this, the voltage of the write pulse can be preset to operate within a specific window: if the total resistance of the path is low (e.g., both the series-connected input and output units are in a low-resistance state), the resulting write current is strong enough to exceed the switching threshold of the output unit, thereby changing its state. If the total resistance of the path is high (e.g., at least one of the input and output units in the path is in a high-resistance state), the resulting write current is weak enough to switch the output unit and maintain its original state. This configuration allows the output unit to switch under the set conditions, thus enabling logical operations to be performed. In some embodiments, during a single operation, one of the two magnetic tunnel junction arrays serves as the input array and the other as the output array. However, during multiple operations, they can be transformed as needed. For example, one magnetic tunnel junction array may serve as the output array during the current operation, storing the result of the current operation. In the next operation, if the result of the current operation needs to be used as input data, the magnetic tunnel junction array storing the result of the current operation can be transformed into the input array, while the other magnetic tunnel junction array can be transformed into the output array.
[0040] In the technical solution provided by this invention, only the source lines or bit lines of the two MRAM arrays need to be connected. Then, by pre-writing a preset resistance state to the output unit and writing input data to the input unit, conditional switching of the output unit can be achieved by applying a write pulse in a reasonable direction. Therefore, in the technical solution provided by this invention, logic operations can be implemented without additional resistors, placeholder working units, or special pulses, thus effectively simplifying the architecture of the in-memory computing device in MRAM. Simultaneously, since one of the two magnetic tunnel junction arrays is used for input data and the other for storing the operation results, voltage crosstalk during array cross-row or cross-column operations can be effectively avoided, thus effectively improving the accuracy of logic operations. Furthermore, since the input and output units can be arbitrarily selected from the corresponding arrays, the flexibility of logic operations is effectively improved.
[0041] As an optional implementation, the in-memory array further includes a reading module. When the in-memory array has an input unit, the reading module is used to read the input data stored in the input unit to determine the accuracy of the input data.
[0042] In some embodiments, since the input data plays a crucial role in logical operations, when the memory array has input units, the input data can be read by the read module after being written into the input units of the memory array for verification.
[0043] As an optional implementation, the in-memory array further includes a reading module. When the in-memory array has an output unit, the reading module is used to read the computation results stored in the output unit.
[0044] In some embodiments, since the calculation result is stored in the output unit after the calculation is completed, the output unit can be read by the reading module in order to obtain the calculation result.
[0045] As an optional implementation method, such as Figure 2 As shown, the interconnect module is used to electrically connect all source lines or all bit lines of the two magnetic tunnel junction arrays.
[0046] In some embodiments, after electrically connecting all source lines or all bit lines of two magnetic tunnel junction arrays, during the operation, the corresponding input and output units can be selected by gating the row driving module and column driving module of each of the two memory arrays. After gating, the input and output units are connected in series.
[0047] As an optional implementation method, such as Figure 3 As shown, one of the two magnetic tunnel junction arrays is a first magnetic tunnel junction array, and the other is a second magnetic tunnel junction array;
[0048] The first magnetic tunnel junction array includes multiple first subarrays, and each first subarray includes two or more columns of first storage cells.
[0049] The second magnetic tunnel junction array includes multiple second subarrays, each of which includes two or more columns of second memory cells;
[0050] The interconnect module includes multiple multiplexers, each multiplexer corresponding to a first subarray and a second subarray. The multiplexer is used to select one or more columns of first memory cells from the first subarray, select one column of second memory cells from the second subarray, and electrically connect the source lines or bit lines of the selected first and second memory cells.
[0051] In some embodiments, each multiplexer corresponds to a first subarray and a second subarray, such that the multiplexer, the first subarray, and the second subarray form an "in-memory logic computing sub-device" capable of independent computation. In practical applications, each "in-memory logic computing sub-device" can perform computation independently without interference from other "in-memory logic computing sub-devices," meaning that multiple "in-memory logic computing sub-devices" can complete computations in parallel. It should be understood that, under the premise of requiring parallel computation, the row-driven module and / or column-driven module of the in-memory array should have the ability to simultaneously select multiple rows and / or columns.
[0052] This invention also provides an MRAM in-memory logic computation method, executed using any one of the foregoing MRAM in-memory logic computation devices, the method comprising:
[0053] Based on the preset logical operation category, k first storage units are selected as input units in one magnetic tunnel junction array, and n second storage units are selected as output units in another magnetic tunnel junction array; where k≥1, n≥1;
[0054] Based on the input data required by the preset logical operation category, the input unit is written into the corresponding resistance state, and the preset resistance state is written into the output unit;
[0055] Configure the input unit and the output unit in a series connection.
[0056] According to the preset logic operation category, write pulses are input to the bit lines of the input unit or the bit lines of the output unit, so that the output unit conditionally flips according to the resistance state of the input unit and stores the operation result in the output unit.
[0057] As an optional implementation, the step of selecting k first memory cells as input cells from one of the magnetic tunnel junction arrays according to a preset logical operation category includes:
[0058] Based on the preset logical operation category, k first storage cells are selected as input cells in the same row or column of one of the magnetic tunnel junction arrays.
[0059] As an optional implementation, after the step of inputting a write pulse to the bit line of the input unit or the bit line of the output unit according to a preset logic operation category, so that the output unit conditionally flips according to the resistance state of the input unit and stores the operation result in the output unit, the method further includes:
[0060] The steps of selecting the output unit from the previous operation as the input unit for the current operation, selecting the output unit for the current operation from another magnetic tunnel junction array, returning the input data required according to the preset logic operation category, writing the input unit to the corresponding resistance state, and writing the preset resistance state to the output unit are used to make the operation result of the previous operation participate in the current operation.
[0061] As an optional implementation, after the step of inputting a write pulse to the bit line of the input unit or the bit line of the output unit according to a preset logic operation category, so that the output unit conditionally flips according to the resistance state of the input unit and stores the operation result in the output unit, the method further includes:
[0062] The output unit of the previous operation is selected as the output unit of the current operation. The input unit of the current operation is selected from another magnetic tunnel junction array. According to the input data required by the preset logic operation category, the input unit is written into the corresponding resistance state. Then, the step of setting the input unit and the output unit in series is returned so that the operation result of the previous operation is used as the preset resistance state in the current operation.
[0063] As an optional implementation, setting the input unit and the output unit in a series configuration includes:
[0064] The k input units are selected using row-driven and column-driven modules so that the k input units are connected in parallel.
[0065] Set the k input units and output units in parallel to be connected in series.
[0066] like Figure 2 As shown, an exemplary MRAM in-memory logic computing device is illustrated, in which the source lines of two magnetic tunnel junction arrays are all electrically connected. Based on this MRAM in-memory logic computing device, the following exemplary method of performing implied logic computation is demonstrated:
[0067] exist Figure 2 In the process, input cells are selected from the top magnetic tunnel junction array, and output cells are selected from the bottom magnetic tunnel junction array; for example, the memory cell at position (WL0, BL0) is selected as the input cell, and the memory cell at position (WL0, BL0) is selected as the output cell. n+1 BL n+1 The storage unit at position ) is the output unit; in this embodiment, the write window of the output unit is set to be able to drive its flip only when the current value of both the input unit and the output unit are in a low-resistance state.
[0068] Write operand A into the input unit and operand B into the output unit;
[0069] The row drive module and column drive module control the selection of input and output units, so that the input and output units form a series path;
[0070] A write pulse is applied to the bit line of the input cell; at this time, one of the following situations exists:
[0071] If A is '0' (low resistance state) and B is '0' (low resistance state), the total resistance of the series circuit is low, the current is strong, and the output unit flips from '0' to '1'.
[0072] If A is '0' (low resistance state) and B is '1' (high resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '1'.
[0073] If A is '1' (high resistance state) and B is '0' (low resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '0'.
[0074] If A is '1' (high resistance state) and B is '1' (high resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '1'.
[0075] Clearly, after the aforementioned operations, the logical result of the implication operation (AIMP B) is stored in the output unit.
[0076] It should be noted that when a write pulse with a positive amplitude is applied to the bit line of an input cell, the high-level side of the input cell is on the bit line side, and the low-level side is on the source line side. Conversely, the high-level side of the output cell is on the source line side, and the low-level side is on the bit line side. Therefore, when A is '0' (low-impedance state) and B is '0' (low-impedance state), only the output cell will flip, not the input cell. Because the flipping of the magnetic tunnel junction is related to the current direction, different write pulse application methods need to be considered for different logic operations; the pulse can be applied to the bit line of the input cell or the bit line of the output cell.
[0077] Still adopting Figure 2 The apparatus shown exemplifies how it performs OR and NOT logical calculations as follows:
[0078] exist Figure 2 In the process, input cells are selected from the top magnetic tunnel junction array, and output cells are selected from the bottom magnetic tunnel junction array; for example, memory cells at positions (WL0, BL0) and (WL1, BL0) are selected as input cells, and memory cells at positions (WL1, BL0) are selected as output cells. n+1 BL n+1 The storage cell at position ) is the output cell; the write window of the output cell is set so that the current value can only drive it to flip when both input cells are in a low-resistance state.
[0079] Write operands A and B into the two input units, and write a preset resistance state into the output unit (the preset resistance state is 0 in the OR operation);
[0080] The row drive module and column drive module control the selection of input and output units and apply a write pulse to the bit line of the input unit; at this time, the following situations exist:
[0081] If A is '0' (low resistance state) and B is '0' (low resistance state), the total resistance of the series circuit is low, the current is strong, and the output unit flips from '0' to '1'.
[0082] If A is '0' (low resistance state) and B is '1' (high resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '0'.
[0083] If A is '1' (high resistance state) and B is '0' (low resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '0'.
[0084] If A is '1' (high resistance state) and B is '1' (high resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '0'.
[0085] Clearly, after the aforementioned operations, the output unit stores the OR NOT logical result (A NOR B).
[0086] In the aforementioned OR / NOT operation, the two selected input units are storage units in the same column. In actual operation, storage units in the same row can also be selected as input units.
[0087] In the two exemplary embodiments described above, a write pulse with a positive amplitude is applied to the bit line of the input unit. It should be understood that a pulse with a positive amplitude can also be applied to the bit line of the output unit. For example, the following method can still be used: Figure 2 The apparatus shown exemplifies how it performs logical calculations as follows:
[0088] exist Figure 2 In the process, input cells are selected from the top magnetic tunnel junction array, and output cells are selected from the bottom magnetic tunnel junction array; for example, memory cells at positions (WL0, BL0) and (WL1, BL0) are selected as input cells, and memory cells at positions (WL1, BL0) are selected as output cells. n+1 BL n+1 The storage cell at position ) is the output cell; the write window of the output cell is set to drive it to flip only when one of the two input cells is in a low-resistance state.
[0089] Write operands A and B into the two input units, and write the preset resistance state into the output unit (in the AND operation, the preset resistance state is 1);
[0090] The row drive module and column drive module select the input and output units and apply a write pulse to the bit line of the output unit; at this time, the following situations exist:
[0091] If A is '0' (low resistance state) and B is '0' (low resistance state), the total resistance of the series circuit is low, the current is strong, and the output unit flips from '1' to '0'.
[0092] If A is '0' (low resistance state) and B is '1' (high resistance state), the total resistance of the series circuit is high, the current is strong, and the output unit flips from '1' to '0'.
[0093] If A is '1' (high resistance state) and B is '0' (low resistance state), the total resistance of the series circuit is high, the current is strong, and the output unit flips from '1' to '0'.
[0094] If A is '1' (high resistance state) and B is '1' (high resistance state), the total resistance of the series circuit is high, the current is weak, and the output unit remains '1'.
[0095] Clearly, after the aforementioned operations, the output unit stores the result of the AND operation (A AND B).
[0096] The foregoing exemplary embodiments illustrate the operation process involving operations, NOR operations and AND operations, but do not constitute a limitation of the present invention. By reasonably setting the write pulse, the write window of the output unit and the preset impedance state, multiple operations such as OR, NAND or XOR can also be performed.
[0097] In addition, such as Figure 3 As shown, an exemplary MRAM in-memory logic computing device is illustrated, in which two magnetic tunnel junction arrays are divided into subarrays, and the corresponding subarrays are selected by a multiplexer. Based on this MRAM in-memory logic computing device, the following exemplary method of performing vector inversion logic computation is demonstrated:
[0098] In the top magnetic tunnel junction array, k memory cells are selected as input cells, and only one input cell is selected in each subarray; in the bottom magnetic tunnel junction array, n memory cells are selected as output cells, and only one output cell is selected in each subarray; in this embodiment, k = n.
[0099] A k-bit input vector A (containing N units from A[0] to A[N-1]) is stored bit by bit in the corresponding input unit, and the n output units are written to logic '0' (low impedance state).
[0100] like Figure 3As shown, the controller is configured with interconnect modules to simultaneously establish N independent, parallel computing paths. The i-th path is specifically responsible for connecting the i-th input unit and the i-th output unit.
[0101] A write pulse is applied to the bit line of each input cell;
[0102] For the i-th output unit, if the input A[i] is '0' (low resistance state), the total resistance of its corresponding path is low and the current is strong, so the i-th output unit flips from '0' to '1'; if the input A[i] is '1' (high resistance state), the total resistance of its corresponding path is high and the current is weak, so the i-th output unit does not flip and remains '0'.
[0103] Clearly, after the aforementioned operations, each of the n output units becomes the inverted bit of the corresponding bit in the input vector A.
[0104] The aforementioned vector inversion logic operation exemplifies the logic operation process, but does not limit the invention. By reasonably setting the write pulse, the write window of the output unit, and the preset impedance state, multiple operations such as IMP, AND, OR, NAND, or NOR can also be performed. It should be understood that this embodiment merely uses multiple subarrays for parallel computation; its actual computational principle is different from... Figure 2 The corresponding exemplary implementations are similar.
[0105] It should be understood that the foregoing embodiments and exemplary embodiments are described using source lines for connection, but this does not limit the present invention. The foregoing embodiments and exemplary embodiments can also use bit lines for connection. However, when using bit lines for connection, the direction of the write pulse will be opposite to that when using source lines for the same logical operation.
[0106] Those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. An MRAM in-memory logic computing device, comprising: The MRAM in-memory logic computing device comprises: two memory computing arrays, each of which comprises a magnetic tunnel junction array, a column driving module for column gating the magnetic tunnel junction array, and a row driving module for row gating the magnetic tunnel junction array; an interconnection module for electrically connecting source lines or bit lines of the two magnetic tunnel junction arrays; a control module for controlling the column driving module and the row driving module to select an input unit storing target input data from one of the two magnetic tunnel junction arrays, and for controlling the column driving module and the row driving module to select an output unit for storing an operation result from the other of the two magnetic tunnel junction arrays.
2. The MRAM in-memory logic computing apparatus of claim 1, wherein, The memory computing array further comprises a reading module for reading input data stored in the input unit when the input unit is present in the memory computing array, so as to determine the accuracy of the input data.
3. The MRAM in-memory logic computing device of claim 1, wherein, The memory computing array further comprises a reading module for reading an operation result stored in the output unit when the output unit is present in the memory computing array.
4. The MRAM in-memory logic computing device of claim 1, wherein, The interconnection module is configured to electrically connect all source lines or all bit lines of the two magnetic tunnel junction arrays.
5. The MRAM in-memory logic computing device of claim 1, wherein, One of the two magnetic tunnel junction arrays is a first magnetic tunnel junction array, and the other is a second magnetic tunnel junction array. The first magnetic tunnel junction array comprises a plurality of first sub-arrays, each of which comprises two or more columns of first memory cells. The second magnetic tunnel junction array comprises a plurality of second sub-arrays, each of which comprises two or more columns of second memory cells. The interconnection module comprises a plurality of multiplexers, each of which corresponds to a first sub-array and a second sub-array, and is configured to select one or more columns of first memory cells from the first sub-array, to select one or more columns of second memory cells from the second sub-array, and to electrically connect source lines or bit lines of the selected first memory cells and second memory cells.
6. A method of in-memory logic computation for MRAM, comprising: The MRAM in-memory logic computing device is used to perform the method of any one of claims 1-5, and the method comprises: selecting k first memory cells in one of the magnetic tunnel junction arrays as input units and selecting n second memory cells in the other of the magnetic tunnel junction arrays as output units according to a preset logic operation category, wherein k≥1 and n≥1; writing the input units into corresponding resistance states according to input data required by the preset logic operation category, and writing a preset resistance state into the output units; setting the input units and the output units to be in a series connection state; inputting a write pulse to a bit line of the input units or a bit line of the output units according to the preset logic operation category, so that the output units are conditionally flipped according to resistance states of the input units, and an operation result is stored in the output units.
7. The method of claim 1, wherein, The selecting k first memory cells in one of the magnetic tunnel junction arrays as input units according to the preset logic operation category comprises: selecting k first memory cells in the same row or the same column of one of the magnetic tunnel junction arrays as input units according to the preset logic operation category.
8. The method of claim 1, wherein, After the step of inputting write pulses to the bit line of the input unit or the bit line of the output unit according to the preset logic operation category, so that the output unit is conditionally flipped according to the resistance state of the input unit, and the operation result is stored in the output unit, the method further comprises: selecting the output unit in the previous operation as the input unit in the current operation, selecting the output unit in the current operation in another magnetic tunnel junction array, returning the input data required according to the preset logic operation category, writing the input unit into the corresponding resistance state, and writing the preset resistance state to the output unit, so that the operation result of the previous operation participates in the current operation.
9. The method of claim 1, wherein, After the step of inputting write pulses to the bit line of the input unit or the bit line of the output unit according to the preset logic operation category, so that the output unit is conditionally flipped according to the resistance state of the input unit, and the operation result is stored in the output unit, the method further comprises: selecting the output unit in the previous operation as the input unit in the current operation, selecting the output unit in the current operation in another magnetic tunnel junction array, returning the input data required according to the preset logic operation category, writing the input unit into the corresponding resistance state, and writing the preset resistance state to the output unit, so that the operation result of the previous operation participates in the current operation.
10. The method of claim 1, wherein, The step of setting the input unit and the output unit in a series state comprises: k input units are gated by row driving modules and column driving modules to form a parallel state; k input units in a parallel state and an output unit are set in a series state.