Electronic device with memory

Abstract

The invention provides an electronic device with a memory. The electronic device comprises a control chip and a first memory, the length of a data signal line between the control chip and the first memory is matched with a first reference length, and the first reference length is the length of a clock signal line between the control chip and the first memory. According to the electronic device, the data signal line between the control chip and the first memory is subjected to equal-length constraint by taking the clock signal line as the reference, so that the data signal line between the control chip and the first memory can meet the time sequence requirement, and the circuit performance and reliability of the electronic device are improved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and in particular to an electronic device with a memory. Background Technology

[0002] Traditional DDR (Double Data Rate) routing designs are rather arbitrary, leading to problems such as mutual interference between DDR traces, interference between DDR traces and DDR power supply, and timing issues with DDR traces not meeting requirements. Summary of the Invention

[0003] The technical problem to be solved by this disclosure is to overcome the above-mentioned defects in the prior art and to provide an electronic device with memory.

[0004] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0005] A first aspect of this disclosure provides an electronic device with memory, including a control chip and a first memory;

[0006] The length of the data signal line between the control chip and the first memory is matched with a first reference length, wherein the first reference length is the length of the clock signal line between the control chip and the first memory.

[0007] Optionally, the first memory includes a data strobe pin and a data signal pin;

[0008] The data signal lines between the control chip and the first memory include a first data signal line between the control chip and the data strobe pin, and multiple second data signal lines between the control chip and the data signal pin.

[0009] The length of the first data signal line matches the first reference length, and the length of each second data signal line matches the length of the first data signal line.

[0010] Optionally, the length of the control signal line between the control chip and the first memory matches the first reference length, and / or,

[0011] The length of the command signal line between the control chip and the first memory is matched with the first reference length.

[0012] Optionally, the electronic device further includes a second memory of the same type as the first memory, and the length of the data signal line between the control chip and the second memory is matched with a second reference length, wherein the second reference length is the length of the clock signal line between the control chip and the second memory;

[0013] The second memory and the first memory are located on opposite sides of the PCB board, and the second memory is located on the back of the first memory;

[0014] The chip select pins of the first memory and the second memory are respectively connected to different GPIO pins of the control chip, and the first memory and the second memory operate in a time-sharing manner.

[0015] The data signal pins of the control chip are connected to both the data signal pins of the first memory and the data signal pins of the second memory.

[0016] Optionally, the number of first memories is at least two, the sum of the data bit widths of all first memories is equal to the data bit width of the control chip, the chip select pins of all first memories are connected to the same GPIO pin of the control chip, and the data signal pins of different first memories are respectively connected to different data signal pins of the control chip.

[0017] Optionally, the control signal pins of the control chip are sequentially connected to the control signal pins of the first memory arranged in sequence;

[0018] The command signal pins of the control chip are connected sequentially to the command signal pins of the first memory arranged in sequence;

[0019] The address signal pins of the control chip are sequentially connected to the address signal pins of the first memory arranged in sequence.

[0020] Optionally, the control signal pins of the control chip and the control signal pins of different first memories are all connected to the first pad, and the distance between the first pad and the control signal pins of different first memories is the same.

[0021] And / or, the command signal pins of the control chip and the command signal pins of different first memories are all connected to the second pad, and the distance between the second pad and the command signal pins of different first memories is the same;

[0022] And / or, the address signal pins of the control chip and the address signal pins of different first memories are all connected to the third pad, and the distance between the third pad and the address signal pins of different first memories is the same.

[0023] Optionally, all first memories are located on the same side of the PCB.

[0024] Optionally, for the differential signal lines in the electronic device, the winding spacing is twice the line width, and / or the winding length is three times the line width.

[0025] Optionally, the projection of the data signal line between the control chip and the first memory onto the adjacent ground plane falls on the ground plane, and the projection of the control signal line and / or command signal line between the control chip and the first memory onto the adjacent ground plane falls on the power plane.

[0026] Optionally, for different signal lines located on the same layer of the PCB board between the control chip and the first memory, the distance between the layer where the signal line is located and the nearest adjacent layer is greater than or equal to 3 times the thickness of the insulating medium.

[0027] Optionally, the first memory is DDR.

[0028] Based on common knowledge in the field, the above optional conditions can be combined arbitrarily to obtain the preferred embodiments of this disclosure.

[0029] The positive improvement of this disclosure is that by using the clock signal line as a reference to constrain the length of the data signal lines between the control chip and the first memory, the timing requirements of the data signal lines between the control chip and the first memory can be met, thereby improving the circuit performance and reliability of the electronic device. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the signal connection between the CPU and two DDR3 chips provided in an embodiment of this disclosure.

[0031] Figure 2 This is a schematic diagram of the signal connection between the CPU and four DDR3 chips provided in an embodiment of this disclosure.

[0032] Figure 3 This is a schematic diagram of the topology of the data line and data passthrough line between a DDR3 chip and a CPU, provided in an embodiment of this disclosure.

[0033] Figure 4 This is a schematic diagram of the topology of the data lines and data pass lines between the DDR3 chips U2 and U3 and the CPU provided in the embodiments of this disclosure, in the vertical direction of the PCB board.

[0034] Figure 5 This is a schematic diagram of the topology of the data lines and data pass lines between the DDR3 chips U4 and U5 and the CPU provided in the embodiments of this disclosure, shown in the vertical direction of the PCB board.

[0035] Figure 6 This is a schematic diagram of the actual PCB layout and routing topology of an ARM architecture CPU and DDR3 chips provided in an embodiment of this disclosure.

[0036] Figure 7 This is a schematic diagram of two routing lines in a set of BUS provided in an embodiment of this disclosure.

[0037] Figure 8 This is a schematic diagram of a rules interface provided in an embodiment of the present disclosure.

[0038] Figure 9 This is a schematic diagram of another rules interface provided for an embodiment of this disclosure.

[0039] Figure 10 This is a schematic diagram of another rule interface provided in an embodiment of the present disclosure.

[0040] Figure 11 This is a schematic diagram of another rule interface provided in an embodiment of the present disclosure.

[0041] Figure 12 This is a schematic diagram of the interface for calculating impedance provided in an embodiment of this disclosure.

[0042] Figure 13 This is a schematic diagram of the layout and wiring of the data lines between the main control chip and a single DDR3 chip provided in an embodiment of this disclosure.

[0043] Figure 14 This is a partial layout and wiring diagram of the control lines or command lines between the main control chip and a single DDR3 chip provided in an embodiment of this disclosure.

[0044] Figure 15 This is a schematic diagram of the data line layout and wiring of the main control chip and two DDR3 chips forming a dual-channel configuration, as provided in an embodiment of this disclosure.

[0045] Figure 16 This diagram illustrates the radiation levels emitted by the 30MHz to 1GHz test frequency band of the cellular 5G and Wi-Fi 7 industrial router provided in this embodiment of the present disclosure. Detailed Implementation

[0046] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0047] It should be noted that the terms "first," "second," etc., used in this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] Most processors come with external dynamic memory (DDR). DDR3 chips are primarily used in servers, industrial motherboards, and medical motherboards. In this embodiment, the substrate includes printed circuit boards (PCBs), SiP (System-in-Package), and integrated circuit boards. This embodiment uses a PCB as an example, but it is not limited to PCBs; the substrate can also be a SiP or an integrated circuit board.

[0049] Timing (equal length) is one of the most important parameters in the entire DDR design. The DDR clock serves as the reference for the entire DDR section, and the clock is a differential clock. If a DDR3 system has two clock signals, there must be two pairs: CLK1 and CLK2. The tolerance between CLK1 and CLK2 is ±20mil. The tolerance within either the CLK1 or CLK2 differential pair is ±5mil. Some systems only have one pair of clock signals, such as systems in consumer electronics composed of ARM architecture CPUs and DDR3.

[0050] This disclosure provides an electronic device with a memory, including a control chip and a first memory; the length of the data signal line between the control chip and the first memory is matched with a first reference length, wherein the first reference length is the length of the clock signal line between the control chip and the first memory.

[0051] In practical applications, the aforementioned control chip can also be called a main control chip, specifically a CPU, DSP, FPGA, GPU, etc. It should be noted that the aforementioned length matching, or equal-length constraint, refers to the requirement that a group of signal lines have the same length or match within a specified length tolerance range. This constraint ensures that signals arrive at their destination synchronously during transmission, avoiding timing issues.

[0052] In this embodiment, the data signal lines between the control chip and the first memory are constrained to the same length based on the clock signal lines, which can ensure that the data signal lines between the control chip and the first memory meet the timing requirements, thereby improving the circuit performance and reliability of the electronic device.

[0053] In one optional implementation, the first memory includes a data strobe pin and a data signal pin; the data signal line between the control chip and the first memory includes a first data signal line between the control chip and the data strobe pin and multiple second data signal lines between the control chip and the data signal pin; the length of the first data signal line matches the first reference length, and the length of each second data signal line matches the length of the first data signal line.

[0054] In practical applications, the aforementioned first memory can be DDR, its data strobe pin can be the DQS pin, and its data signal pins can be the DQ pins (including DQ0 to DQ7 pins). Taking a CPU as the control chip as an example, the data signal lines between the CPU and the DDR include the first data signal line between the CPU and the DQS pin, and multiple second data signal lines between the CPU and the DQ pin. The length of the first data signal line matches the length of the aforementioned clock signal line, i.e., the first data signal line and the clock signal line are constrained to be of equal length. The length of each second data signal line matches the length of the first data signal line, i.e., the second data signal line and the first data signal line are constrained to be of equal length.

[0055] In this embodiment, the first data signal line is constrained to the same length as the clock signal line, and the second data signal line is constrained to the same length as the first data signal line, so that both the first and second data signal lines meet the timing requirements.

[0056] In one optional implementation, the length of the control signal line between the control chip and the first memory matches the first reference length. Specifically, the control signal line can be a signal line between the control chip and the control pins of the DDR, where the DDR control pins can be pins such as CKE, ODT, and CS. In this implementation, the control signal line between the control chip and the first memory is constrained to the same length as the clock signal line, ensuring that the control signal line also meets timing requirements.

[0057] In one optional implementation, the length of the command signal line between the control chip and the first memory matches the first reference length. Specifically, the control signal line can be the signal line between the control chip and the command pins of the DDR, where the DDR command pins can be BA0-BA2, RAS#, CAS#, WE#, etc. In this implementation, by using the clock signal line as a reference for equal-length constraint on the command signal line between the control chip and the first memory, the command signal line can also meet timing requirements.

[0058] In one optional embodiment, the electronic device further includes a second memory of the same type as the first memory. The length of the data signal line between the control chip and the second memory matches a second reference length, wherein the second reference length is the length of the clock signal line between the control chip and the second memory. The second memory and the first memory are located on opposite sides of a PCB board, with the second memory located on the back of the first memory. The chip select pins of the first memory and the second memory are respectively connected to different GPIO pins of the control chip, and the first memory and the second memory operate in a time-sharing manner. The data signal pins of the control chip are simultaneously connected to the data signal pins of both the first memory and the second memory.

[0059] In this configuration, the chip select pins of the first and second memories are connected to different GPIO pins of the control chip. By outputting different chip select signals from different GPIO pins of the control chip, the two memories can be controlled to operate in a time-sharing manner. In a specific implementation, the chip select pin of the DDR memory can be the CS# pin.

[0060] In this embodiment, by setting two memory devices stacked on opposite sides of the PCB board in the electronic device, the fan-out from the via to the two memory devices is very short and symmetrically distributed, which can reduce the stub size and increase the capacity.

[0061] In one optional implementation, the number of first memories is at least two, the sum of the data bit widths of all first memories is equal to the data bit width of the control chip, the chip select pins of all first memories are connected to the same GPIO pin of the control chip, and the data signal pins of different first memories are respectively connected to different data signal pins of the control chip.

[0062] In a specific example, the electronic device includes two DDRs, each with a 16-bit data width, and the control chip has a 32-bit data width. In this embodiment, when the data width of the first memory is smaller than the data width of the control chip, the data width of the control chip can be adjusted by setting multiple first memories and having the control chip simultaneously select these first memories through the same GPIO pin. It should be noted that the data signal pins of the control chip and the data signal pins of the first memory are connected point-to-point.

[0063] In one optional embodiment, the control signal pins of the control chip are sequentially connected to the control signal pins of the first memory arranged in sequence; the command signal pins of the control chip are sequentially connected to the command signal pins of the first memory arranged in sequence; and the address signal pins of the control chip are sequentially connected to the address signal pins of the first memory arranged in sequence. In this embodiment, the control signal pins of the control chip are not connected to the control signal pins of the multiple first memory locations, the command signal pins of the control chip are not connected to the command signal pins of the multiple first memory locations, and the address signal pins of the control chip are not connected to the address signal pins of the multiple first memory locations. See the following for details. Figure 6 The connection relationship.

[0064] In one optional embodiment, the control signal pins of the control chip and the control signal pins of different first memories are all connected to the first pad, and the distance between the first pad and the control signal pins of different first memories is the same.

[0065] In one optional embodiment, the command signal pins of the control chip and the command signal pins of different first memories are all connected to the second pad, and the distance between the second pad and the command signal pins of different first memories is the same.

[0066] In one optional embodiment, the address signal pins of the control chip and the address signal pins of different first memories are all connected to a third pad, and the distance between the third pad and the address signal pins of different first memories is the same.

[0067] In the above embodiments, by setting the pads connecting different control signal pins, different command signal pins, or different address signal pins to be at the same distance from the corresponding pins of different memories, the speed of accessing different memories can be made the same.

[0068] In one alternative implementation, all first memories are located on the same side of the PCB board. In this embodiment, all first memories used to implement the data bit width of the control chip are located on the same side of the PCB board.

[0069] In one optional embodiment, the winding spacing of the differential signal lines in the electronic device is twice the line width. In another optional embodiment, the winding length of the differential signal lines in the electronic device is three times the line width.

[0070] In a specific example, if the line width of the differential signal line is W, the winding spacing is h, and the winding length is L, then: h = 2W, L = 3W. This setting can make the impedance of the differential signal line continuous, thereby obtaining a clear eye diagram and avoiding data packet loss.

[0071] In one optional embodiment, the projection of the data signal lines between the control chip and the first memory onto the adjacent ground plane falls on the ground plane, and the projection of the control signal lines and / or command signal lines between the control chip and the first memory onto the adjacent ground plane falls on the power plane. In this embodiment, the data signal lines between the control chip and the first memory use the ground plane as the reference plane, and the control signal lines and / or command signal lines between the control chip and the first memory use the power plane as the reference plane.

[0072] In one optional implementation, for different signal lines located on the same layer of the PCB board between the control chip and the first memory, the distance between the layer containing the signal line and the nearest adjacent layer is greater than or equal to three times the thickness of the insulating medium. In this implementation, by setting the distance between the layer containing the signal line and the nearest adjacent layer to be greater than or equal to three times the thickness of the insulating medium, crosstalk between different signal lines located on the same layer of the PCB board can be effectively avoided.

[0073] The electronic device provided in the embodiments of this disclosure will be described in detail below through specific examples.

[0074] Figure 1 This is a single-channel signal connection between the CPU and two DDR3 chips, using a typical point-to-point connection. DQS0, DQ0-DQ15, and DM1 form the lower 16 data lines, connecting the CPU and DDR3 chip U2 point-to-point. They are constrained by length (tolerance) based on DQS; the specific tolerances for these constraints should be found in the datasheets of the CPU, DSP, FPGA, GPU, etc. DQS1, DQ16-DQ31, and DM2 form the higher 16 data lines, connecting the CPU and DDR3 chip U3 point-to-point. They are also constrained by length (tolerance) based on DQS; the specific tolerances for these constraints should be found in the datasheets of the CPU, DSP, FPGA, GPU, etc. DQS is a differential line, with a tolerance of ±5mil within each differential pair. They use CLK as the reference for equal length constraints (i.e., tolerances). The specific tolerances for equal length constraints should be based on the datasheets of the CPU, DSP, FPGA, GPU, and other devices. If a DDR3 system has two clock signals, both clock signals must be subject to equal length constraints. DQS uses both clock signals for equal length constraints.

[0075] DDR3 can be divided into 4-bit, 8-bit, and 16-bit based on its bit width. If the DDR3 controller in the CPU has a bit width of 32 bits, it can choose to connect eight 4-bit DDR3 chips, four 8-bit DDR3 chips, or two 16-bit DDR3 chips.

[0076] Figure 2 A topology diagram showing the data lines of the DDR3 memory chip and the CPU is provided. It should be noted that... Figure 2 The main control chip in it is a CPU, but in practical applications it can also be replaced with a DSP or FPGA control chip.

[0077] like Figure 2 As shown, the DDR3 data line has a point-to-point structure. If the CPU has a 16-bit bit width, it can only support one DDR3 chip. To support two DDR3 chips, a DDR3 chip can be placed on the back of the front DDR3 chip, with the two chips facing opposite directions. This results in a very short fan-out from the via to the pins of the two DDR3 chips, and they are symmetrically distributed. Because DDR speeds are very high, this design results in a very small stub, minimizing the impact on signal integrity. This design can expand the capacity of external DDR3 chips on the CPU, but it requires an additional CS pin for the chip select signal of the other DDR3 chip. In this case, a 16-bit CPU can support two external DDR3 chips, increasing capacity without increasing the bit width (remaining 16-bit). This topology requires time-sharing of the DDR memory in software. Specifically, the two DDR3 chips cannot work simultaneously; the increased capacity is controlled by two CS chip select signals: when one DDR3 chip is refreshed, the other is working.

[0078] DDR3 data lines have a point-to-point structure. If the CPU has a 32-bit bit width, it can support two DDR3 chips. The CPU's 32 data lines (16-bit address) are arranged as follows: the high-order 16 data lines support one DDR3 chip, and the low-order 16 data lines support another DDR3 chip. This external DDR3 chip configuration requires only one CS pin. The CPU's CLK, control, and command pins are directly connected in series with the two DDR3 chips. Alternatively, one DDR3 chip can be placed on the back of each of the two front-side DDR3 chips, expanding to four DDR3 chips. However, this requires an additional CS pin for selecting the two back-side DDR3 chips.

[0079] Figure 3A topology diagram of the data lines and data passthrough lines between the DDR3 chips and the CPU is provided. U1 is the main control chip CPU. In practical applications, the main control chip can also be a DSP or FPGA, etc. U2, U3, U4, and U5 are four DDR3 chips. Figure 4 A schematic diagram of the topology of the data lines and data gate lines between DDR3 chips U2 and U3 and the CPU in the vertical direction of the PCB board is given. Figure 5 A schematic diagram of the topology of the data lines and data passthrough lines between the DDR3 chips U4 and U5 and the CPU, shown in the vertical direction on the PCB board, is provided. (Continue reading...) Figure 3-5 The main control chip U1, together with DDR3 chips U2, U3, U4, and U5, forms a complete 32-bit main control chip + DDR3 system; the main control chip U1, together with DDR3 chips U2 and U3, forms the lower 16-bit main control chip + DDR3 system; the main control chip U1, together with DDR3 chips U4 and U5, forms the higher 16-bit main control chip + DDR3 system; the main control chip U1, DDR3 chips U2, and U3 are located on the T layer (TOP layer, i.e., the top layer) of PCB board 103; the main control chip U1, DDR3 chips U4, and U5 are located on the B layer (BOTTOM layer, i.e., the bottom layer) of PCB board 103; the projections of DDR3 chips U2 and U3 in the vertical direction of PCB board 103 are basically overlapping; the projections of DDR3 chips U4 and U5 in the vertical direction of PCB board 103 are also basically overlapping.

[0080] The main control chip U1, together with DDR3 chips U2 and U3, forms the lower 16-bit main control chip and DDR system. Taking DQ0 (DQ0-DQ15, DQS0 / DQS1, CS1 / CS2) as an example, the methods and concepts for DQ1-DQ15, DQS0 / DQS1, and CS1 / CS2 are the same as for DQ0. The pins and pads 73 of the main control chip U1's DQ0 are connected to vias 66 via DQ0 traces 68 on the T layer of the PCB board 103. Via 66 vertically passes through the T layer and inner layers of the PCB board 103 to the B layer. On the T layer of the PCB board 103, via 66 connects to the DQ0 pins and pads 62 of the DDR3 chip U2 via traces 65 and 65, respectively. On the B layer of the PCB board 103, via 66 connects to the DQ0 pins and pads 62 of the DDR3 chip U3 via traces 67 and 67, respectively. The pins and pads 64 are connected; the length of the trace 68 from the pin and pad 73 of the DQ0 of the main control chip U1 to the T-layer DQ0 trace 66 of the via 66 is L1; the length of the trace 65 from the via 66 to the DQ0 pin and pad 62 of the T-layer DDR3 chip U2 is L2, and L1>>L2; the length of the trace 67 from the via 66 to the DQ0 pin and pad 64 of the B-layer DDR3 chip U3 is L3; and L1>>L3. Via 66 is positioned close to the DQ0 pin and pad 62 of the T-layer DDR3 chip U2 and the DQ0 pin and pad 64 of the B-layer DDR3 chip U3. In other words, via 66 is positioned at the center between the DQ0 pin and pad 62 of the T-layer DDR3 chip U2 and the DQ0 pin and pad 64 of the B-layer DDR3 chip U3, ensuring that L2 and L3 are approximately equal, while strictly controlling the lengths of L2 and L3.

[0081] The chip select CS1 pin and pad 72 of the main control chip U1 are connected to via 100. Via 100 is connected to via 69 near the CS pin and pad 61 of the DDR3 chip U2 through the inner layer trace 75 of the PCB board 103. Via 69 runs through the T layer, inner layer and B layer of the PCB board 103. The CS pin and pad 61 of the DDR3 chip U2 on the T layer are connected to via 69 through the T layer trace 70.

[0082] The chip select CS2 pin and pad 71 of the main control chip U1 are connected to via 101. Via 101 is connected to via 74 near the CS pin and pad 63 of the DDR3 chip U3 through the inner layer trace 76 of the PCB board 103. Via 74 passes through the T layer, inner layer and B layer of the PCB board 103. The CS pin and pad 63 of the DDR3 chip U3 on the B layer are connected to via 74 through the trace 77 of the B layer.

[0083] Continue reading Figure 3-5The main control chip U1, together with DDR3 chips U4 and U5, forms a high 16-bit main control chip + DDR system. Taking DQ16 (DQ16-DQ31, DQ2 / DQ3, CS1 / CS2) as an example, the method and approach for DQ17-DQ32, DQ2 / DQ3, and CS1 / CS2 are the same. The DSQ0 pin and pad 84 of the main control chip U1 are connected to via 86 via a DQ16 trace 88 on the T layer of the PCB board 103. The via 86 vertically passes through the T layer and inner layers of the PCB board 103 to the B layer. The via 86 connects to the DQ16 pin and pad 82 of the DDR3 chip U4 via a trace 85 on the T layer of the PCB board 103. The via 86 connects to the DQ16 pin and pad 82 of the DDR3 chip U4 via a trace 87 on the B layer of the PCB board 103. The pin and pad 84 are connected; the length of the trace 88 from the pin and pad 84 of the main control chip U1 to the T-layer DQ16 trace 88 of via 686 is L4; the length of the trace 85 from the via 86 to the T-layer DQ16 pin and pad 82 of the T-layer DDR3 chip U4 is L5, and L4 >> L5; the length of the trace 87 from the via 86 to the B-layer DQ16 pin and pad 84 of the B-layer DDR3 chip U5 is L6; and L4 >> L6. Via 86 is positioned close to the DQ16 pin and pad 82 of the T-layer DDR3 chip U4 and the DQ16 pin and pad 84 of the B-layer DDR3 chip U5. In other words, via 86 is positioned at the center between the DQ16 pin and pad 82 of the T-layer DDR3 chip U4 and the DQ16 pin and pad 84 of the B-layer DDR3 chip U5, ensuring that L5 and L6 are approximately equal, while strictly controlling the lengths of L5 and L6.

[0084] A via 78 is placed near the CS pin and pad 81 of the DDR3 chip U4. The via 78 passes through the T layer, inner layer and B layer of the PCB board 103. The CS pin and pad 81 of the DDR3 chip U4 on the T layer are connected to the via 78 through the T layer trace 90. The via 78 is then connected to the via 69 through the inner layer trace 175. In other words, the chip select CS1 pin and pad 72 of the main control chip U1 are connected to the CS pin and pad 61 of the DDR3 chip U2 through the via 100, the inner layer trace 75, the via 69 and the T layer trace 70. The chip select CS1 pin and pad 72 of the main control chip U1 are connected to the CS pin and pad 81 of the DDR3 chip U4 on the T layer through the via 100, the inner layer trace 75, the via 69, the inner layer trace 175 and the via 78 and the T layer trace 177. That is, the chip select CS1 pin and pad 72 of the main control chip U1 are connected to the CS pin and pad 61 of the T-layer DDR3 chip U2 and the CS pin and pad 81 of the T-layer DDR3 chip U4.

[0085] A via 89 is provided near the CS pin and pad 83 of the DDR3 chip U5. The via 89 passes through the T layer, inner layer and B layer of the PCB board 103. The CS pin and pad 83 of the DDR3 chip U5 on the T layer are connected to the via 89 through the T layer trace 177; and the via 89 is then connected to the via 74 through the inner layer trace 176.

[0086] In other words, the chip select CS2 pin and pad 71 of the main control chip U1 are connected to the CS pin and pad 63 of the B-layer DDR3 chip U3 through via 101, inner layer trace 76, via 74, and B-layer trace 77. Meanwhile, the chip select CS1 pin and pad 72 of the main control chip U1 are connected to the CS pin and pad 83 of the B-layer DDR3 chip U5 through via 101, inner layer trace 76, via 74, inner layer trace 176, via 89, and B-layer trace 177. In other words, the chip select CS2 pin and pad 71 of the main control chip U1 are connected together with the CS pin and pad 63 of the B-layer DDR3 chip U3 and the CS pin and pad 83 of the B-layer DDR3 chip U5.

[0087] A high level is enabled for the CS select pin and pad 61 of DDR3 chip U2, the CS select pin and pad 63 of DDR3 chip U3, the CS select pin and pad 81 of DDR3 chip U4, and the CS select pin and pad 83 of DDR3 chip U5, while a low level is enabled for the CS select pin and pad 61 of DDR3 chip U2, the CS select pin and pad 63 of DDR3 chip U3, the CS select pin and pad 81 of DDR3 chip U4, and the CS select pin and pad 83 of DDR3 chip U5.

[0088] When the chip select CS pin and pad 72 of the main control chip U1 are high, the chip select CS pin and pad 71 of the main control chip U1 are low. The CS pin and pad 61 of the T-layer DDR3 chip U2 and the CS pin and pad 81 of the T-layer DDR3 chip U4 are momentarily pulled high. At this time, data communication occurs between the DQ0~DQ15, DQS0 / DQS1, and CS (lower 16 bits) of the main control chip U1 and the DQ0~DQ15, DQS0 / DQS1, and CS (lower 16 bits) of the T-layer U2. Data communication occurs between DQ16-DQ31, DQ2 / DQ3, and CS2 (high 16 bits) of U1 and DQ16-DQ31, DQ2 / DQ3, and CS2 (high 16 bits) of T-layer U4. Meanwhile, when the CS pin and pad 63 of B-layer DDR3 chip U3 and the CS pin and pad 83 of B-layer DDR3 chip U5 are momentarily pulled low, B-layer DDR3 chip U3 and B-layer DDR3 chip U5 are in a disabled state, meaning they do not work at this time.

[0089] When the chip select CS pin and pad 71 of the main control chip U1 are high, the chip select CS pin and pad 72 of the main control chip U1 are low. The CS pin and pad 63 of the B-layer DDR3 chip U3 and the CS pin and pad 83 of the B-layer DDR3 chip U5 are momentarily pulled high. At this time, data communication occurs between the DQ0~DQ15, DQS0 / DQS1, and CS (lower 16 bits) of the main control chip U1 and the DQ0~DQ15, DQS0 / DQS1, and CS (lower 16 bits) of the B-layer U3. Data communication occurs between DQ16-DQ31, DQ2 / DQ3, and CS2 (high 16 bits) of U1 and DQ16-DQ31, DQ2 / DQ3, and CS2 (high 16 bits) of U5 in layer B. When the CS pin and pad 61 of DDR3 chip U2 in layer T and the CS pin and pad 81 of DDR3 chip U4 in layer T are momentarily pulled low, DDR3 chips U2 and U4 in layer T are in an inactive state, meaning they do not work at this time.

[0090] When the main control chip U1 sends a chip select signal CS1 through the chip select CS pin and pad 72 to select the T-layer DDR3 chip U2 and T-layer DDR3 chip U4 to work, the DQ0 pin and pad 73 of U1 communicate with the DDR3 chip U2 through the T-layer DQ0 trace 68, via 66, trace 65, and the DQ0 pin and pad 62 of the DDR3 chip U2. At this time, the DDR3 chip U3 is not working, and the via 66 is connected to the DQ0 pin and pad 64 of the DDR3 chip U3 through the B-layer trace 67. The B-layer trace 67 is equivalent to a redundant trace, which has an antenna effect. Moreover, the transmission rate of DQ0 is very high, which can easily cause abnormalities such as overshoot, backtracking, and ringing of the DQ0 signal. Therefore, the length of L3 must be strictly controlled, preferably L3≤5mm.

[0091] The DQ16 pin and pad 84 of U1 communicate with the DDR3 chip U4 via the DQ16 trace 88, via 86, trace 85, and the DQ16 pin and pad 82 of the DDR3 chip U4. At this time, the DDR3 chip U5 is not working. The via 86 is connected to the DQ16 pin and pad 84 of the DDR3 chip U5 via the B-layer trace 87. The B-layer trace 87 is equivalent to a redundant trace, which has an antenna effect. Moreover, the transmission rate of DQ16 is very high, which can easily cause abnormalities such as overshoot, backtracking, and ringing of the DQ16 signal. Therefore, the length of L6 must be strictly controlled, preferably L6≤5mm.

[0092] When the main control chip U1 sends a chip select signal CS2 through the chip select CS pin and pad 71 to select the B-layer DDR3 chip U3 and B-layer DDR3 chip U5 to work, the DQ0 pin and pad 73 of U1 communicates with the DDR3 chip U3 through the T-layer DQ0 trace 68, via 66, B-layer trace 67, and the DQ0 pin and pad 64 of the DDR3 chip U3. At this time, the DDR3 chip U2 is not working, and the via 66 is connected to the DQ0 pin and pad 62 of the DDR3 chip U2 through the T-layer trace 65. The T-layer trace 65 is equivalent to a redundant trace, which has an antenna effect. Moreover, the transmission rate of DQ0 is very high, which can easily cause abnormalities such as overshoot, backtracking, and ringing of the DQ0 signal. Therefore, the length of L2 must be strictly controlled, preferably L2≤5mm.

[0093] The DQ16 pin and pad 84 of U1 communicate with the DDR3 chip U5 via the T-layer DQ16 trace 88, via 86, B-layer trace 87, and the DQ16 pin and pad 84 of the DDR3 chip U5. At this time, the DDR3 chip U4 is not working. The via 86 is connected to the DQ16 pin and pad 82 of the DDR3 chip U4 via the T-layer trace 85. The T-layer trace 85 is equivalent to a redundant trace, which has an antenna effect. Moreover, the transmission rate of DQ16 is very high, which can easily cause abnormalities such as overshoot, backtracking, and ringing of the DQ16 signal. Therefore, the length of L5 must be strictly controlled, preferably L5≤5mm.

[0094] Under the control of chip select signal CS1, the main control chip U1, together with DDR3 chips U2 (low 16 bits) and U4 (high 16 bits), forms a 32-bit system; under the control of chip select signal CS2, the main control chip U1, together with DDR3 chips U3 (low 16 bits) and U5 (high 16 bits), forms a 32-bit system. This mode not only expands the bandwidth of the main control chip U1 from 16-bit to 32-bit access to DDR3 chips, but also enables the main control chip U1 to efficiently handle complex mathematical operations, support larger-scale software projects and complex data structures, etc., and is widely used in high-end consumer electronics products (such as smartphones and tablets) and high-performance computing fields (such as the Internet of Things and image processing). Simultaneously, the selection modes using chip select signals CS1 and CS2 enable single-channel dynamic memory with more than double the capacity.

[0095] Figure 6 The topology of the actual PCB layout and routing for an ARM architecture CPU and DDR3 chips is presented. Control signals, address / command signals, and clock signals are routed using a fly-by topology.

[0096] The control signals are single-wire, and they are constrained by equal length (i.e., tolerance) based on CLK1. The specific tolerance of the equal length constraint should be based on the datasheet of the main control chip U1, such as the CPU, DSP, FPGA, or GPU. If it is a DDR3 memory module that comes with an x86 platform, there are two pairs of differential clocks. Both pairs of differential clocks also need to be constrained by equal length, and the tolerance range for the two pairs of differential clocks is ±20mil.

[0097] Address and command signals are single-wire, and they are constrained to the same length based on CLK1 or CLK2. The specific tolerance for this constraint should be based on the datasheet of the CPU, DSP, FPGA, GPU, or other main control chip U1. For DDR3 memory modules on x86 platforms, which have two pairs of differential clocks, these pairs also require equal-length constraints, with a tolerance range of ±20mil.

[0098] DQS stands for Differential Lines, and the tolerance within a DQS differential pair is ±5mil. They are constrained to the same length based on CLK1 or CLK2. The specific tolerance for this constraint should be based on the datasheet of the CPU, DSP, FPGA, GPU, or other main control chip U1. For DDR3 memory modules on an x86 platform, which have two pairs of differential clocks, both pairs also require equal-length constraints, with a tolerance range of ±20mil.

[0099] The DDR3 control signals consist of: DDR_BA1, Ddr_Ba0, Ddr_Ba2, DDR_RST_N, Ddr_Cke, Ddr_Rasn, Ddr_Casn, Ddr_Wen, Ddr_Cs_N, and Ddr_Odt.

[0100] The DDR3 address / command signals consist of: ADDR0 to ADDR15, BA0, BA1, BA2, CAS, RAS, and WE, where ADDR0 to ADDR15 are 16 groups of address signals.

[0101] Using the A22 to B22 traces in CLK as the length equalization basis (or the A23 to B23 traces as the length equalization basis, with a ±5mil length equalization constraint between differential clocks), the A1 to B1 traces...A21 to B21 traces meet the tolerance requirements, that is, the address / command signals from the main control chip to DDR3 chip 1 are of equal length. This tolerance is based on the specifications of the main control chips such as CPU, DSP, and FPGA.

[0102] Using the A22 to C22 traces in CLK as the basis for equal length (or the A23 to C23 traces as the basis for equal length, with a ±5mil equal length constraint between differential clocks), the traces from A1 to C1... and from A21 to C21 meet the tolerance requirements, that is, the address / command signals from the main control chip CPU to DDR3 chip 2 are of equal length. This tolerance is based on the specifications of the main control chips such as CPU, DSP, and FPGA.

[0103] Using the A22 to B22 traces in CLK as the basis for equal length (or the A23 to B23 traces as the basis for equal length, with a ±5mil equal length constraint between differential clocks), the A24 to B24 traces...A26 to B26 traces meet the tolerance requirements, that is, the control signals from the main control chip to DDR3 chip 1 are of equal length. This tolerance is based on the specifications of the main control chips such as CPU, DSP, and FPGA.

[0104] Using the A22 to C22 trace in CLK as the length equalization basis (or the A23 to C23 trace as the length equalization basis, with a ±5mil length equalization constraint between differential clocks), the traces from A24 to C24... to A26 to C26 meet the tolerance requirements, that is, the control signals from the main control chip to DDR3 chip 2 are of equal length. This tolerance is based on the specifications of the main control chips such as CPU, DSP, and FPGA. Table 1 gives the ARM architecture CPU and DDR3 signals and their functional descriptions.

[0105] Table 1. Description of ARM architecture CPU and DDR3 signals and their functions.

[0106]

[0107]

[0108] Here's an example of setting equal-length rules for DDR3 memory on an Intel x86 platform security memory motherboard:

[0109] When routing two memory modules (DDR3) on the PCB, the routing requirements are as follows:

[0110] Regarding the routing requirements between bus lines: Within a group of buses of equal length, all bus lines from Memory 1 to the CPU must be of equal length with an error margin of 10 mil; similarly, all bus lines from Memory 2 to the CPU must be of equal length with an error margin of 10 mil. Taking two routes within a group of buses as an example, refer to... Figure 7 Assume the distance from A to C is equal to the distance from A' to C', and the inter-group error is set to 10 mil; assume the distance from B to C is equal to the distance from B' to C, and the inter-group error is set to 10 mil. The specific rules are as follows: Figure 8 As shown. The trace length between memory 1 and memory 2 should be between 425 and 525 mils, and cannot exceed 100 mils. Specific rules are as follows: Figure 9 As shown.

[0111] There is a requirement that DQS and CLK be of equal length: (CLK + 1500mil) > DQS > (CLK - 2500mil); the settings are as follows:

[0112] First, we need to calculate the offset and error:

[0113] Offset: [1500mil + (-2500mil)] / 2 = -1000mil / 2 = -500mil;

[0114] Length error: [1500mil - (-2500mil)] / 2 = 4000mil / 2 = 2000mil;

[0115] Input the above calculated values ​​as follows: Figure 10 The rules shown are sufficient; this rule compares the length of CLK, so this rule must also be added to CLK. The rules for setting the longest and shortest traces are as follows: Figure 11 As shown.

[0116] Regarding differential routing requirements: A group of BUS lines contains two sets of differential lines. The differential lines are of equal length to other BUS lines, with an error range of 10 mil. The requirement for equal length within a differential line pair is as follows: The differential pair between memory 1 and memory 2 has an equal length of 2 mil. Assume the error between A to B and A' to B' is 2 mil; assume B to C and B' to C are of equal length, with an inter-pair error of 2 mil.

[0117] In principle, DDR3 address, command, and control signals use the DDR3 power plane as the reference plane. In rare cases, however, some DDR3 address, command, and control signals may use the GND plane as the reference plane. The DQ, DQS, and DM signals must use the GND plane as the reference plane.

[0118] Table 2 lists the relevant parameters of DDR3 chips and memory modules as specified by the JEDEC standard. As shown in Table 2, the differential clock frequency for DDR3-800 is 400MHz, and for DDR3-1600 it is 800MHz. The clock, data, address / control, and command signals of DDR3 are all at very high speeds, and in principle, strict impedance control is necessary to prevent signal reflections that could cause malfunctions in the CPU+DDR3 system. Based on current market applications, DDR3 memory can be broadly categorized into three types.

[0119] Table 2 shows the relevant parameters of DDR3 chips and memory modules as specified in the JEDEC standard.

[0120]

[0121] Category 1: DDR3 impedance design based on a general-purpose platform

[0122] For high-frequency, high-speed signals, there are three universal impedance types worldwide: 50 ohms for single-wire signals (e.g., RF signals), 75 ohms for single-wire signals (e.g., VGA signals), and 100 ohms for differential signals. The impedance of DDR3 on universal platforms also follows this principle: 50 ohms for single-wire signals: data lines (DQ), address / control lines, and command lines; 100 ohms for differential signals: DQS and differential clock signals.

[0123] For example, in a server designed based on an ARM architecture processor from Calxeda, a single DDR3 line is 50 ohms: data line DQ, address / control line, and command line; a differential line is 100 ohms: DQS and differential clock.

[0124] For example, in a server designed based on Marvell's ARM architecture processor, a single DDR3 line is 50 ohms: data line DQ, address / control line, and command line; a differential line is 100 ohms: DQS and differential clock.

[0125] The second category is impedance design based on the Intel x86 platform.

[0126] The impedance design of DDR3 on the Intel x86 platform is different from the industry standard impedance. Sometimes the impedance design varies for each x86 platform. Please refer to the manual of the platform for specific details.

[0127] For example, the DQS and differential clock impedance of DDR3 is 65 ohms. The impedances of DQS and differential clock are not mentioned further; we will only provide the line width and spacing for DQS and differential clock. The impact of layer stacking on this impedance will not be considered. A single line (data line DQ, address / control, command) has an impedance of 55 ohms, and there are also other impedances of 45 ohms, etc. Please refer to the platform's manual for specific details.

[0128] The third category involves impedance design for DDR3 in consumer electronics products based on ARM or MIPS platforms.

[0129] Consumer electronics products based on the ARM platform mainly include routers, switches, set-top boxes, and smart gateways, while those based on the MIPS platform mainly include set-top boxes. For cost reasons, in consumer electronics, ARM CPUs + DDR3 chips (MIPS CPUs + DDR3 chips) do not perform impedance control on the 50-ohm single lines of the DDR3 data lines (DQ, address / control, and command lines); the CPU handles this internally. For example, low-cost two-layer boards cannot perform impedance control, so it can be omitted. However, DQS and differential clock signals must be strictly controlled to 100 ohms. Figure 12 The calculated impedance of 100 ohms for a two-layer plate with a thickness of 1.2 mm is given.

[0130] DDR3 operates at a very high speed. DDR3 is divided into 6 signal groups: data line DQ, address line, control line, command line, DQS, and differential clock. There is crosstalk between signals within each group and between signals between different groups. Therefore, strictly controlling the spacing between them according to the CPU's manual or reference design is necessary to avoid crosstalk problems.

[0131] This example uses a set-top box composed of a Hisilicon CPU and DDR3 memory chips. The following settings are made for different DDR signals on the same layer:

[0132] The distance between the DQS signal and the DQ signal is set to 12 mil;

[0133] The distance between DQ signals is set to 12 mil;

[0134] The distance between the DQ signal and the CLK signal is set to 24 mil;

[0135] The distance between the address signal and the CLK signal is set to 24 mil;

[0136] The distance between address signals is set to 12 mil.

[0137] The voltage values ​​for the DDR-related reference power supply are shown below:

[0138] The SDRAM reference power supply is 3.3V;

[0139] The DDR1 reference power supply is 2.5V;

[0140] The DDR2 reference power supply is 1.8V;

[0141] The DDR3 reference power supply is 1.5V;

[0142] The DDR4 reference power supply is 1.2V.

[0143] The difference in clock signals between x86 CPU + DDR3 and consumer ARM CPU + DDR3: Because x86 CPUs typically come with DDR3 memory modules, and these modules contain a large number of DDR3 chips, a single pair of differential clocks would have very limited driving capability. Therefore, two pairs of differential clocks are used, greatly enhancing the ability of the differential clocks to drive multiple DDR3 chips. In contrast, consumer products (such as set-top boxes, routers, PONs, and switches) generally use ARM architecture, where the CPU typically supports only one or two DDR3 chips. A single pair of differential clocks is sufficient to drive one or two DDR3 chips.

[0144] Industrial or medical motherboards on the x86 platform typically use two independent DDR3 channels to increase their data processing capabilities, while servers usually have four or more independent DDR3 channels. However, consumer ARM CPUs with DDR3 are different; they have limited data processing capacity and, due to cost considerations, generally only use a single-channel DDR3.

[0145] For DM signals, DDR3 chips have a 16-bit bandwidth. When only 8 bits need to be read, the extra 8 bits can be masked. For example, when only the high 8 bits of data need to be read, the low 8 bits can be masked.

[0146] For applications with extremely stringent reliability requirements (such as industrial, aerospace, marine motherboards, or server motherboards), an additional set of DDR3 chips with ECC functionality must be added. ECC, or error correction, corrects data errors on normally functioning DDR3 chips. A standard hardware configuration includes eight DDR3 chips and one DDR3 chip with ECC functionality.

[0147] Figure 13 A schematic diagram of the data line layout between the main control chip and a single DDR3 chip is provided. Taking only the DQ0 to DQ7 data lines as an example, traces 1 to 10 are led out from the pins and pads a1 to a10 of the main control chip 101. Traces 1 to 10 connect from the pins and pads a1 to a10 of the main control chip 101 to the pins and pads e1 to e10 of the DDR3 chip 200, respectively. Traces 1 to 8 transmit data information for DQ0 to DQ7, while traces 9 and 10 transmit data information for DSQ0 and DQS1, respectively. The lengths of traces 1 to 8 are equalized with reference to the lengths of traces 9 and 10; that is, the lengths of DQ0 to DQ7 are equalized with reference to DQS0 to DQS1, satisfying relevant timing requirements. Because if the traces 1 to 10 from the pins and pads a1 to a10 of the main control chip 101 to the pins and pads e1 to e10 of the DDR3 chip 200 are all straight lines, the lengths of traces 1 to 10 will be different. Therefore, a setting is made in traces 1 to 10. The purpose of using trace 0 as the equal-length trace is to ensure that the lengths of traces 1 through 10 remain consistent, and to maintain timing synchronization between the data of DQ0 through DQ7 and DSQ0 and DQS1 during high-speed flipping, thus preventing timing errors. Which trace among traces 1 through 10 is shorter needs to be set. The more zeros a shape has, the more it can be controlled by setting... The shape of the trace 0 is used to compensate for the length of the shorter traces among traces 1 to 10.

[0148] Figure 14A partial layout and routing diagram of the control lines or command lines between the main controller chip and a single DDR3 chip is provided. The main controller chip 101 is packaged in a BGA package or a dual-row QFN package or a triple-row QFN package. It is not possible to bring out all the lead wires of the connection pins and pads between the main controller chip 101 and the DDR3 chip. Therefore, it is necessary to run short traces and drill holes (i.e., fan-out) near the pins and pads inside the BGA package (or dual-row QFN package or triple-row QFN package). Multiple short traces 51 are led out from the pins and pads b1-b8 of the main control chip 101. A via 21 is placed near each short trace 51, and each short trace 51 is connected to an individual via 21. Each individual via 21 runs vertically from the T layer to the B layer on the PCB board 103. Traces 110-117 are led out from the inner layer of each individual via 21, and these traces 110-117 are connected to the pins and pads f1-f8 of the DDR3 chip 200. Traces 110-117 are used to transmit control or command signals. The lengths of the control or command signal lines are equal to the clock line to meet timing requirements. If the traces 110-117 on the pins and pads b1-b8 of the DDR3 chip 200 were all straight lines, their lengths would be different. Therefore, a via 21 is set within the traces 110-117. The purpose of routing 0 with equal length is to ensure that the lengths of routing 110 to 117 are consistent, and to keep the control signal or command signal synchronized with the clock during high-speed switching, so as to avoid timing errors.

[0149] Figure 15 A schematic diagram of the data line layout for a dual-channel configuration consisting of a main control chip and two DDR3 chips is provided. The dual-channel configuration is illustrated using only the DQ0 to DQ9 data lines as an example. The pins and pads a1 to a10 of the main control chip 101 are respectively led out to traces 1 to 10. Traces 1 to 10 connect from pins a1 to a10 of the main control chip 101 to the pins and pads e1 to e10 of the DDR3 chip 200, respectively. Traces 1 to 10 transmit data from DQ0 to DQ9, while traces 9 and 10 transmit data from DSQ0 and DQS1, respectively.

[0150] The pins and pads a11-a20 of the main control chip 101 are respectively led out to traces 11-20. Traces 11-20 connect from the pins and pads a11-a20 of the main control chip 101 to the pins and pads e1-e10 of the DDR3 chip 201. Traces 11-18 transmit data for DQ16-DQ23, while traces 19-20 transmit data for DSQ1 and DQS2 respectively. The lengths of traces 11-18 are equal to the lengths of traces 19 and 20. Because if all traces 11-20 from the pins and pads a11-a20 of the main control chip 101 to the pins and pads e1-e10 of the DDR3 chip 201 were straight lines, the lengths of traces 11-20 would be inconsistent. Therefore, traces 11-20 are configured with... The purpose of setting trace 0 to be of equal length is to ensure that traces 11 to 20 maintain a consistent length and to ensure that the data from DQ16 to DQ23 remains synchronized with DSQ1 and DQS2 during high-speed flipping, thus preventing timing errors. Which trace among traces 11 to 20 is shorter needs to be set. The more zeros a shape has, the more it can be controlled by setting... The shape of the trace 0 is used to compensate for the length of shorter traces.

[0151] See Figure 15 The main control chip 101 has two built-in independent DDR3 controllers. These controllers have pins and pads a1-a10 and a11-a20 respectively. Pins and pads a1-a10 of the main control chip 101 are used to connect with pins and pads e1-e10 of the DDR3 chip 200, and pins and pads a11-a20 of the main control chip 101 are used to connect with pins and pads e1-e10 of the DDR3 chip 201. In other words, the data (DQ), data strobe (DQS), clock (CLK), control, and command signal lines between the main control chip 101 and the DDR3 chip 200 are all independent. The lengths of the data (DQ), data strobe (DQS), control, and command signal lines between the main controller chip 101 and the DDR3 chip 200 are determined indirectly or directly with reference to the clock (CLK1) line between the main controller chip 101 and the DDR3 chip 200. The lengths of the data (DQ), data strobe (DQS), control, and command signal lines between the main controller chip 101 and the DDR3 chip 201 are also determined indirectly or directly with reference to the clock (CLK2) line between the main controller chip 101 and the DDR3 chip 201. They are independent of each other, and there is no length constraint between the main controller chip 101 and the DDR3 chip 200, or between the main controller chip 101 and the DDR3 chip 201.

[0152] and Figure 13 , Figure 14 The comparison shows a single-channel DDR3 system composed of the main control chip 101 and the DDR3 chip 200. Figure 15 The main control chip 101 shown, together with DDR3 chips 200 and DDR3 chips 201, forms a dual-channel DDR3 system. The dual-channel DDR3 system has the following two advantages:

[0153] First, data transfer efficiency: Dual-channel memory offers higher memory bandwidth, theoretically achieving higher data transfer efficiency than single-channel memory. This is because dual-channel memory allows read and write operations to use different channels, enabling simultaneous read and write operations and effectively doubling the memory bandwidth. In practical applications, this can significantly improve the performance of software that frequently exchanges data with memory.

[0154] Secondly, multitasking capabilities: Dual-channel memory significantly reduces memory latency and improves system performance during multitasking and the operation of large applications. This provides a smoother experience for users such as gamers, video editors, and 3D renderers who need to process large amounts of data and handle high-load tasks.

[0155] In practice, the aforementioned electronic devices can be dashcams, Wifi5 / Wifi6 / Wifi7 routers, mobile phones, VR / AR products, tablets, laptops, industrial computers, medical equipment, servers, 100G switches, wireless base station motherboards, etc.

[0156] The following is the testing process for an embodiment of this disclosure:

[0157] To demonstrate the rationality and practicality of the electronic device with memory provided in the above embodiments, taking the application of a 4-layer substrate in a cellular 5G+Wifi7 industrial router as an example, EMI radiation tests were conducted on the cellular 5G and Wifi7 industrial routers. The EMI radiation test and analysis process is given below.

[0158] EMI radiation is an important EMC test indicator in EU CE certification, China 3C certification, and North American FCC certification. This document primarily uses a complete solar energy device as an example to illustrate its performance testing. Both the RE radiation test standard and the CE conducted emission test standard adopt EN55022 2008 / GB9254 2008, testing the 0.15MHz~0.5MHz, 0.5MHz~30MHz, 30MHz~1GHz, and 1GHz~6GHz frequency bands of the vehicle-mounted wireless equipment. These frequency bands all meet the Class B testing requirements of the EN55022 2008 / GB9254 2008 standard. Figure 16The radiation values emitted in the 30 MHz to 1 GHz test frequency band of the entire cellular 5G and Wifi7 industrial routers are given. Figure 16 In Figure 16 , what A refers to is the safety limit of the 3C certification standard. Being lower than this safety limit is considered qualified; what B refers to is the fluctuation curve of the radiation data of the tested product. From Figure 16 it can be seen that line B is far from line A, that is to say, it is much smaller than the safety standard value, indicating that the EMI radiation index is well controlled. That is, an electronic device with a memory provided in this embodiment of the present disclosure has no impact on the radiation of the entire product.

[0159] Although the specific implementation manners of the present disclosure have been described above, those skilled in the art should understand that this is only an example. The protection scope of the present disclosure is defined by the appended claims. Without departing from the principles and essence of the present disclosure, those skilled in the art can make various changes or modifications to these implementation manners, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. An electronic device with a memory, characterized in that The control chip and the first memory are connected through a data signal line, a clock signal line, a control signal line, a command signal line and an address signal line. The length of the data signal line between the control chip and the first memory matches a first reference length, wherein the first reference length is the length of the clock signal line between the control chip and the first memory. 2.The electronic device of claim 1, wherein, The first memory comprises a data strobe pin and a data signal pin. The data signal line between the control chip and the first memory comprises a first data signal line between the control chip and the data strobe pin and a plurality of second data signal lines between the control chip and the data signal pin. The length of the first data signal line matches the first reference length, and the length of each second data signal line matches the length of the first data signal line. 3.The electronic device of claim 1, wherein, The length of the control signal line between the control chip and the first memory matches the first reference length, and / or, The length of the command signal line between the control chip and the first memory matches the first reference length. 4.The electronic device of claim 1, wherein, The electronic device further comprises a second memory, which is of the same type as the first memory, and the length of the data signal line between the control chip and the second memory matches a second reference length, wherein the second reference length is the length of the clock signal line between the control chip and the second memory. The second memory is located on the other side of the PCB board from the first memory, and the second memory is located on the back of the first memory. The chip select pin of the first memory and the chip select pin of the second memory are respectively connected to different GPIO pins of the control chip, and the first memory and the second memory work in time division mode. The data signal pin of the control chip is connected to the data signal pin of the first memory and the data signal pin of the second memory at the same time. 5.The electronic device of claim 1, wherein, The number of the first memories is at least two, the sum of the data bit widths of all the first memories is equal to the data bit width of the control chip, the chip select pins of all the first memories are connected to the same GPIO pin of the control chip, and the data signal pins of different first memories are respectively connected to different data signal pins of the control chip. 6.The electronic device of claim 5, wherein, The control signal pins of the control chip are sequentially connected to the control signal pins of the first memories arranged in sequence. The command signal pins of the control chip are sequentially connected to the command signal pins of the first memories arranged in sequence. The address signal pins of the control chip are sequentially connected to the address signal pins of the first memories arranged in sequence. 7.The electronic device of claim 5, wherein, The control signal pins of the control chip and the control signal pins of different first memories are connected to a first pad, and the distances between the first pad and the control signal pins of different first memories are consistent. And / or, the command signal pins of the control chip and the command signal pins of different first memories are connected to a second pad, and the distances between the second pad and the command signal pins of different first memories are consistent. And / or, the address signal pins of the control chip and the address signal pins of the different first memories are connected with the third pads, and the distances between the third pads and the address signal pins of the different first memories are consistent. 8.The electronic device of claim 3, wherein, The data signal lines between the control chip and the first memories fall on the projection of the adjacent ground layers on the ground plane, and the control signal lines and / or the command signal lines between the control chip and the first memories fall on the projection of the adjacent ground layers on the power plane. 9.The electronic device of claim 1, wherein, For the different signal lines between the control chip and the first memories on the same layer of the PCB, the distance between the layer where the signal lines are located and the nearest adjacent layer is greater than or equal to 3 times the thickness of the insulating medium. 10.The electronic device of any one of claims 1-9, wherein, The first memories are DDR.

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