Background calibration DRAM PHY ZQ voltage comparator error calibration method and circuit

Abstract

The invention aims to provide a DRAM PHY ZQ voltage comparator error calibration method and circuit for background calibration. The method comprises the following steps: setting state parameters of a first state machine and performing background calibration; and setting the second state machine to perform ZQ calibration according to the calibration result of the first state machine. Through a step-by-step cooperation mechanism of background calibration and ZQ calibration, the calibration time is shorter, the efficiency is high, the control logic is more concise, the calibration result can be reused, and repeated calibration is reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a method and circuit for calibrating the error of a DRAM PHY ZQ voltage comparator in a background calibration manner. Background Technology

[0002] ZQ calibration is an impedance matching technique used in Dynamic Random Access Memory (DRAM) systems, primarily in DDR, LPDDR, and HBM memory systems. Its main purpose is to ensure signal integrity between the memory controller and the DRAM chip. Typically, the PHY implements a ZQ calibration engine designed to match target resistance values ​​to account for the effects of process, voltage, and temperature variations. Due to factors such as analog design quality, process packaging, and temperature and voltage variations during chip operation, voltage comparator results are affected, leading to errors in the comparator calibration results during ZQ calibration. These errors can affect circuits using the calibrated values. Therefore, it is necessary to eliminate these voltage comparator errors during ZQ calibration.

[0003] Existing ZQ calibration methods generally involve a two-stage inverted voltage comparator, averaging the two calibration results, and independently calibrating the voltage comparator before each ZQ calibration. These methods have the following drawbacks: the inverted comparator method has significant time overhead, requiring two calibration cycles to eliminate comparator errors, adding two rounds of overhead. When temperature, voltage, and process conditions change, periodic calibration may be necessary, resulting in fewer calibration cycles within the same time period. The inverted comparator method has a complex control module design, requiring control of the flipping process, processing of the flipped comparison results, and a value calculation for both calibrations. The calibration results cannot be reused; the two-stage PUPD calibration essentially includes an error calibration action, making it impossible to save and reuse these results for future use. Independent voltage comparator calibration performs poorly under conditions of significant environmental variation. Integrating the voltage comparator calibration into the ZQ calibration allows for result reuse. However, the reuse of calibration results depends on the conditions of the previous ZQ calibration. If the interval between two calibration results is long or environmental conditions change significantly, the previous calibration result is unreliable. Each calibration requires performing a voltage comparator calibration operation. Summary of the Invention

[0004] The purpose of this invention is to provide a method and circuit for calibrating the error of a DRAM PHY ZQ voltage comparator with background calibration. This method achieves shorter calibration time, higher efficiency, simpler control logic, and reusable calibration results by using a step-by-step collaborative mechanism of background calibration and ZQ calibration, thereby reducing repeated calibration.

[0005] A method for calibrating the error of a DRAM PHY ZQ voltage comparator in a background calibration manner, comprising: Set the state parameters of the first state machine and perform background calibration; The second state machine is configured to perform ZQ calibration based on the calibration results of the first state machine.

[0006] Preferably, setting the state parameters of the first state machine and performing background calibration includes: Check the calibration interval counter; The first state machine performs background calibration; Save the calibration results to the register and update the background calibration completion flag.

[0007] Preferably, setting the second state machine to perform ZQ calibration based on the calibration result of the first state machine includes: Read the calibration results from the registers; The second state machine performs pull-up impedance calibration and pull-down impedance calibration; Save the calibration results to a register.

[0008] Preferably, it further includes setting the cooperation conditions for the first state machine and the second state machine, specifically: When the first state machine has completed the first calibration, if the second state machine receives a calibration enable signal while the first state machine is running, the first state machine stops the current calibration and allows the second state machine to start working. If the first state machine has not completed the first calibration, and the second state machine receives a calibration enable signal while the first state machine is running, the second state machine will wait for the first state machine to complete the current calibration before starting to work.

[0009] Preferably, the first state machine performing background calibration includes: The DAC calibration voltage comparator is adjusted by successive approximation. The positive terminal of the comparator is connected to the VREF voltage, and the negative terminal is connected to the DAC. The reference voltage VREF and the negative terminal voltage are compared to obtain the comparison results.

[0010] A background-calibrated DRAM ZQ voltage comparator error calibration circuit is applied to a background-calibrated DRAM PHY ZQ voltage comparator error calibration method, comprising: a digital ZQ calibration control module, an external reference resistor, and a comparator calibration module; The digital ZQ calibration control module is connected to the comparator calibration module and is used to perform ZQ calibration. When performing ZQ PU calibration, the pull-up resistor and the external reference resistor form a voltage divider circuit. The voltage at the midpoint of the two resistors is connected to the positive terminal of the comparator and compared with the calibrated voltage comparator. The calibration test is connected to the external reference resistor. After the PU calibration is completed, the PD calibration is performed. At this time, the external reference resistor is not required. The internal pull-up resistor and the internal pull-down resistor form a voltage divider circuit. The pull-up resistor is configured with the PU calibration result value. The voltage between the two internal resistors is connected to the positive terminal of the comparator and compared with the calibrated voltage comparator.

[0011] Preferably, the digital ZQ calibration control module includes: a first state machine and a second state machine; The first state machine is connected to the second state machine and is used to perform comparator calibration; The second state machine performs ZQ calibration based on the output of the first state machine.

[0012] Preferably, the comparator calibration module includes: a first resistor, a second resistor, a third resistor, a first selector, a second selector, and a first comparator; One end of the first resistor is connected to the power supply voltage, and the other end is connected to the negative input terminal of the first selector and an external reference resistor; One end of the second resistor is connected to the power supply voltage, and the other end is connected to the positive input terminal of the first selector and the third resistor; One end of the third resistor is connected to the second resistor, and the other end is grounded; The output of the first selector is connected to the negative input of the second selector; The positive input terminal of the second selector is connected to the reference voltage, and the output terminal is connected to the positive input terminal of the first comparator; The negative input terminal of the first comparator is connected to the DAC.

[0013] An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device performs a background calibration method for a DRAM PHY ZQ voltage comparator error.

[0014] A computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor of an electronic device, cause the processor to perform a background calibration method for a DRAM PHY ZQ voltage comparator error.

[0015] The beneficial effects of this invention are as follows: 1. The first state machine of this invention uses the successive approximation (SAR) method to calibrate the voltage comparator offset, requiring only a single calibration and eliminating the need for two forward and reverse operations, thus saving time. The second state machine directly reuses the calibration result of the first state machine, reducing redundant calculations and improving calibration efficiency. It is suitable for high-frequency calibration scenarios and can perform more rounds of calibration within the same time. 2. The first state machine of this invention requires only a single voltage comparator calibration and eliminates the need to flip the comparator, simplifying the control logic. The second state machine directly reads the calibration value of the first state machine without additional calculations, reducing the complexity of the state machine. 3. The calibration result of the first state machine can be locked and stored in a register for direct reading and reuse by the second state machine. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a background calibration method for a DRAM PHY ZQ voltage comparator error. Figure 2 This is a schematic diagram of a background calibration circuit for a DRAM ZQ voltage comparator. Figure 3 This is a flowchart of the voltage comparator background calibration process of the present invention; Figure 4 This is a flowchart of the ZQ calibration process of the present invention; Figure 5 This is a diagram illustrating the collaboration between the first and second state machines of the present invention. Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0022] Existing ZQ calibration methods generally involve a two-stage inverted voltage comparator, averaging the two calibration results, and independently calibrating the voltage comparator before each ZQ calibration. These methods have the following drawbacks: the inverted comparator method has significant time overhead, requiring two calibration cycles to eliminate comparator errors, adding two rounds of overhead. When temperature, voltage, and process conditions change, periodic calibration may be necessary, resulting in fewer calibration cycles within the same time period. The inverted comparator method has a complex control module design, requiring control of the flipping process, processing of the flipped comparison results, and a value calculation for both calibrations. The calibration results cannot be reused; the two-stage PUPD calibration essentially includes an error calibration action, making it impossible to save and reuse these results for future use. Independent voltage comparator calibration performs poorly under conditions of significant environmental variation. Integrating the voltage comparator calibration into the ZQ calibration allows for result reuse. However, the reuse of calibration results depends on the conditions of the previous ZQ calibration. If the interval between two calibration results is long or environmental conditions change significantly, the previous calibration result is unreliable. Each calibration requires performing a voltage comparator calibration operation.

[0023] The first state machine of this invention uses the successive approximation (SAR) method to calibrate the voltage comparator offset, requiring only a single calibration and eliminating the need for two forward and reverse operations, thus saving time. The second state machine directly reuses the calibration result of the first state machine, reducing redundant calculations and improving calibration efficiency. It is suitable for high-frequency calibration scenarios and can perform more calibration rounds within the same time. The first state machine of this invention only requires a single voltage comparator calibration and does not require flipping the comparator, simplifying the control logic. The second state machine directly reads the calibration value of the first state machine without additional calculations, reducing the complexity of the state machine. The calibration result of the first state machine can be locked and stored in a register for direct reading and reuse by the second state machine.

[0024] Example 1 A method for calibrating the error of a DRAM PHY ZQ voltage comparator in a background calibration manner, referenced Figure 1 ,include: S100, set the state parameters of the first state machine and perform background calibration; S200, set the second state machine to perform ZQ calibration based on the calibration result of the first state machine.

[0025] ZQ calibration is a technique used to ensure that DDR memory maintains signal integrity under varying temperature and voltage conditions. ZQ calibration improves signal quality and stability by calibrating the on-resistance of the DRAM's output driver and the resistance of its on-chip termination circuit (ODT). The main purpose of ZQ calibration is to improve signal integrity and enhance the strength of the output signal. Under varying temperature and voltage conditions, uncalibrated termination resistors can affect signal quality, while improperly adjusted output drivers can cause valid signal transitions to deviate from the reference level, thus affecting the accuracy of data and strobe signals. ZQ calibration ensures that the DRAM's output driver on-resistance and ODT values ​​remain optimal under various operating conditions, thereby reducing signal reflections and ringing, and improving signal stability and reliability.

[0026] In DDR3, ZQ calibration is performed using a 240-ohm low-tolerance reference resistor. This resistor is connected to the ZQ pin of the DDR3. The calibration process is controlled by the on-chip calibration engine (ODCE), triggered by issuing a ZQCL command. The calibration process occurs under different operating states, such as 512 clock cycles during power-on initialization, 256 clock cycles when exiting self-refresh operation, and 64 clock cycles in other cases. After calibration, the calibration value is stored in the DRAM's I / O.

[0027] Preferably, in step S100, setting the state parameters of the first state machine and performing background calibration includes: S110, Check the calibration interval counter; S120, the first state machine performs background calibration; S130 saves the calibration results to the register and updates the background calibration completion flag.

[0028] Idle state: If the first state machine _EN=1 and the second state machine _EN=0, enter the waiting state for the calibration interval counter to return to zero. If the second state machine _EN=1 and the initial voltage comparator calibration is not yet complete, then enter the voltage comparator calibration process. Wait count check: Checks if the calibration interval counter wait_count is 0. Yes: Initiates the voltage comparator calibration process. No: Decrements the counter and rechecks until wait_count = 0. Calibration Initiation: The DAC calibration voltage comparator is adjusted sequentially, with the positive terminal connected to the VREF voltage and the negative terminal connected to the DAC. The reference voltage VREF is compared with the negative terminal voltage to obtain the comparison result. The digital circuitry is adjusted multiple times until the negative terminal voltage matches or closely approximates VREF. Once this is complete, the voltage comparator calibration is considered finished, and the negative terminal is fixed at the DAC calibration result. Saving Results: After the voltage comparator calibration is complete, the calibration results are saved to the register, and the background calibration completion flag is updated. After calibration, the process is as follows: reset the waiting calibration interval counter and return to the idle state.

[0029] Preferably, in step S200, setting the second state machine to perform ZQ calibration based on the calibration result of the first state machine includes: S210, read the calibration result of the register; S220, the second state machine performs pull-up impedance calibration and pull-down impedance calibration; S230 saves the calibration results to a register.

[0030] Idle State: The second state machine is in the idle state by default, waiting for the second state machine _EN=1 signal to trigger. If the second state machine _EN=1, then check the backCalDone flag of the first state machine. The backCalDone flag is the voltage comparator background calibration completion flag.

[0031] Voltage comparator result check: If backCalDone=1, proceed directly to the next step. If backCalDone=0, the second state machine enters a waiting state until the first state machine completes calibration and sets backCalDone=1. Backfill calibration results: Read the calibration results locked by the first state machine from the register and apply them. Initiate ZQ calibration: Perform ZQ calibration based on the calibration results provided by the first state machine. Perform PU calibration: Perform pull-up impedance calibration and update relevant registers. Perform PD calibration: Perform pull-down impedance calibration and update relevant registers. After all calibration steps are completed, the second state machine returns to its initial idle state, waiting for the next trigger.

[0032] Preferably, it further includes setting the cooperation conditions for the first state machine and the second state machine, specifically: When the first state machine has completed the first calibration, if the second state machine receives a calibration enable signal while the first state machine is running, the first state machine stops the current calibration and allows the second state machine to start working. If the first state machine has not completed the first calibration, and the second state machine receives a calibration enable signal while the first state machine is running, the second state machine will wait for the first state machine to complete the current calibration before starting to work.

[0033] The second state machine can only perform ZQ calibration after the first state machine has completed the voltage comparator calibration (backCalDone=1) to ensure the calibration data is valid. If the first state machine fails to complete the first calibration, the second state machine will wait (wait for the first state machine's backCal Done). Priority control of the second state machine: When the first state machine is running, if the second state machine's _EN=1 and the first state machine's first calibration is not yet complete, the second state machine will wait; if the second state machine's _EN=1 and the first state machine's first calibration is complete, the first state machine will immediately terminate the current calibration and let the second state machine take over. This design ensures that the ZQ calibration of the second state machine can be performed with priority and guarantees that the voltage comparator is reliable before ZQ calibration, because the first and second state machines may use the same control signals (such as calibration pull-up / pull-down values, calibration enable signals, etc.). Only one FSM (Finite State Machine) state machine is allowed to control the ZQ analog unit at any given time. Collaboration sequence: First state machine: Responsible for performing voltage comparator calibration in the background, providing real-time calibration data to the second state machine, and simplifying the ZQ calibration process, reducing time overhead. Second state machine: Responsible for ZQ calibration (PU / PD), relying on the results from the first state machine for more accurate adjustments.

[0034] Preferably, in step S120, the first state machine performs background calibration including: S121, successively approximates and adjusts the DAC calibration voltage comparator, with the positive terminal of the comparator connected to the VREF voltage and the negative terminal connected to the DAC; S122 compares the reference voltage VREF and the negative terminal voltage to obtain the comparison result.

[0035] In this embodiment of the invention, a global reset can also be performed. The global reset condition is: if the second state machine _EN=1 in a certain state of the first state machine, the current process is immediately terminated, the waiting calibration interval counter is reset, and the process returns to the idle state. Affected states include: waiting count check and calibration start: if the second state machine _EN=1 and the first state machine's initial calibration is not completed, the counter check is skipped and calibration is performed directly until completion, then the result is locked and the counter is reset.

[0036] Example 2 A background-calibrated DRAM ZQ voltage comparator error calibration circuit is applied to a background-calibrated DRAM PHY ZQ voltage comparator error calibration method, comprising: a digital ZQ calibration control module, an external reference resistor, and a comparator calibration module; The digital ZQ calibration control module is connected to the comparator calibration module and is used to perform ZQ calibration. When performing ZQ PU calibration, the pull-up resistor and the external reference resistor form a voltage divider circuit. The voltage at the midpoint of the two resistors is connected to the positive terminal of the comparator and compared with the calibrated voltage comparator. The calibration test is connected to the external reference resistor. After the PU calibration is completed, the PD calibration is performed. At this time, the external reference resistor is not required. The internal pull-up resistor and the internal pull-down resistor form a voltage divider circuit. The pull-up resistor is configured with the PU calibration result value. The voltage between the two internal resistors is connected to the positive terminal of the comparator and compared with the calibrated voltage comparator.

[0037] Compared to existing comparator calibration methods (such as the inverted comparator method and the independent voltage comparator calibration method), this solution effectively addresses the shortcomings of traditional methods through a step-by-step collaborative mechanism of a first state machine (background calibration) + a second state machine (ZQ calibration), offering the following significant advantages: Shorter calibration time and higher efficiency: The first state machine uses the successive approximation (SAR) method to calibrate the voltage comparator offset, requiring only a single calibration and eliminating the need for two forward and reverse operations, saving time. The second state machine directly reuses the calibration results from the first state machine, reducing redundant calculations and improving calibration efficiency. Suitable for high-frequency calibration scenarios, allowing for more calibration rounds to be performed within the same timeframe. Simplified control logic: The first state machine requires only a single voltage comparator calibration, eliminating the need for comparator flipping, thus simplifying the control logic. The second state machine directly reads the calibration values ​​from the first state machine, eliminating the need for additional calculations and reducing state machine complexity. Reusable calibration results reduce redundant calibration: The calibration results from the first state machine can be locked and stored in a register for direct reading and reuse by the second state machine. Support for dynamic calibration updates: If the environment changes significantly, the continuous background calibration of the first state machine ensures that the second state machine can obtain the latest and most valid calibration data. If the environment is stable, the background calibration frequency of the first state machine can be reduced, and the second state machine can reuse previous calibration values, avoiding redundant operations and reducing energy consumption. It exhibits strong environmental adaptability and reliable calibration. The first and second state machines work collaboratively: the first state machine is responsible for quickly responding to environmental changes (such as voltage / temperature fluctuations) and dynamically updating the voltage comparator calibration values. The second state machine only performs ZQ calibration after the first state machine's calibration is completed, ensuring that the voltage comparator is always based on the latest environmental conditions. It is suitable for high-frequency, high-precision scenarios. The first state machine provides a high-precision voltage comparator reference, ensuring that comparator errors are minimized. The ZQ calibration (PU / PD) of the second state machine is based on a stable reference, improving signal integrity. This invention, through a step-by-step calibration + collaborative multiplexing mechanism, comprehensively surpasses traditional methods in terms of speed, reliability, and hardware efficiency, and is particularly suitable for scenarios with strict requirements for calibration speed and accuracy.

[0038] Preferably, the digital ZQ calibration control module includes: a first state machine and a second state machine; The first state machine is connected to the second state machine and is used to perform comparator calibration; The second state machine performs ZQ calibration based on the output of the first state machine.

[0039] The main function of the digital ZQ calibration control module is to ensure that the DRAM device maintains the correct output impedance under various operating conditions, thereby guaranteeing the integrity of high-speed signals and the stability of the system. An external precision resistor is connected to the ZQ pin of the chip, and ZQ calibration is performed using this reference resistor. The impedance of the internal output driver of the DRAM is adjusted by comparing it with this reference resistor. This process ensures that the output impedance of the DRAM remains within a suitable range under conditions of temperature changes and voltage fluctuations, thereby improving the system's noise immunity and transmission stability. In this embodiment of the invention, a voltage comparator calibration must be performed first before ZQ calibration to ensure the accuracy and validity of the calibration data.

[0040] Preferably, the comparator calibration module includes: a first resistor, a second resistor, a third resistor, a first selector, a second selector, and a first comparator; One end of the first resistor is connected to the power supply voltage, and the other end is connected to the negative input terminal of the first selector and an external reference resistor. One end of the second resistor is connected to the power supply voltage, and the other end is connected to the positive input terminal of the first selector and the third resistor; One end of the third resistor is connected to the second resistor, and the other end is grounded; The output of the first selector is connected to the negative input of the second selector; The positive input of the second selector is connected to the reference signal, and its output is connected to the positive input of the first comparator. The negative input of the first comparator is connected to the DAC.

[0041] In this embodiment of the invention, the comparator calibration module is in an idle state: if FSM0_EN=1 and FSM1_EN=0, it enters the waiting period for the calibration interval counter to reset to zero. If FSM1_EN=1 and the first voltage comparator calibration is not completed, it enters the voltage comparator calibration process. Wait count check: Check if the calibration interval counter wait_count is 0. Yes: Start the voltage comparator calibration process. No: Decrement the counter and check again until wait_count=0. Calibration start: Gradually adjust the DAC calibration voltage comparator, connect the positive terminal of the comparator to the VREF voltage, and the negative terminal to the DAC, compare the reference voltage VREF and the negative terminal voltage, obtain the comparison result, and adjust the digital circuit multiple times to make the negative terminal voltage consistent with or close to VREF. After completion, the voltage comparator calibration is considered complete, and at this time the negative terminal is fixed to the DAC. Saving the calibration result: After the voltage comparator calibration is completed, the calibration result is saved to the register, and the background calibration completion flag is updated. Processing after calibration: Reset the waiting period counter and return to the idle state. Example 3 An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions. When the chip executes the computer instructions, the electronic device performs a background calibration method for a DRAM PHY ZQ voltage comparator error.

[0042] refer to Figure 6 The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, memory 22, input device 23, and output device 24 are coupled together via connectors, which may include various interfaces, transmission lines, or buses, etc., and are not limited in this embodiment of the invention. It should be understood that in the various embodiments of the invention, coupling refers to mutual connection through a specific method, including direct connection or indirect connection through other devices, such as through various interfaces, transmission lines, buses, etc.

[0043] The processor 21 can be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Optionally, the processor can also be other types of processors, etc., and this embodiment of the invention is not limited thereto.

[0044] The memory 22 can be used to store computer program instructions, as well as various types of computer program code, including program code for executing the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), which is used for related instructions and data.

[0045] Input device 23 is used to input data and / or signals, and output device 24 is used to output data and / or signals. Output device 24 and input device 23 can be independent devices or an integrated device.

[0046] Example 4 A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to perform a background calibration method for a DRAM PHY ZQ voltage comparator error.

[0047] The first state machine of this invention uses the successive approximation (SAR) method to calibrate the voltage comparator offset, requiring only a single calibration and eliminating the need for two forward and reverse operations, thus saving time. The second state machine directly reuses the calibration result of the first state machine, reducing redundant calculations and improving calibration efficiency. It is suitable for high-frequency calibration scenarios and can perform more calibration rounds within the same time. The first state machine of this invention only requires a single voltage comparator calibration and does not require flipping the comparator, simplifying the control logic. The second state machine directly reads the calibration value of the first state machine without additional calculations, reducing the complexity of the state machine. The calibration result of the first state machine can be locked and stored in a register for direct reading and reuse by the second state machine.

[0048] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method of DRAM PHY ZQ voltage comparator error calibration for background calibration, the method comprising: The method comprises the following steps: setting state parameters of a first state machine and performing background calibration; setting a second state machine to perform ZQ calibration according to the calibration result of the first state machine.

2. The method of claim 1, wherein the method further comprises: The step of setting state parameters of a first state machine and performing background calibration comprises the following steps: checking a calibration interval counter; the first state machine performs background calibration; saving the calibration result to a register and updating a background calibration completion flag.

3. The method of claim 1, wherein the method further comprises: determining a ZQ voltage value for the DRAM PHY ZQ voltage comparator; and determining a ZQ voltage value for the DRAM PHY ZQ voltage comparator based on the determined ZQ voltage value. The step of setting a second state machine to perform ZQ calibration according to the calibration result of the first state machine comprises the following steps: reading the calibration result from the register; the second state machine performs pull-up impedance calibration and pull-down impedance calibration; saving the calibration result to the register.

4. The method of claim 1, wherein the method further comprises: The method further comprises setting cooperation conditions of the first state machine and the second state machine, specifically: when the first state machine has completed the first calibration, if the second state machine receives a calibration enable signal when the first state machine is running, the first state machine stops the current calibration and allows the second state machine to start working; when the first state machine has not completed the first calibration, if the second state machine receives a calibration enable signal when the first state machine is running, the second state machine waits for the first state machine to complete the current calibration and then starts working.

5. The method of claim 2, wherein the method further comprises: determining a ZQ voltage value for the DRAM PHY ZQ voltage comparator; and determining a ZQ voltage value for the DRAM PHY ZQ voltage comparator based on the determined ZQ voltage value. The step of the first state machine performing background calibration comprises the following steps: adjusting a DAC calibration voltage comparator by successive approximation, with the positive electrode of the comparator connected to a VREF voltage and the negative electrode connected to the DAC; comparing the reference voltage VREF and the negative electrode voltage to obtain a comparison result.

6. A background calibrated DRAM ZQ voltage comparator error calibration circuitry applied to the background calibrated DRAM PHY ZQ voltage comparator error calibration method of any one of claims 1-5, wherein, The method comprises the following steps: a digital ZQ calibration control module, an external reference resistor and a comparator calibration module; the digital ZQ calibration control module is connected to the comparator calibration module and is used for performing ZQ calibration, when performing ZQ PU calibration, a pull-up resistor and the external reference resistor form a voltage dividing circuit, the voltage at the middle point of the two resistors is connected to the positive electrode of the comparator and a voltage comparator after calibration for comparison; the calibration inspection is connected to the external reference resistor, after completing PU calibration, PD calibration is performed, at this time, the internal pull-up resistor and the internal pull-down resistor form a voltage dividing circuit, the pull-up resistor is configured as a PU calibration result value, and the voltage at the middle point of the two internal resistors is connected to the positive electrode of the comparator and a voltage comparator after calibration for comparison.

7. The background calibrated DRAM ZQ voltage comparator error calibration circuit of claim 6, wherein, The digital ZQ calibration control module comprises a first state machine and a second state machine; the first state machine is connected to the second state machine and is used for performing comparator calibration; the second state machine performs ZQ calibration according to the output result of the first state machine.

8. The background calibrated DRAM ZQ voltage comparator error calibration circuit of claim 6, wherein, The comparator calibration module comprises a first resistor, a second resistor, a third resistor, a first selector, a second selector and a first comparator; one end of the first resistor is connected to a power supply voltage, and the other end is connected to the negative input end of the first selector and an external reference resistor; one end of the second resistor is connected to the power supply voltage, and the other end is connected to the positive input end of the first selector and the third resistor; one end of the third resistor is connected to the second resistor, and the other end is connected to the ground; the output end of the first selector is connected to the negative input end of the second selector; the positive input end of the second selector is connected to a reference voltage, and the output end is connected to the positive input end of the first comparator; The negative input of the first comparator is connected with the DAC.

9. An electronic device, comprising: Comprise: A chip, a processor and a memory, the memory is used for storing computer program code, the computer program code includes computer instructions, under the circumstance of executing the computer instructions, the electronic equipment executes a kind of background calibration DRAM PHY ZQ voltage comparator error calibration method as claimed in any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, the computer program includes program instructions, the program instructions are executed by the processor of the electronic equipment, so that the processor executes the background calibration DRAM PHY ZQ voltage comparator error calibration method of any one of claims 1 to 5.

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