Memory, programming method of memory and memory system

Abstract

The invention discloses a memory, an operation method of the memory and a memory system, and relates to the technical field of memory, the memory comprises a memory array and a peripheral circuit, the memory array comprises a plurality of memory units which are coupled with a first bit line and a plurality of word lines respectively, the plurality of word lines comprise a selected word line coupled with the storage unit to be programmed; a peripheral circuit configured to: apply a precharge voltage to the plurality of word lines; sequentially reducing the pre-charging voltage applied to the plurality of word lines to a first turn-off voltage according to the arrangement sequence of the memory units coupled to the plurality of word lines in the memory array; applying a programming voltage to a selected word line of the plurality of word lines; and applying a turn-on voltage to other word lines among the plurality of word lines. As the plurality of word lines are sequentially turned off, electrons in the channels are driven to move from the channels to one end and are drawn away, so that the electrons in the channels are prevented from influencing the voltage difference between the word lines and the channels.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a memory programming method, and a storage system. Background Technology

[0002] Three-dimensional (3D) memory typically comprises multiple arrays of memory strings, each containing multiple levels of cascaded memory cells. With the development of communication and big data technologies, user demand for memory capacity is gradually increasing. Since memory capacity is affected by the number of memory string levels, the requirement for the number of memory string levels is also increasing accordingly.

[0003] As the number of layers in a 3D memory string increases, the distance between layers decreases, leading to severe programming interference between word lines (WL) during memory programming. Summary of the Invention

[0004] This application provides a memory, a method for programming the memory, and a storage system. The technical solution is as follows:

[0005] On one hand, a memory is provided, the memory comprising:

[0006] The storage array and peripheral circuitry include a plurality of storage cells coupled to a first bit line and to a plurality of word lines, the plurality of word lines including a selected word line coupled to a storage cell to be programmed.

[0007] The peripheral circuit is configured as follows:

[0008] Apply a pre-charge voltage to the multiple word lines;

[0009] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0010] A programming voltage is applied to the selected word line among the plurality of word lines; and an on-state voltage is applied to the other word lines among the plurality of word lines.

[0011] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0012] The first shutdown voltage is applied to each of the multiple word lines sequentially according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array; or...

[0013] The first shutdown voltage is applied to the multiple word lines in groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0014] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0015] Obtain the grouping configuration information of the multiple word lines, wherein the grouping configuration information includes multiple groups obtained by dividing the multiple word lines, wherein at least two word lines in the same group are arranged adjacently in the storage array;

[0016] The first shutdown voltage is applied sequentially to the word lines in multiple groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0017] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0018] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to a first intermediate voltage, where the first intermediate voltage is the voltage between the pre-charge voltage and the first shutdown voltage.

[0019] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the first intermediate voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0020] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0021] Along the direction from the drain-select gate to the source-select gate, the pre-charge voltage applied to the plurality of word lines is sequentially reduced to the first turn-off voltage; or,

[0022] Along the direction from the source select gate to the drain select gate, the pre-charge voltage applied to the plurality of word lines is sequentially reduced to the first turn-off voltage.

[0023] In an optional embodiment, the plurality of word lines includes a selected word line coupled to a memory cell to be programmed and a deselected word line coupled to a programmed memory cell.

[0024] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0025] A verification voltage is applied to the selected word line among the plurality of word lines; and a read voltage is applied to the other word lines among the plurality of word lines.

[0026] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the second shutdown voltage is applied to the multiple word lines in sequence;

[0027] A programming voltage is applied to the selected word line among the plurality of word lines; and an on-state voltage is applied to the other word lines among the plurality of word lines.

[0028] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0029] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the verification voltage or read voltage applied to the multiple word lines is sequentially reduced to a second intermediate voltage; the second intermediate voltage is the voltage between the verification voltage and the second shutdown voltage, or the second intermediate voltage is the voltage between the read voltage and the second shutdown voltage;

[0030] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the second intermediate voltage applied to the multiple word lines is sequentially reduced to the second shutdown voltage.

[0031] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0032] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to some of the multiple word lines is sequentially reduced to the first shutdown voltage at a preset word line interval.

[0033] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0034] Multiple target character lines are determined from the multiple character lines according to a preset interval algorithm, wherein there is at least one character line between two adjacent target character lines;

[0035] According to the arrangement order of the memory cells coupled to the plurality of target word lines in the memory array, the pre-charge voltage applied to the plurality of target word lines is sequentially reduced to the first shutdown voltage.

[0036] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0037] After the multiple word lines have been reduced to the first shutdown voltage, a programming voltage is simultaneously applied to the selected word line among the multiple word lines, and an on-state voltage is applied to the other word lines among the multiple word lines.

[0038] On the other hand, a method for programming a memory is provided, the method comprising:

[0039] Apply pre-charge voltage to multiple word lines;

[0040] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0041] A programming voltage is applied to the selected word line among the plurality of word lines; and an on-state voltage is applied to the other word lines among the plurality of word lines.

[0042] In an optional embodiment, the step of sequentially reducing the pre-charge voltage applied to the multiple word lines to a first shutdown voltage according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array includes:

[0043] The first shutdown voltage is applied to each of the multiple word lines sequentially according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array; or...

[0044] The first shutdown voltage is applied to the multiple word lines in groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0045] In an optional embodiment, applying the first shutdown voltage to the multiple word lines in groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array includes:

[0046] Obtain the grouping configuration information of the multiple word lines, wherein the grouping configuration information includes multiple groups obtained by dividing the multiple word lines, wherein at least two word lines in the same group are arranged adjacently in the storage array;

[0047] The first shutdown voltage is applied sequentially to the word lines in multiple groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0048] In an optional embodiment, the step of sequentially reducing the pre-charge voltage applied to the multiple word lines to a first shutdown voltage according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array includes:

[0049] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to a first intermediate voltage, where the first intermediate voltage is the voltage between the pre-charge voltage and the first shutdown voltage.

[0050] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the first intermediate voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0051] In an optional embodiment, the step of sequentially reducing the pre-charge voltage applied to the multiple word lines to a first shutdown voltage according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array includes:

[0052] Along the direction from the drain-select gate to the source-select gate, the pre-charge voltage applied to the plurality of word lines is sequentially reduced to the first turn-off voltage; or,

[0053] Along the direction from the source select gate to the drain select gate, the pre-charge voltage applied to the plurality of word lines is sequentially reduced to the first turn-off voltage.

[0054] In an optional embodiment, the plurality of word lines includes a selected word line coupled to a memory cell to be programmed and a deselected word line coupled to a programmed memory cell.

[0055] In an optional embodiment, the method further includes:

[0056] A verification voltage is applied to the selected word line among the plurality of word lines; and a read voltage is applied to the other word lines among the plurality of word lines.

[0057] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the second shutdown voltage is applied to the multiple word lines in sequence;

[0058] A programming voltage is applied to the selected word line among the plurality of word lines; and an on-state voltage is applied to the other word lines among the plurality of word lines.

[0059] In an optional embodiment, applying a second shutdown voltage sequentially to the plurality of word lines according to the arrangement order of the memory cells coupled to the plurality of word lines in the memory array includes:

[0060] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the verification voltage or read voltage applied to the multiple word lines is sequentially reduced to a second intermediate voltage; the second intermediate voltage is the voltage between the verification voltage and the second shutdown voltage, or the second intermediate voltage is the voltage between the read voltage and the second shutdown voltage;

[0061] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the second intermediate voltage applied to the multiple word lines is sequentially reduced to the second shutdown voltage.

[0062] In an optional embodiment, the step of sequentially reducing the pre-charge voltage applied to the multiple word lines to a first shutdown voltage according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array includes:

[0063] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to some of the multiple word lines is sequentially reduced to the first shutdown voltage at a preset word line interval.

[0064] In an optional embodiment, the step of sequentially reducing the pre-charge voltage applied to a portion of the multiple word lines to the first shutdown voltage according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array at preset word line intervals includes:

[0065] Multiple target character lines are determined from the multiple character lines according to a preset interval algorithm, wherein there is at least one character line between two adjacent target character lines;

[0066] According to the arrangement order of the memory cells coupled to the plurality of target word lines in the memory array, the pre-charge voltage applied to the plurality of target word lines is sequentially reduced to the first shutdown voltage.

[0067] In an optional embodiment, applying a programming voltage to the selected word line among the plurality of word lines; and applying an on-state voltage to the other word lines among the plurality of word lines includes:

[0068] After the multiple word lines have been reduced to the first shutdown voltage, a programming voltage is simultaneously applied to the selected word line among the multiple word lines, and an on-state voltage is applied to the other word lines among the multiple word lines.

[0069] On the other hand, a storage system is provided, the storage system comprising:

[0070] One or more memories as described in any of the above embodiments, and,

[0071] A memory controller coupled to the memory and configured to control the memory.

[0072] The technical solution provided in this application may include the following beneficial effects:

[0073] When programming a selected word line, after applying a pre-charge voltage during the pre-charge phase, the pre-charge voltage applied to the word lines is sequentially reduced to a preset turn-off voltage according to the arrangement order of the multiple word lines. Since the pre-charge voltages on the word lines are turned off sequentially, when the first word line is turned off, the second word line adjacent to the first word line has not yet been turned off, thereby generating a potential difference from the first word line to the second word line in the channel. This drives the electrons in the channel to move from the direction of the first word line to the direction of the second word line. As the multiple word lines are turned off sequentially, the electrons in the channel are driven to move from the channel to one end and are extracted. This avoids the electrons in the channel from affecting the voltage difference between the word line and the channel, thus affecting the programming effect of the erase state L0 after the pre-charge phase and reducing programming interference of L0. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 This is a schematic diagram of the structure of a 3D memory provided in an illustrative embodiment of this application;

[0076] Figure 2 This is a schematic diagram illustrating a programming result provided in an exemplary embodiment of this application;

[0077] Figure 3 This is a schematic diagram illustrating another programming result provided by an exemplary embodiment of this application;

[0078] Figure 4 This is a method for programming a memory provided in an exemplary embodiment of this application;

[0079] Figure 5 Based on Figure 4 The illustrated embodiment provides a voltage shutdown schematic diagram;

[0080] Figure 6 Based on Figure 4 The illustrated embodiment provides a schematic diagram of group voltage shutdown;

[0081] Figure 7 Based on Figure 4 The illustrated embodiment provides a voltage shutdown schematic diagram;

[0082] Figure 8 This is another exemplary embodiment of the present application providing a method for programming a memory;

[0083] Figure 9 Based on Figure 8 The illustrated embodiment provides a voltage shutdown schematic diagram;

[0084] Figure 10 Based on Figure 8 The illustrated embodiment provides a schematic diagram of group voltage shutdown;

[0085] Figure 11 This is another exemplary embodiment of the present application providing a method for programming a memory;

[0086] Figure 12 Based on Figure 11 The illustrated embodiment provides a schematic diagram of voltage shutdown via an intermediate voltage;

[0087] Figure 13This is a schematic diagram of the structure of a memory provided in an exemplary embodiment of this application;

[0088] Figure 14 This is a schematic diagram of the structure of a storage system provided in an exemplary embodiment of this application. Detailed Implementation

[0089] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0090] The memory programming method provided in this application embodiment can be applied to a memory. This memory can be a 3D memory, such as a 3D NAND flash memory.

[0091] 3D memory is a multi-layered, stacked memory; schematically, this 3D memory is a 3D NAND flash memory. For example... Figure 1 As shown, the 3D memory 100 includes multiple memory strings 110 arranged in a direction parallel to the substrate's bearing surface, and multiple memory cells 120 in each memory string 110 are arranged in a direction perpendicular to the substrate's bearing surface. That is, the multiple memory cells included in the 3D memory are arranged in a three-dimensional array on the substrate, forming a memory array.

[0092] One end of the storage string 110 is connected to the bit line (BL), and the other end is connected to the source line (SL).

[0093] The memory cells in each memory string are also connected to memory cells in other memory strings via word lines (WL). For example, if each memory string can include 64 memory cells, then the 3D memory can include 64 word lines WL<63:0>, and each word line is connected to a portion of memory cells located on the same layer (i.e., having the same height relative to the substrate). It should be noted that 64 memory cells is only a specific example, and the application is not limited to this. In some embodiments, each memory string can include more than 64 memory cells, such as 128, 196, etc. In the 3D memory, the memory cells connected to the same word line are called a memory page, and all memory strings sharing a set of word lines are called a memory block.

[0094] The storage string 110 also includes an upper select transistor connected to the drain of the first storage cell and a lower select transistor connected to the source of the last storage cell. The upper select transistor is also called a top select gate (TSG) or a drain select gate (DSG). The lower select transistor is also called a bottom select gate (BSG) or a source select gate (SSG).

[0095] The gate of the TSG is connected to the drain select line (DSL), the source of the TSG is connected to the drain of the first memory cell, and the drain of the TSG is connected to the bit line.

[0096] The gate of the BSG is connected to the source select line (SSL), the drain of the BSG is connected to the source of the last memory cell, and the source of the BSG is connected to the source line.

[0097] Depend on Figure 1 It is known that the memory cells in memory string 110 share a set of memory lines (WL) with the memory cells in other memory strings. Assuming each memory string includes m+1 memory cells, the 3D memory can include m+1 WLs: WL0 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., at the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell located on the same layer, and the gate connection lines between each control gate, constitute a WL.

[0098] Based on the amount of data that a storage unit can store, storage units can be classified into Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), and Quad-Level Cell (QLC), etc. Each SLC can store 1 bit of data, each MLC can store 2 bits, each TLC can store 3 bits, and each QLC can store 4 bits. In 3D memory, the data stored in storage units located in the same layer can form k storage pages, where k is the number of bits of data that each storage unit can store.

[0099] In this embodiment, the storage cell in the 3D memory can be a floating-gate field-effect transistor (FET) or a charge-trap FET, or other data-storing FET. The TSG and BSG can be ordinary FETs or data-storing FETs. The floating-gate FET includes a source, a drain, and two gates. Both gates are conductors, and one is a control gate (CG), while the other is a floating gate (FG), referred to simply as a floating gate. The control gate is used to connect word lines, and the floating gate is used to store data. The charge-trap FET includes a source, a drain, a control gate, and a charge-trap layer. This charge-trap layer is the data-storing cell and is made of an insulating material such as silicon nitride. The following description uses a floating-gate FET as an example to illustrate the data writing principle of the storage cell.

[0100] When writing data into a memory cell, a programming voltage is applied to the control gate of the floating-gate field-effect transistor (FET), causing electrons in the FET's channel to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that different threshold voltages Vth require different voltages applied to the control gate to turn the FET on. Therefore, the magnitude of the threshold voltage Vth of the FET reflects the content of the stored data.

[0101] It should be understood that in 3D memory, the channels of each memory cell in each memory string can be connected sequentially to form a columnar structure perpendicular to the substrate.

[0102] As the number of layers in a 3D memory string increases, the distance between layers decreases, leading to severe programming interference between write lines (WLs) during memory programming. For illustrative purposes, please refer to [reference needed]. Figure 2 With the development of 3D storage technology, the number of storage unit layers in the storage string increases, resulting in a longer storage string length. In order to reduce the space occupied by the 3D storage string, the layer height of the storage string is compressed, which leads to a reduction in the distance between storage unit layers in the storage string.

[0103] The reduced distance between memory cell layers can cause interference between adjacent write layers (WL) during the memory cell programming process, thus affecting the programming effect. Specifically, when programming a memory cell, the erase state (L0) and multiple programming states need to be programmed separately based on the memory cell type. The programming process for the erase state can be affected by the influence of adjacent WL, leading to interference in the programming result of the erase state (L0). Figure 2As shown in the L0 programming results, curve 210 represents the programming result of the erase state L0. The intersection of curve 210 with other curves (representing the programming state) indicates that there is interference in the programming result of the erase state L0.

[0104] The causes of L0 programming interference include the following: During the boosting phase, it is typically necessary to raise the boosting potential of the channel near the selected word line to a preset height, thereby reducing the voltage difference between the selected word line and the channel and minimizing L0 programming interference caused by electron tunneling. However, residual electrons in the channel can lower the boosting potential, resulting in L0 programming interference remaining relatively significant.

[0105] This is illustrative; please refer to it. Figure 3 Curve 310 represents the channel potential. After the selected word line is programmed, the boosting potential decreases due to the residual electrons in the channel, which affects the programming effect of subsequent word lines and causes L0 programming interference during subsequent word line programming.

[0106] In this embodiment, by sequentially applying turn-off voltages to the word lines during the pre-charging phase, electrons in the channel are discharged from the channel in the order of the turn-off voltage application, thereby preventing the boosting potential in the channel from being reduced and avoiding L0 programming interference during programming of the selected word lines.

[0107] Figure 4 This application provides a method for programming a memory, which can be executed by peripheral circuitry of the memory. The method includes at least the following steps.

[0108] Step 401: Apply a pre-charge voltage to the multiple word lines.

[0109] Before applying a programming voltage to a selected word line, a pre-charge voltage must first be applied to the selected word line. In some embodiments, a pre-charge voltage is applied to the selected word line and the deselected word line coupled to other memory cells coupled to the first bit line, which refers to the bit line coupled to the memory cell to be programmed that is coupled to the selected word line, and this selected bit line is also coupled to other unprogrammed or programmed memory cells. Optionally, a pre-charge voltage is applied to the selected word line and the deselected word line coupled to the programmed memory cells.

[0110] In some embodiments, for a memory string coupled to the first bit line, a precharge voltage is applied to the select word line coupled to the memory cell to be programmed in the memory string and the deselect word line coupled to the programmed memory cell in the memory string.

[0111] Specifically, the memory cells in the memory string are programmed sequentially along the direction from DSG to SSG; or, the memory cells in the memory string are programmed sequentially along the direction from SSG to DSG.

[0112] Step 402: According to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0113] Optionally, the multiple word lines include a selected word line coupled to the memory cell to be programmed and a deselected word line coupled to the programmed memory cell.

[0114] In some embodiments, the first shutdown voltage is less than the pre-charge voltage, and the first shutdown voltage is a pre-configured voltage less than the pre-charge voltage. In some embodiments, the first shutdown voltage is 0V, or the first shutdown voltage is a voltage less than a preset voltage threshold, such as: the preset voltage threshold is 0.5V, and the first shutdown voltage is any voltage less than 0.5V.

[0115] In some embodiments, the first shutdown voltage applied to the multiple word lines may be the same or different.

[0116] Optionally, when the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first turn-off voltage, at least one of the following methods is included:

[0117] First, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the first turn-off voltage is applied to each of the multiple word lines one by one.

[0118] Optionally, for the deselect word line coupled to the programmed memory cell in the memory string and the select word line coupled to the unprogrammed memory cell, a first shutdown voltage is applied to the deselect word line and the select word line one by one according to the arrangement order of the programmed memory cell and the unprogrammed memory cell in the memory string.

[0119] In some embodiments, if the memory cells in the memory string are programmed sequentially, then a first shutdown voltage is applied to the deselect word line and the select word line one by one according to the programming order of the memory cells in the memory string.

[0120] This is illustrated by taking the programming of storage units in a storage string from DSG to SSG as an example. For example... Figure 5As shown, following the arrangement order of the memory cells, the precharge voltage Vpre of WL0 to WLn-1 up to WLn is sequentially reduced to the first shutdown voltage V0, which can be 0V. The shutdown of the precharge voltages of WL0 to WLn is performed sequentially. That is, after WL0 is reduced to the first shutdown voltage V0, WL1 is reduced to the first shutdown voltage V0, and so on, until WLn-2 is reduced to the first shutdown voltage V0, then WLn-1 is reduced to the first shutdown voltage V0, and finally the selected word line WLn is reduced to the first shutdown voltage V0.

[0121] After applying a pre-charge voltage to the deselect and select word lines, as WL0 to WLn are turned off sequentially, a potential difference is generated in the channel from WL0 to WLn. This drives electrons in the channel to move towards the SSG direction and are extracted from the SSG side. As a result, the boosting potential of the channel near the select word line WLn meets the potential requirements, reducing the interference of the select word line WLn during the L0 programming stage.

[0122] Second, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the first shutdown voltage is applied to the multiple word lines in groups.

[0123] Optionally, for the deselect word line coupled to the programmed memory cell in the memory string and the select word line coupled to the unprogrammed memory cell, a first shutdown voltage is applied to the deselect word line and the select word line in a grouped manner according to the arrangement order of the programmed memory cell and the unprogrammed memory cell in the memory string.

[0124] In some embodiments, if the memory cells in the memory string are programmed sequentially, then a first shutdown voltage is applied to the deselect word line and the select word line in groups according to the programming order of the memory cells in the memory string.

[0125] In some embodiments, the grouping is for deselect word lines, where the precharge voltage applied to the selected word lines is reduced to the first shutdown voltage after the deselect word lines are reduced to the first shutdown voltage.

[0126] Optionally, group configuration information of multiple word lines is obtained, including multiple groups obtained by dividing the multiple word lines, wherein at least two word lines in the same group are arranged adjacently in the memory array. A first shutdown voltage is applied sequentially to the word lines in the multiple groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, on a group-by-group basis.

[0127] The grouping relationship of multiple character lines is preset, or the number of character lines within a group is preset.

[0128] Taking the preset grouping relationship of multiple word lines as an example, that is, the memory pre-stores the grouping relationship between multiple word lines coupled to the memory string, and the memory cells coupled to word lines in the same group are arranged sequentially adjacently in the memory string. For example, WL0~WLn-z-1 is one group, WLn-z~WLn-y-1 is another group. Illustratively, this is an example of programming memory cells in the memory string from DSG to SSG. Figure 6 As shown, according to the arrangement order of the memory cells, the precharge voltage Vpre of WL0 to WLn is sequentially reduced to the first shutdown voltage V0, which can be 0V. The shutdown of the precharge voltages of WL0 to WLn is performed sequentially in groups. That is, after WL0 to WLn-z-1 are reduced to the first shutdown voltage V0, WLn-z to WLn-y-1 are reduced to the first shutdown voltage V0, and so on, group by group, until WLn-a to WLn-1 are reduced to the first shutdown voltage V0, at which point the selected word line WLn is reduced to the first shutdown voltage V0.

[0129] After applying a pre-charge voltage to the deselect and select word lines, as the groups from WL0 to WLn are turned off sequentially, a potential difference is generated in the channel from WL0 to WLn. This drives electrons in the channel to move towards the SSG direction and are extracted from the SSG side. As a result, the boosting potential of the channel near the select word line WLn meets the potential requirements, reducing the interference of the select word line WLn during the L0 programming stage.

[0130] In this method, the voltages from WL0 to WLn are turned off sequentially in groups, which avoids the large number of control operations and the large amount of control calculations required when turning off WL0 to WLn one by one, thus improving the turn-off efficiency.

[0131] Taking a pre-set number of word lines within a group as an example, illustratively speaking, the number of word lines within a group is 3, and the memory cells coupled to word lines in the same group are arranged sequentially adjacent to each other in the memory string. For example, WL0 to WL2 are one group, WL3 to WL5 are another group, and so on, until WLn-1 is assigned to a group for shutdown. Finally, the selected word line WLn is reduced to the first shutdown voltage.

[0132] Third, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the pre-charge voltage applied to some of the multiple word lines is reduced to the first shutdown voltage at a preset word line interval.

[0133] In this process, multiple target word lines are determined from multiple word lines according to a preset interval algorithm, wherein there is at least one word line interval between any two adjacent target word lines. Based on the arrangement order of the memory cells coupled to the multiple target word lines in the memory array, the pre-charge voltage applied to the multiple target word lines is sequentially reduced to the first turn-off voltage.

[0134] Indicatively, the preset interval algorithm is m = 2a - 1, where a is greater than or equal to 1, and m represents the word line number of the target word line. That is, word lines with odd-numbered line numbers are selected as target word lines. From multiple word lines, WL1, WL3, WL5, ..., WLn-1 (if n-1 is odd) are determined as target word lines. According to the arrangement order of the memory cells coupled to the multiple target word lines in the memory array, the pre-charge voltage applied to the multiple target word lines is reduced to the first shutdown voltage, and the pre-charge voltage applied to the selected word line WLn is also reduced to the first shutdown voltage. Referring to the above example, the pre-charge voltages applied to WL1, WL3, WL5, ..., WLn-1 are sequentially reduced to the first shutdown voltage, and the pre-charge voltage applied to WLn is reduced to the first shutdown voltage.

[0135] After applying a pre-charge voltage to the deselect and select word lines, as WL0 to WLn are sequentially turned off, a potential difference is generated in the channel from WL0 to WLn. This drives electrons in the channel to move towards the SSG direction and are extracted from the SSG side. As a result, the boosting potential of the channel near the select word line WLn meets the potential requirements, reducing the interference of the select word line WLn during the L0 programming stage.

[0136] In this way, the voltage intervals from WL0 to WLn are turned off sequentially, avoiding the large number of control operations and the large amount of control calculations required when turning off WL0 to WLn one by one, thus improving the turn-off efficiency.

[0137] It is worth noting that, in the above embodiments, the example of programming the storage cells in the storage string from DSG to SSG is used for illustration. In some embodiments, the storage cells in the storage string can also be programmed from SSG to DSG.

[0138] That is, in the embodiments of this application, the pre-charge voltage applied to multiple word lines is sequentially reduced to the first turn-off voltage along the direction from the drain select gate to the source select gate; or, the pre-charge voltage applied to multiple word lines is sequentially reduced to the first turn-off voltage along the direction from the source select gate to the drain select gate.

[0139] Specifically, when the pre-charge voltage applied to multiple word lines is sequentially reduced to the first turn-off voltage along the direction from the drain selection gate to the source selection gate, the source line voltage is turned on, that is, a preset voltage is applied to or not applied to the source line SL, so that electrons in the channel are discharged from the source line. When the pre-charge voltage applied to multiple word lines is sequentially reduced to the first turn-off voltage along the direction from the source selection gate to the drain selection gate, the bit line voltage is turned on, that is, a preset voltage is applied to or not applied to the bit line BL, so that electrons in the channel are discharged from the bit line.

[0140] This explanation uses the example of programming memory cells in a memory string from SSG to DSG, and applying the first turn-off voltage to each word line sequentially according to the arrangement of the memory cells coupled to multiple word lines in the memory array. For illustrative purposes, please refer to [reference needed]. Figure 7 Following the arrangement of the memory cells, the precharge voltage Vpre of WL0 to WLn-1 up to WLn is sequentially reduced to the first shutdown voltage V0, which can be 0V. The shutdown of the precharge voltages of WL0 to WLn is performed sequentially. That is, after WL0 is reduced to the first shutdown voltage V0, WL1 is reduced to the first shutdown voltage V0, and so on, until WLn-2 is reduced to the first shutdown voltage V0, then WLn-1 is reduced to the first shutdown voltage V0, and finally the selected word line WLn is reduced to the first shutdown voltage V0.

[0141] In some embodiments, to avoid a large voltage difference that would result from sequentially lowering the word line to the first turn-off voltage when the pre-charge voltage is high, thereby generating hot carrier injection (HCI), the pre-charge voltage can be lowered to a first intermediate voltage first, and then lowered from the first intermediate voltage to the first turn-off voltage.

[0142] Step 403: Apply a programming voltage to a selected word line among the multiple word lines, and apply an on-state voltage to the other word lines among the multiple word lines.

[0143] After applying a first shutdown voltage to multiple word lines, a programming voltage is applied to a selected word line to complete the L0 programming of the memory cell coupled to the selected word line.

[0144] Optionally, after applying a first shutdown voltage to the multiple word lines, an on-state voltage is applied to the deselect word line among the multiple word lines that is coupled to the programmed memory cell.

[0145] In summary, the method provided in this embodiment, when programming a selected word line, applies a pre-charge voltage during the pre-charge phase, and then sequentially reduces the pre-charge voltage applied to the word lines to a preset shutdown voltage according to the arrangement order of the multiple word lines. Since the pre-charge voltage on the word lines is turned off sequentially, when the first word line is turned off, the second word line adjacent to the first word line has not yet been turned off, thereby generating a potential difference from the first word line to the second word line in the channel. This drives the electrons in the channel to move from the direction of the first word line to the direction of the second word line. As the multiple word lines are turned off sequentially, the electrons in the channel are driven to move from the channel to one end and are extracted, thus avoiding the electrons in the channel from affecting the voltage difference between the word line and the channel, thereby affecting the programming effect of the erase state L0 after the pre-charge phase and reducing programming interference of L0.

[0146] In an optional embodiment, the aforementioned shutdown voltage is applied to both the pre-charge voltage phase and the verification voltage phase. Figure 8 This is another exemplary embodiment of a memory programming method provided in this application, which can be executed by peripheral circuitry of the memory. After step 403 above, the method includes at least the following steps.

[0147] Step 404: Apply a verification voltage to a selected word line among the multiple word lines, and apply a read voltage to the other word lines among the multiple word lines.

[0148] In other words, after applying a programming voltage to a selected word line, it is necessary to verify the programming result of the memory cell coupled to the selected word line, that is, to verify whether the memory cell coupled to the selected word line meets the programming voltage requirements. Therefore, a verification voltage is applied to the selected word line coupled to the memory cell to be programmed among the multiple word lines, and a read voltage is applied to the deselected word line coupled to the programmed memory cell among the multiple word lines.

[0149] Step 405: Apply the second shutdown voltage to the multiple word lines sequentially according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0150] In some embodiments, the second shutdown voltage is less than the verification voltage, or the second shutdown voltage is less than the read voltage, and the second shutdown voltage is a pre-configured voltage less than both the verification voltage and the read voltage. In some embodiments, the second shutdown voltage is 0V, or the second shutdown voltage is a voltage less than a preset voltage threshold, such as a preset voltage threshold of 0.5V, where the second shutdown voltage is any voltage less than 0.5V.

[0151] In some embodiments, the second shutdown voltage applied to the multiple word lines may be the same or different.

[0152] Optionally, when the verification voltage / read voltage applied to multiple word lines is sequentially reduced to the second shutdown voltage, at least one of the following methods is included:

[0153] First, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, a second shutdown voltage is applied to each of the multiple word lines one by one.

[0154] Optionally, for the deselect word lines coupled to programmed and unprogrammed memory cells in the memory string and the select word lines coupled to the memory cells to be programmed, a second turn-off voltage is applied to the deselect word lines and select word lines one by one according to the arrangement order of the memory cells in the memory string.

[0155] In some embodiments, if the memory cells in the memory string are programmed sequentially, then a second shutdown voltage is applied to the deselect word line and the select word line one by one according to the programming order of the memory cells in the memory string.

[0156] This is illustrated by taking the programming of storage units in a storage string from DSG to SSG as an example. For example... Figure 9 As shown, according to the arrangement order of the memory cells, the verification voltage Vverify or read voltage Vread of WL0 to WLn-1 up to WLn are sequentially reduced to the second shutdown voltage V0, which can be 0V. The shutdown of the verification voltage or read voltage of WL0 to WLn is performed sequentially. That is, after WL0 is reduced to the second shutdown voltage V0, WL1 is reduced to the second shutdown voltage V0, and so on, until WLn-2 is reduced to the second shutdown voltage V0, then WLn-1 is reduced to the second shutdown voltage V0, and finally the selected word line WLn is reduced to the second shutdown voltage V0.

[0157] After applying a verification voltage or a read voltage to the select word line and the select word line, as WL0 to WLn are turned off in sequence, a potential difference is generated in the channel from WL0 to WLn. This drives the electrons in the channel to move towards the SSG direction and be extracted from the SSG side. As a result, the boosting potential of the channel near the select word line WLn meets the potential requirements, reducing the interference of the select word line WLn during the programming phase of the programming state.

[0158] Second, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, a second shutdown voltage is applied to multiple word lines in groups.

[0159] Optionally, for the deselect word line coupled to the programmed memory cell in the memory string and the select word line coupled to the unprogrammed memory cell, a second shutdown voltage is applied sequentially to the deselect word line and the select word line according to the arrangement order of the programmed memory cell and the unprogrammed memory cell in the memory string, in groups.

[0160] In some embodiments, if the memory cells in the memory string are programmed sequentially, then a second shutdown voltage is applied to the deselect word line and the select word line in groups according to the programming order of the memory cells in the memory string.

[0161] In some embodiments, the grouping is for the deselect word line, and after the deselect word line is reduced to the second shutdown voltage, the verification voltage applied on the selected word line is reduced to the second shutdown voltage.

[0162] Optionally, group configuration information of multiple word lines is obtained, including multiple groups obtained by dividing the multiple word lines, wherein at least two word lines in the same group are arranged adjacently in the memory array. A second shutdown voltage is applied sequentially to the word lines in the multiple groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, on a group-by-group basis.

[0163] The grouping relationship of multiple character lines is preset, or the number of character lines within a group is preset.

[0164] Taking the preset grouping relationship of multiple word lines as an example, that is, the memory pre-stores the grouping relationship between multiple word lines coupled to the memory string, and the memory cells coupled to word lines in the same group are arranged sequentially adjacently in the memory string. For example, WL0~WLn-z-1 is one group, WLn-z~WLn-y-1 is another group. Illustratively, this is an example of programming memory cells in the memory string from DSG to SSG. Figure 10 As shown, according to the arrangement order of the memory cells, the verification voltage Vverify or read voltage Vread of WL0 to WLn are sequentially reduced to the second shutdown voltage V0, which can be 0V. The shutdown of WL0 to WLn is performed sequentially in groups. That is, after WL0 to WLn-z-1 are reduced to the second shutdown voltage V0, WLn-z to WLn-y-1 are reduced to the second shutdown voltage V0, and so on, group by group, until WLn-a to WLn-1 are reduced to the second shutdown voltage V0, at which point the selected word line WLn is reduced to the second shutdown voltage V0.

[0165] After applying a verification voltage or read voltage to the select word line and the select word line, as the groups from WL0 to WLn are turned off sequentially, a potential difference is generated in the channel from WL0 to WLn. This drives the electrons in the channel to move towards the SSG direction and be extracted from the SSG side. As a result, the boosting potential of the channel near the select word line WLn meets the potential requirements, reducing the interference of the select word line WLn during the L0 programming stage.

[0166] In this method, the voltages from WL0 to WLn are turned off sequentially in groups, which avoids the large number of control operations and the large amount of control calculations required when turning off WL0 to WLn one by one, thus improving the turn-off efficiency.

[0167] Taking a pre-set number of word lines within a group as an example, illustratively speaking, the number of word lines within a group is 3, and the memory cells coupled to word lines in the same group are arranged sequentially adjacently in the memory string. For example, WL0 to WL2 are one group, WL3 to WL5 are another group, and so on, until WLn-1 is assigned to a group for shutdown. Finally, the selected word line WLn is reduced to the second shutdown voltage.

[0168] Third, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the verification voltage or read voltage applied to some of the multiple word lines is reduced to the second shutdown voltage at a preset word line interval.

[0169] In this process, multiple target word lines are determined from multiple word lines according to a preset interval algorithm, wherein there is at least one word line interval between any two adjacent target word lines. Based on the arrangement order of the memory cells coupled to the multiple target word lines in the memory array, the verification voltage or read voltage applied to the multiple target word lines is sequentially reduced to the second shutdown voltage.

[0170] It is worth noting that, in the above embodiments, the example of programming the storage cells in the storage string from DSG to SSG is used for illustration. In some embodiments, the storage cells in the storage string can also be programmed from SSG to DSG.

[0171] That is, in the embodiments of this application, the verification voltage or read voltage applied to multiple word lines is sequentially reduced to the second turn-off voltage along the direction from the drain select gate to the source select gate; or, the verification voltage or read voltage applied to multiple word lines is sequentially reduced to the second turn-off voltage along the direction from the source select gate to the drain select gate.

[0172] The memory cells in the memory string are programmed from SSG to DSG, and a second turn-off voltage is applied to each of the multiple word lines in the memory array according to the arrangement order of the memory cells coupled to the multiple word lines.

[0173] Step 406: Apply a programming voltage to a selected word line among the multiple word lines, and apply an on-state voltage to the other word lines among the multiple word lines.

[0174] In summary, the method provided in this embodiment, when programming a selected word line, applies a verification voltage or a read voltage during the programming verification stage, and then sequentially reduces the voltage applied to the word lines to a preset second shutdown voltage according to the arrangement order of the multiple word lines. Since the shutdown is sequential, when the first word line is shut down, the second word line adjacent to the first word line has not yet been shut down, thereby generating a potential difference from the first word line to the second word line in the channel. This drives the electrons in the channel to move from the direction of the first word line to the direction of the second word line. As the multiple word lines are shut down sequentially, the electrons in the channel are driven to move from the channel to one end and are drawn away. This avoids the electrons in the channel affecting the voltage difference between the word line and the channel, thereby affecting the programming effect of other word line programming states after the programming stage and reducing programming interference.

[0175] In some embodiments, when the pre-charge voltage is large, reducing the voltage applied to the first word line to the first turn-off voltage will result in a large voltage difference between the first word line and the adjacent second word line, thereby generating the HCI effect. In this embodiment, by setting a first intermediate voltage, when the pre-charge voltage is turned off, the pre-charge voltage is first reduced to the first intermediate voltage, and then reduced from the first intermediate voltage to the first turn-off voltage. Figure 11 This is another exemplary embodiment of the present application providing a memory programming method, which can be executed by the memory's peripheral circuitry. Step 402 described above can also include the following steps.

[0176] Step 4021: According to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first intermediate voltage.

[0177] The first intermediate voltage is the voltage between the pre-charge voltage and the first turn-off voltage. In some embodiments, the first intermediate voltage is a preset voltage.

[0178] In some embodiments, the first intermediate voltage applied to the multiple word lines may be the same or different.

[0179] Optionally, when the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first intermediate voltage, at least one of the following methods is included:

[0180] First, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, a first intermediate voltage is applied to each of the multiple word lines one by one.

[0181] Optionally, for the deselect word line coupled to the programmed memory cell in the memory string and the select word line coupled to the unprogrammed memory cell, a first intermediate voltage is applied to the deselect word line and the select word line one by one according to the arrangement order of the programmed memory cell and the unprogrammed memory cell in the memory string.

[0182] In some embodiments, if the memory cells in the memory string are programmed sequentially, then a first intermediate voltage is applied to the deselect word line and the select word line one by one according to the programming order of the memory cells in the memory string.

[0183] This is illustrated by taking the programming of storage units in a storage string from DSG to SSG as an example. For example... Figure 12 As shown, according to the arrangement order of the memory cells, the pre-charge voltage Vpre of WL0 to WLn-1 up to WLn is sequentially reduced to the first intermediate voltage Vpre1. Specifically, after WL0 is reduced to the first intermediate voltage Vpre1, WL1 is reduced to the first intermediate voltage Vpre1 ​​and then sequentially turned off, until WLn-2 is reduced to the first intermediate voltage Vpre1, then WLn-1 is reduced to the first intermediate voltage Vpre1, and finally the selected word line WLn is reduced to the first intermediate voltage Vpre1.

[0184] After applying a pre-charge voltage to the deselect and select word lines, the voltage is sequentially reduced from WL0 to WLn to the first intermediate voltage Vpre1, and then reduced from the first intermediate voltage Vpre1 ​​to the first turn-off voltage. This can generate a potential difference in the channel from WL0 to WLn, thereby driving electrons in the channel to move towards the SSG direction. It can also avoid the excessive voltage difference caused by directly reducing the voltage from the pre-charge voltage to the first turn-off voltage, which would produce the HCI effect.

[0185] Second, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the first intermediate voltage is applied to the multiple word lines in groups.

[0186] Optionally, for the deselect word line coupled to the programmed memory cell in the memory string and the select word line coupled to the unprogrammed memory cell, a first intermediate voltage is applied sequentially to the deselect word line and the select word line according to the arrangement order of the programmed memory cell and the unprogrammed memory cell in the memory string, in groups.

[0187] In some embodiments, if the memory cells in the memory string are programmed sequentially, then a first intermediate voltage is applied to the deselect word line and the select word line in groups according to the programming order of the memory cells in the memory string.

[0188] In some embodiments, the grouping is for deselect word lines, and after the deselect word lines are reduced to a first intermediate voltage, the precharge voltage applied to the selected word lines is reduced to the first intermediate voltage.

[0189] Optionally, group configuration information of multiple word lines is obtained, including multiple groups obtained by dividing the multiple word lines, wherein at least two word lines in the same group are arranged adjacently in the memory array. A first intermediate voltage is applied sequentially to the word lines in the multiple groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, on a group-by-group basis.

[0190] The grouping relationship of multiple character lines is preset, or the number of character lines within a group is preset.

[0191] Third, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the pre-charge voltage applied to some of the multiple word lines is reduced to the first intermediate voltage with a preset word line interval.

[0192] In this process, multiple target word lines are determined from multiple word lines according to a preset interval algorithm, wherein there is at least one word line interval between any two adjacent target word lines. Based on the arrangement order of the memory cells coupled to the multiple target word lines in the memory array, the pre-charge voltage applied to the multiple target word lines is sequentially reduced to a first intermediate voltage.

[0193] Indicatively, the preset interval algorithm is m = 2a - 1, where a is greater than or equal to 1, and m represents the word line number of the target word line. That is, word lines with odd-numbered line numbers are selected as target word lines. From multiple word lines, WL1, WL3, WL5, ..., WLn-1 (if n-1 is odd) are determined as target word lines. The pre-charge voltage applied to the multiple target word lines is reduced to a first intermediate voltage according to the arrangement order of the memory cells coupled to the multiple target word lines in the memory array. The pre-charge voltage applied to the selected word line WLn is also reduced to the first intermediate voltage. In conjunction with the above example, the pre-charge voltages applied to WL1, WL3, WL5, ..., WLn-1 are sequentially reduced to the first intermediate voltage, and the pre-charge voltage applied to WLn is also reduced to the first intermediate voltage.

[0194] It is worth noting that, in the above embodiments, the example of programming the storage cells in the storage string from DSG to SSG is used for illustration. In some embodiments, the storage cells in the storage string can also be programmed from SSG to DSG.

[0195] That is, in the embodiments of this application, the pre-charge voltage applied to multiple word lines is sequentially reduced to a first intermediate voltage along the direction from the drain select gate to the source select gate; or, the pre-charge voltage applied to multiple word lines is sequentially reduced to a first intermediate voltage along the direction from the source select gate to the drain select gate.

[0196] Step 4022: According to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the first intermediate voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0197] In some embodiments, after a preset time interval after applying a first intermediate voltage to a word line, the first intermediate voltage applied to the word line is reduced to a first shutdown voltage, thereby producing the effect that the first intermediate voltage applied to multiple word lines is sequentially reduced to the first shutdown voltage.

[0198] In other embodiments, reducing the pre-charge voltage applied to the multiple word lines to a first intermediate voltage is done in the same or different manner as reducing the first intermediate voltage applied to the multiple word lines to a first shutdown voltage.

[0199] Schematic representation of reducing the pre-charge voltage applied to multiple word lines to a first intermediate voltage, and then to a first turn-off voltage, includes at least one of the following methods:

[0200] 1. Apply a first intermediate voltage to each of the multiple word lines in the order in which the memory cells coupled to the multiple word lines are arranged in the memory array; and apply a first shutdown voltage to each of the multiple word lines in the order in which the memory cells coupled to the multiple word lines are arranged in the memory array.

[0201] 2. Apply a first intermediate voltage to each word line in the order in which the memory cells coupled to the multiple word lines are arranged in the memory array; after the multiple word lines in the same group reach the first intermediate voltage, apply a first shutdown voltage to the multiple word lines in the order in which the memory cells coupled to the multiple word lines are arranged in the memory array, in groups.

[0202] 3. According to the arrangement order of the memory cells coupled to multiple word lines in the memory array, apply a first intermediate voltage to the multiple word lines in groups; according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, apply a first shutdown voltage to the multiple word lines one by one using the first intermediate voltage.

[0203] Fourth, according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, apply a first intermediate voltage to the multiple word lines in groups; according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, apply a first shutdown voltage to the multiple word lines in groups.

[0204] 5. According to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the pre-charge voltage applied to some of the word lines is reduced to a first intermediate voltage at a preset word line interval; according to the arrangement order of the memory cells coupled to multiple word lines in the memory array, the first intermediate voltage applied to the word lines whose voltage has been reduced to the first intermediate voltage is reduced to a first shutdown voltage at a preset word line interval.

[0205] It is worth noting that the above-described method of reducing the pre-charge voltage applied to multiple word lines to a first intermediate voltage and then to a first shutdown voltage is merely an illustrative example, and the embodiments of this application do not limit this.

[0206] In summary, the method provided in this embodiment, when programming a selected word line, applies a verification voltage or a read voltage during the programming verification stage, and then sequentially reduces the voltage applied to the word lines to a preset second shutdown voltage according to the arrangement order of the multiple word lines. Since the shutdown is sequential, when the first word line is shut down, the second word line adjacent to the first word line has not yet been shut down, thereby generating a potential difference from the first word line to the second word line in the channel. This drives the electrons in the channel to move from the direction of the first word line to the direction of the second word line. As the multiple word lines are shut down sequentially, the electrons in the channel are driven to move from the channel to one end and are drawn away. This avoids the electrons in the channel affecting the voltage difference between the word line and the channel, thereby affecting the programming effect of other word line programming states after the programming stage and reducing programming interference.

[0207] Figure 13 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 13 As shown, the memory includes peripheral circuitry 1300 and a storage array 1310.

[0208] The peripheral circuit 1300 is used to write data to the storage array 1310 and to read data from the storage array 1310.

[0209] The peripheral circuitry 1300 includes: a voltage generator 1302, a page buffer / sensor amplifier 1304, a column decoder / bit line (BL) driver 1306, a row decoder / word line (WL) driver 1308, a peripheral logic unit 1312, a register 1314, input / output circuitry 1316, and a data bus 1318. It should be understood that in some examples, it may also include... Figure 13 Additional peripheral circuitry not shown.

[0210] Page buffer / sensor amplifier 1304 can be configured to read data from memory array 1310 and program (write) data to memory array 1310 according to control signals from peripheral logic unit 1312. In one example, page buffer / sensor amplifier 1304 can store a page of programming data (write data) to be programmed into a page of memory array 1310. In another example, page buffer / sensor amplifier 1304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, page buffer / sensor amplifier 1304 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0211] The column decoder / bit line driver 1306 can be configured to be controlled by the peripheral logic unit 1312 and to select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 1302.

[0212] The line decoder / word line driver 1308 can be configured to be controlled by the peripheral logic unit 1312 and to select / deselect blocks of the memory array 1310 and select / deselect word lines of the blocks. The line decoder / word line driver 1308 can also be configured to use word line voltages (V) generated from the voltage generator 1302. WL The line decoder / word line driver 1308 drives the word lines. In some embodiments, the line decoder / word line driver 1308 can also select / deselect and drive the source select gate line and the drain select gate line. Illustratively, the line decoder / word line driver 1308 is configured to perform an erase operation on a memory cell coupled to one or more selected word lines.

[0213] Voltage generator 1302 can be configured to be controlled by peripheral logic unit 1312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 1310.

[0214] Peripheral logic unit 1312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Peripheral logic unit 1312 includes the above-described... Figure 13 The control circuit shown is shown.

[0215] Register 1314 can be coupled to peripheral logic unit 1312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 1316 can be coupled to peripheral logic unit 1312 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to peripheral logic unit 1312, as well as to buffer status information received from peripheral logic unit 1312 and relay it to the host. Input / output circuitry 1316 can also be coupled to column decoder / bitline driver 1306 via data bus 1318 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory array 1310.

[0216] It should be emphasized that the peripheral circuit 1300 is configured to perform the memory programming method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0217] Figure 14 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 14 As shown, the storage system 1400 includes: one or more memories 1410, and a memory controller 1420 coupled to the memories 1410 and configured to control the memories 1410.

[0218] Storage system 1400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0219] Optionally, the storage system 1400 may include a host and a storage subsystem, the storage subsystem having one or more memories 1410 and a memory controller 1420. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 1410. Alternatively, the host may be configured to receive data from the memory 1410.

[0220] According to some implementations, the memory controller 1420 is also coupled to a host. The memory controller 1420 can manage data stored in the memory 1410 and communicate with the host.

[0221] In some implementations, the memory controller 1420 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0222] In some implementations, the memory controller 1420 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multi media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0223] The memory controller 1420 can be configured to control the operation of the memory 1410, such as read, erase, and program operations. The memory controller 1420 can also be configured to manage various functions relating to data stored or to be stored in the memory 1410, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1420 is also configured to process error correcting codes (ECCs) relating to data read from or written to the memory 1410.

[0224] The memory controller 1420 can also perform any other suitable functions, such as formatting the memory 1410. The memory controller 1420 can communicate with external devices according to a specific communication protocol.

[0225] The memory controller 1420 and one or more memories 1410 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1400 can be implemented and packaged into different types of end electronic products.

[0226] Schematic illustration: The memory controller 1420 and a single memory 1410 can be integrated into a memory card. The memory card can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card, an SD card, UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0227] Schematic, the memory controller 1420 and multiple memories 1410 may be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0228] It is understood that the memory controller 1420 can perform memory programming methods as provided in any embodiment of this disclosure.

[0229] This application provides a control circuit, which includes programmable logic circuitry and / or program instructions. This control circuit can be used to implement the memory programming method provided in the foregoing embodiments of this application. The programming operation includes a first programming stage and a second programming stage.

[0230] Indicative, such as Figure 13As shown, the memory includes peripheral circuitry 1300 and a memory array 1310. The memory array includes multiple memory cells coupled to the first bit line and coupled to multiple word lines respectively. Among the multiple word lines, there is a selected word line coupled to the memory cell to be programmed.

[0231] The peripheral circuit 1300 is configured to apply a pre-charge voltage to the plurality of word lines;

[0232] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0233] A programming voltage is applied to the selected word line among the plurality of word lines; and an on-state voltage is applied to the other word lines among the plurality of word lines.

[0234] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0235] The first shutdown voltage is applied to each of the multiple word lines sequentially according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array; or...

[0236] The first shutdown voltage is applied to the multiple word lines in groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0237] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0238] Obtain the grouping configuration information of the multiple word lines, wherein the grouping configuration information includes multiple groups obtained by dividing the multiple word lines, wherein at least two word lines in the same group are arranged adjacently in the storage array;

[0239] The first shutdown voltage is applied sequentially to the word lines in multiple groups according to the arrangement order of the memory cells coupled to the multiple word lines in the memory array.

[0240] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0241] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to the multiple word lines is sequentially reduced to a first intermediate voltage, where the first intermediate voltage is the voltage between the pre-charge voltage and the first shutdown voltage.

[0242] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the first intermediate voltage applied to the multiple word lines is sequentially reduced to the first shutdown voltage.

[0243] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0244] Along the direction from the drain-select gate to the source-select gate, the pre-charge voltage applied to the plurality of word lines is sequentially reduced to the first turn-off voltage; or,

[0245] Along the direction from the source select gate to the drain select gate, the pre-charge voltage applied to the plurality of word lines is sequentially reduced to the first turn-off voltage.

[0246] In an optional embodiment, the plurality of word lines includes a selected word line coupled to a memory cell to be programmed and a deselected word line coupled to a programmed memory cell.

[0247] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0248] A verification voltage is applied to the selected word line among the plurality of word lines; and a read voltage is applied to the other word lines among the plurality of word lines.

[0249] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the second shutdown voltage is applied to the multiple word lines in sequence;

[0250] A programming voltage is applied to the selected word line among the plurality of word lines; and an on-state voltage is applied to the other word lines among the plurality of word lines.

[0251] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0252] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the verification voltage or read voltage applied to the multiple word lines is sequentially reduced to a second intermediate voltage; the second intermediate voltage is the voltage between the verification voltage and the second shutdown voltage, or the second intermediate voltage is the voltage between the read voltage and the second shutdown voltage;

[0253] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the second intermediate voltage applied to the multiple word lines is sequentially reduced to the second shutdown voltage.

[0254] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0255] According to the arrangement order of the memory cells coupled to the multiple word lines in the memory array, the pre-charge voltage applied to some of the multiple word lines is sequentially reduced to the first shutdown voltage at a preset word line interval.

[0256] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0257] Multiple target character lines are determined from the multiple character lines according to a preset interval algorithm, wherein there is at least one character line between two adjacent target character lines;

[0258] According to the arrangement order of the memory cells coupled to the plurality of target word lines in the memory array, the pre-charge voltage applied to the plurality of target word lines is sequentially reduced to the first shutdown voltage.

[0259] In an optional embodiment, the peripheral circuit 1300 is further configured to:

[0260] After the multiple word lines have been reduced to the first shutdown voltage, a programming voltage is simultaneously applied to the selected word line among the multiple word lines, and an on-state voltage is applied to the other word lines among the multiple word lines.

[0261] This application provides an electronic device, the electronic device comprising:

[0262] One or more memories as described in any of the above embodiments, and,

[0263] A memory controller coupled to the memory and configured to control the memory.

[0264] This application provides a computer-readable storage medium storing instructions that, when executed on a control circuit, implement the memory programming method provided in the foregoing embodiments of this application.

[0265] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0266] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0267] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, comprising: The memory includes a memory array and a peripheral circuit, the memory array includes a plurality of memory cells coupled with a first bit line and a plurality of word lines respectively, and the plurality of word lines include a selected word line to which a memory cell to be programmed is coupled; The peripheral circuit is configured to: apply a pre-charge voltage to the plurality of word lines; lower the pre-charge voltage applied to the plurality of word lines to a first off voltage in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array; apply a programming voltage to the selected word line among the plurality of word lines and apply an on voltage to other word lines among the plurality of word lines.

2. The memory of claim 1, wherein, The peripheral circuit is further configured to: apply the first off voltage to the plurality of word lines one by one in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array; or apply the first off voltage to the plurality of word lines in groups in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array.

3. The memory of claim 2, wherein, The peripheral circuit is further configured to: obtain grouping configuration information of the plurality of word lines, the grouping configuration information including a plurality of groups obtained by grouping the plurality of word lines, and at least two word lines in a same group are arranged adjacently in the memory array; apply the first off voltage to word lines in the groups one by one in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array.

4. The memory of any one of claims 1 to 3, wherein, The peripheral circuit is further configured to: lower the pre-charge voltage applied to the plurality of word lines to a first intermediate voltage in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array, the first intermediate voltage being a voltage between the pre-charge voltage and the first off voltage; lower the first intermediate voltage applied to the plurality of word lines to the first off voltage in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array.

5. The memory of any one of claims 1 to 3, wherein, The peripheral circuit is further configured to: lower the pre-charge voltage applied to the plurality of word lines to the first off voltage in an order of drain select gate to source select gate; or lower the pre-charge voltage applied to the plurality of word lines to the first off voltage in an order of source select gate to drain select gate.

6. The memory according to any one of claims 1 to 3, wherein the plurality of word lines include a selected word line to which a memory cell to be programmed is coupled and a deselected word line to which a programmed memory cell is coupled.

7. The memory of any one of claims 1 to 3, wherein, The peripheral circuit is further configured to: apply a verify voltage to the selected word line among the plurality of word lines and apply a read voltage to other word lines among the plurality of word lines; lower the pre-charge voltage applied to the plurality of word lines to a first off voltage in an order of arrangement of memory cells coupled with the plurality of word lines in the memory array; apply a programming voltage to the selected word line among the plurality of word lines and apply an on voltage to other word lines among the plurality of word lines.

8. The memory of claim 7, wherein, The peripheral circuit is further configured to: According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the verification voltage or the read voltage applied by the plurality of word lines is sequentially lowered to a second intermediate voltage; the second intermediate voltage is a voltage between the verification voltage and the second off voltage, or the second intermediate voltage is a voltage between the read voltage and the second off voltage; According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the second intermediate voltage applied by the plurality of word lines is sequentially lowered to the second off voltage.

9. The memory of any one of claims 1 to 3, wherein, The peripheral circuit is further configured to: According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the pre-charge voltage applied by part of the plurality of word lines is sequentially lowered to the first off voltage with a preset word line interval.

10. The memory of claim 9, wherein, The peripheral circuit is further configured to: According to a preset interval algorithm, a plurality of target word lines are determined from the plurality of word lines, wherein at least one word line is arranged between two adjacent target word lines; According to the arrangement order of the storage units coupled with the plurality of target word lines in the storage array, the pre-charge voltage applied by the plurality of target word lines is sequentially lowered to the first off voltage.

11. The memory of any one of claims 1 to 3, wherein, The peripheral circuit is further configured to: After the plurality of word lines are lowered to the first off voltage, a programming voltage is applied to the selected word lines in the plurality of word lines, and an on voltage is applied to other word lines in the plurality of word lines.

12. A method of programming a memory, comprising: The method comprises: applying a pre-charge voltage to a plurality of word lines; According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the pre-charge voltage applied by the plurality of word lines is sequentially lowered to the first off voltage; applying a programming voltage to the selected word lines in the plurality of word lines, and applying an on voltage to other word lines in the plurality of word lines.

13. The method of claim 12, wherein, According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the pre-charge voltage applied by the plurality of word lines is sequentially lowered to the first off voltage, comprising: According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the first off voltage is applied to the plurality of word lines one by one; or According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the first off voltage is applied to the plurality of word lines in groups.

14. The method of claim 13, wherein, According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the first off voltage is applied to the plurality of word lines in groups, comprising: obtaining grouping configuration information of the plurality of word lines, the grouping configuration information comprising a plurality of groups divided from the plurality of word lines, wherein at least two word lines in the same group are arranged adjacently in the storage array; According to the arrangement order of the storage units coupled with the plurality of word lines in the storage array, the first off voltage is sequentially applied to the word lines in the groups in units of groups.

15. The method according to any one of claims 12 to 14, characterized in that, The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising:

16. The method of any one of claims 12 to 14, wherein, The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising:

17. The method of any one of claims 12 to 14, wherein: The plurality of word lines include a selected word line to which a memory cell to be programmed is coupled and a deselected word line to which a memory cell already programmed is coupled.

18. The method of any one of claims 12 to 14, wherein, The method further comprises: applying a verify voltage to the selected word line among the plurality of word lines and applying a read voltage to other word lines among the plurality of word lines; applying a second off voltage to the plurality of word lines in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array; applying a program voltage to the selected word line among the plurality of word lines and applying a pass voltage to other word lines among the plurality of word lines.

19. The method of claim 18, wherein, The second off voltage is applied to the plurality of word lines in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The verify voltage or the read voltage applied by the plurality of word lines is sequentially lowered to a second intermediate voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array; the second intermediate voltage is a voltage between the verify voltage and the second off voltage, or the second intermediate voltage is a voltage between the read voltage and the second off voltage; The second intermediate voltage applied by the plurality of word lines is sequentially lowered to the second off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array.

20. The method of any one of claims 12 to 14, wherein, The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage in an order of arrangement of the memory cells coupled to the plurality of word lines in the memory array, comprising: The pre-charge voltage applied by the plurality of word lines is sequentially lowered to a first off voltage 21. The method of claim 20, wherein, The arrangement order of the storage units coupled to the plurality of word lines in the memory array, to sequentially lower the pre-charge voltage applied by the part of the plurality of word lines to the first off voltage with preset word line interval, comprises: determining a plurality of target word lines from the plurality of word lines according to a preset interval algorithm, wherein at least one word line is spaced between two adjacent target word lines; according to the arrangement order of the storage units coupled to the plurality of target word lines in the memory array, sequentially lowering the pre-charge voltage applied by the plurality of target word lines to the first off voltage.

22. The method of any one of claims 12 to 14, wherein, applying a programming voltage to the selected word line in the plurality of word lines; and applying an on voltage to other word lines in the plurality of word lines, comprising: after the plurality of word lines is lowered to the first off voltage is completed, simultaneously applying a programming voltage to the selected word line in the plurality of word lines, and applying an on voltage to other word lines in the plurality of word lines.

23. A storage system, characterized by The storage system comprises: one or more memories as claimed in any of claims 1 to 11, and a memory controller coupled to the memory and configured to control the memory.

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