Memory, memory system, programming method of memory and storage medium

Abstract

The invention provides a memory, a memory system, a programming method of the memory and a storage medium, and relates to the technical field of storage. The memory includes: a memory cell array including an outer memory chip and an inner memory chip; and a peripheral circuit; the peripheral circuit is configured to determine an initial programming voltage used for executing programming operation on a selected storage unit, the initial programming voltage corresponds to a storage piece where the selected storage unit is located, and the initial programming voltage corresponding to an outer side storage piece is larger than the initial programming voltage corresponding to an inner side storage piece; and performing programming operation on the selected memory unit according to the initial programming voltage. According to the scheme, the programming efficiency and the data stability can be improved while interference to the adjacent storage units caused by programming can be avoided as much as possible.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a storage system, a method for programming the memory, and a storage medium. Background Technology

[0002] In memory products such as NAND, incremental step programming (ISPP) is typically used to perform programming operations.

[0003] In related technologies, when a peripheral circuit programs a selected memory cell in a memory, it can start from the initial programming voltage and perform one or more programming operations on the selected memory cell in a sequentially increasing manner until the state of the selected memory cell reaches the target state, or the number of programming operations reaches a threshold. Summary of the Invention

[0004] This application provides a memory, a memory system, a memory programming method, and a memory medium, which can improve the programming efficiency of memory cells in the outermost memory chips of a memory cell array. The technical solution is as follows:

[0005] On one hand, a memory is provided, the memory comprising: a memory cell array including outer memory chips and inner memory chips, the outer memory chips being the outermost memory chips in the memory cell array; the inner memory chips being the other memory chips in the memory cell array besides the outer memory chips; and peripheral circuitry; the peripheral circuitry being configured to: determine a starting programming voltage used to perform a programming operation on a selected memory cell, the starting programming voltage corresponding to the memory chip in which the selected memory cell is located, the starting programming voltage corresponding to the outer memory chip being greater than the starting programming voltage corresponding to the inner memory chip; and perform a programming operation on the selected memory cell according to the starting programming voltage.

[0006] In an optional embodiment, in the outer storage chip, the diameter of the via of one or more storage strings located on the outermost side of the storage cell array is larger than the diameter of the vias of other storage strings in the storage cell array.

[0007] In an optional embodiment, the peripheral circuit is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip containing the selected memory cell is the outer memory chip or the inner memory chip; and determine the starting programming voltage based on the memory chip type indication information.

[0008] In an optional embodiment, the peripheral circuit is configured to: when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a first voltage corresponding to the inner memory chip as the starting programming voltage; and when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the outer memory chip, determine a second voltage corresponding to the outer memory chip as the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a second voltage corresponding to the inner memory chip as the starting programming voltage. The starting programming voltage is determined as follows: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, a first offset voltage is added to the first voltage to obtain the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, a second voltage corresponding to the inner memory chip is determined as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the first offset voltage is subtracted from the second voltage to obtain the starting programming voltage.

[0009] In an optional embodiment, the peripheral circuit is configured to: determine the initial programming voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the initial programming voltage is inversely correlated with the memory chip spacing distance.

[0010] In an optional embodiment, the peripheral circuitry is further configured to determine the step voltage of the Incremental Step Pulse Programming (ISPP) used to perform a programming operation on the selected memory cell; the peripheral circuitry is configured to perform an ISPP operation on the selected memory cell based on the initial programming voltage and the step voltage; wherein the step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

[0011] In an optional embodiment, the peripheral circuit is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip containing the selected memory cell is the outer memory chip or the inner memory chip; and determine the step voltage based on the memory chip type indication information.

[0012] In an optional embodiment, the peripheral circuit is configured to: when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a third voltage corresponding to the inner memory chip as the step voltage; and when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the outer memory chip, determine a fourth voltage corresponding to the outer memory chip as the step voltage; or, when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a third voltage corresponding to the inner memory chip as the step voltage. The step voltage is determined as follows: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the step voltage is obtained by adding a second offset voltage to the third voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the fourth voltage corresponding to the inner memory chip is determined as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the step voltage is obtained by subtracting the second offset voltage from the fourth voltage.

[0013] In an optional embodiment, the peripheral circuit is configured to: determine the step voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the step voltage is inversely correlated with the memory chip spacing distance.

[0014] In an optional embodiment, the memory chip type indication information includes one or more of the following: the memory chip number where the selected memory cell is located; the physical address of the selected memory cell; and an indication identifier in the write command, which is used to instruct the selected memory cell to perform a programming operation.

[0015] On the other hand, a storage system is provided, the storage system comprising: a memory and a controller; the memory cell array includes outer memory chips and inner memory chips, the outer memory chips being the outermost memory chips in the memory cell array; the inner memory chips being the other memory chips in the memory cell array besides the outer memory chips; the controller is configured to send a write command to the memory; the memory is configured to receive the write command; the memory is configured to determine, based on the write command, a starting programming voltage for performing a programming operation on a selected memory cell, the starting programming voltage corresponding to the memory chip where the selected memory cell is located, wherein the starting programming voltage corresponding to the outer memory chip is greater than the starting programming voltage corresponding to the inner memory chip; and to perform a programming operation on the selected memory cell based on the starting programming voltage.

[0016] In an optional embodiment, in the outer storage chip, the diameter of the via of one or more storage strings located on the outermost side of the storage cell array is larger than the diameter of the vias of other storage strings in the storage cell array.

[0017] In an optional embodiment, the memory is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip containing the selected memory cell is the outer memory chip or the inner memory chip; and determine the starting programming voltage based on the memory chip type indication information.

[0018] In an optional embodiment, the memory is configured to: when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a first voltage corresponding to the inner memory chip as the starting programming voltage; and when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the outer memory chip, determine a second voltage corresponding to the outer memory chip as the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a second voltage corresponding to the inner memory chip as the starting programming voltage. The starting programming voltage is determined by adding a first offset voltage to the first voltage when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the second voltage corresponding to the inner memory chip is determined as the starting programming voltage, and when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the first offset voltage is subtracted from the second voltage to obtain the starting programming voltage.

[0019] In an optional embodiment, the memory is configured to: determine the initial programming voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the initial programming voltage is inversely related to the memory chip spacing distance.

[0020] In an optional embodiment, the memory is further configured to determine the step voltage of the Incremental Step Pulse Programming (ISPP) used to perform a programming operation on the selected memory cell; the memory is configured to perform an ISPP operation on the selected memory cell based on the initial programming voltage and the step voltage; wherein the step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

[0021] In an optional embodiment, the memory is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip containing the selected memory cell is the outer memory chip or the inner memory chip; and determine the step voltage based on the memory chip type indication information.

[0022] In an optional embodiment, the memory is configured to: when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a third voltage corresponding to the inner memory chip as the step voltage; and when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the outer memory chip, determine a fourth voltage corresponding to the outer memory chip as the step voltage; or, when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determine a third voltage corresponding to the inner memory chip as the step voltage. The step voltage is determined as follows: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the step voltage is obtained by adding a second offset voltage to the third voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the fourth voltage corresponding to the inner memory chip is determined as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the step voltage is obtained by subtracting the second offset voltage from the fourth voltage.

[0023] In an optional embodiment, the memory is configured to: determine the step voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the step voltage is inversely related to the memory chip spacing distance.

[0024] In an optional embodiment, the memory chip type indication information includes one or more of the following: the memory chip number where the selected memory cell is located; the physical address of the selected memory cell; and an indication identifier in the write command, which is used to instruct the selected memory cell to perform a programming operation.

[0025] On the other hand, a method for programming a memory is provided. The memory includes a memory cell array and peripheral circuitry. The memory cell array includes outer memory chips and inner memory chips. The outer memory chips are the outermost memory chips in the memory cell array. The inner memory chips are the other memory chips in the memory cell array besides the outer memory chips. The method includes: the peripheral circuitry determining a starting programming voltage used to perform a programming operation on a selected memory cell. The starting programming voltage corresponds to the memory chip where the selected memory cell is located, and the starting programming voltage corresponding to the outer memory chip is greater than the starting programming voltage corresponding to the inner memory chip. The peripheral circuitry then performs a programming operation on the selected memory cell based on the starting programming voltage.

[0026] In an optional embodiment, in the outer storage chip, the diameter of the via of one or more storage strings located on the outermost side of the storage cell array is larger than the diameter of the vias of other storage strings in the storage cell array.

[0027] In an optional embodiment, the peripheral circuitry determines the starting programming voltage used to perform a programming operation on the selected memory cell, including: the peripheral circuitry acquiring memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip containing the selected memory cell is the outer memory chip or the inner memory chip; and the peripheral circuitry determining the starting programming voltage based on the memory chip type indication information.

[0028] In an optional embodiment, the peripheral circuit determines the starting programming voltage based on the memory chip type indication information, including: when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, the peripheral circuit determines a first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the outer memory chip, the peripheral circuit determines a second voltage corresponding to the outer memory chip as the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, the peripheral circuit determines a second voltage corresponding to the inner memory chip as the starting programming voltage. The first voltage corresponding to the setting is determined as the starting programming voltage. When the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the peripheral circuit adds a first offset voltage to the first voltage to obtain the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the peripheral circuit determines the second voltage corresponding to the inner memory chip as the starting programming voltage. When the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the peripheral circuit subtracts the first offset voltage from the second voltage to obtain the starting programming voltage.

[0029] In an optional embodiment, the peripheral circuitry determines the initial programming voltage used to perform a programming operation on the selected memory cell, including: the peripheral circuitry determining the initial programming voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the initial programming voltage is inversely correlated with the memory chip spacing distance.

[0030] In an optional embodiment, the method further includes: the peripheral circuit determining a step voltage for Incremental Step Pulse Programming (ISPP) used to perform a programming operation on the selected memory cell; the peripheral circuit performing a programming operation on the selected memory cell based on the initial programming voltage, including: the peripheral circuit performing an ISPP operation on the selected memory cell based on the initial programming voltage and the step voltage; wherein the step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

[0031] In an optional embodiment, the peripheral circuitry determines the step voltage of the Incremental Step Pulse Programming (ISPP) used to perform a programming operation on the selected memory cell, including: the peripheral circuitry acquiring memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip containing the selected memory cell is the outer memory chip or the inner memory chip; and the peripheral circuitry determining the step voltage based on the memory chip type indication information.

[0032] In an optional embodiment, the peripheral circuit determines the step voltage based on the memory chip type indication information, including: when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determining a third voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the outer memory chip, determining a fourth voltage corresponding to the outer memory chip as the step voltage; or, when the memory chip type indication information indicates that the memory chip containing the selected memory cell is the inner memory chip, determining a fourth voltage corresponding to the inner memory chip as the step voltage. The third voltage corresponding to the chip is determined as the step voltage. When the chip type indication information indicates that the chip where the selected memory cell is located is the outer chip, the second offset voltage is added to the third voltage to obtain the step voltage; or, when the chip type indication information indicates that the chip where the selected memory cell is located is the outer chip, the fourth voltage corresponding to the inner chip is determined as the step voltage. When the chip type indication information indicates that the chip where the selected memory cell is located is the inner chip, the second offset voltage is subtracted from the fourth voltage to obtain the step voltage.

[0033] In an optional embodiment, the peripheral circuitry determines the step voltage of the Incremental Step Pulse Programming (ISPP) used to perform a programming operation on the selected memory cell, including: the peripheral circuitry determining the step voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the step voltage is inversely correlated with the memory chip spacing distance.

[0034] In an optional embodiment, the memory chip type indication information includes one or more of the following: the memory chip number where the selected memory cell is located; the physical address of the selected memory cell; and an indication identifier in the write command, which is used to instruct the selected memory cell to perform a programming operation.

[0035] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a memory in a storage system, implement the memory programming method as described in any of the above embodiments.

[0036] The technical solution provided in this application may include the following beneficial effects:

[0037] In 3D NAND flash memory, due to manufacturing processes and techniques, the actual size of the outermost cells in the cell array often deviates significantly from the designed size. Programming these cells with large size discrepancies typically requires higher programming voltages to succeed. To address this, in this application, the cell array is divided into outermost cells and inner cells. For cells on the outermost cells, the peripheral circuitry uses a higher initial programming voltage. This higher initial programming voltage reduces the number of programming attempts required for cells with larger size discrepancies (improving programming efficiency) and increases the success rate of a single programming attempt (improving data stability). Conversely, for cells on the inner cells, the peripheral circuitry uses a lower initial programming voltage, which suppresses interference with neighboring cells. In other words, the solution provided in this application improves programming efficiency and data stability while minimizing interference with neighboring cells caused by programming. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the structure of a memory card involved in this application;

[0041] Figure 3 This is a schematic diagram of the structure of a solid-state driver involved in this application;

[0042] Figure 4 This is a block diagram of a memory illustrated in an exemplary embodiment of this application;

[0043] Figure 5 This is a schematic circuit diagram of a memory shown in an exemplary embodiment of this application;

[0044] Figure 6 This is a cross-sectional side view of a storage string shown in an exemplary embodiment of this application;

[0045] Figure 7 This is a schematic diagram of a storage cell array;

[0046] Figure 8 This is a schematic diagram of another type of storage cell array;

[0047] Figure 9 This is a structural block diagram of a memory provided in an exemplary embodiment of this application;

[0048] Figure 10 This is a schematic diagram illustrating the programming effects involved in the embodiments of this application;

[0049] Figure 11 This is a programming diagram of a memory according to an embodiment of this application;

[0050] Figure 12 This is a programming diagram of another memory involved in an embodiment of this application;

[0051] Figure 13 This is a programming diagram of yet another type of memory involved in an embodiment of this application;

[0052] Figure 14 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application;

[0053] Figure 15 This is a flowchart of a memory programming method provided in an exemplary embodiment of this application. Detailed Implementation

[0054] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0055] The computer system provided in this application embodiment may include a host and a storage system. The storage system may include 3D memory, such as 3D NAND flash memory.

[0056] Figure 1 This is a schematic diagram of a computer system provided in one embodiment of this application. Figure 1 As shown, the computer system 10 includes: one or more memories 100, and a controller 200 coupled to the memories 100 and configured to control the memories 100. The controller 200 may also be referred to as a memory controller.

[0057] Controller 200 can be configured to control operations performed by memory 100, such as read, erase, and program operations. Controller 200 can also be configured to manage various functions related to data stored or to be stored in memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to memory 100. Controller 200 can also perform any other suitable functions, such as formatting memory 100.

[0058] The controller 200 can also communicate with external devices according to a specific communication protocol. For example, the controller 200 can communicate with external devices through at least one of various interface protocols. The interface protocol can be Universal Serial Bus (USB) protocol, Multi-Media Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Development Environment (IDE) protocol, FireWire protocol, etc.

[0059] In an optional embodiment, the controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices can be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In this scenario, such as... Figure 1 As shown, the computer system 10 also includes a host 300. A controller 200 is coupled to the host 300. The controller 200 can manage data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0060] In other embodiments, the controller 200, and one or more memories 100, can be integrated into various types of storage devices.

[0061] As an example, Figure 2 This is a schematic diagram of the structure of a memory card involved in this application. Figure 2 As shown, the controller 200 and a single memory 100 can be integrated into the memory card 40. The memory card 40 may include PCMCIA (PC) cards, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 40 may also include a connector 410 for coupling the memory card 40 to the host.

[0062] As another example Figure 3 This is a schematic diagram of the structure of a solid-state drive involved in this application. Figure 3 As shown, the controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 50. The solid-state drive 50 may also include a connector 510 for coupling the solid-state drive 50 to the host. The storage capacity and / or operating speed of the solid-state drive 50 is greater than that of the memory card 40.

[0063] also, Figures 1 to 3The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0064] Figure 4 This is a block diagram illustrating a memory according to an exemplary embodiment of this application. (Reference) Figure 4 The memory 400 may include a memory cell array 401, a page buffer 404, a column decoder 406, a row decoder 408, a voltage generator 410, a control logic unit 412, a register 414, and data input / output circuitry 416. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0065] Page buffer 404 can be configured to read data from memory cell array 401 and program (write) data to memory cell array 401 according to control signals from control logic unit 412. In one example, page buffer 404 can store data to be programmed into selected pages of memory cell array 401 (write data). In another example, page buffer 404 can output read data during a programming verification operation to ensure that data has been correctly programmed into the corresponding memory cell coupled to the selected word line of memory cell array 401. Column decoder 406 can operate in response to control signals provided by control logic unit to select one or more NAND memory strings in memory cell array 401. Row decoder can operate in response to control signals provided by control logic unit and select / deselect selected rows of memory cell array 401. Row decoder can also be configured to supply voltage generated from voltage generator 410 to selected and unselected word lines of memory cell array 401. As described in detail below, row decoder 408 is configured to perform erase operations on memory cells coupled to one or more selected word lines of memory cell array 401. Voltage generator 410 can use external or internal power supply voltages to generate various voltages required by the memory, such as programming voltage, read voltage, pass voltage, verification voltage, bit line voltage, and combinations thereof.

[0066] Control logic unit 412 can be coupled to voltage generator 410, page buffer 404, column decoder 406, row decoder 408, and data input / output circuit 416, etc., and is configured to control the operation of each peripheral circuit. Control logic unit can generate operation signals in response to commands or control signals from the memory controller. Register 414 can be coupled to control logic unit 412 and includes a status register, command register, and address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit. Data input / output circuit 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 412, and to buffer status information received from control logic unit 412 and relay it to the host. Data input / output circuit 416 can also be coupled to column decoder and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 401.

[0067] Figure 5 This is a schematic circuit diagram of a memory shown in an exemplary embodiment of this application. Figure 5 As shown, memory 500 may include a memory cell array device 501 and peripheral circuitry 502 coupled to the memory cell array device 501. The memory cell array device 501 may be a NAND flash memory cell array, wherein memory cells 506 are provided in the form of an array of NAND memory strings 508, each NAND memory string 508 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 508 includes a plurality of memory cells 506 coupled in series and stacked vertically. Each memory cell 506 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. In some embodiments, each memory cell 506 is a single-level cell (SLC) having two possible memory states and capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 506 is a multilevel cell capable of storing more than a single bit of data in more than two memory states. For example, each cell can store two bits (i.e., Multi-Level Cell (MLC)), three bits (i.e., Triple-Level Cell (TLC)), or four bits (i.e., Quad-Level Cell (QLC)).

[0068] like Figure 5 As shown, each NAND memory string 508 may include at least one source select transistor 510 at its source end and at least one drain select transistor 512 at its drain end. The source select transistor 510 and drain select transistor 512 may be configured to activate a selected NAND memory string 508 during read and program operations. In some embodiments, the sources of NAND memory strings 508 in the same block 504 are coupled via the same source line (SL). According to some embodiments, the drain select transistor 512 of each NAND memory string 508 is coupled to a corresponding bit line 516. In some embodiments, each NAND memory string 508 is configured to be selected or deselected by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding drain select transistor 512 via one or more drain select lines 513 and / or by applying a select voltage or deselect voltage (e.g., 0V) to the corresponding source select transistor 510 via one or more source select lines 515.

[0069] like Figure 5 As shown, the memory cell array may include multiple blocks. In some embodiments, each block 504 is a basic data unit for erase operations, that is, all memory cells 506 on the same block 504 are erased simultaneously.

[0070] Figure 6 This is a cross-sectional side view of a storage string illustrated in an exemplary embodiment of this application. See also: Figure 6 The memory string 508 can extend vertically through the memory cell stack layer 620 above the doped semiconductor layer 610. The doped semiconductor layer 610 is coupled to the source line. In some embodiments, the doped semiconductor layer 610 is an N-type doped semiconductor layer, in which case the doped semiconductor layer 610 can serve as a substrate, i.e., an N-type substrate. In other embodiments, the doped semiconductor layer 610 is a P-type doped semiconductor layer, in which case the doped semiconductor layer 610 is a P-well in the substrate, i.e., a P-type substrate.

[0071] The memory cell stack 620 includes alternating gate conductive layers 630 and gate-to-gate dielectric layers 640. The logarithm of the gate conductive layers 630 and gate-to-gate dielectric layers 640 in the memory cell stack 620 determines the number of memory cells in the memory array. The gate conductive layers 630 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In one possible implementation, each gate conductive layer 630 includes a metal layer, such as a tungsten layer. In some implementations, each gate conductive layer 630 includes a doped polysilicon layer. Each gate conductive layer 630 may include a gate surrounding a memory cell and may extend laterally at the top of the memory cell stack 620 as a drain select line (DSL) 513, at the bottom of the memory cell stack 620 as a source select line (SSL) 515, or between the DSL and SSL as a word line (WL) 670.

[0072] like Figure 6 As shown, the memory string 508 also includes a channel structure 650 extending vertically through the memory cell stack layer 620. The channel structure 650 includes channel vias filled with at least one semiconductor material (such as a semiconductor channel) and at least one dielectric material (such as a memory film). In some embodiments, the semiconductor channel includes silicon (such as a memory film). In some embodiments, the memory film is a composite dielectric layer including a tunnel layer, a trap layer, and a barrier layer. The channel structure 650 may have a cylindrical shape (such as a pillar shape). According to some embodiments, the semiconductor channel, the trap layer (also referred to as the memory layer), and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The trap layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide.

[0073] like Figure 6 As shown, a doped semiconductor layer 660 is stacked on top of the memory cell stacking layer 620 in the memory string 508. The doped semiconductor layer 660 is also called the bit line contact. The doped semiconductor layer 660 is coupled to the bit line and is an N-type doped semiconductor layer.

[0074] When the doped semiconductor layer 660 is an N-type doped semiconductor layer, the memory string 508 can be erased using a gate-induced drain leakage (GIDL) erasure method via the bit lines coupled to the doped semiconductor layer 660 and the DSL coupled to the TSG in the memory string 508. For example, an erase voltage is applied to the bit lines coupled to the doped semiconductor layer 660, so that the erase voltage acts on the doped semiconductor layer 660. A voltage smaller than the erase voltage is applied to the DSL coupled to the TSG in the memory string 508, creating a voltage difference between the gate of the TSG and the doped semiconductor layer 660. This voltage difference causes band-to-band tunneling at the location between the gate of the TSG and the doped semiconductor layer 660, generating GIDL. Holes in the GIDL move from this location into the channel of the memory string 508, thereby injecting holes into the channel of the memory string 508 from this location, increasing the channel potential. A voltage less than the erase voltage (referred to as a low voltage, such as 0V) is applied to the word line coupled to each memory cell in the memory string 508 to apply the low voltage to the gate of the memory cell. As the channel potential of the memory cell increases, the voltage difference between the gate and the channel of the memory cell increases. When the voltage difference is greater than the tunneling voltage of the memory cell, the voltage difference causes a tunneling effect between the channel and the gate of the memory cell. As a result, the holes in the channel of the memory cell tunnel to the memory layer of the memory cell to eliminate the electrons in the memory layer, thereby erasing the memory cell.

[0075] In some embodiments, when the doped semiconductor layer 610 is an N-type doped semiconductor layer, the sub-string block can be erased using a GIDL erasure method via the source line coupled to the doped semiconductor layer 610 and the SSL coupled to the BSG in the memory string 508. For example, an erase voltage is applied to the source line, and a voltage lower than the erase voltage (referred to as a low voltage) is applied to the SSL coupled to the BSG, causing a GIDL to be generated at the position between the gate of the BSG and the doped semiconductor layer 610. Holes in the GIDL move towards the channel, thereby injecting holes into the channel of the memory string 508 from this position, increasing the potential of the channel. A low voltage is applied to the word line coupled to each memory cell in the memory string 508. As the channel potential of the memory cell increases, when the voltage difference between the gate of the memory cell and the channel of the memory cell is greater than the tunneling voltage of the memory cell, the holes in the channel tunnel to the memory layer of the memory cell to eliminate electrons in the memory layer, thereby erasing the memory cell.

[0076] Based on this, when both the doped semiconductor layer 610 and the doped semiconductor layer 610 are N-type doped semiconductor layers, the peripheral circuit can perform the GIDL erasure operation on the storage string 508 at either end (i.e., single-ended GIDL erasure), or it can perform the GIDL erasure operation on both ends of the storage string 508 (i.e., double-ended GIDL erasure).

[0077] In other embodiments, when the doped semiconductor layer 610 is a P-type doped semiconductor layer, the memory string 508 is erased based on the erasure method of the P-type doped semiconductor layer. For example, an erase voltage is applied to the source line to apply the erase voltage to the P-type doped semiconductor layer, causing holes to be generated in the P-type doped semiconductor layer. A low voltage is applied to the BSG of the memory string 508 and the word lines coupled to each memory cell, so that the low voltage applies to the gate of the BSG and the gate of each memory cell. Since the low voltage is less than the erase voltage, holes move from the P-type doped semiconductor layer to the channel of the memory string 508 to inject holes from the P-type doped semiconductor layer into the channel, causing the channel potential to rise. As the channel potential of the memory cell increases, when the voltage difference between the gate of the memory cell and the channel of the memory cell is greater than the tunneling voltage of the memory cell, the holes in the channel tunnel to the memory layer of the memory cell to eliminate electrons in the memory layer, thereby erasing the memory cell.

[0078] Therefore, when the doped semiconductor layer 660 is an N-type doped semiconductor layer and the doped semiconductor layer 610 is a P-type doped semiconductor layer, double-ended erasure can be performed on the memory string 508. For example, a single-ended GIDL erasure can be performed at the end of the memory string 508 closest to the N-type doped semiconductor layer, and an erasure based on the P-type doped semiconductor layer can be performed at the other end of the memory string 508. Alternatively, single-ended erasure can be performed on the memory string 508. For example, a single-ended GIDL erasure can be performed at the end of the memory string 508 closest to the P-type doped semiconductor layer, without performing an erasure based on the P-type doped semiconductor layer at the other end of the memory string 508; or, a single-ended GIDL erasure can be performed at the end of the memory string 508 closest to the P-type doped semiconductor layer, and an erasure based on the P-type doped semiconductor layer can be performed at the other end of the memory string 508.

[0079] For any technical details not disclosed in the above memory-related hardware embodiments, please refer to the descriptions of the computer system embodiments and method embodiments of this application for understanding.

[0080] Please refer to Figure 7 This illustrates a schematic diagram of a memory cell array. Figure 7 As shown, the storage cell array is divided into multiple storage slices (String), each storage slice contains multiple storage strings, and multiple storage slices (String) Figure 7The diagram shows two memory chips forming a pointer memory area, and multiple pointer memory areas (shown as two memory chips) constitute a pointer memory area. Figure 7 The diagram shows three pointer memory regions that constitute a memory block. Adjacent memory chips within the same pointer memory region, as well as different pointer memory regions, are isolated by a gate isolation structure.

[0081] In the embodiments of this application, such as Figure 7 As shown, in the structure of the above-mentioned memory cell array, the outermost memory chip (e.g., Figure 7 The memory chips 701 and 702 are called outer memory chips, and the other memory chips besides the outer memory chips are called inner memory chips.

[0082] With the development of the semiconductor industry, 3D NAND requires higher bit density, and NAND with porous (through-channel) structures can effectively improve bit density.

[0083] A channel hole (VH) is a narrow, elongated hole in 3D NAND flash memory that runs perpendicular to the wafer surface from top to bottom and through multiple layers of memory cells. These vias penetrate the entire stacked structure and are filled with conductive material, forming conductive channels between each memory layer. This allows electrons to move between memory cells for read, write, and erase operations.

[0084] In porous 3D NAND products, due to the manufacturing process, as the number of vias in the memory cell array increases, the process variation also increases. This results in the via size (diameter) of the memory cell located at the edge of the memory cell array being significantly larger than the via size of the memory cell corresponding to other memory cells.

[0085] Please refer to Figure 8 This illustrates a schematic diagram of another type of memory cell array. For example... Figure 8 As shown, in a 3D NAND product with a porous structure, the memory chips in the memory cell array are divided into outer memory chips and inner memory chips. The diameter of the via 801 of the memory string located at the edge of the entire memory cell array in the outer memory chip is larger than the diameter of the via 802 of other memory cells in the memory cell array.

[0086] NAND flash memory products use incremental step pulse programming (ISPP) to perform programming operations. Because each memory cell is in a different state, for a memory cell in good condition, programming may only require a single voltage application (i.e., the initial programming voltage). However, for a memory cell in poor condition, it may be necessary to increase the programming voltage based on the initial programming voltage to complete the programming operation. The increased voltage value is broken down into multiple sub-steps, each increasing the voltage by a small amount (also called step voltage). Then, it is verified whether the memory cell has reached the target voltage. If the target voltage is reached, the programming is successful, and the current programming operation ends. If the target voltage is not reached, and the number of programming attempts (or the programming pulse count) has not reached its maximum value, the step voltage is increased again based on the previous programming voltage to perform the programming operation on the memory cell.

[0087] In one scenario, when a memory (such as a TLC NAND flash memory) is programmed using the ISPP (Intense Programming Process) method, a program-multiple-verification (IPF) programming mode can be employed. This means that starting from the initial programming voltage, after each programming operation on a memory cell, it is verified whether the cell has reached the target voltage. If the target voltage is not reached, the voltage step is increased, and the programming operation is repeated until the cell reaches the target voltage or the maximum number of programming operations is reached. In this IPF programming mode, if a lower initial programming voltage is used for all memory cells, then when programming cells in the memory strings located at the edge of the array, the required programming voltage is higher. Therefore, the number of programming operations for cells in the memory strings at the edge of the array will also be higher. For example, if cells in non-edge memory strings require 1-3 programming operations, cells in edge memory strings may require 5-6, leading to a decrease in programming efficiency for cells in the edge memory strings.

[0088] In another scenario, memory (such as SLC NAND flash memory) can also use a single-program, zero-verification programming mode (i.e., 1P0V mode) when performing programming operations via ISPP. This means that when programming a memory cell, only the initial programming voltage is used once, and there is no need to verify whether the memory cell has reached the target voltage. In this single-program, zero-verification mode, if a lower initial programming voltage is used for all memory cells, when programming cells in the memory strings at the edge of the array, the required programming voltage is higher. Therefore, after a single programming operation with the initial programming voltage, the voltage of the memory cells at the edge of the array may not reach the target state, resulting in a poor E1 (read window) index and affecting the stability of the data stored in that cell.

[0089] Furthermore, regardless of whether it is a programming mode of multiple programming and multiple verification or a programming mode of single programming and zero verification, if a higher initial programming voltage is uniformly used for all memory cells, although it can improve the programming efficiency and data stability of memory cells in the memory string at the edge of the memory cell array, other memory cells may cause interference to neighboring memory cells due to the higher initial programming voltage, thereby affecting the accuracy of the data stored in neighboring memory cells.

[0090] To address the aforementioned issues, the solutions presented in subsequent embodiments of this application employ a novel programming method for the memory, which can improve programming efficiency and data stability while minimizing interference to adjacent memory cells caused by programming.

[0091] Figure 9 This is a structural block diagram of a memory provided in an exemplary embodiment of this application, such as... Figure 9 As shown, the memory 900 includes: a memory cell array 902, which includes outer memory chips and inner memory chips. The outer memory chips are the outermost memory chips in the memory cell array; the inner memory chips are the other memory chips in the memory cell array besides the outer memory chips; and...

[0092] Peripheral circuit 901; the peripheral circuit 901 is configured to: determine the starting programming voltage used to perform a programming operation on a selected memory cell, the starting programming voltage corresponding to the memory chip on which the selected memory cell is located, the starting programming voltage corresponding to the outer memory chip being greater than the starting programming voltage corresponding to the inner memory chip; and perform a programming operation on the selected memory cell according to the starting programming voltage.

[0093] The selected memory cell mentioned above refers to the memory cell that the peripheral circuit 901 is currently programming, or the selected memory cell can also be called the memory cell to be programmed.

[0094] The aforementioned outer memory chip refers to a memory chip located at the edge of a memory cell array. In other words, in the memory cell array, an outer memory chip has adjacent memory chips isolated from each other on one side by a gate isolation structure, while the other side has no adjacent memory chips. Correspondingly, in the memory cell array, an inner memory chip has adjacent memory chips isolated from each other on both sides by a gate isolation structure.

[0095] In the aforementioned memory, when the peripheral circuit 901 performs a programming operation, it applies a programming voltage on a per-segment basis (one segment of memory is called a string). That is, when the peripheral circuit 901 performs a programming operation on a selected memory cell, it needs to apply a programming voltage to the entire string containing that selected memory cell. Therefore, in this embodiment, the peripheral circuit 901 can use different starting programming voltages for the outer and inner memory cells in the memory cell array 902. Specifically, when the selected memory cell is a memory cell in an outer memory cell, the peripheral circuit 901 starts with a higher starting programming voltage and applies a programming voltage to the outer memory cell containing the selected memory cell. In the 1P0V programming mode, only one programming operation needs to be performed on the selected memory cell using the starting programming voltage. However, in the programming mode of multiple programming and multiple verification, it may be necessary to start with the starting programming voltage and increase the programming voltage sequentially to perform multiple programming operations on the selected memory cell.

[0096] In 3D NAND flash memory, due to process and technology limitations, it is difficult to guarantee the consistency of the process among the individual memory cells in the array. This results in a significant discrepancy between the actual size and the design size of the outermost memory cells. Programming these cells with large size errors often requires a higher programming voltage to succeed. To address this, in this application, the memory chips in the array are divided into outer chips (located at the outermost edge of the array) and inner chips (excluding the outer chips). For the memory cells on the outer chips, the peripheral circuitry uses a larger initial programming voltage to perform the programming operation. This larger initial programming voltage reduces the number of programming attempts required for the outer chips with larger size errors (improving programming efficiency) and increases the success rate of a single programming attempt (improving data stability). Conversely, for the memory cells on the inner chips, the peripheral circuitry uses a smaller initial programming voltage to perform the programming operation. This smaller initial programming voltage suppresses interference with neighboring memory cells. In other words, the solution provided in this application can improve programming efficiency and data stability while minimizing interference to neighboring memory cells caused by programming.

[0097] In other words, the above-described solution in this application provides a programming control scheme in which the peripheral circuitry in the memory can select different starting programming voltages based on the string containing the selected memory cell. Specifically, using a higher starting programming voltage for the outer string than for the inner string reduces the programming pulse count of the outer string, improves the programming time of the outer string, and achieves better results for memories with more vias and poorer process consistency.

[0098] Specifically, for example, in the multiple programming and multiple verification programming mode, the scheme shown in the above embodiments uses a higher initial programming voltage for the memory cells in the outer memory chip and a lower initial programming voltage for the memory cells in the inner memory chip. This allows the memory cells in the outer memory chip to reach the target voltage with fewer programming cycles, just like the memory cells in the inner memory chip. This enables the memory cells in the outer memory chip to have similar programming efficiency to the memory cells in the inner memory chip. For example, with the scheme shown in the above embodiments, both the memory cells in the outer memory chip and the memory cells in the inner memory chip can reach the target voltage in 1-3 programming cycles.

[0099] For example, in the programming mode of one-time programming and zero-verification, the scheme shown in the above embodiment uses a higher initial programming voltage for the memory cells in the outer memory chip and a lower initial programming voltage for the memory cells in the inner memory chip. This allows the memory cells in the outer memory chip to reach the target voltage through a single programming operation, just like the memory cells in the inner memory chip. As a result, the data in the memory cells in the outer memory chip can have similar stability to the data in the memory cells in the inner memory chip.

[0100] To more intuitively describe the effect that the solution shown in the above embodiments can achieve in a programming mode of single-programming and zero-verification, please refer to... Figure 10 The diagram illustrates the programming effects involved in the embodiments of this application.

[0101] like Figure 10 As shown in section (a), when a 15V initial programming voltage is used for all memory cells, the E1 performance of memory cells in the outer memory chip after the first programming operation is worse than that of memory cells in the inner memory chip after the first programming operation. This means that the data stability of memory cells in the outer memory chip is worse after the first programming operation.

[0102] like Figure 10 As shown in section (b), when a 15V initial programming voltage is used for the memory cells in the inner memory chip and a 15V + offset initial programming voltage is used for the memory cells in the outer memory chip, the E1 performance of the memory cells in the outer memory chip after the first programming operation is not significantly lower than that of the memory cells in the inner memory chip after the first programming operation. This means that the data stability of the memory cells in the outer memory chip is effectively improved after the first programming operation.

[0103] Based on the scheme shown in the above embodiments, in an optional embodiment, the diameter of the via of one or more memory strings located on the outermost side of the memory cell array in the outer memory chip is larger than the diameter of the via of other memory strings in the memory cell array.

[0104] For specific examples, please refer to the above. Figure 8Due to manufacturing process limitations, in a memory cell array, while the diameter of the vias corresponding to memory cells at the edges is typically equal to the designed diameter (with a sufficiently small error), the size of the vias corresponding to memory cells at the edges is significantly larger than the designed diameter, and the error between the two is substantial. In this case, the programming voltage required for programming a memory cell in one or more memory strings on the outermost edge of the array is usually greater than the programming voltage required for programming other memory cells.

[0105] Based on the solution shown in the above embodiments, in an optional embodiment, the peripheral circuit 901 is configured to: acquire memory chip type indication information, which is used to indicate whether the memory chip where the selected memory cell is located is the outer memory chip or the inner memory chip; and determine the starting programming voltage according to the memory chip type indication information.

[0106] In this embodiment of the application, before the peripheral circuit performs a programming operation on the selected memory cell, it can first obtain information that indicates the type of memory chip where the selected memory cell is located (i.e., the memory chip type indication information mentioned above), and then determine the starting programming voltage to perform the programming operation on the selected memory cell based on the obtained information.

[0107] The above embodiments of this application provide a feasible solution for indicating to the peripheral circuit 901, through memory chip type indication information, whether the memory chip containing the selected memory cell is an outer memory chip or an inner memory chip.

[0108] Based on the scheme shown in the above embodiments, in an optional embodiment, the storage chip type indication information includes one or more of the following: the number of the storage chip where the selected storage cell is located; the physical address of the selected storage cell; and an indication identifier in the write command, which is used to indicate that a programming operation is performed on the selected storage cell.

[0109] In one exemplary scheme, the aforementioned storage chip type indication information may be information that directly indicates whether the storage chip where the selected storage cell is located is an outer storage chip or an inner storage chip. For example, the storage chip type indication information may include a type identifier of the storage chip where the selected storage cell is located. Specifically, for example, when the type identifier is 1, it indicates that the storage chip where the selected storage cell is located is an outer storage chip, and when the type identifier is 0, it indicates that the storage chip where the selected storage cell is located is an inner storage chip. For another example, when the type identifier is 0, it indicates that the storage chip where the selected storage cell is located is an outer storage chip, and when the type identifier is 1, it indicates that the storage chip where the selected storage cell is located is an inner storage chip.

[0110] In another exemplary embodiment, the aforementioned storage chip type indication information may also be information that indirectly indicates whether the storage chip where the selected storage cell is located is an outer storage chip or an inner storage chip. For example, the storage chip type indication information may include the identifier (such as the number) of the storage chip where the selected storage cell is located, the physical address of the selected storage cell, and other information. Through this information, it can be indirectly indicated whether the storage chip where the selected storage cell is located is an outer storage chip or an inner storage chip.

[0111] The aforementioned peripheral circuit 901 obtaining the memory chip type indication information can refer to the peripheral circuit 901 querying or generating the memory chip type indication information internally based on the write command after receiving a write command to perform a programming operation on the selected memory cell.

[0112] For example, after receiving a write command to perform a programming operation on a selected memory cell, the peripheral circuit 901 can query or generate memory chip type indication information based on the physical address of the selected memory cell carried in the write command; for example, the peripheral circuit 901 queries or determines the number or type of the memory chip where the selected memory cell is located based on the physical address of the selected memory cell, and then determines the starting programming voltage based on the number or type of the memory chip where the selected memory cell is located.

[0113] Taking the example of the peripheral circuit 901 querying or determining the type of memory chip where the selected memory cell is located based on the physical address of the selected memory cell, this process can be implemented through the following steps S1-1 and S1-2:

[0114] In step S1-1, the peripheral circuit 901 can query the number of the memory chip where the selected memory cell is located locally based on the physical address of the selected memory cell. For example, the peripheral circuit 901 pre-stores the correspondence between the numbers of each memory chip and each physical address range. Based on this correspondence, the peripheral circuit 901 can query the physical address range where the physical address of the selected memory cell is located, and thus determine the number of the memory chip where the selected memory cell is located.

[0115] In step S1-2, when the number of the storage chip where the selected storage unit is located is a specified number, the peripheral circuit 901 determines that the type of the storage chip where the selected storage unit is located is an outer storage string; when the number of the storage chip where the selected storage unit is located is not the specified number, the peripheral circuit 901 determines that the type of the storage chip where the selected storage unit is located is an inner storage string. For example, the peripheral circuit 901 has a specified number corresponding to the outer storage chip pre-set. After obtaining the number of the storage chip where the selected storage unit is located, the peripheral circuit 901 can determine whether the number of the storage chip where the selected storage unit is located belongs to the specified number. If so, the storage chip where the selected storage unit is located is determined to be an outer storage chip; otherwise, the storage chip where the selected storage unit is located is determined to be an inner storage chip.

[0116] Taking the example of the peripheral circuit 901 querying or determining the type of memory chip where the selected memory cell is located based on the physical address of the selected memory cell, this process can also be implemented through the following steps S2-1:

[0117] In step S2-1, when the physical address of the selected memory cell belongs to the specified address, the peripheral circuit 901 determines that the type of the memory chip where the selected memory cell is located is an outer memory chip; when the physical address of the selected memory cell does not belong to the specified address, the peripheral circuit 901 determines that the type of the memory chip where the selected memory cell is located is an inner memory chip. For example, the peripheral circuit 901 pre-sets the physical address of the memory cell corresponding to the outer memory chip as the specified address. After obtaining the physical address of the selected memory cell, the peripheral circuit 901 can determine whether the physical address of the selected memory cell belongs to the specified address. If it does, the peripheral circuit 901 determines that the memory chip where the selected memory cell is located is an outer memory chip; otherwise, the peripheral circuit 901 determines that the peripheral circuit 901 is an inner memory chip.

[0118] The aforementioned peripheral circuit 901 acquiring memory chip type indication information can refer to the peripheral circuit 901 acquiring the aforementioned memory chip type indication information transmitted externally. For example, the peripheral circuit 901 can receive the aforementioned memory chip type indication information sent by the controller.

[0119] For example, the write command sent by the controller to the peripheral circuit 901 may include the aforementioned indication identifier. After receiving the write command to perform programming operations on the selected memory cell, the peripheral circuit 901 can extract the aforementioned memory chip type indication information (i.e., the aforementioned indication identifier) ​​from the write command. The indication identifier may indicate, include, or be implemented as the type identifier of the memory chip where the selected memory cell is located.

[0120] Based on the scheme shown in the above embodiments, in an optional embodiment, the method by which the peripheral circuit determines the initial programming voltage may include any of the following:

[0121] 1) The peripheral circuit 901 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, determine the first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, determine the second voltage corresponding to the outer memory chip as the starting programming voltage.

[0122] For example, the peripheral circuit 901 described above can be configured with two starting programming voltages, namely the first voltage and the second voltage. The first voltage corresponds to the inner memory chip, and the second voltage corresponds to the outer memory chip. When memory chip type indication information is obtained, and the memory chip type indication information indicates that the physical address of the selected memory cell belongs to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit 901 can determine that the starting programming voltage is the second voltage. Conversely, when the memory chip type indication information indicates that the physical address of the selected memory cell does not belong to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is not a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit 901 can determine that the starting programming voltage is the first voltage.

[0123] 2) The peripheral circuit 901 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, determine the first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, add a first offset voltage to the first voltage to obtain the starting programming voltage.

[0124] For example, the peripheral circuit 901 can be configured with an initial programming voltage (i.e., the first voltage) for the inner memory chip and an offset voltage (i.e., the first offset voltage). When memory chip type indication information is obtained, and the memory chip type indication information indicates that the physical address of the selected memory cell belongs to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit 901 can determine that the initial programming voltage is the first voltage + the first offset voltage. Conversely, when the memory chip type indication information indicates that the physical address of the selected memory cell does not belong to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is not a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit 901 can determine that the initial programming voltage is the first voltage.

[0125] 3) The peripheral circuit 901 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, determine the second voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, subtract the first offset voltage from the second voltage to obtain the starting programming voltage.

[0126] For example, the peripheral circuit 901 can be configured with an initial programming voltage (i.e., the second voltage) for the outer memory chip and an offset voltage (i.e., the first offset voltage). When memory chip type indication information is obtained, and the memory chip type indication information indicates that the physical address of the selected memory cell belongs to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit 901 can determine that the initial programming voltage is the second voltage. Conversely, when the memory chip type indication information indicates that the physical address of the selected memory cell does not belong to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is not a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit 901 can determine that the initial programming voltage is the second voltage minus the first offset voltage.

[0127] Based on the solutions shown in the above embodiments, please refer to Figure 11 This illustrates a programming diagram of a memory according to an embodiment of this application. Figure 11 As shown, the memory includes peripheral circuitry 901 and a memory cell array 902. The memory cell array 902 contains four memory chips, where memory chips 0 and 3 are outer memory chips, and memory chips 1 and 2 are inner memory chips. Peripheral circuitry 901 receives a write command 1 from the controller, which includes a write address of address 1. The memory cell corresponding to address 1 is located on memory chip 0. Peripheral circuitry 901 uses a starting programming voltage 1 to perform a programming operation on the selected memory cell (i.e., the memory cell corresponding to address 1). Peripheral circuitry 901 also receives a write command 2 from the controller, which includes a write address of address 2. The memory cell corresponding to address 2 is located on memory chip 2. Peripheral circuitry 901 uses a starting programming voltage 2 to perform a programming operation on the selected memory cell (i.e., the memory cell corresponding to address 2). The starting programming voltage 1 is greater than the starting programming voltage 2; for example, the starting programming voltage 1 is 17V and the starting programming voltage 2 is 15V.

[0128] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit can further determine the starting programming voltage as follows:

[0129] The peripheral circuit 901 is configured to determine the starting programming voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the starting programming voltage is inversely related to the memory chip spacing distance.

[0130] The memory chip spacing can be represented by the number of memory chips between the memory chip containing the selected memory cell and the closest outer memory chip in the memory cell array. For example, when the memory chip containing the selected memory cell is an outer memory chip, the memory chip spacing is 0; when the memory chip containing the selected memory cell is an adjacent memory chip to the outer memory chip, the memory chip spacing is 1, and so on.

[0131] Alternatively, the aforementioned chip spacing can be represented by the difference between the chip number of the selected memory cell and the chip number of the closest outermost memory cell in the memory cell array. For example, suppose the memory cell array contains 4 memory cells, numbered 0, 1, 2 and 3, where memory cells numbered 0 and 3 are outer memory cells and memory cells numbered 1 and 2 are inner memory cells. When the memory cell number of the selected memory cell is 0 or 3, the chip spacing is 0, and when the memory cell number of the selected memory cell is 1 or 2, the chip spacing is 1.

[0132] In this embodiment, the peripheral circuit 901 can be configured with an initial programming voltage for the memory chip, which decreases as the distance between the memory chip and the outer memory chip increases. Specifically, in the memory cell array, the memory chip closer to the edge of the memory cell array has a higher initial programming voltage, and conversely, the memory chip closer to the center of the memory cell array has a lower initial programming voltage. The initial programming voltage of the memory chip can decrease in a step-like manner or linearly as the distance between the memory chip and the outer memory chip increases.

[0133] For example, the peripheral circuit 901 can be configured with a correspondence or calculation formula between the memory chip spacing distance and the starting programming voltage. The peripheral circuit 901 can then query or substitute the above correspondence or calculation formula based on the memory chip spacing distance to obtain the starting programming voltage used for programming the selected memory cell.

[0134] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit 901 is further configured to determine the step voltage of the incremental step pulse programming (ISPP) used to perform programming operations on the selected memory cell; and to perform an ISPP operation on the selected memory cell according to the starting programming voltage and the step voltage; wherein the step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

[0135] In this embodiment, under the multiple programming and multiple verification programming mode, the peripheral circuit 901, for the memory cells in the outer memory chip, can not only use a higher initial programming voltage to perform programming operations, but also a higher step voltage. This further increases the programming voltage for the memory cells in the outer memory chip under the multiple programming and multiple verification programming mode, thereby further improving the programming efficiency of the memory cells in the outer memory chip. For example, the programming voltage corresponding to each programming operation under different initial programming voltages and step voltages is shown in Table 1.

[0136] Table 1

[0137]

[0138] In this embodiment, under the multiple programming and multiple verification programming mode, for memory cells in the inner memory chip, the peripheral circuit 901 can use the starting programming voltage and step voltage shown in Scheme 1 to perform programming operations. For memory cells in the outer memory chip, the peripheral circuit 901 can use the starting programming voltage and step voltage shown in Scheme 2 or Scheme 3 to perform programming operations. Specifically, for memory cells in the outer memory chip, when using the starting programming voltage and step voltage shown in Scheme 3 to perform programming operations, except for the programming voltage during the first programming, the programming voltage during each subsequent programming will be higher than the programming voltage shown in Scheme 2. This further improves the programming efficiency of memory cells in the outer memory chip compared to Scheme 2. For example, assuming that a selected memory cell in the outer memory chip requires a programming voltage of 17.6V, then using the starting programming voltage and step voltage shown in Scheme 2 requires 4 programming operations, while using the starting programming voltage and step voltage shown in Scheme 3 only requires 3 programming operations.

[0139] Based on the solution shown in the above embodiments, in an optional embodiment, the peripheral circuit 901 is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip where the selected memory cell is located is the outer memory chip or the inner memory chip; and determine the step voltage based on the memory chip type indication information.

[0140] In the embodiments of this application, in the programming mode of multiple programming and multiple verification, before the peripheral circuit performs programming operation on the selected memory cell, it can first obtain information that can indicate the type of memory chip where the selected memory cell is located (i.e., the above-mentioned memory chip type indication information), and then determine which step voltage to use to perform programming operation on the selected memory cell based on the obtained information.

[0141] Based on the scheme shown in the above embodiments, in an optional embodiment, the method by which the peripheral circuit determines the step voltage may include any of the following:

[0142] 1) The peripheral circuit 901 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, determine the third voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, determine the fourth voltage corresponding to the outer memory chip as the step voltage.

[0143] For example, the peripheral circuit 901 can be configured with two step voltages, namely the third voltage and the fourth voltage. The third voltage corresponds to the inner memory chip, and the fourth voltage corresponds to the outer memory chip. When memory chip type indication information is obtained, and the memory chip type indication information indicates that the physical address of the selected memory cell belongs to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit 901 can determine that the step voltage is the fourth voltage. Conversely, when the memory chip type indication information indicates that the physical address of the selected memory cell does not belong to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is not a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit 901 can determine that the step voltage is the third voltage.

[0144] 2) The peripheral circuit 901 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, determine the third voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, add a second offset voltage to the third voltage to obtain the step voltage.

[0145] For example, the peripheral circuit 901 can be configured with a step voltage (i.e., the third voltage) for the inner memory chip and an offset voltage (i.e., the second offset voltage). When memory chip type indication information is obtained, and the memory chip type indication information indicates that the physical address of the selected memory cell belongs to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit 901 can determine that the step voltage is the third voltage + the second offset voltage. Conversely, when the memory chip type indication information indicates that the physical address of the selected memory cell does not belong to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is not a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit 901 can determine that the step voltage is the third voltage.

[0146] 3) The peripheral circuit 901 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, determine the fourth voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, subtract the second offset voltage from the fourth voltage to obtain the step voltage.

[0147] For example, the peripheral circuit 901 can be configured with a step voltage (i.e., the fourth voltage) for the outer memory chip and an offset voltage (i.e., the second offset voltage). When memory chip type indication information is obtained, and the memory chip type indication information indicates that the physical address of the selected memory cell belongs to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit 901 can determine that the step voltage is the fourth voltage. Conversely, when the memory chip type indication information indicates that the physical address of the selected memory cell does not belong to a specified address, or indicates that the number of the memory chip where the selected memory cell is located is not a specified number, or indicates that the type of the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit 901 can determine that the step voltage is the fourth voltage minus the second offset voltage.

[0148] Based on the solutions shown in the above embodiments, please refer to Figure 12 This illustrates a programming diagram of another memory according to an embodiment of this application. Figure 12As shown, memory chips 0 and 3 are outer memory chips, and memory chips 1 and 2 are inner memory chips. The peripheral circuit 901 receives a write command 1 from the controller, which includes a write address of address 1. The memory cell corresponding to address 1 is located on memory chip 0. The peripheral circuit 901 uses a starting programming voltage 1 and a step voltage 1 to perform a programming operation on the selected memory cell (i.e., the memory cell corresponding to address 1). The peripheral circuit 901 also receives a write command 2 from the controller, which includes a write address of address 2. The memory cell corresponding to address 2 is located on memory chip 2. The peripheral circuit 901 uses a starting programming voltage 2 and a step voltage 2 to perform a programming operation on the selected memory cell (i.e., the memory cell corresponding to address 2). The starting programming voltage 1 is greater than the starting programming voltage 2, and the step voltage 1 is greater than the step voltage 2. For example, the starting programming voltage 1 is 17V, the starting programming voltage 2 is 15V, the step voltage 1 is 0.3V, and the step voltage 2 is 0.2V.

[0149] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit can further determine the step voltage as follows:

[0150] The peripheral circuit 901 is configured to determine the step voltage based on the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip containing the selected memory cell and the outer memory chip; wherein the step voltage is inversely related to the memory chip spacing distance.

[0151] In this embodiment, the peripheral circuit 901 can be configured with a step voltage for the memory chip, which decreases as the distance between the memory chip and the outer memory chip increases. Specifically, in the memory cell array, the closer the memory chip is to the edge of the memory cell array, the higher its step voltage; conversely, the closer the memory chip is to the center of the memory cell array, the lower its step voltage. The step voltage of the memory chip can decrease in a step-like manner or linearly as the distance between the memory chip and the outer memory chip increases.

[0152] For example, the peripheral circuit 901 can set a correspondence or calculation formula between the memory chip spacing distance and the step voltage. The peripheral circuit 901 can obtain the step voltage used for programming the selected memory cell by querying or substituting the above correspondence or calculation formula according to the memory chip spacing distance.

[0153] based on Figure 9In another possible implementation of the memory shown, in a programming mode of multiple programming and multiple verification, the peripheral circuit 901 can be configured to: determine the step voltage used to perform a programming operation on a selected memory cell, the step voltage corresponding to the memory chip on which the selected memory cell is located, the step voltage corresponding to the outer memory chip being greater than the step voltage corresponding to the inner memory chip, and the outer memory chip having the same starting programming voltage as the main memory chip; and perform a programming operation on the selected memory cell according to the starting programming voltage and the step voltage.

[0154] In the embodiments of this application, in the programming mode of multiple programming and multiple verification, the starting programming voltage can be ignored for the outer memory chip and the inner memory chip, and only the step voltage can be distinguished.

[0155] For example, under the same initial programming voltage and different step voltages, the programming voltage corresponding to each programming operation is shown in Table 2.

[0156] Table 2

[0157]

[0158] In this embodiment, under the multiple programming and multiple verification programming mode, for memory cells in the inner memory chip, the peripheral circuit 901 can use the starting programming voltage and step voltage shown in Scheme 1 to perform programming operations, while for memory cells in the outer memory chip, the peripheral circuit 901 can use the starting programming voltage and step voltage shown in Scheme 4 to perform programming operations. Specifically, for memory cells in the outer memory chip, because a higher step voltage is used to perform programming operations, except for the programming voltage during the first programming, the programming voltage during each subsequent programming operation will be higher than the programming voltage when using the starting programming voltage and step voltage shown in Scheme 1, thereby also improving the programming efficiency of memory cells in the outer memory chip. For example, assuming that a selected memory cell in the outer memory chip requires a programming voltage of 15.6V, if the starting programming voltage and step voltage shown in Scheme 1 are used to perform programming operations, four programming operations are required, while if the starting programming voltage and step voltage shown in Scheme 4 are used, only three programming operations are required.

[0159] Based on the solutions shown in the above embodiments, please refer to Figure 13 This illustrates a programming diagram of yet another type of memory according to an embodiment of this application. For example... Figure 13As shown, memory chips 0 and 3 are outer memory chips, and memory chips 1 and 2 are inner memory chips. The peripheral circuit 901 receives a write command 1 from the controller, which includes a write address of address 1. The memory cell corresponding to address 1 is located on memory chip 0. The peripheral circuit 901 uses a starting programming voltage 1 and a step voltage 1 to perform a programming operation on the selected memory cell (i.e., the memory cell corresponding to address 1). The peripheral circuit 901 also receives a write command 2 from the controller, which includes a write address of address 2. The memory cell corresponding to address 2 is located on memory chip 2. The peripheral circuit 901 uses a starting programming voltage 1 and a step voltage 2 to perform a programming operation on the selected memory cell (i.e., the memory cell corresponding to address 2). The starting programming voltage 1 and starting programming voltage 2 are the same, and the step voltage 1 is greater than the step voltage 2. For example, the starting programming voltage 1 and starting programming voltage 2 are both 15V, the step voltage 1 is 0.3V, and the step voltage 2 is 0.2V.

[0160] Figure 14 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 14 As shown, the storage system 1400 includes: one or more memories 1410, and,

[0161] A controller 1420 is coupled to the memory 1410 and configured to control the memory 1410.

[0162] The storage system 1400 may be all or part of a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0163] Optionally, the storage system 1400 may include a host and a storage subsystem, the storage subsystem having one or more memories 1410 and a controller 1420. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 1410. Alternatively, the host may be configured to receive data from the memory 1410.

[0164] According to some implementations, controller 1420 is also coupled to a host. Controller 1420 can manage data stored in memory 1410 and communicate with the host.

[0165] In some implementations, the controller 1420 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0166] In some implementations, the controller 1420 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0167] Controller 1420 can be configured to control operations of memory 1410, such as read, erase, and program operations. Controller 1420 can also be configured to manage various functions relating to data stored or to be stored in memory 1410, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 1420 is also configured to process error correction codes (ECC) relating to data read from or written to memory 1410.

[0168] Controller 1420 can also perform any other suitable functions, such as formatting memory 1410. Controller 1420 can communicate with external devices according to a specific communication protocol.

[0169] The controller 1420 and one or more memories 1410 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1400 can be implemented and packaged into different types of end electronic products.

[0170] Schematic illustration: Controller 1420 and a single memory 1410 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0171] Schematic, the controller 1420 and multiple memories 1410 may be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0172] The aforementioned memory 1410 can be implemented as Figures 1 to 3 The memory 100 in any of the illustrated embodiments; the controller 1420 described above can be implemented as Figures 1 to 3 Controller 200 in any of the illustrated embodiments.

[0173] In the embodiments of this application, the memory cell array in the memory includes outer memory chips and inner memory chips. The outer memory chip is the outermost memory chip in the memory cell array; the inner memory chip is the other memory chip in the memory cell array besides the outer memory chip.

[0174] The controller 1420 is configured to send write commands to the memory.

[0175] The memory 1410 is configured to receive write commands; determine the starting programming voltage to be used to perform a programming operation on the selected memory cell according to the write command, the starting programming voltage corresponding to the memory chip where the selected memory cell is located, and the starting programming voltage corresponding to the outer memory chip is greater than the starting programming voltage corresponding to the inner memory chip; and perform a programming operation on the selected memory cell according to the starting programming voltage.

[0176] Based on the scheme shown in the above embodiments, in an optional embodiment, in the outer storage chip, the diameter of the via of one or more storage strings located on the outermost side of the storage cell array is larger than the diameter of the via of other storage strings in the storage cell array.

[0177] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip where the selected memory cell is located is an outer memory chip or an inner memory chip; and determine the starting programming voltage based on the memory chip type indication information.

[0178] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, determine a first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an outer memory chip, determine a second voltage corresponding to the outer memory chip as the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, determine a first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the selected memory cell is located is an outer memory chip, add a first offset voltage to the first voltage to obtain the starting programming voltage; or, when the memory chip type indication information indicates that the selected memory cell is located is an outer memory chip, determine a second voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the selected memory cell is located is an inner memory chip, subtract the first offset voltage from the second voltage to obtain the starting programming voltage.

[0179] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is configured to: determine the starting programming voltage according to the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip where the selected memory cell is located and the outer memory chip; wherein, the starting programming voltage is inversely related to the memory chip spacing distance.

[0180] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is further configured to determine the step voltage of the incremental step pulse programming (ISPP) used to perform a programming operation on the selected memory cell; and to perform an ISPP operation on the selected memory cell according to the starting programming voltage and the step voltage; wherein the step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

[0181] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is configured to: acquire memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip where the selected memory cell is located is an outer memory chip or an inner memory chip; and determine the step voltage according to the memory chip type indication information.

[0182] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is configured to: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, determine the third voltage corresponding to the inner memory chip as a step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an outer memory chip, determine the fourth voltage corresponding to the outer memory chip as a step voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, determine the third voltage corresponding to the inner memory chip as a step voltage; when the memory chip type indication information indicates that the selected memory cell is located is an outer memory chip, add a second offset voltage to the third voltage to obtain the step voltage; or, when the memory chip type indication information indicates that the selected memory cell is located is an outer memory chip, determine the fourth voltage corresponding to the inner memory chip as a step voltage; when the memory chip type indication information indicates that the selected memory cell is located is an inner memory chip, subtract the second offset voltage from the fourth voltage to obtain the step voltage.

[0183] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410 is configured to: determine the step voltage according to the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip where the selected memory cell is located and the outer memory chip; wherein, the step voltage is inversely correlated with the memory chip spacing distance.

[0184] Based on the scheme shown in the above embodiments, in an optional embodiment, the memory 1410, the memory chip type indication information includes one or more of the following: the number of the memory chip where the selected memory cell is located; the physical address of the selected memory cell; and the indication identifier in the write command, which is used to instruct the selected memory cell to perform a programming operation.

[0185] Please refer to Figure 15 This is a flowchart illustrating a programming method for a memory provided in an exemplary embodiment of this application. The memory includes a memory cell array and peripheral circuitry. The memory cell array includes outer memory chips and inner memory chips. The outer memory chips are the outermost memory chips in the memory cell array; the inner memory chips are the other memory chips in the memory cell array besides the outer memory chips. Figure 15 As shown, the method may include the following steps.

[0186] Step 1510: The peripheral circuit determines the starting programming voltage used to perform programming operations on the selected memory cell. The starting programming voltage corresponds to the memory chip where the selected memory cell is located. The starting programming voltage corresponding to the outer memory chip is greater than the starting programming voltage corresponding to the inner memory chip.

[0187] Step 1520: The peripheral circuit performs a programming operation on the selected memory cell according to the initial programming voltage.

[0188] Based on the scheme shown in the above embodiments, in an optional embodiment, in the outer storage chip, the diameter of the via of one or more storage strings located on the outermost side of the storage cell array is larger than the diameter of the via of other storage strings in the storage cell array.

[0189] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit determines the starting programming voltage used to perform programming operations on the selected memory cell, including: the peripheral circuit obtains memory chip type indication information, which is used to indicate whether the memory chip where the selected memory cell is located is an outer memory chip or an inner memory chip; the peripheral circuit determines the starting programming voltage according to the memory chip type indication information.

[0190] Based on the solutions shown in the above embodiments, in an optional embodiment, the peripheral circuit determines the starting programming voltage according to the memory chip type indication information, including: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit determines the first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an outer memory chip, the peripheral circuit determines the second voltage corresponding to the outer memory chip as the starting programming voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, the peripheral circuit determines the second voltage corresponding to the outer memory chip as the starting programming voltage. The first voltage corresponding to the inner memory chip is determined as the starting programming voltage. When the memory chip type indication information indicates that the selected memory cell is located on an outer memory chip, the peripheral circuit adds a first offset voltage to the first voltage to obtain the starting programming voltage. Alternatively, when the memory chip type indication information indicates that the selected memory cell is located on an outer memory chip, the peripheral circuit determines the second voltage corresponding to the inner memory chip as the starting programming voltage. When the memory chip type indication information indicates that the selected memory cell is located on an inner memory chip, the peripheral circuit subtracts the first offset voltage from the second voltage to obtain the starting programming voltage.

[0191] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit determines the starting programming voltage used to perform programming operations on the selected memory cell, including: the peripheral circuit determines the starting programming voltage according to the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip where the selected memory cell is located and the outer memory chip; wherein, the starting programming voltage is inversely correlated with the memory chip spacing distance.

[0192] Based on the scheme shown in the above embodiments, in an optional embodiment, the above method further includes: the peripheral circuit determining the step voltage of the incremental step pulse programming (ISPP) used to perform programming operations on the selected memory cell; the peripheral circuit performing programming operations on the selected memory cell according to the starting programming voltage, including: the peripheral circuit performing an ISPP operation on the selected memory cell according to the starting programming voltage and the step voltage; wherein, the step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

[0193] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit determines the step voltage of the incremental step pulse programming (ISPP) used to perform programming operations on the selected memory cell, including: the peripheral circuit acquiring memory chip type indication information, which is used to indicate whether the memory chip where the selected memory cell is located is an outer memory chip or an inner memory chip; the peripheral circuit determining the step voltage according to the memory chip type indication information.

[0194] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit determines the step voltage according to the memory chip type indication information, including: when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, determining the third voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an outer memory chip, determining the fourth voltage corresponding to the outer memory chip as the step voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an inner memory chip, determining the third voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an outer memory chip, adding a second offset voltage to the third voltage to obtain the step voltage; or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is an outer memory chip, determining the fourth voltage corresponding to the inner memory chip as the step voltage; when the memory chip type indication information indicates that the selected memory cell is located is an inner memory chip, subtracting the second offset voltage from the fourth voltage to obtain the step voltage.

[0195] Based on the scheme shown in the above embodiments, in an optional embodiment, the peripheral circuit determines the step voltage of the incremental step pulse programming (ISPP) used to perform programming operations on the selected memory cell, including: the peripheral circuit determines the step voltage according to the memory chip spacing distance; the memory chip spacing distance is the distance between the memory chip where the selected memory cell is located and the outer memory chip; wherein, the step voltage is inversely correlated with the memory chip spacing distance.

[0196] Based on the scheme shown in the above embodiments, in an optional embodiment, the storage chip type indication information includes one or more of the following: the number of the storage chip where the selected storage cell is located; the physical address of the selected storage cell; and the indication identifier in the write command, which is used to instruct the selected storage cell to perform a programming operation.

[0197] This application provides a computer-readable storage medium storing instructions that, when executed on the peripheral circuitry of a memory in a storage system, implement, as follows: Figure 15 The illustrated embodiment provides a method for programming a memory. Optionally, the memory may be as follows: Figure 9 The controller shown, the storage system can be as follows: Figure 14 The storage system shown.

[0198] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0199] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0200] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A memory, comprising: The memory comprises: a memory cell array comprising an outer storage sheet and an inner storage sheet, the outer storage sheet being a storage sheet at an outermost side in the memory cell array, the inner storage sheet being a storage sheet other than the outer storage sheet in the memory cell array, and a peripheral circuit; The peripheral circuit is configured to: determine a starting programming voltage used for performing a programming operation on a selected memory cell, the starting programming voltage corresponding to a storage sheet where the selected memory cell is located, the starting programming voltage corresponding to the outer storage sheet being greater than the starting programming voltage corresponding to the inner storage sheet; perform a programming operation on the selected memory cell according to the starting programming voltage.

2. The memory of claim 1, wherein, In the outer storage sheet, a diameter of a channel via of one or more memory strings at the outermost side of the memory cell array is greater than a diameter of a channel via of other memory strings in the memory cell array.

3. The memory of claim 1, wherein, The peripheral circuit is configured to: obtain storage sheet type indication information, the storage sheet type indication information being used to indicate whether the storage sheet where the selected memory cell is located is the outer storage sheet or the inner storage sheet; determine the starting programming voltage according to the storage sheet type indication information.

4. The memory of claim 3, wherein, The peripheral circuit is configured to: when the storage sheet type indication information indicates that the storage sheet where the selected memory cell is located is the inner storage sheet, determine a first voltage set corresponding to the inner storage sheet as the starting programming voltage; when the storage sheet type indication information indicates that the storage sheet where the selected memory cell is located is the outer storage sheet, determine a second voltage set corresponding to the outer storage sheet as the starting programming voltage; or when the storage sheet type indication information indicates that the storage sheet where the selected memory cell is located is the inner storage sheet, determine a first voltage set corresponding to the inner storage sheet as the starting programming voltage; when the storage sheet type indication information indicates that the storage sheet where the selected memory cell is located is the outer storage sheet, add a first offset voltage to the first voltage to obtain the starting programming voltage; or, when the storage sheet type indication information indicates that the storage sheet where the selected memory cell is located is the outer storage sheet, determine a second voltage set corresponding to the inner storage sheet as the starting programming voltage; when the storage sheet type indication information indicates that the storage sheet where the selected memory cell is located is the inner storage sheet, subtract a first offset voltage from the second voltage to obtain the starting programming voltage.

5. The memory of claim 1, wherein, The peripheral circuit is configured to: determine the starting programming voltage according to a storage sheet spacing distance; the storage sheet spacing distance being a distance between the storage sheet where the selected memory cell is located and the outer storage sheet; wherein the starting programming voltage is inversely related to the storage sheet spacing distance.

6. The memory of claim 1, wherein The peripheral circuit is further configured to determine a step voltage of an incremental step pulse programming (ISPP) used for performing a programming operation on the selected memory cell; The peripheral circuit is configured to perform an ISPP operation on the selected memory cell according to the initial programming voltage and the step voltage. The step voltage corresponding to the outer storage tile is greater than the step voltage corresponding to the inner storage tile.

7. The memory of claim 6, wherein, The peripheral circuit is configured to: obtain storage tile type indication information, the storage tile type indication information being used to indicate whether a storage tile where the selected memory cell is located is the outer storage tile or the inner storage tile; determine the step voltage according to the storage tile type indication information.

8. The memory of claim 7, wherein, The peripheral circuit is configured to: when the storage tile type indication information indicates that the storage tile where the selected memory cell is located is the inner storage tile, determine a third voltage corresponding to the inner storage tile as the step voltage; when the storage tile type indication information indicates that the storage tile where the selected memory cell is located is the outer storage tile, determine a fourth voltage corresponding to the outer storage tile as the step voltage; or when the storage tile type indication information indicates that the storage tile where the selected memory cell is located is the inner storage tile, determine a third voltage corresponding to the inner storage tile as the step voltage; when the storage tile type indication information indicates that the storage tile where the selected memory cell is located is the outer storage tile, add a second offset voltage to the third voltage to obtain the step voltage; or when the storage tile type indication information indicates that the storage tile where the selected memory cell is located is the outer storage tile, determine a fourth voltage corresponding to the inner storage tile as the step voltage; when the storage tile type indication information indicates that the storage tile where the selected memory cell is located is the inner storage tile, subtract a second offset voltage from the fourth voltage to obtain the step voltage.

9. The memory of claim 6, wherein, The peripheral circuit is configured to: determine the step voltage according to a storage tile interval distance; the storage tile interval distance is a distance between the storage tile where the selected memory cell is located and the outer storage tile; The step voltage is inversely related to the storage tile interval distance.

10. The memory of claim 3 or 7, wherein, The storage tile type indication information includes one or more of the following information: a number of the storage tile where the selected memory cell is located; obtain a physical address of the selected memory cell; an indication in a write command, the write command being used to indicate that a programming operation is performed on the selected memory cell.

11. A storage system, characterized by The storage system includes a memory and a controller; an array of memory cells in the memory includes an outer storage tile and an inner storage tile, the outer storage tile being an outermost storage tile in the array of memory cells; the inner storage tile being other storage tiles in the array of memory cells except the outer storage tile; the controller is configured to send a write command to the memory; the memory is configured to receive the write command; The memory is configured to determine, according to the write command, a starting programming voltage used for performing a programming operation on the selected memory cell, the starting programming voltage corresponding to a storage slice where the selected memory cell is located, the starting programming voltage corresponding to the outer storage slice being greater than the starting programming voltage corresponding to the inner storage slice; and perform a programming operation on the selected memory cell according to the starting programming voltage.

12. The storage system of claim 11, wherein, In the outer storage slice, a diameter of a channel via of one or more memory strings located at the outermost side of the memory cell array is greater than a diameter of a channel via of other memory strings in the memory cell array.

13. The storage system of claim 11, wherein, The memory is configured to: obtain storage slice type indication information, the storage slice type indication information being used to indicate whether the storage slice where the selected memory cell is located is the outer storage slice or the inner storage slice; determine the starting programming voltage according to the storage slice type indication information.

14. The storage system of claim 13, wherein, The memory is configured to: when the storage slice type indication information indicates that the storage slice where the selected memory cell is located is the inner storage slice, determine a first voltage corresponding to the inner storage slice as the starting programming voltage; when the storage slice type indication information indicates that the storage slice where the selected memory cell is located is the outer storage slice, determine a second voltage corresponding to the outer storage slice as the starting programming voltage; or, when the storage slice type indication information indicates that the storage slice where the selected memory cell is located is the inner storage slice, determine a first voltage corresponding to the inner storage slice as the starting programming voltage; when the storage slice type indication information indicates that the storage slice where the selected memory cell is located is the outer storage slice, add a first offset voltage to the first voltage to obtain the starting programming voltage; or, when the storage slice type indication information indicates that the storage slice where the selected memory cell is located is the outer storage slice, determine a second voltage corresponding to the inner storage slice as the starting programming voltage; when the storage slice type indication information indicates that the storage slice where the selected memory cell is located is the inner storage slice, subtract a first offset voltage from the second voltage to obtain the starting programming voltage.

15. The storage system of claim 11, wherein, The memory is configured to: determine the starting programming voltage according to a storage slice spacing distance; the storage slice spacing distance being a distance between the storage slice where the selected memory cell is located and the outer storage slice; wherein the starting programming voltage is inversely related to the storage slice spacing distance.

16. The storage system of claim 11, wherein: the memory is further configured to determine a step voltage of an incremental step pulse programming (ISPP) used for performing a programming operation on the selected memory cell; the memory is configured to perform an ISPP operation on the selected memory cell according to the starting programming voltage and the step voltage; wherein the step voltage corresponding to the outer storage slice is greater than the step voltage corresponding to the inner storage slice.

17. The storage system of claim 16, wherein, the memory is configured to: acquire storage chip type indication information, the storage chip type indication information being used to indicate whether a storage chip where the selected storage unit is located is the outer storage chip or the inner storage chip; determine the step voltage according to the storage chip type indication information.

18. The storage system of claim 17, wherein, The memory is configured to: when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the inner storage chip, determine a third voltage set corresponding to the inner storage chip as the step voltage; when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the outer storage chip, determine a fourth voltage set corresponding to the outer storage chip as the step voltage; or, when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the inner storage chip, determine a third voltage set corresponding to the inner storage chip as the step voltage; when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the outer storage chip, add a second offset voltage to the third voltage to obtain the step voltage; or, when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the outer storage chip, determine a fourth voltage set corresponding to the inner storage chip as the step voltage; when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the inner storage chip, subtract a second offset voltage from the fourth voltage to obtain the step voltage.

19. The storage system of claim 16, wherein, The memory is configured to: determine the step voltage according to a storage chip interval distance; the storage chip interval distance is a distance between the storage chip where the selected storage unit is located and the outer storage chip; wherein the step voltage is inversely related to the storage chip interval distance.

20. The storage system of claim 13 or 17, wherein, The storage chip type indication information includes one or more of the following information: a number of the storage chip where the selected storage unit is located; acquire a physical address of the selected storage unit; an indication in a write command, the write command being used to indicate that a programming operation is performed on the selected storage unit.

21. A method of programming a memory, comprising: The memory includes a storage unit array and a peripheral circuit, the storage unit array includes an outer storage chip and an inner storage chip, the outer storage chip is the outermost storage chip in the storage unit array; the inner storage chip is other storage chip in the storage unit array except the outer storage chip; The method includes: The peripheral circuit determines a starting programming voltage used for performing a programming operation on a selected storage unit, the starting programming voltage corresponding to a storage chip where the selected storage unit is located, the starting programming voltage corresponding to the outer storage chip is greater than the starting programming voltage corresponding to the inner storage chip; The peripheral circuit performs a programming operation on the selected storage unit according to the starting programming voltage.

22. The method of claim 21, wherein, In the outer storage chip, the diameter of the channel via of one or more storage strings located at the outermost side of the storage unit array is greater than the diameter of the channel via of other storage strings in the storage unit array.

23. The method of claim 21, wherein, The peripheral circuit determines a starting programming voltage used for performing a programming operation on the selected memory cell, including: The peripheral circuit acquires memory chip type indication information, the memory chip type indication information being used to indicate whether the memory chip where the selected memory cell is located is the outer memory chip or the inner memory chip; The peripheral circuit determines the starting programming voltage according to the memory chip type indication information.

24. The method of claim 23, wherein, The peripheral circuit determines the starting programming voltage according to the memory chip type indication information, including: When the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the peripheral circuit determines a first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the peripheral circuit determines a second voltage corresponding to the outer memory chip as the starting programming voltage; or, When the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the peripheral circuit determines a first voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the peripheral circuit adds a first offset voltage to the first voltage to obtain the starting programming voltage; Or, when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the outer memory chip, the peripheral circuit determines a second voltage corresponding to the inner memory chip as the starting programming voltage; when the memory chip type indication information indicates that the memory chip where the selected memory cell is located is the inner memory chip, the peripheral circuit subtracts a first offset voltage from the second voltage to obtain the starting programming voltage.

25. The method of claim 21, wherein, The peripheral circuit determines a starting programming voltage used for performing a programming operation on the selected memory cell, including: The peripheral circuit determines the starting programming voltage according to a memory chip spacing distance; the memory chip spacing distance is a distance between the memory chip where the selected memory cell is located and the outer memory chip; The starting programming voltage is inversely related to the memory chip spacing distance.

26. The method of claim 21, wherein, The method further includes: The peripheral circuit determines a step voltage of an incremental step pulse programming (ISPP) used for performing a programming operation on the selected memory cell; The peripheral circuit performs a programming operation on the selected memory cell according to the starting programming voltage, including: The peripheral circuit performs an ISPP operation on the selected memory cell according to the starting programming voltage and the step voltage; The step voltage corresponding to the outer memory chip is greater than the step voltage corresponding to the inner memory chip.

27. The method of claim 26, wherein, The peripheral circuit determines a step voltage of an incremental step pulse programming (ISPP) used for performing a programming operation on the selected memory cell, including: The peripheral circuit acquires storage chip type indication information, which is used to indicate whether the storage chip where the selected storage unit is located is the outer storage chip or the inner storage chip. The peripheral circuit determines the step voltage according to the storage chip type indication information.

28. The method of claim 27, wherein, The peripheral circuit determines the step voltage according to the storage chip type indication information, including: when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the inner storage chip, a third voltage corresponding to the inner storage chip is determined as the step voltage; when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the outer storage chip, a fourth voltage corresponding to the outer storage chip is determined as the step voltage; or, when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the inner storage chip, a third voltage corresponding to the inner storage chip is determined as the step voltage; when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the outer storage chip, a second offset voltage is added to the third voltage to obtain the step voltage; or, when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the outer storage chip, a fourth voltage corresponding to the inner storage chip is determined as the step voltage; when the storage chip type indication information indicates that the storage chip where the selected storage unit is located is the inner storage chip, a second offset voltage is subtracted from the fourth voltage to obtain the step voltage.

29. The method of claim 26, wherein, The peripheral circuit determines the step voltage of an incremental step pulse programming (ISPP) used for performing a programming operation on the selected storage unit, including: The peripheral circuit determines the step voltage according to a storage chip interval distance; the storage chip interval distance is a distance between the storage chip where the selected storage unit is located and the outer storage chip. The step voltage is inversely related to the storage chip interval distance.

30. The method of claim 23 or 27, wherein, The storage chip type indication information includes one or more of the following information: a number of the storage chip where the selected storage unit is located; acquiring a physical address of the selected storage unit; an indication in a write command, which is used to indicate that a programming operation is performed on the selected storage unit.

31. A computer-readable storage medium, comprising: The computer readable storage medium stores instructions, which, when running on a memory in a storage system, implement the programming method of the memory as claimed in any one of claims 21 to 30.

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