Quad flat no-lead (QFN) packaging structure of full flip chip and preparation method of QFN packaging structure

Abstract

The invention discloses a full flip chip QFN packaging structure and a preparation method thereof. The packaging structure comprises a first metal frame, a second metal frame, a first chip, a second chip and a plastic packaging part. The first back surface of the first metal frame is downwards stacked on the second front surface of the second metal frame to form a metal frame assembly, the first chip is inversely arranged on the back surface of the metal frame assembly, and the second chip is inversely arranged on the front surface of the metal frame assembly; the plastic package part carries out integral plastic package on the first chip, the second chip and the metal frame assembly, and the top end surface of the second metal conductive column is exposed. By adopting the double-layer frame structure design, the stacked arrangement of a plurality of flip chips is realized, the limitation in the prior art that the chips can only be flipped on the front surface of one frame is overcome, the complexity of the whole product structure is remarkably improved, and the development requirements of miniaturization and portability of electronic products are met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a QFN package structure for a fully flip-chip and its fabrication method. Background Technology

[0002] In recent years, with the rapid development of electronic technology, integrated circuit packaging has been developing towards miniaturization and multi-functionality. Stacked packaging has become an important technical means to meet the requirements of smaller, lighter, and more functional products.

[0003] The Quad Flat No-lead Package (QFN) has been widely used due to its advantages such as short conductive paths between internal pins and pads, low self-inductance, and low internal line resistance. However, existing QFN packaging methods are mainly designed for single-type chips. It is difficult to simultaneously implement FC (Flip Chip) and WB (WireBond) packages in frame-type products. Furthermore, the pin spacing between frame-structured packages is usually large, which cannot generate more pin outputs or realize more functional chip packages.

[0004] Furthermore, existing QFN packaged products all involve mounting chips on the front side of a single frame; these can be flip-chip, standard-mount, or multiple standard-mount chips arranged side-by-side or stacked. However, it is currently not possible to stack multiple flip-chip chips within a QFN package, which results in a relatively simple overall product structure for QFN packages.

[0005] Therefore, in order to meet the growing demand for miniaturization and portability of electronic products, a new packaging technology is urgently needed to realize the layout of multiple flip chips integrated in QFN packaged products, increase the complexity of the overall product structure, and thus achieve greater functional integration and better performance.

[0006] Therefore, finding a new packaging solution that can overcome these defects has become an important direction for current technological development. Summary of the Invention

[0007] To address the aforementioned issues, this invention provides a QFN package structure for a fully flip-chip chip that can increase the complexity of the overall product structure, achieve greater functional integration and superior performance, as well as a method for its fabrication.

[0008] In a first aspect, the present invention discloses a method for fabricating a QFN package structure for a fully flip-chip, the method comprising the following steps: S1. A first metal frame is provided, the first metal frame having a first front side, a first back side and a first through hole, the first front side having a plurality of first flip pads for mounting a first flip chip, the plurality of first flip pads surrounding the first through hole, and the first back side having a plurality of first metal conductive pillars. S2. A second metal frame is provided, the second metal frame having a second front side and a second back side, the second front side having a second flip-chip pad and a plurality of conductive pillar pads; the second back side having a third flip-chip pad and a second metal conductive pillar. S3. Stack the first back side of the first metal frame face down on the second front side of the second metal frame; make the position of the second flip pad correspond to the first through hole, and weld the first metal conductive post to the conductive post pad to form a metal frame assembly. The back side of the metal frame assembly is the first front side of the first metal frame, and the front side of the metal frame assembly is the second back side of the second metal frame. S4. A first chip is provided, which is flip-chip mounted on the back of the metal frame assembly. Some of the conductive bumps of the first chip are electrically connected to the first flip-chip pad, and the other conductive bumps are electrically connected to the second flip-chip pad. S5. Provide a second chip, which is flip-chip mounted on the front side of the metal frame assembly, and the conductive bumps of the second chip are electrically connected to the third flip-chip pad. S6. The first chip, the second chip, and the metal frame assembly are encapsulated together to expose the top surface of the second metal conductive pillar, forming a QFN package structure.

[0009] Secondly, the present invention also discloses a QFN package structure for a fully flip-chip prepared by the above preparation method, which includes a first metal frame, a second metal frame, a first chip, a second chip, and a molding compound. The first metal frame has a first front side, a first back side, and a first through hole. The first front side is provided with a plurality of first flip-chip pads for mounting first flip chips. The plurality of first flip-chip pads are arranged around the first through hole. The first back side is provided with a plurality of first metal conductive pillars. The second metal frame has a second front side and a second back side. The second front side is provided with a second flip-chip pad and a plurality of conductive pillar pads. The second back side is provided with a third flip-chip pad and a second metal conductive pillar. The first back side of the first metal frame is stacked face down on the second front side of the second metal frame; the position of the second flip pad corresponds to the first through hole, and the first metal conductive pillar is welded to the conductive pillar pad to form a metal frame assembly. The back side of the metal frame assembly is the first front side of the first metal frame, and the front side of the metal frame assembly is the second back side of the second metal frame. The first chip is flip-chip mounted on the back of the metal frame assembly. Some of the conductive bumps of the first chip are electrically connected to the first flip-chip pad, and the other conductive bumps are electrically connected to the second flip-chip pad. The second chip is flip-chip mounted on the front side of the metal frame assembly, and the conductive bumps of the second chip are electrically connected to the third flip-chip pad. The encapsulation unit encapsulates the first chip, the second chip, and the metal frame assembly as a whole, with the top surface of the second metal conductive pillar exposed.

[0010] Compared with the prior art, the beneficial effects of the present invention are: This invention provides a new technical solution for a QFN package structure of a fully flip-chip to achieve higher packaging density and improve electrical performance transmission.

[0011] This invention, by adopting a double-layer frame structure design, enables the stacking of multiple flip chips, overcoming the limitation of existing technologies that can only flip chips on the front of a frame. This significantly improves the overall product structure complexity and meets the development needs of miniaturization and portability of electronic products.

[0012] This invention simplifies the chip-frame connection process by setting metal guide pillars and guide pillar pads on the front and back frames respectively, and adopting flip-chip bonding technology, thereby improving the interconnection quality and reliability between chips and solving the problem that the existing flip-chip and conventional chip packaging processes need further optimization.

[0013] This invention provides a variety of flip-chip layouts by setting metal bumps of different heights on the front and back sides of the metal frame assembly and using a flip-chip bonding process. This overcomes the shortcomings of existing lead frame designs that cannot adequately meet the requirements of high-density, multi-I / O packaging.

[0014] This invention achieves a flexible heat dissipation design for the chip by setting a second metal conductive pillar as an external communication port on the front side of the metal frame assembly, combined with an optional chip back-side exposed process, thus meeting the heat dissipation performance requirements of different products. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the QFN package structure of the fully flip-chip in this invention; Figure 2 This is a schematic diagram of the structure of the first metal frame in this invention; Figure 3 This is a schematic diagram of the structure of the second metal frame in this invention; Figure 4 This is a schematic diagram of the metal frame assembly in this invention; Figure 5This is a schematic diagram of the structure of the metal frame assembly with the first chip and the second chip flipped in this invention.

[0016] Labeling: First metal frame 1; First front side 101; First back side 102; First through hole 103; First flip pad 104; First metal conductive pillar 105; Second metal frame 2; Second front side 201; Second back side 202; Second flip pad 203; Conductive pillar pad 204; Third flip pad 205; Second metal conductive pillar 206; Second through hole 207; First chip 3; Low conductive bump 301; High conductive bump 302; Second chip 4; Conductive bump 401; Molded package 5; Metal frame assembly 6. Detailed Implementation

[0017] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0018] like Figure 1 As shown, the present invention discloses a QFN package structure for a fully flip-chip, which includes a first metal frame 1, a second metal frame 2, a first chip 3, a second chip 4, and a molding compound 5.

[0019] The first metal frame 1 has a first front side 101, a first back side 102 and a first through hole 103. The first front side 101 is provided with a plurality of first flip-chip pads 104 for mounting the first chip 3. The plurality of first flip-chip pads 104 are arranged around the first through hole 103. The first back side 102 is provided with a plurality of first metal conductive pillars 105.

[0020] The second metal frame 2 has a second front side 201 and a second back side 202. The second front side 201 is provided with a second flip-chip pad 203 and a plurality of conductive pillar pads 204. The second back side 202 is provided with a third flip-chip pad 205 and a second metal conductive pillar 206.

[0021] In specific implementation, the second metal frame 2 also has a second through hole 207. Multiple second through holes 207 can be provided, as long as they do not affect the overall structural strength of the second metal frame 2. This facilitates the passage of molding compound in the molding process.

[0022] The first back side 102 of the first metal frame 1 is stacked downwards on the second front side 201 of the second metal frame 2; the position of the second flip pad 203 corresponds to the first through hole 103, and the first metal conductive post 105 is soldered to the conductive post pad 204 to form a metal frame assembly 6. The back side of the metal frame assembly 6 is the first front side 101 of the first metal frame 1, and the front side of the metal frame assembly 6 is the second back side 202 of the second metal frame 2.

[0023] The first chip 3 is flip-chip mounted on the back of the metal frame assembly 6. Some of the conductive bumps of the first chip 3 are electrically connected to the first flip-chip pad 104, and the other conductive bumps are electrically connected to the second flip-chip pad 203.

[0024] In specific implementation, the first chip 3 has a low-profile conductive bump 301 and a high-profile conductive bump 302 on its front side. The low-profile conductive bump 301 is electrically connected to the first flip-chip pad 104, and the high-profile conductive bump 302 passes through the first via 103 and is electrically connected to the second flip-chip pad 203. The high-profile conductive bump 302 is located away from the inner wall of the first via 103. The structure of the high and low-profile conductive bumps is quite ingenious, which simplifies the connection process between the first chip 3 and the second metal frame 2 and the second chip 4, and improves the interconnection quality and reliability between the chips.

[0025] The second chip 4 is flip-chip mounted on the front side of the metal frame assembly 6, and the conductive bumps 401 of the second chip 4 are electrically connected to the third flip-chip pad 205.

[0026] The molding section 5 encapsulates the first chip 3, the second chip 4, and the metal frame assembly 6 as a whole, while the top surface of the second metal conductive pillar 206 is exposed.

[0027] This invention, by adopting a double-layer frame structure design, enables the stacking of multiple flip chips, overcoming the limitation of existing technologies that can only flip chips on the front of a frame. This significantly improves the overall product structure complexity and meets the development needs of miniaturization and portability of electronic products.

[0028] The method for fabricating the above-mentioned QFN package structure of a fully flip-chip includes the following steps: S1. A first metal frame 1 is provided. The first metal frame 1 has a first front side 101, a first back side 102, and a first through hole 103. The first front side 101 is provided with a plurality of first flip-chip pads 104 for mounting a first chip. The plurality of first flip-chip pads 104 are arranged around the first through hole 103. The first back side 102 is provided with a plurality of first metal conductive pillars 105. The structure of the first metal frame 1 is as follows: Figure 2 As shown.

[0029] S2. A second metal frame 2 is provided, the second metal frame 2 having a second front side 201 and a second back side 202, the second front side 201 having a second flip-chip pad 203 and a plurality of conductive pillar pads 204; the second back side 202 having a third flip-chip pad 205 and a second metal conductive pillar 206.

[0030] In specific implementation, the second metal frame 2 also has a second through hole 207 to facilitate the passage of molding compound during the molding process. The structure of the second metal frame 2 is as follows: Figure 3As shown.

[0031] Both the first metal frame 1 and the second metal frame 2 are made of high-purity copper, which has good structural strength and a thickness of 0.1-0.15 mm.

[0032] S3. Stack the first back side 102 of the first metal frame 1 face down on the second front side 201 of the second metal frame 2; align the position of the second flip-chip pad 203 with the first through hole 103, and solder the first metal conductive post 105 to the conductive post pad 204 to form a metal frame assembly 6. The back side of the metal frame assembly 6 is the first front side 101 of the first metal frame 1, and the front side of the metal frame assembly 6 is the second back side 202 of the second metal frame 2. The structure of the metal frame assembly 6 is as follows: Figure 4 As shown.

[0033] S4. A first chip 3 is provided, which is flip-chip mounted on the back side of the metal frame assembly 6. Some of the conductive bumps of the first chip 3 are electrically connected to the first flip pad 104, and the other conductive bumps are electrically connected to the second flip pad 203.

[0034] In specific implementation, the front side of the first chip 3 is provided with a low conductive bump 301 and a high conductive bump 302. The low conductive bump 301 is electrically connected to the first flip pad 104, and the high conductive bump 302 passes through the first through hole 103 and is electrically connected to the second flip pad 203. The high conductive bump 302 is away from the inner wall of the first through hole 103.

[0035] S5. A second chip 4 is provided, which is flip-chip mounted on the front side of the metal frame assembly 6. The conductive bumps 401 of the second chip 4 are electrically connected to the third flip-chip pad 205.

[0036] The second metal conductive pillar 206 serves as an external communication port, and its height is greater than that of the second chip 4. The positions of some of the second metal conductive pillars 206 correspond to the conductive pillar pads 204.

[0037] The structure of the metal frame assembly 6, which incorporates the first chip 3 and the second chip 4, is as follows: Figure 5 As shown.

[0038] S6. The first chip 3, the second chip 4, and the metal frame assembly 6 are integrally encapsulated to form the encapsulated portion 5, exposing the top surface of the second metal conductive pillar 206, forming a shape as shown in the image. Figure 1 The QFN package structure shown.

[0039] Based on the product's heat dissipation requirements, the back of the metal frame assembly 6 can be thinned to expose the back of the first chip 3, thereby increasing heat dissipation efficiency.

[0040] In specific implementation, the diameter of the first metal conductive post 105 is 0.05mm-0.2mm and the height is 0.05mm-0.2mm; the diameter of the second metal conductive post 206 is 0.1mm-0.3mm and the height is 0.15-0.35mm.

[0041] Depending on the specific process flow, the order of some of the above steps can be adjusted.

[0042] This invention simplifies the chip-frame connection process by setting metal guide pillars and guide pillar pads on the front and back frames respectively, and adopting flip-chip bonding technology, thereby improving the interconnection quality and reliability between chips and solving the problem that the existing flip-chip and conventional chip packaging processes need further optimization.

[0043] This invention provides a variety of chip flip-chip layouts by setting metal bumps of different heights on the front and back sides of the metal frame assembly 6 and using a flip-chip bonding process. This overcomes the shortcomings of existing lead frame designs that cannot adequately meet the requirements of high-density, multi-I / O packaging.

[0044] This invention achieves a flexible heat dissipation design for the chip by setting a second metal conductive post 206 as an external communication port on the front side of the metal frame assembly 6, combined with the optional chip back-side exposed process, thus meeting the heat dissipation performance requirements of different products.

[0045] The above descriptions are merely some embodiments of the present invention. It should be noted that those skilled in the art can make other modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A method of fabricating a QFN package structure of full flip-chip, characterized in that, The method comprises the following steps: S1, providing a first metal frame, the first metal frame having a first front face, a first back face and a first through hole, the first front face being provided with a plurality of first flip-chip pads for mounting first flip-chip, the plurality of first flip-chip pads being arranged around the first through hole, the first back face being provided with a plurality of first metal conductive pillars; S2, providing a second metal frame, the second metal frame having a second front face and a second back face, the second front face being provided with a second flip-chip pad and a plurality of conductive pillar pads; the second back face being provided with a third flip-chip pad and a second metal conductive pillar; S3, stacking the first back face of the first metal frame downward on the second front face of the second metal frame; the position of the second flip-chip pad corresponds to the first through hole, and the first metal conductive pillar is welded to the conductive pillar pad to form a metal frame assembly, the back face of the metal frame assembly being the first front face of the first metal frame, and the front face of the metal frame assembly being the second back face of the second metal frame; S4, providing a first chip, the first chip being flip-chip mounted on the back face of the metal frame assembly, part of the conductive bumps of the first chip being electrically connected to the first flip-chip pad, and the other conductive bumps being electrically connected to the second flip-chip pad; S5, providing a second chip, the second chip being flip-chip mounted on the front face of the metal frame assembly, the conductive bumps of the second chip being electrically connected to the third flip-chip pad; S6, integrally plastic packaging the first chip, the second chip and the metal frame assembly to expose the top surface of the second metal conductive pillar to form a QFN packaging structure.

2. The method of claim 1, wherein, In step S4, the first chip has short conductive bumps and high conductive bumps, the short conductive bumps being electrically connected to the first flip-chip pad, and the high conductive bumps being electrically connected to the second flip-chip pad through the first through hole, the high conductive bumps being away from the inner wall of the first through hole.

3. The method of claim 2, wherein, The height of the second metal conductive pillar is greater than the height of the second chip, and part of the second metal conductive pillars correspond to the conductive pillar pads.

4. The method of claim 3, wherein, The second metal frame further has a second through hole for facilitating the passing of plastic packaging material in the plastic packaging process.

5. The method of claim 4, wherein, The back face of the metal frame assembly is thinned to expose the back face of the first chip.

6. The method of claim 5, wherein, The first metal frame and the second metal frame are both made of copper material and have a thickness of 0.1-0.15 mm.

7. The method of claim 6, wherein, The first metal conductive pillar has a diameter of 0.05-0.2 mm and a height of 0.05-0.2 mm; and the second metal conductive pillar has a diameter of 0.1-0.3 mm and a height of 0.15-0.35 mm.

8. A QFN package structure of full flip-chip, prepared by the method according to any one of claims 1-7, characterized in that, The first metal frame, the second metal frame, the first chip, the second chip and the plastic packaging part are included. The first metal frame has a first front face, a first back face and a first through hole, the first front face being provided with a plurality of first flip-chip pads for mounting first flip-chip, the plurality of first flip-chip pads being arranged around the first through hole, the first back face being provided with a plurality of first metal conductive pillars; The second metal frame has a second front face and a second back face, the second front face being provided with a second flip-chip pad and a plurality of conductive pillar pads; the second back face being provided with a third flip-chip pad and a second metal conductive pillar; The second metal frame has a second front face and a second back face, the second front face being provided with a second flip-chip pad and a plurality of conductive pillar pads; the second back face being provided with a third flip-chip pad and a second metal conductive pillar; The first back surface of the first metal frame is stacked downwardly on the second front surface of the second metal frame; the positions of the second flip chips correspond to the first through holes, and the first metal conductive pillars are welded to the conductive pillar pads to form a metal frame assembly, the back surface of the metal frame assembly is the first front surface of the first metal frame, and the front surface of the metal frame assembly is the second back surface of the second metal frame; The first chip is flipped on the back surface of the metal frame assembly, part of the conductive bumps of the first chip are electrically connected with the first flip chips, and the other conductive bumps are electrically connected with the second flip chips; The second chip is flipped on the front surface of the metal frame assembly, and the conductive bumps of the second chip are electrically connected with the third flip chips; The plastic encapsulation part integrally encapsulates the first chip, the second chip and the metal frame assembly, and the top end surfaces of the second metal conductive pillars are exposed.

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