Bump packaging structure of semiconductor chip, forming method of bump packaging structure and display driving chip
By using highly conductive metals such as copper and nickel as the core in the packaging structure of the display driver chip, and encapsulating it with a gold-plated layer on the surface, the problems of poor conductivity and reliability are solved, and the cost is reduced.
Patent Information
- Application Number
- CN202410866785.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-12-30
AI Technical Summary
Existing display driver chip packaging bump structures suffer from poor conductivity and reliability, as well as high manufacturing costs. In particular, gold bumps are expensive, copper/nickel/gold stacked bumps are prone to failure in high-temperature or corrosive environments, and palladium/gold stacked bumps have insufficient conductivity.
Using high-conductivity, low-cost metals such as copper, nickel, palladium, and silver as the bump core, and electroplating a stable metal layer such as gold on the surface, a bump packaging structure for encapsulating semiconductor chips is formed.
It achieves excellent conductivity and stable reliability, reduces process costs, and is suitable for packaging display driver chips.
Smart Images
Figure CN121237757A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a bump packaging structure of semiconductor chip, a forming method thereof and a display driving chip. BACKGROUND
[0002] With the continuous development of integrated circuit technology, electronic products are becoming more and more miniaturized, intelligent, high-performance and high-reliability. Integrated circuit packaging technology not only directly affects the performance of integrated circuits, electronic modules and even the whole machine, but also restricts the miniaturization, low cost and reliability of the whole electronic system. Under the condition of gradually reducing the size of integrated circuit wafer and continuously improving the integration level, the electronic industry puts forward higher and higher requirements for integrated circuit packaging technology. The packaging bump structure of semiconductor chip prepared by integrated circuit packaging technology usually refers to a technology used in the integrated circuit packaging process, in which the "bump" is a small metal column or metal point connecting the semiconductor chip and the external circuit (such as PCB board), and the bump structure plays an important role in packaging technology, which is crucial for realizing high-performance, miniaturized and low-cost electronic devices. The main function of the packaging bump structure is to provide electrical connection, so it must have high electrical conductivity to ensure that signals or power can be transmitted efficiently and reliably. In high-speed or high-frequency applications, the electrical conductivity of the packaging bump structure directly affects the integrity of the signal, and a bump structure with low resistivity helps to reduce signal loss and delay during transmission. In addition, the semiconductor and electronic industry usually requires mass production, so the manufacturing cost is an important consideration, and the use of low-cost materials can reduce the overall production cost and improve the market competitiveness of the product. At present, the preparation process of packaging bump structure is facing many challenges, including the miniaturization of bump structure, material selection, process complexity, manufacturing cost, reliability and other problems, solving the above problems is crucial to improve the performance of the bump structure and reduce the production cost.
[0003] Especially for the display driving chip used for driving the display panel to work, its narrow shape makes the area for setting the packaging bump structure extremely limited, and with the rapid development of the display panel industry, the area of the display driving chip is also continuously reduced, so the advanced packaging technology of the corresponding display driving chip also needs rapid development.
[0004] At present, the package bump structure of display driving chip mainly has three kinds: the first kind is gold bump (AU Bump), the conductive property and reliability of this gold bump are excellent, but the cost is higher; the second kind is copper / nickel / gold stack bump (CU / NI / AU stack Bump), copper, nickel and gold are stacked in turn, so that the sidewall of copper is exposed, the conductive property of this copper / nickel / gold stack bump is good, and the cost is reasonable, but since copper is more active, it is more likely to react chemically in high temperature or corrosive environment, thereby causing the problems such as the decrease of the conductive property of copper / nickel / gold stack bump, connection failure and the like; the third kind is palladium / gold stack bump (PD / AU stack Bump), the cost of this palladium / gold stack bump is between that of gold bump and copper / nickel / gold stack bump, but since the conductive property of palladium is not as good as that of copper or silver and the like, the overall conductive property may be reduced, and the use of palladium / gold stack bump may cause larger voltage drop, thereby affecting the integrity of signal and the performance of device.
[0005] As an example, a gold bump package structure is provided as shown in Figure 1 The metal layer 5 of the gold bump package structure is pure gold, which is not doped with other metals. Although the gold bump package structure has good conductive property and chemical stability, it also has challenges, for example: pure gold as the bulk material of the bump package structure will greatly increase the process cost; pure gold is relatively soft, which may cause the bump package structure to be damaged during the packaging process or in the subsequent assembly and use process; the density of pure gold is relatively high, which may increase the overall weight of the package. SUMMARY
[0006] The purpose of the present application is to overcome the defects of poor conductive property and reliability and high process cost of the driving IC package bump structure in the prior art.
[0007] In order to achieve the above purpose, the present application provides a forming method of a bump package structure of a semiconductor chip, comprising:
[0008] A semiconductor chip is provided, and a metal pad layer is formed on the surface of the semiconductor chip;
[0009] A first photoresist layer is formed on the metal pad layer, and part of the first photoresist layer is removed by exposure and development to form a first opening;
[0010] A first metal layer is filled in the first opening;
[0011] A second photoresist layer is formed on the surface of the first metal layer and the first photoresist layer, and a second opening is formed by exposure and development, the second opening is arranged outside the first metal layer;
[0012] forming a second metal layer in the second opening, the second metal layer wrapping the upper surface and sidewall of the first metal layer;
[0013] removing the first and second photoresist layers to obtain a bump package structure of the semiconductor chip.
[0014] Optionally, the material of the first metal layer is any one or a combination of more than one of copper, nickel, palladium, and silver.
[0015] Optionally, the material of the second metal layer is any one of gold, platinum, titanium, and tantalum.
[0016] Optionally, the first and second metal layers are formed by an electroplating process.
[0017] Optionally, the thickness of the first metal layer is 5-9 mm.
[0018] Optionally, the thickness of the second metal layer is 1-5 mm.
[0019] Optionally, a passivation layer is further formed on the surface of the semiconductor chip, the metal pad layer is embedded in the passivation layer, the passivation layer is provided with a third opening exposing the upper surface of the metal pad layer.
[0020] Optionally, before the first photoresist layer is formed, a metal barrier layer is further formed on the upper surface of the metal pad layer and the passivation layer, and a metal seed layer is further formed on the upper surface of the metal barrier layer.
[0021] Optionally, the material of the passivation layer comprises any one of silicon nitride, silicon oxide, and silicon oxynitride.
[0022] Optionally, the material of the metal pad layer is at least one of aluminum, copper, nickel, tin-lead alloy, and tin-silver alloy.
[0023] Optionally, the material of the metal barrier layer comprises any one of titanium and tungsten titanium.
[0024] Optionally, the material of the metal seed layer comprises any one of copper, nickel, palladium, silver, gold, platinum, titanium, and tantalum.
[0025] Optionally, before the passivation layer is formed, the method further comprises pretreating the semiconductor chip and manufacturing steps of the semiconductor device.
[0026] Optionally, before the first metal layer is filled in the first opening, the method further comprises a cleaning step.
[0027] Optionally, before the second metal layer is formed in the second opening, the method further comprises a cleaning step.
[0028] The application further provides a bump packaging structure of a semiconductor chip, which at least comprises:
[0029] a bump body with a first metal layer;
[0030] a second metal layer wrapping the upper surface and the sidewall of the first metal layer;
[0031] The material of the first metal layer is any one or any combination of more than one of copper, nickel, palladium and silver, and the material of the second metal layer is any one of gold, platinum, titanium and tantalum.
[0032] Optionally, the bump packaging structure of the semiconductor chip is arranged on a metal pad layer of the semiconductor chip and forms an electrical connection with the metal pad layer.
[0033] Optionally, a passivation layer is further formed on the surface of the semiconductor chip, and the metal pad layer is embedded in the passivation layer, and there is a metal barrier layer and a metal seed layer between the metal pad layer and the first metal layer.
[0034] The application further provides a display driving chip, which at least comprises the bump packaging structure of the semiconductor chip as described in any one of the above.
[0035] Compared with the prior art, the application has at least the following beneficial effects:
[0036] The bump packaging structure of the semiconductor chip formed by the forming method of the application comprises a bump body with a first metal layer, a second metal layer wrapping the upper surface and the sidewall of the first metal layer, the material of the first metal layer is any one or any combination of more than one of copper, nickel, palladium and silver, and the material of the second metal layer is any one of gold, platinum, titanium and tantalum. A high-conductivity and low-cost metal or alloy such as copper and nickel is used as the core of the bump, and a metal layer with good stability such as gold is electroplated on the surface of the core of the bump to form a wrapped bump packaging structure of a semiconductor chip, which can ensure good conductivity and stable reliability and greatly reduce the process cost. BRIEF DESCRIPTION OF DRAWINGS
[0037] Figure 1 FIG. 1 is a schematic diagram of a gold bump packaging structure in the prior art.
[0038] Figure 2 FIG. 2 is a flowchart of a forming method of a bump packaging structure of a semiconductor chip according to the application.
[0039] Figure 3 FIG. 3 is a schematic diagram of a forming process of a first opening of a semiconductor chip according to the application.
[0040] Figure 4 This is a schematic diagram of the structure of the first metal layer filled in the first opening of the semiconductor chip according to the present invention.
[0041] Figure 5 This is a schematic diagram illustrating the formation process of the second opening in the semiconductor chip of the present invention.
[0042] Figure 6 This is a schematic diagram of the structure of the second metal layer filled in the second opening of the semiconductor chip according to the present invention.
[0043] Figure 7 This is a complete schematic diagram of the semiconductor bump structure formed according to the present invention.
[0044] Wherein, 1-metal pad, 2-passivation layer, 3-metal barrier layer, 4-metal seed layer, 5-metal layer, 51-first metal layer, 52-second metal layer, 61-first photoresist layer, 62-second photoresist layer, 7-mask, 81-first opening, 82-second opening. Detailed Implementation
[0045] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0046] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0047] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0048] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clearly illustrate the purpose of this invention.
[0049] Based on the above, the present invention provides a bump package structure for a semiconductor chip and a method for forming the same. The bump package structure for the semiconductor chip formed by the method comprises: a bump body having a first metal layer; and a second metal layer encapsulating the upper surface and sidewalls of the first metal layer. The first metal layer is made of any one or a combination of more than one of copper, nickel, palladium, and silver; and the second metal layer is made of any one of gold, platinum, titanium, and tantalum. By using a highly conductive metal or alloy such as copper or nickel as the bump core, and electroplating a layer of a relatively stable metal such as gold on the surface of the bump core, a bump package structure for an encapsulated semiconductor chip is formed. This structure ensures excellent conductivity and stable reliability while significantly reducing process costs.
[0050] like Figure 2 As shown, a method for forming a bump package structure for a semiconductor chip according to the present invention includes:
[0051] Step S1: Provide a semiconductor chip, wherein a metal pad is formed on the surface of the semiconductor chip.
[0052] First, the semiconductor chip undergoes pretreatment and semiconductor device manufacturing steps. After device manufacturing is complete, a bump package structure is formed to achieve electrical connection between the device structure and the outside. Before forming the bump package structure on the semiconductor chip, the semiconductor chip is cleaned to remove contaminants and oxide layers from the semiconductor chip surface during device manufacturing. A clean semiconductor chip surface helps improve the adhesion of subsequent deposited materials to the semiconductor chip, ensuring the mechanical and electrical stability of the bump package structure. Removing conductive particles from the semiconductor chip surface also prevents short circuits during bump package structure formation, which could lead to product failure. After cleaning the semiconductor chip, surface planarization technology can be applied to ensure a smooth, defect-free semiconductor chip surface. Some embodiments also include forming an insulating layer, such as silicon dioxide or silicon nitride, on the surface of the semiconductor chip to isolate different metal layers and prevent short circuits.
[0053] A metal pad 1 is deposited on the surface of the semiconductor chip using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other metal deposition techniques. The metal pad 1 provides electrical connection between the semiconductor chip and the subsequent bump package structure, ensuring efficient signal or power transmission. The metal pad 1 also provides mechanical support for the subsequently formed bump package structure, ensuring it maintains its shape and position and preventing deformation or damage during packaging or use. In some embodiments, the metal pad 1 can be made of any one of aluminum, copper, nickel, tin-lead alloy, or tin-silver alloy.
[0054] like Figure 3 As shown, after depositing a metal pad 1 on the surface of the semiconductor chip, a passivation layer 2 is deposited on the metal pad 1, such that the metal pad 1 is embedded in the passivation layer 2. The passivation layer 2 has an opening in the middle, exposing the upper surface of the metal pad 1 so that the metal pad 1 can establish an electrical connection with external circuits or other components. The passivation layer 2 can prevent the metal pad 1 from oxidizing in air, maintaining its conductivity; provide additional protection, making the metal pad 1 more resistant to chemical corrosion; slow down the migration of metal ions, helping to improve the electrical stability and reliability of the device; and provide electrical insulation to prevent short circuits between different metal layers. In some embodiments, the material of the passivation layer 2 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.
[0055] To prevent metal atoms in the metal pad 1 from diffusing into the passivation layer 2 or the surrounding medium, thereby avoiding potential short circuits or electromigration problems, a metal barrier layer 3 is formed on the upper surface of the metal pad 1 and the passivation layer 2. The metal barrier layer 3 is made of low-resistivity titanium or tungsten titanide. The metal barrier layer 3 protects the underlying metal pad 1 from chemical corrosion or physical damage, improves the adhesion between the passivation layer 2 and the metal pad 1, thereby improving the mechanical stability of the structure, and can act as a catalyst for subsequent processes (such as electroplating bump packaging structures), promoting the uniform deposition of subsequent metal layers. The metal barrier layer 3 does not affect the electrical connection between the bump packaging structure and the metal pad 1. A metal seed layer 4 is also formed on the upper surface of the metal barrier layer 3. The metal seed layer 4 facilitates the deposition of subsequent materials. During the subsequent electroplating of the bump packaging structure, the metal seed layer 4 provides the necessary electrical conductivity path, allowing the current to be distributed uniformly, thereby achieving a uniform electroplating process. In some embodiments, the metal seed layer 4 comprises any one of copper, nickel, palladium, silver, gold, platinum, titanium, and tantalum.
[0056] Step S2: A first photoresist layer 61 is formed on the metal pad 1. By exposure and development, a portion of the first photoresist layer 61 is removed to form a first opening 81.
[0057] like Figure 3 As shown, in order to deposit a bump packaging structure in a specific area of the metal pad 1, liquid photoresist is uniformly coated onto the metal pad 1 using a spin coating process to form a first photoresist layer 61. A photolithography machine is used to expose and develop the pattern on the mask 7 onto the first photoresist layer 61 using ultraviolet light, forming the desired pattern. The first photoresist layer 61 corresponding to the exposed area above the metal pad 1 is then etched away to form a first opening 81. A cleaning process is then performed on the semiconductor chip to remove etching residues.
[0058] Step S3: Fill the first metal layer 51 into the first opening 81.
[0059] like Figure 4 As shown, a semiconductor chip with the first opening 81 formed is placed in an electroplating solution and connected to a power source. Metal ions migrate under the influence of an electric field and are reduced and deposited on the metal seed layer 4, gradually filling the first opening 81 to form a first metal layer 51 with a thickness of 5mm to 9mm. This first metal layer 51 serves as the bump body. The material of the first metal layer 51 is selected based on its excellent conductivity, chemical reactivity, and low cost, such as copper, nickel, palladium, or silver. The final material selection depends on the requirements of the final application and cost considerations; in this embodiment, the first metal layer is selected from copper.
[0060] Step S4: A second photoresist layer 62 is formed on the surface of the first metal layer 51 and the first photoresist layer 61, and a second opening 82 is formed by exposure and development. The second opening 82 surrounds the first metal layer 51.
[0061] like Figure 5 As shown, in order to electroplate a second metal layer 52 onto the surface of the first metal layer 51, which serves as the bump body, so that the second metal layer 52 encapsulates the upper surface and sidewalls of the first metal layer 51, liquid photoresist is uniformly coated onto the surfaces of the first metal layer 51 and the first photoresist layer 61 using a spin-coating process to form a second photoresist layer 62. A photolithography machine is used to expose and develop the pattern on the mask 7 onto the second photoresist layer 62 using ultraviolet light, forming the desired pattern. The sidewalls and upper surface of the second photoresist layer 62 of the first metal layer 51 are then etched away to form a second opening 82, which surrounds the first metal layer 51. A cleaning process is then performed on the semiconductor chip to remove etching residues.
[0062] Step S5: A second metal layer 52 is formed in the second opening 82, and the second metal layer 52 covers the upper surface and sidewalls of the first metal layer 51.
[0063] like Figure 6As shown, a semiconductor chip with the second opening 82 formed is placed in an electroplating solution and connected to a power source. Metal ions migrate under the influence of an electric field and are reduced and deposited on the metal seed layer 4 and the sidewalls of the first metal layer 51, gradually filling the second opening 82 to form a second metal layer 52 with a thickness of 1mm to 5mm. The second metal layer 52 encapsulates the first metal layer 51, forming a wrap-around bump packaging structure. The material of the second metal layer 52 is selected based on its excellent stability and high conductivity, such as gold, platinum, titanium, or tantalum. The final material selection depends on the requirements of the final application and cost considerations; in this embodiment, gold is selected for the second metal layer. Since the second metal layer only wraps the upper surface and sidewalls of the first metal layer, it does not require excessive material, greatly saving process costs and reducing the overall weight of the bump structure, resulting in a more refined bump packaging structure.
[0064] Step S6: Remove the first photoresist layer 61 and the second photoresist layer 62 to obtain the bump package structure of the semiconductor chip.
[0065] like Figure 7 As shown, specific chemical reagents are used to clean the first photoresist layer 61 and the second photoresist layer 62, exposing the bump package structure of the semiconductor chip and ensuring reliable electrical connection between the bump package structure and other electronic components or circuits. The bump package structure includes at least: a bump body having a first metal layer 51; a second metal layer 52, which wraps around the upper surface and sidewalls of the first metal layer 51; the first metal layer 51 is made of any one or any combination of copper, nickel, palladium, and silver; the second metal layer 52 is made of any one of gold, platinum, titanium, and tantalum. The bump package structure of the semiconductor chip is disposed on the metal pad layer 1 of the semiconductor chip and forms an electrical connection with the metal pad layer 1. A passivation layer 2 is also formed on the surface of the semiconductor chip. The metal pad layer 1 is embedded in the passivation layer 1. Between the metal pad layer 1 and the first metal layer 51, there is a metal barrier layer 3 and a metal seed layer 4. The metal barrier layer 3 is made of low-resistivity titanium or tungsten titanate, and the metal seed layer 4 contains any one of copper, nickel, palladium, silver, gold, platinum, titanium, and tantalum. The bump package structure of the semiconductor chip obtained by the above formation method can be used in display driver chips.
[0066] In summary, this invention forms a first photoresist layer on a semiconductor chip with a metal pad, removes part of the first photoresist layer through exposure and development to form a first opening, fills the first opening with a first metal layer, the first metal layer being any one of copper, nickel, palladium, and silver, forms a second photoresist layer on the surface of the first metal layer and the first photoresist layer, forms a second opening through exposure and development, and forms a second metal layer within the second opening, such that the second metal layer wraps the upper surface and sidewalls of the first metal layer, the second metal layer being any one of gold, platinum, titanium, and tantalum. The resulting bump package structure has excellent conductivity and reliability, and by wrapping a higher-cost metal layer on the surface and sidewalls of a lower-cost metal layer, it greatly saves on process costs.
[0067] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method of forming a bump package structure of a semiconductor chip, characterized by, Comprising: Providing a semiconductor chip, a metal pad layer is formed on the surface of the semiconductor chip; Forming a first photoresist layer on the metal pad layer, by exposure and development, removing part of the first photoresist layer, forming a first opening; Filling the first metal layer in the first opening; Forming a second photoresist layer on the surface of the first metal layer and the first photoresist layer, forming a second opening by exposure and development, the second opening is surrounded by the first metal layer outside; Forming a second metal layer in the second opening, the second metal layer wraps the upper surface and the sidewall of the first metal layer; Removing the first photoresist layer and the second photoresist layer, obtaining the bump package structure of the semiconductor chip.
2. The formation method of claim 1, wherein, The material of the first metal layer is any one or any combination of the above of copper, nickel, palladium, silver.
3. The formation process of claim 1 wherein, The material of the second metal layer is any one of gold, platinum, titanium, tantalum.
4. The formation process of claim 1 wherein, The first metal layer and the second metal layer are formed by electroplating process.
5. The formation process of claim 1 wherein, The thickness of the first metal layer is 5mm-9mm.
6. The formation process of claim 1 wherein, The thickness of the second metal layer is 1mm-5mm.
7. The formation process of claim 1 wherein, A passivation layer is also formed on the surface of the semiconductor chip, the metal pad layer is embedded in the passivation layer, the passivation layer is provided with a third opening, which exposes the upper surface of the metal pad layer.
8. The formation method of claim 7 wherein, Before forming the first photoresist layer, a metal barrier layer is also formed on the upper surface of the metal pad layer and the passivation layer, and a metal seed layer is also formed on the upper surface of the metal barrier layer.
9. The formation method of claim 7 wherein, The material of the passivation layer includes any one of silicon nitride, silicon oxide, silicon oxynitride.
10. The formation process of claim 1 wherein, The material of the metal pad layer is at least one of aluminum, copper, nickel, tin-lead alloy, tin-silver alloy.
11. The formation method of claim 8, wherein, The material of the metal barrier layer includes any one of titanium and tungsten titanium.
12. The formation process of claim 8 wherein, The material of the metal seed layer includes any one of copper, nickel, palladium, silver, gold, platinum, titanium, tantalum.
13. The formation process of claim 7 wherein, Before forming the passivation layer, it also includes pretreatment of the semiconductor chip and each step of semiconductor device manufacturing.
14. The formation process of claim 1 wherein, Before filling the first metal layer in the first opening, it also includes a cleaning step.
15. The formation process of claim 1 wherein, Before forming the second metal layer in the second opening, it also includes a cleaning step.
16. A bump package structure of a semiconductor chip, characterized by comprising: The bump package structure of the semiconductor chip at least includes: The bump body with the first metal layer; The second metal layer wraps the upper surface and the sidewall of the first metal layer; the material of the first metal layer is any one or any combination of the above of copper, nickel, palladium, silver; the material of the second metal layer is any one of gold, platinum, titanium, tantalum.
17. The bump package structure of a semiconductor chip as claimed in claim 16, wherein The bump package structure of the semiconductor chip is arranged on the metal pad layer of the semiconductor chip and forms an electrical connection with the metal pad layer.
18. The bump package structure of a semiconductor chip as claimed in claim 17, wherein The surface of the semiconductor chip also has a passivation layer, the metal pad layer is embedded in the passivation layer, and there is also a metal barrier layer and a metal seed layer between the metal pad layer and the first metal layer.
19. A display driving chip, characterized in that, The display driving chip at least includes the bump package structure of the semiconductor chip as claimed in any one of claims 16-18.