Surface-mounted power element and manufacturing method thereof

Abstract

The invention discloses a surface mounting power component and a manufacturing method thereof, the surface mounting power component comprises a substrate formed by an insulation core plate and a patterned metal layer, and the patterned metal layer comprises a base island area and a pin area; the step-shaped feature structure is arranged in the pin area, the step-shaped feature structure comprises a convex part and a peripheral part, and the peripheral part is lower than the convex part; the conductive material layer is arranged on the peripheral part of the stepped feature structure; a semiconductor die attached to the patterned metal layer in the base island region; a lead including a lead terminal bonded to a peripheral portion of the stepped feature through a conductive material layer; routing to connect the semiconductor die and the protruding portion of the stepped feature structure; and the plastic package body wraps the substrate, the stepped feature structure, the semiconductor crystal grains and the bonding wires, and at least partially wraps the leads.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an improved surface mount power device and its manufacturing method. Background Technology

[0002] Surface mount power devices (SMPDs) are electronic components that are mounted directly on the surface of a printed circuit board (PCB) using surface mount technology (SMT). They offer a unique combination of high performance, compact size, and enhanced thermal management, making them ideal for a wide range of applications in power electronics.

[0003] SMPDs can be assembled using direct copper bonding (DCB), direct bonded copper (DBC), active metal brazing (AMB), or direct plated copper (DPC) ceramic substrates. They offer excellent thermal conductivity and low thermal resistance, enabling the SMPD package structure to effectively dissipate heat from the active components, thus giving it higher power density and efficiency than standard discrete component structures.

[0004] However, existing SMPD packaging processes encounter lead frame tilting or warping, leading to problems such as micro-bouncing effect, poor wire bonding, or mold flash, which need to be further overcome. Summary of the Invention

[0005] The main objective of this invention is to provide an improved power semiconductor device to overcome the shortcomings or disadvantages of the prior art.

[0006] This invention provides a surface-mount power device, comprising: a substrate, the substrate including a ceramic insulating core plate and a first patterned metal layer disposed on a first surface of the ceramic insulating core plate, wherein the first patterned metal layer includes a base island region and a first pin region; at least one first stepped feature structure disposed within the first pin region, wherein the at least one first stepped feature structure includes a first protrusion portion and a first peripheral portion, wherein the first peripheral portion is lower than the first protrusion portion; and a first conductive material layer disposed on the first peripheral portion of the first stepped feature structure. On the edge portion; at least one semiconductor die, attached to the first patterned metal layer within the base island region; at least one first lead, including a first lead terminal, wherein the first lead terminal is bonded to the first peripheral portion of the first stepped feature structure through the first conductive material layer; at least one bonding wire, connecting the at least one semiconductor die and the first protrusion portion of the first stepped feature structure; and a molding compound, covering the substrate, the at least one first stepped feature structure, the at least one semiconductor die, the at least one bonding wire, and at least partially covering the at least one first lead.

[0007] According to an embodiment of the present invention, the first lead terminal has a Y-shaped structure and directly contacts the first conductive material layer.

[0008] According to an embodiment of the present invention, the first peripheral portion is a U-shaped recessed area that has been partially etched, partially surrounding the first protruding portion.

[0009] According to an embodiment of the present invention, the first protrusion is closer to the base island region and the first protrusion is directly connected to the first peripheral portion. It is integrally formed in structure to constitute the at least one first stepped feature structure.

[0010] According to embodiments of the present invention, the substrate includes a direct copper bonding (DCB) substrate, a direct bonded copper (DBC) substrate, an active metal brazing (AMB) substrate, or a direct plated copper (DPC) substrate.

[0011] According to an embodiment of the present invention, the at least one semiconductor die includes an insulated gate bipolar transistor (IGBT), a power MOSFET, a bipolar junction transistor (BJT), a silicon carbide (SiC) power device, a gallium nitride (GaN) power device, a high electron mobility transistor (HEMT), or a fast recovery diode (FRD).

[0012] According to an embodiment of the present invention, the surface mount power element further includes a second patterned metal layer disposed on a second surface of the ceramic insulating core board.

[0013] According to an embodiment of the present invention, the second patterned metal layer is exposed from one side of the molding compound and is in direct contact with a heat sink.

[0014] In summary, because the wire bonding point falls on the first protrusion of the first stepped feature structure rather than on the first lead terminal during the wire bonding process, problems such as micro-bouncing effect and poor bonding strength can be effectively avoided. Furthermore, the male-female wedge design of the first lead terminal and the first protrusion makes installation and positioning more convenient and precise, preventing substrate offset or rotation, and improving lead frame tilt or warping, thus effectively solving the mold flash problem.

[0015] To further understand the features and technical content of this invention, please refer to the following detailed description and accompanying drawings. However, these descriptions and drawings are only for illustrating the invention and are not intended to limit the scope of protection of the invention in any way. Attached Figure Description

[0016] Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating a surface-mount power device according to an embodiment of the present invention, wherein... Figure 7 To be Figure 6 A side view diagram of the structure after it has been flipped up and down. Figure 9 To be Figure 8 A side view diagram of the structure after it has been flipped up and down.

[0017] Figures 10A to 10C These are enlarged schematic diagrams of the first step-shaped feature structure as illustrated in different embodiments.

[0018] Figures 11A to 11C They are respectively the corresponding Figures 10A to 10C A partially enlarged schematic diagram of the first stepped feature structure LS1 and the first lead terminal LT1 after wire bonding.

[0019] Figure 12 This is a cross-sectional structural diagram of a surface-mount power device according to an embodiment of the present invention.

[0020] The reference numerals in the attached figures are explained as follows:

[0021] 1 Surface Mount Power Components

[0022] 10 substrates

[0023] 11 Ceramic Insulation Core Board

[0024] 12 Second patterned metal layer

[0025] 13 Second patterned metal layer

[0026] 20 conductor frames

[0027] 30 Molded Body

[0028] Taipei 101 Island District

[0029] 102 First Pin Area

[0030] 103 second pin area

[0031] 310 heatsink

[0032] CP1 First Chip Mounting Pad

[0033] CP2 Second Chip Mounting Pad

[0034] DB1 First Dam

[0035] DB2 Second Dam

[0036] IR1 first protrusion

[0037] IR2 second protrusion

[0038] L1 first lead

[0039] L2 second lead

[0040] LS1 first-step feature structure

[0041] LS2 second-step feature structure

[0042] LT1 first lead terminal

[0043] LT2 second lead terminal

[0044] LO1 pin 1

[0045] LO2 pin 2

[0046] PR1 First Peripheral Section

[0047] PR2 Second Peripheral Section

[0048] R-shaped depression feature

[0049] S1 First Surface

[0050] S2 Second Surface

[0051] SD1 First Semiconductor Chip

[0052] SD2 Second Semiconductor Die

[0053] SP1 First Conductive Material Layer

[0054] SP2 Second Conductive Material Layer

[0055] WB1's first line of attack

[0056] WB2's second batting average

[0057] WB3's third line

[0058] WR1 First Wire Bonding Area

[0059] WR2 second bonding area Detailed Implementation

[0060] The following specific embodiments illustrate the implementation of the "surface-mount power device and its manufacturing method" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0061] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.

[0062] Please see Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating a surface-mount power device according to an embodiment of the present invention. It should be understood that... Figures 1 to 9 The invention is illustrated using a single-sided cooling (SSC) power device package structure as an example. However, the invention is not limited thereto. Those skilled in the art will understand that the invention can also be applied to other package types, such as double-sided cooling (DSC) power device packages or TOXX standard packages.

[0063] like Figure 1As shown, firstly, a substrate 10 is provided, which may include a ceramic insulating core 11 and a first patterned metal layer 12, such as a patterned copper metal layer, disposed on a first surface S1 of the ceramic insulating core 11. According to an embodiment of the present invention, a second patterned metal layer may be disposed on a second surface S2 of the ceramic insulating core 11 opposite to the first surface S1 for heat dissipation purposes (which will be further explained later). For example, the patterned copper metal layer disposed on the first surface S1 and the second surface S2 of the ceramic insulating core 11 may be formed using direct copper bonding (DCB), direct bonded copper (DBC), active metal brazing (AMB), or direct plated copper (DPC) techniques, depending on actual needs, but is not limited thereto.

[0064] According to an embodiment of the present invention, a first patterned metal layer 12 disposed on a first surface S1 of a ceramic insulating core board 11 includes, for example, a first chip mounting pad CP1 and a second chip mounting pad CP2 formed in a base island region 101, a first wire bonding region WR1 and a second wire bonding region WR2, and a plurality of first stepped feature structures LS1 and a plurality of second stepped feature structures LS2 respectively formed in a first pin region 102 and a second pin region 103. Six first stepped feature structures LS1 and three second stepped feature structures LS2 are illustrated in the figure. However, it should be understood that the number and arrangement of the aforementioned first chip mounting pad CP1, second chip mounting pad CP2, first wire bonding region WR1, second wire bonding region WR2, first stepped feature structures LS1 and second stepped feature structures LS2 are merely illustrative examples, and the present invention is not limited thereto.

[0065] According to embodiments of the present invention, for example, a plurality of first stepped feature structures LS1 in the first pin region 102 may be disconnected from the large-area metal pattern formed in the base island region 101 without direct contact. According to embodiments of the present invention, for example, a plurality of second stepped feature structures LS2 in the second pin region 103 may not be disconnected from the large-area metal pattern formed in the base island region 101; in other words, the second stepped feature structures LS2 may be in direct contact with the metal pattern formed in the base island region 101. However, it should be understood that the above metal pattern layout is merely illustrative and the present invention is not limited thereto.

[0066] According to an embodiment of the present invention, for example, a plurality of first stepped feature structures LS1 within the first pin region 102 are arranged separately along one side of the substrate 10. According to an embodiment of the present invention, for example, each first stepped feature structure LS1 may include a first protrusion portion IR1 and a first peripheral portion PR1, wherein the first peripheral portion PR1 may be a half-etched U-shaped recessed region, partially surrounding the first protrusion portion IR1. According to an embodiment of the present invention, the first protrusion portion IR1 closer to the base island region 101 is directly connected to the U-shaped recessed first peripheral portion PR1, and is integrally formed to form the first stepped feature structure LS1.

[0067] According to an embodiment of the present invention, for example, a plurality of second stepped feature structures LS2 within the second pin region 102 are arranged separately from each other along opposite sides of the substrate 10. According to an embodiment of the present invention, for example, each second stepped feature structure LS2 may include a second protruding portion IR2 and a second peripheral portion PR2, wherein the second peripheral portion PR2 is also a half-etched U-shaped recessed region, partially surrounding the second protruding portion IR2. According to an embodiment of the present invention, the second protruding portion IR2 directly connected to the base island region 101 and the U-shaped recessed second peripheral portion PR2 are structurally integrally formed to form the second stepped feature structure LS2.

[0068] Please also refer to Figures 10A to 10C These are partially enlarged schematic diagrams of the first stepped feature structure LS1 illustrated according to different embodiments. Those skilled in the art will understand that the plurality of second stepped feature structures LS2 located on the other side of the substrate 10 may also have the same or similar characteristics. Figures 10A to 10C The structure of is not elaborated further below for the sake of simplicity.

[0069] like Figure 10A As shown, the first stepped feature structure LS1 includes a first protruding portion IR1 and a first peripheral portion PR1. The first protruding portion IR1 may have a semi-circular structure extending towards the side of the substrate 10, and the first peripheral portion PR1 may be a U-shaped recessed area that has been partially etched, partially surrounding the first protruding portion IR1. The upper surface of the first peripheral portion PR1 is lower than the upper surface of the first protruding portion IR1. According to an embodiment of the present invention, the first protruding portion IR1, which is closer to the base island region 101, is directly connected to the U-shaped recessed first peripheral portion PR1, and they are structurally integrally formed.

[0070] like Figure 10BAs shown, the first stepped feature structure LS1 includes a first protruding portion IR1 and a first peripheral portion PR1. The first protruding portion IR1 may have a semi-circular structure extending towards the side of the substrate 10. The first peripheral portion PR1 may be a fully etched U-shaped region (as shown by the dashed line area), and the first peripheral portion PR1 partially surrounds the first protruding portion IR1. The first peripheral portion PR1 is defined by a portion of the first surface S1 of the ceramic insulating core board 11; that is, the first peripheral portion PR1 does not contain a copper metal layer. According to an embodiment of the present invention, the sidewall of the first protruding portion IR1 may have a recessed feature R.

[0071] like Figure 10C As shown, the first stepped feature structure LS1 also includes a first protruding portion IR1 and a first peripheral portion PR1. Figure 10A In the middle, the first protrusion IR1 has a semi-circular structure extending toward the side of the substrate 10, in Figure 10C In the first peripheral portion PR1, the junction between the first protruding portion IR1 and the first peripheral portion PR1 is straight. The first peripheral portion PR1 may be a partially etched recessed area. The upper surface of the first peripheral portion PR1 is lower than the upper surface of the first protruding portion IR1. According to an embodiment of the present invention, the first protruding portion IR1, which is closer to the base island region 101, is directly connected to the recessed first peripheral portion PR1, and is integrally formed in structure.

[0072] like Figure 2 As shown, a first conductive material layer SP1 and a second conductive material layer SP2 are then formed on the first peripheral portion PR1 of the first stepped feature structure LS1 and the second peripheral portion PR2 of the second stepped feature structure LS2, respectively. According to an embodiment of the present invention, the first conductive material layer SP1 and the second conductive material layer SP2 may include, but are not limited to, solder paste or press-less silver sintering paste. According to an embodiment of the present invention, for example, the first conductive material layer SP1 and the second conductive material layer SP2 can be formed on the first peripheral portion PR1 and the second peripheral portion PR2 respectively using a printing method. According to an embodiment of the present invention, for example, the above printing method may include screen printing or jet printing, but is not limited thereto. According to an embodiment of the present invention, for example, the upper surfaces of the first conductive material layer SP1 and the second conductive material layer SP2 may be coplanar with the upper surfaces of the first protrusion IR1 and the second protrusion IR2, respectively. According to other embodiments of the present invention, for example, the upper surfaces of the first conductive material layer SP1 and the second conductive material layer SP2 may be lower than the upper surfaces of the first protrusion IR1 and the second protrusion IR2, respectively.

[0073] like Figure 3As shown, the first semiconductor die SD1 and the second semiconductor die SD2 are then bonded to the first chip mounting pad CP1 and the second chip mounting pad CP2 within the base island region 101, respectively. According to embodiments of the present invention, the first semiconductor die SD1 and the second semiconductor die SD2 may be power chips, but are not limited thereto. The type of power chip can be adjusted and varied according to actual needs. For example, the power chip may be an insulated-gate bipolar transistor (IGBT), a power MOSFET, a bipolar junction transistor (BJT), a silicon carbide (SiC) power device, a gallium nitride (GaN) power device, a high electron mobility transistor (HEMT), or a fast recovery diode (FRD).

[0074] like Figure 4 As shown, the leadframe 20 is then mounted onto the substrate 10. According to an embodiment of the invention, the leadframe 20 is a metal frame, typically made of copper or a copper alloy, formed by stamping or etching to create a plurality of first leads L1 and a plurality of second leads L2 respectively connected to the first dam bar DB1 and the second dam bar DB2. According to an embodiment of the invention, the first leads L1 and the second leads L2 each have a first lead terminal LT1 and a second lead terminal LT2, which are respectively bonded to the first peripheral portion PR1 of the first stepped feature structure LS1 and the second peripheral portion PR2 of the second stepped feature structure LS2. For example, the first lead terminal LT1 and the second lead terminal LT2 may have a Y-shaped structure, directly contacting the first conductive material layer SP1 and the second conductive material layer SP2 respectively.

[0075] Subsequently, vacuum reflow and flux clean processes can be performed to form a strong solder joint. According to an embodiment of the present invention, the first lead terminal LT1 and the second lead terminal LT2 will not directly contact the first protrusion IR1 of the first stepped feature structure LS1 and the second protrusion IR2 of the second stepped feature structure LS2.

[0076] like Figure 5As shown, a wire bonding process is then performed, for example, wedge bonding. Multiple first bond wires WB1 are formed between the first semiconductor die SD1 and the first protrusion IR1 of the corresponding first stepped feature structure LS1, and between the second semiconductor die SD2 and the first protrusion IR1 of the corresponding first stepped feature structure LS1. A second bond wire WB2 is formed between the first semiconductor die SD1 and the second wire bonding region WR2, and a third bond wire WB3 is formed between the second semiconductor die SD2 and the first wire bonding region WR1. According to embodiments of the present invention, the first bond wires WB1, WB2, and WB3 may contain gold or copper wires, but are not limited thereto.

[0077] Please also refer to Figures 11A to 11C They correspond to Figures 10A to 10C The diagram shows a partially enlarged view of the first stepped feature structure LS1 and the first lead terminal LT1 after wire bonding. (See attached image.) Figure 11A As shown, one end of the first bonding wire WB1 is directly bonded to the first protruding portion IR1 of the first stepped feature structure LS1, which maintains a distance from the first lead terminal LT1. Figure 11B As shown, one end of the first wire bonding WB1 is also directly bonded to the first protrusion IR1 of the first stepped feature structure LS1, maintaining a distance from the first lead terminal LT1. Furthermore, the first conductive material layer SP1 can overflow through capillary action to the recessed feature R on the sidewall of the first protrusion IR1, further increasing the stability of the bonding structure. Figure 11C As shown, one end of the first wire bonding WB1 is also directly bonded to the first protruding portion IR1 of the first stepped feature structure LS1, which maintains a distance from the first lead terminal LT1.

[0078] Because the wire bonding process involves placing the bonding point on the first protrusion IR1 of the first stepped feature structure LS1, rather than on the first lead terminal LT1, problems such as micro-bouncing effect and poor bonding strength can be effectively avoided. Furthermore, through methods such as... Figure 11A and Figure 11B In the design of the Y-shaped first lead terminal LT1 and the first protrusion IR1, the male and female wedge design makes the installation and positioning more convenient and accurate, avoids substrate offset or rotation, and can improve the tilt or warping of the lead frame, thus effectively solving the mold flash problem.

[0079] like Figure 6 and Figure 7As shown, next, a molding process is performed, for example, film-assisted molding (FAM), in which the substrate 10, the first semiconductor die SD1, the second semiconductor die SD2, the first wire bond WB1, the second wire bond WB2, the third wire bond WB3, a portion of the first lead L1, and a portion of the second lead L2 are encapsulated with a resin molding compound to form an encapsulant 30. Figure 7 It can be seen that a heat sink 310 can be formed on one side of the encapsulation body 30, which directly contacts another copper metal layer on the second surface S2 of the ceramic insulating core plate 11.

[0080] like Figure 8 and Figure 9 As shown, the next steps can be marking, dam barcutting, dejunk trimming, tin plating, etc., to form a surface mount power component 1, which includes a first pin LO1 and a second pin LO2 extending from the two end faces of the molding compound 30 in a gullwing shape.

[0081] Please see Figure 12 This is a cross-sectional structural diagram of a surface-mount power device according to an embodiment of the present invention, wherein the same areas, materials, and layers are still represented by the same reference numerals. Figure 12 As shown, the surface-mount power device 1 includes a substrate 10. According to an embodiment of the present invention, for example, the substrate 10 includes a ceramic insulating core 11, a first patterned metal layer 12 disposed on a first surface S1 of the ceramic insulating core 11, and a second patterned metal layer 13 disposed on a second surface S2 of the ceramic insulating core 11. The substrate 10 may be a direct copper bonding (DCB) substrate, a direct bonded copper (DBC) substrate, an active metal brazing (AMB) substrate, or a direct plated copper (DPC) substrate, but is not limited thereto.

[0082] According to an embodiment of the present invention, the first patterned metal layer 12 includes a base island region 101, a first pin region 102, and a second pin region 103. At least one first stepped feature structure LS1 and at least one second stepped feature structure LS2 are respectively disposed in the first pin region 102 and the second pin region 103. According to an embodiment of the present invention, for example, the first stepped feature structure LS1 may include a first protruding portion IR1 and a first peripheral portion PR1, wherein the first peripheral portion PR1 is lower than the first protruding portion IR1. For example, the first peripheral portion PR1 may be a partially etched U-shaped recessed region, partially surrounding the first protruding portion IR1. According to an embodiment of the present invention, the first protruding portion IR1 closer to the base island region 101 is directly connected to the U-shaped recessed first peripheral portion PR1, and is integrally formed to form the first stepped feature structure LS1.

[0083] According to an embodiment of the present invention, for example, the second stepped feature structure LS2 may include a second protruding portion IR2 and a second peripheral portion PR2, wherein the second peripheral portion PR2 is also a U-shaped recessed region that has been partially etched, partially surrounding the second protruding portion IR2. According to an embodiment of the present invention, the second protruding portion IR2 directly connected to the first patterned metal layer 12 in the base island region 101 and the U-shaped recessed second peripheral portion PR2 are integrally formed in structure to form the second stepped feature structure LS2.

[0084] According to embodiments of the present invention, for example, a first conductive material layer SP1 and a second conductive material layer SP2 are respectively disposed on the first peripheral portion PR1 of the first stepped feature structure LS1 and the second peripheral portion PR2 of the second stepped feature structure LS2. According to embodiments of the present invention, the first conductive material layer SP1 and the second conductive material layer SP2 may include, but are not limited to, solder paste or pressureless silver sintering paste.

[0085] According to an embodiment of the present invention, the surface-mount power device 1 further includes a first semiconductor die SD1, which is attached to a first patterned metal layer 12 within the base island region 101. According to an embodiment of the present invention, the first semiconductor die SD1 may be, for example, a power chip, but is not limited thereto. The type of power chip can be adjusted and varied according to actual needs. For example, the power chip may be an insulated-gate bipolar transistor (IGBT), a power MOSFET, a bipolar junction transistor (BJT), a silicon carbide (SiC) power device, a gallium nitride (GaN) power device, a high electron mobility transistor (HEMT), or a fast recovery diode (FRD).

[0086] According to an embodiment of the present invention, the surface-mount power element 1 further includes at least one first lead L1 and at least one second lead L2. According to an embodiment of the present invention, for example, the first lead L1 and the second lead L2 each have a first lead terminal LT1 and a second lead terminal LT2, which are respectively bonded to the first peripheral portion PR1 of the first stepped feature structure LS1 and the second peripheral portion PR2 of the second stepped feature structure LS2 via a first conductive material layer SP1 and a second conductive material layer SP2. For example, the first lead terminal LT1 and the second lead terminal LT2 may have a Y-shaped structure, directly contacting the first conductive material layer SP1 and the second conductive material layer SP2, respectively, and forming a strong contact after sintering.

[0087] According to an embodiment of the present invention, the first lead terminal LT1 and the second lead terminal LT2 will not directly contact the first protrusion IR1 of the first stepped feature structure LS1 and the second protrusion IR2 of the second stepped feature structure LS2.

[0088] According to an embodiment of the present invention, the surface mount power element 1 further includes at least one first bonding wire WB1 connecting the first semiconductor die SD1 and the first protrusion IR1 of the first stepped feature structure LS1. According to an embodiment of the present invention, the first bonding wire WB1 may comprise gold wire or copper wire, but is not limited thereto.

[0089] According to an embodiment of the present invention, the surface mount power device 1 further includes a molding compound 30, which covers the substrate 10, the first semiconductor die SD1, the first wire bonding WB1, a portion of the first lead L1, and a portion of the second lead L2. According to an embodiment of the present invention, the second patterned metal layer 13 of the substrate 10 can be exposed. A heat sink 310 can be formed on one side of the molding compound 30, which directly contacts the second patterned metal layer 13. The other ends of the first lead L1 and a portion of the second lead L2 extend from two opposite end faces of the molding compound 30 to form a first pin LO1 and a second pin LO2, respectively.

[0090] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A surface mount power component, characterized by Comprising: a substrate, the substrate comprising a ceramic insulating core board and a first patterned metal layer disposed on a first surface of the ceramic insulating core board, wherein the first patterned metal layer comprises a base island region and a first pin region; at least one first stepped feature disposed within the first pin region, wherein the at least one first stepped feature comprises a first raised portion and a first peripheral portion, and wherein the first peripheral portion is lower than the first raised portion; a first conductive material layer disposed on the first peripheral portion of the first stepped feature; at least one semiconductor die attached to the first patterned metal layer within the base island region; at least one first lead comprising a first lead terminal, wherein the first lead terminal is joined to the first peripheral portion of the first stepped feature through the first conductive material layer; at least one wire joining the at least one semiconductor die and the first raised portion of the first stepped feature; and a plastic encapsulation covering the substrate, the at least one first stepped feature, the at least one semiconductor die, the at least one wire, and at least partially covering the at least one first lead.

2. The surface mount power component of claim 1, wherein, The first lead terminal has a Y-shaped structure directly contacting the first conductive material layer, and the first peripheral portion is a U-shaped recessed region partially surrounding the first raised portion.

3. The surface mount power component of claim 1, wherein, The first raised portion is closer to the base island region, and the first raised portion is directly connected to the first peripheral portion, which is integrally formed in structure, constituting the at least one first stepped feature.

4. The surface mount power component of claim 1, wherein, The substrate comprises a direct copper bonding substrate, a direct copper clad laminate substrate, an active metal brazing substrate, or a direct electroplated copper substrate.

5. The surface mount power component of claim 1, wherein, The first conductive material layer comprises a solder paste or a no-pressure silver sintering paste.

6. The surface mount power component of claim 1, wherein, The first lead terminal does not directly contact the first raised portion of the first stepped feature.

7. The surface mount power component of claim 1, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, aluminum, and combinations thereof. The first patterned metal layer further comprises a second pin region.

8. The surface mount power component of claim 7, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, and aluminum. Further comprising at least one second stepped feature disposed within the second pin region, and the at least one second stepped feature comprises a second raised portion and a second peripheral portion, and the second peripheral portion is a U-shaped recessed region partially surrounding the second raised portion.

9. The surface mount power component of claim 8, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, and aluminum. The second raised portion is directly connected to the first patterned metal layer within the base island region, and the second raised portion and the second peripheral portion are integrally formed in structure, constituting the at least one second stepped feature.

10. The surface mount power component of claim 8, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, and aluminum. Further comprising a second conductive material layer disposed on the second peripheral portion of the second stepped feature, and the second conductive material layer comprises a solder paste or a no-pressure silver sintering paste.

11. The surface mount power component of claim 10, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, and aluminum. Further comprising at least one second lead, the at least one second lead comprising a second lead terminal joined to the second peripheral portion of the second stepped feature through the second conductive material layer.

12. The surface mount power component of claim 11, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, and aluminum. The second lead terminal does not directly contact the second raised portion of the second stepped feature.

13. The surface mount power component of claim 1, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, aluminum, and combinations thereof. A second patterned metal layer is disposed on a second surface of the ceramic insulating core board.

14. The surface mount power component of claim 13, wherein the first and second conductive layers are formed of a conductive material selected from the group consisting of copper, silver, gold, and aluminum. The second patterned metal layer is exposed from one side of the plastic package and directly contacts a heat sink.

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