Semiconductor structure, forming method, semiconductor device and storage system

Abstract

The invention provides a semiconductor structure, a method for forming the semiconductor structure, a semiconductor device and a storage system, and relates to the technical field of semiconductors. According to the semiconductor structure, the first conductive layer, the second conductive layer and the third conductive layer are sequentially arranged in the contact structure from outside to inside, so that the second conductive layer can be isolated from the insulating core through the third conductive layer under the condition that the insulating core is arranged in the contact structure, and direct contact between the second conductive layer and the insulating core is avoided; therefore, the oxide in the insulating core is prevented from being damaged by the fluorine residues in the second conductive layer in the heat treatment process, and the stability of the structure is enhanced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for forming a semiconductor structure, a semiconductor device, and a memory system. Background Technology

[0002] With the development of semiconductor technology, the feature size of semiconductor devices is shrinking and the integration density is increasing. The process and manufacturing technology of planar memory cells have become challenging and costly, leading to the emergence of three-dimensional semiconductor structures. Three-dimensional semiconductor structures stack memory cells in a three-dimensional manner, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure, a method for forming a semiconductor structure, a semiconductor device, and a memory system.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a stacked structure; and a contact structure penetrating at least a portion of the stacked structure, the contact structure including a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer, the second conductive layer, and the third conductive layer being disposed sequentially from the outside to the inside.

[0007] According to one embodiment of this disclosure, both the first conductive layer and the third conductive layer include a first material, and the second conductive layer includes a second material, wherein the first material is different from the second material.

[0008] According to one embodiment of this disclosure, the first material is titanium nitride.

[0009] According to one embodiment of this disclosure, the thickness of the third conductive layer is between 10 nm and 30 nm.

[0010] According to one embodiment of this disclosure, the thickness of the third conductive layer is 20 nm.

[0011] According to one embodiment of this disclosure, the contact structure further includes an insulating core, and the first conductive layer, the second conductive layer, the third conductive layer and the insulating core are arranged sequentially from the outside to the inside.

[0012] According to one embodiment of the present disclosure, the contact structure includes a first portion that extends through at least a portion of the stacked structure along a first direction. The first portion of the contact structure includes a first conductive layer, a second conductive layer, a third conductive layer, and an insulating core.

[0013] According to one embodiment of this disclosure, in a cross-section at the end of the first portion of the contact structure along the first direction, the second conductive layer is annular, and the cross-section is perpendicular to the first direction.

[0014] According to one embodiment of this disclosure, the stacked structure includes a first stacked structure and a second stacked structure. The first stacked structure includes a fourth conductive layer and a dielectric layer alternately stacked along a first direction. The fourth conductive layer includes a second material. The second stacked structure is divided into a first region and a second region. The first region of the second stacked structure includes the fourth conductive layer and the dielectric layer alternately stacked along the first direction. The second region of the second stacked structure includes the dielectric layer stacked along the first direction. The contact structure is located in the second stacked structure. A first portion of the contact structure penetrates at least a portion of the second stacked structure along the first direction. The contact structure further includes a second portion. The second portion of the contact structure connects to the fourth conductive layer of the first region of the second stacked structure along a second direction. The second portion of the contact structure extends between the fourth conductive layer and the adjacent dielectric layer in the first region of the second stacked structure.

[0015] According to one embodiment of the present disclosure, the dielectric layer of the first region of the second stacked structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer are respectively adjacent to a fourth conductive layer, and the second portion of the contact structure extends between the corresponding fourth conductive layer and the first dielectric layer.

[0016] According to one embodiment of the present disclosure, the second portion of the contact structure includes the first conductive layer, and the first conductive layer in the second portion of the contact structure extends between a corresponding fourth conductive layer and an adjacent dielectric layer.

[0017] According to one embodiment of the present disclosure, the first conductive layer in the second portion of the contact structure is connected to a corresponding fourth conductive layer along the second direction.

[0018] According to one embodiment of the present disclosure, the second part of the contact structure further includes the second conductive layer, and the second conductive layer in the second part of the contact structure is connected to a corresponding fourth conductive layer along the second direction.

[0019] According to one embodiment of this disclosure, the thickness of the first conductive layer in the second part of the contact structure is in a preset ratio to the thickness of the second conductive layer.

[0020] According to one embodiment of the present disclosure, the semiconductor structure further includes a channel structure located in the first stacked structure, the channel structure penetrating at least a portion of the first stacked structure along the first direction.

[0021] According to one embodiment of this disclosure, the first region of the second stacked structure further includes a high dielectric constant dielectric layer disposed between the fourth conductive layer and the adjacent dielectric layer, the high dielectric constant dielectric layer being connected to the first conductive layer in the second portion of the contact structure.

[0022] According to one embodiment of this disclosure, the first region of the second stacked structure further includes a fifth conductive layer disposed between the fourth conductive layer and the high dielectric constant dielectric layer, the fifth conductive layer comprising the first material, and the fifth conductive layer being connected to the first conductive layer in the second portion of the contact structure.

[0023] According to one embodiment of this disclosure, the first direction is perpendicular to the second direction.

[0024] According to another aspect of this disclosure, a semiconductor structure is provided, comprising: a stacked structure; and a contact structure penetrating at least a portion of the stacked structure, the contact structure comprising a first conductive layer, a second conductive layer, and an insulating core, wherein the first conductive layer, the second conductive layer, and the insulating core are disposed sequentially from the outside to the inside, wherein the insulating core is made of a non-oxide insulating material.

[0025] According to one embodiment of this disclosure, the insulating core is made of at least one of silicon nitride or polycrystalline silicon.

[0026] According to one embodiment of this disclosure, the first conductive layer includes a first material, and the second conductive layer includes a second material, wherein the first material is different from the second material.

[0027] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a stacked structure; forming a contact hole through the stacked structure; forming a first conductive layer in the contact hole; forming a second conductive layer on the surface of the first conductive layer in the contact hole; and forming a third conductive layer on the surface of the second conductive layer in the contact hole.

[0028] According to one embodiment of this disclosure, both the first conductive layer and the third conductive layer include a first material, and the second conductive layer includes a second material, wherein the first material is different from the second material.

[0029] According to one embodiment of this disclosure, the first material is titanium nitride.

[0030] According to one embodiment of the present disclosure, a third conductive layer is formed on the surface of the second conductive layer in the contact hole, including: forming a third conductive layer with a thickness between 10 nm and 30 nm on the surface of the second conductive layer in the contact hole.

[0031] According to one embodiment of the present disclosure, a third conductive layer with a thickness between 10 nm and 30 nm is formed on the surface of the second conductive layer in the contact hole, including: forming a third conductive layer with a thickness of 20 nm on the surface of the second conductive layer in the contact hole.

[0032] According to one embodiment of the present disclosure, the surface of the third conductive layer in the contact hole is filled with an insulating core.

[0033] According to an embodiment of the present disclosure, the stacked structure includes a first stacked structure and a second stacked structure; the contact hole includes a first portion; forming the stacked structure includes: alternately stacking a sacrificial layer and a dielectric layer along a first direction; replacing a portion of the sacrificial layer with a fourth conductive layer to form a first region of the first stacked structure and the second stacked structure; forming a contact hole through the stacked structure includes: at least penetrating a second region of the second stacked structure along the first direction to the corresponding sacrificial layer to form a first portion of the contact hole.

[0034] According to one embodiment of the present disclosure, the contact hole further includes a second portion; forming a contact hole through the stacked structure further includes: removing a corresponding sacrificial layer in the second stacked structure from the first portion of the contact hole along a second direction to form a second portion of the contact hole; forming a first conductive layer in the contact hole includes: forming a first conductive layer in the first portion and the second portion of the contact hole.

[0035] According to one embodiment of the present disclosure, forming a second conductive layer on the surface of a first conductive layer in the contact hole includes: forming a second conductive layer on the surface of the first conductive layer in a first portion and a second portion of the contact hole.

[0036] According to one embodiment of the present disclosure, forming a second conductive layer on the surface of a first conductive layer in the contact hole includes: forming a second conductive layer on the surface of the first conductive layer in a first portion of the contact hole.

[0037] According to one embodiment of the present disclosure, a third conductive layer is formed on the surface of the second conductive layer in the contact hole, including: forming the third conductive layer on the surface of the second conductive layer in the first portion of the contact hole.

[0038] According to one embodiment of the present disclosure, filling the surface of the third conductive layer in the contact hole with an insulating core includes: filling the surface of the third conductive layer with an insulating core in the first portion of the contact hole.

[0039] According to one embodiment of this disclosure, replacing a portion of the sacrificial layer with a fourth conductive layer includes: removing a portion of the sacrificial layer to form a groove in the sacrificial layer; depositing a high-dielectric-constant dielectric layer on the surface of a dielectric layer adjacent to the sacrificial layer exposed in the groove; depositing a fifth conductive layer on the surface of the high-dielectric-constant dielectric layer; and depositing the fourth conductive layer on the surface of the fifth conductive layer.

[0040] According to one embodiment of this disclosure, the method further includes: forming a channel hole by at least partially penetrating a first region of the first stacked structure and the second stacked structure along the first direction; replacing a portion of the sacrificial layer with a fourth conductive layer to form a first region of the first stacked structure and the second stacked structure, including: replacing a portion of the sacrificial layer with a fourth conductive layer from the channel hole to form a first region of the first stacked structure and the second stacked structure; the method further includes: forming a channel structure in the channel hole of the first stacked structure and forming a virtual channel structure in the channel hole of the first region of the second stacked structure.

[0041] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a stacked structure; forming a contact hole through the stacked structure; forming a first conductive layer in the contact hole; forming a second conductive layer on the surface of the first conductive layer in the contact hole; and filling the surface of the second conductive layer in the contact hole with a non-oxide insulating material.

[0042] According to another aspect of this disclosure, a semiconductor device is provided, comprising any of the semiconductor structures described above.

[0043] According to another aspect of this disclosure, a storage system is provided, including a semiconductor device as described above and a controller coupled to the semiconductor device, the controller being configured to control the semiconductor device.

[0044] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0045] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0046] Figure 1 A schematic diagram of a semiconductor structure including a virtual channel structure and a contact structure is shown according to an exemplary embodiment.

[0047] Figure 2 China Figure 1 The view along direction A towards plane BC.

[0048] Figure 3 An exemplary schematic diagram of a contact structure that generates cracks is shown.

[0049] Figure 4 A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment of the present disclosure.

[0050] Figure 5 It shows the Figure 4 A schematic diagram showing a cross-section of the semiconductor structure.

[0051] Figure 6 for Figure 5 A cross-sectional view of the first part 502 of the intermediate contact structure 404 at point D, parallel to the plane BC.

[0052] Figure 7 It is based on Figure 4 and Figure 5 This diagram illustrates a layout of a semiconductor structure.

[0053] Figure 8 according to Figure 1 An exemplary diagram illustrates a crack appearing at the junction of the contact structure and the high-speed path.

[0054] Figure 9 Show Figure 5 A schematic diagram of the connection between the intermediate contact structure and the high-speed path.

[0055] Figure 10 according to Figure 9 A schematic diagram is shown showing the second part of the contact structure extending between the fourth conductive layer and the two adjacent dielectric layers.

[0056] Figure 11 A schematic diagram of the second part of another contact structure is shown.

[0057] Figure 12 Show Figure 11 A schematic diagram of the connection between the intermediate contact structure and the high-speed path.

[0058] Figure 13A according to Figure 1 and Figure 8 An embodiment of a material layer between a fourth conductive layer and its adjacent dielectric layer is shown.

[0059] Figure 13B according to Figure 13A An exemplary diagram illustrates a crack appearing at the junction of the contact structure and the high-speed path.

[0060] Figure 14 It is based on Figure 9 and Figure 13A , Figure 13B The diagram shown illustrates the junction of the contact structure with another high-speed path.

[0061] Figure 15 It is based on Figures 11 to 13B A schematic diagram of another contact structure at the junction with the high-speed path is shown.

[0062] Figure 16 A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment of the present disclosure.

[0063] Figure 17 A flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown.

[0064] Figure 18 It shows Figure 17 The step S1710 shown is a schematic diagram of the processing procedure in one embodiment.

[0065] Figure 19 It shows Figure 17 The step S1710 shown is a schematic diagram of the processing procedure in another embodiment.

[0066] Figure 20 according to Figure 17 A flowchart illustrating another method for forming the semiconductor structure in an embodiment of this disclosure is shown.

[0067] Figure 21 Show Figure 17 The steps S1702 and S1704 shown are schematic diagrams of the processing procedure in one embodiment.

[0068] Figure 22 According to Figure 9 A method for forming a contact structure is shown.

[0069] Figure 23 According to Figure 11 Another method for forming a contact structure is shown.

[0070] Figure 24 Show Figure 21 The step S2104 shown is a schematic diagram of the processing procedure in one embodiment.

[0071] Figure 25 An embodiment of this disclosure illustrates a method for forming a channel structure.

[0072] Figure 26 A schematic cross-sectional view of a semiconductor structure after the formation of a contact hole is shown according to an exemplary embodiment.

[0073] Figure 27A according to Figure 22 A schematic cross-sectional view of a semiconductor structure after the formation of a first conductive layer in a contact hole is shown.

[0074] Figure 27B according to Figure 23 A schematic cross-sectional view of a semiconductor structure after the formation of a first conductive layer in a contact hole is shown.

[0075] Figure 28 according to Figure 22 and Figure 27A A schematic cross-sectional view of a semiconductor structure after a second conductive layer is formed on the surface of a first conductive layer in a contact hole is shown.

[0076] Figure 29 according to Figure 22 , Figure 27A and Figure 28 A schematic cross-sectional view of a semiconductor structure is shown after a third conductive layer is formed on the surface of the second conductive layer in a contact hole.

[0077] Figure 30 according to Figure 22 , Figure 27A , Figure 28 and Figure 19 A schematic cross-sectional view of a semiconductor structure after filling the contact hole with an insulating core is shown.

[0078] Figure 31 according to Figure 30 A schematic cross-sectional view of a semiconductor structure after chemical mechanical polishing of the surface following filling of the contact hole with an insulating core is shown.

[0079] Figure 32 according to Figure 31 A schematic cross-sectional view of a semiconductor structure after undergoing further surface chemical mechanical polishing is shown.

[0080] Figure 33 A flowchart of another method for forming a semiconductor structure according to an embodiment of this disclosure is shown.

[0081] Figure 34 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0082] Figure 35A A block diagram of a memory system is shown as an example.

[0083] Figure 35B A block diagram of another memory system is shown as an example. Detailed Implementation

[0084] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0085] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0086] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0087] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0088] In this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure whose thickness is less than the thickness of a uniform or non-uniform continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, a dielectric layer adjacent to a fourth conductive layer may include a first dielectric layer and a second dielectric layer adjacent to it on both sides of the extending plane of the fourth conductive layer.

[0089] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0090] This disclosure uses the application of three-dimensional (3D) semiconductor structures in 3D NAND flash memory as an example for illustration, but is not limited thereto.

[0091] In 3D memory devices such as 3D NAND, the semiconductor structure uses a stacked structure to provide the gate conductor of the transistor, a channel structure that runs through the stacked structure to provide the channel layer and gate layer (including the select gate and word line) of the transistor, and a contact structure that runs through the stacked structure to realize the conductive channel connecting the channel structure to the external circuit. Figure 1 A schematic diagram of a semiconductor structure including a virtual channel structure and a contact structure is shown according to an exemplary embodiment. Figure 1 As shown, the stacked structure is composed of dielectric layers 1064 stacked in planes parallel to directions B and C (BC plane). A contact structure 101 penetrates the portion where dielectric layers 1064 and 104 are alternately stacked along direction A, perpendicular to the BC plane. A virtual channel structure 108 penetrates the stacked structure along direction A. The conductive layer 1062 of the virtual channel structure 108 (word line) is electrically connected to the conductive layer 112 of the contact structure 101 through a conductive channel 110. The conductive layers of the virtual channel structure 108 are connected to the channel structure (word line). Figure 1 The conductive layers (not shown) are connected accordingly, and the conductive layers penetrating the virtual channel structure 108 serve as a "high-speed path" to realize the electrical connection between the channel structure and the contact structure.

[0092] In semiconductor structures, such as stacked structures and (virtual) channel structures, tungsten (W) is commonly used as the material for forming the conductive layer. The W conductive layer is formed by thermal decomposition or hydrogen reduction of a tungsten source containing fluorine compounds (such as tungsten hexafluoride (WF6)). During the reaction, fluorine residues, such as hydrogen fluoride (HF), are generated in the pores of the W conductive layer. During subsequent heat treatment, these fluorine residues can easily corrode the surrounding oxides or dielectric layers, leading to leakage current in the device. For example, the fluorine in the residues can replace the oxygen in the Si-O bonds of the dielectric oxide (OX, usually including silicon dioxide (SiO2)) to form new Si-F bonds. Since the bond energy of Si-F is lower than that of Si-O, the OX containing Si-F bonds is more prone to breakdown under the influence of an electric field, resulting in a decrease in hard breakdown voltage (HBV) and the occurrence of leakage current.

[0093] Figure 2 An exemplary embodiment illustrates a layout diagram of contact structures in a layout design. Figure 2 China Figure 1 A view along direction A towards plane BC, for example, could be a portion of the contact structure region of a storage block truncated along direction C. (See reference...) Figure 1 The gate line slot (GLS) 130 can isolate the gate conductive layers of adjacent memory blocks. High-speed path conductive layers 1062 can be arranged on both sides of the gate line slot 130. Figure 1 (Only one side is shown in the image). Figure 2 As shown, a contact structure 101 of a storage block is arranged between two "high-speed path" conductive layers 1062. The conductive layer 112 of the contact structure 101 can be, for example, a W layer. The contact structure 101 is filled with an OX dielectric 102 (for example, SiO2) as an insulating core, forming a W ring structure.

[0094] During the heat treatment process, the dielectric layer 104 (e.g., a nitrogen oxide NO layer) in the contact structure region and the contact structure are subjected to the compressive force 2002 caused by the thermal expansion of the "high-speed path" conductive layer 1062 (e.g., W). Under the W ring structure, the OX filled in the contact structure 101 is easily damaged by fluorine residues during the heat treatment process, resulting in cracks 124 between the W conductive layer 112 and the OX dielectric 102. Figure 3 An example of a contact structure that generates cracks is shown. Figure 3 As shown, the white gap is crack 124 that appears between the W conductive layer 112 and the OX dielectric 102. The crack between the conductive layer and the insulating core in the contact structure makes the structure more unstable, making it more difficult to resist stress changes, thus exacerbating leakage current.

[0095] Figure 4 A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment of the present disclosure. Figure 4 The semiconductor structure shown may include a stacked structure 402 and a contact structure 404. The contact structure 404 penetrates at least a portion of the stacked structure 402. The contact structure 404 may include a first conductive layer 410, a second conductive layer 412, and a third conductive layer 413 disposed sequentially from the outside in. (Refer to...) Figure 4 The stacking plane of the stacking structure 402 can be parallel to the BC plane, and the contact structure 404 can penetrate at least part of the stacking structure 402 along the A direction.

[0096] In some embodiments, the second conductive layer 412 can be the main conductive layer connecting the (gate) conductive layer, which serves as a conductive path to realize the channel structure, to the external circuit. The first conductive layer 410 and the third conductive layer 413 can serve as barrier layers isolating the second conductive layer 412 from the surrounding oxide, and can also serve as adhesive layers bonding the second conductive layer 412 to the sidewall of the contact hole. For example, the first conductive layer 410 and the third conductive layer 413 can both include a first material, and the second conductive layer 412 can include a second material, wherein the first material is different from the second material. The first material can be at least one of tantalum nitride (TaN) or titanium nitride (TiN), for example, TiN.

[0097] In some embodiments, the thickness of the third conductive layer 413 can be between 10nm and 30nm, for example, it can be 10nm, 15nm, 20nm, 25nm, 30nm, etc.

[0098] In some embodiments, the contact structure 404 may further include an insulating core 414, with the first conductive layer 410, the second conductive layer 412, the third conductive layer 413, and the insulating core 414 arranged sequentially from the outside in. Taking a columnar structure as an example, the first conductive layer 410, the second conductive layer 412, the third conductive layer 413, and the insulating core 414 may be arranged radially along the BC plane section, pointing towards the center. The insulating core 414 may be made of the same OX material as the aforementioned medium 102, for example, SiO2.

[0099] According to the semiconductor structure provided in the embodiments of this disclosure, by sequentially providing a first conductive layer, a second conductive layer, and a third conductive layer from the outside to the inside in the contact structure, the second conductive layer and the insulating core can be isolated by the third conductive layer when an insulating core is provided in the contact structure, thus avoiding direct contact between the second conductive layer and the insulating core. This avoids damage to the oxides in the insulating core by the fluorine residues in the second conductive layer during heat treatment, thereby enhancing the stability of the structure.

[0100] Figure 5 It shows the Figure 4 A schematic diagram showing a cross-section of the semiconductor structure. (See attached image.) Figure 5 As shown, the contact structure 404 may include a first portion 502, and the first portion 502 of the contact structure 404 may be along a first direction (e.g., Figure 4 , 5 The first portion 502 of the contact structure 404 may include a first conductive layer 410, a second conductive layer 412, a third conductive layer 413 and an insulating core 414, which penetrate at least part of the stacked structure 402 in the direction A.

[0101] In some embodiments, the second conductive layer 412 may be annular on a cross section perpendicular to the first direction at the end of the first portion 502 of the contact structure 404 along the first direction. Figure 6 according to Figure 5 An example of a ring-shaped conductive layer in a contact structure is shown. Figure 6 for Figure 5 A cross-sectional view of the first part 502 of the intermediate contact structure 404, parallel to the BC plane at point D. (Refer to...) Figure 5 and Figure 6 The first conductive layer 410, the second conductive layer 412, the third conductive layer 413, and the insulating core 414 can be arranged sequentially along the radial direction of the cross section towards the center. When the second conductive layer 412 includes W material, the annular shape of the second conductive layer 412 in the figure is the aforementioned "W ring".

[0102] In some embodiments, the contact structure 404 may further include a second portion 504 extending along a second direction (e.g., the B direction) on a plane parallel to the BC plane. The second portion 504 of the contact structure 404 may be formed together with the first portion 502. Implementations of this formation can be found in [reference needed]. Figure 22 and Figure 23 The second direction can be perpendicular to the first direction. The implementation methods for each layer in the second part 504 of the contact structure 404 can be found in [reference needed]. Figure 9 and Figure 12 .

[0103] Figure 7 It is based on Figure 4 and Figure 5 This diagram illustrates a layout of a semiconductor structure. Figure 7 An exemplary layout of a storage block in the BC plane is shown. Figure 7 In the semiconductor structure shown, the stacked structure may include a first stacked structure 702 and a second stacked structure 704. The first stacked structure 702 may include a first stacked structure along a first direction (e.g., Figure 7 The fourth conductive layer and dielectric layer (alternating stacked in the A direction) Figure 7(The fourth conductive layer and dielectric layer are not shown in the first stacked structure 702). The channel structure 7082 may be located in the first stacked structure 702 and may penetrate at least a portion of the first stacked structure 702 along the first direction (direction A).

[0104] The second stacked structure 704 can be divided into a first region 7042 and a second region 7044. (See reference...) Figure 1 and) Figure 5 The virtual channel structure 7086 may be disposed in the first region 7042 of the second stacked structure 704, and at least partially penetrates the fourth conductive layer 7064 and the dielectric layer 7062 that are alternately stacked along the first direction in the first region 7042 of the second stacked structure 704. The fourth conductive layer 7064 connected by the virtual channel structure 7086 is electrically connected to a corresponding fourth conductive layer (not shown) in the first stacked structure 702.

[0105] The second region 7044 of the second stacked structure 704 may include dielectric layers stacked along the first direction, for example, it may be a dielectric layer stacked along the first direction. Figure 1 The dielectric layers 1064 and 104 are stacked alternately. A contact structure 404 may be located in a second region 7044 of the second stacked structure 704. A first portion 502 of the contact structure 404 may penetrate at least a portion of the second region 7044 of the second stacked structure 704 along a first direction, and a second portion 504 of the contact structure 404 may extend along a second direction (e.g., along a second direction). Figure 7 (In the direction of B or the opposite direction of B) connects to the corresponding fourth conductive layer 7064 of the first region 7042 of the second stacked structure 704. After the second part 504 of the contact structure 404 is formed, it can be in the shape of a disk parallel to the BC plane, as shown in the reference. Figure 7 The position of the circular structure can be seen as a dashed line in the view along direction A.

[0106] According to thermodynamic principles, an increase in temperature intensifies the thermal motion of molecules, thereby increasing the frequency and force of collisions between molecules within an object. These collisions can overcome some intermolecular attraction, increasing the spacing between molecules and causing the object to expand in volume—a phenomenon known as expansion. Table 1 below shows the coefficients of thermal expansion for different materials based on experimental data.

[0107] Table 1

[0108]

[0109] Reference Figure 5 The second portion 504 of the contact structure 404 may be the first conductive layer 410, which may include a first material, such as TiN material, and is connected to the fourth conductive layer 7064 of the first region 7042 of the second stacked structure 704 (corresponding to...). Figure 1The "high-speed path" (in []) may include a second material, such as W material. As shown in Table 1, the thermal expansion coefficient of TiN is much larger than that of W. Therefore, during the heat treatment process, the volume changes at the second part of the contact structure and the high-speed path are different. That is, the volume expansion of the second part of the contact structure is larger, resulting in deformation due to thermal stress mismatch at the "handshake" between the second part of the contact structure and the high-speed path. This deformation here may become a path for the diffusion of fluorine residues, leading to an exacerbation of the leakage current phenomenon caused by fluorine residue damage.

[0110] Figure 8 According to Figure 1 An exemplary schematic diagram showing cracks at the junction of the contact structure and the high-speed path. Figure 1 Shown is the second stacked structure where the virtual channel structure and the contact structure are located. Similar to Figure 7 , the second stacked structure can be divided into a first region 8042 and a second region 8044 at the junction of the conductive layer penetrated by the contact structure and the virtual channel structure. As Figure 1 shown, the first region 8042 of the second stacked structure is provided with the second part of the contact structure, i.e., the conductive channel 110, and the second region 8044 of the second stacked structure is provided with the high-speed path, i.e., the conductive layer 1062 penetrated by the virtual channel structure 108. Using Figure 8 the "handshake" structure between the second part of the contact structure and the high-speed path shown, when the second part of the contact structure uses TiN material and the conductive layer 1062 uses W material, referring to Table 1 above, during the heat treatment process, the self-thermal stress F1 of the conductive layer 1062 is different from the self-thermal stress F2 of the conductive channel 110, and F1 < F2, resulting in cracks 122 at the "handshake" between the conductive channel 110 and the conductive layer 1062. These cracks 122 may become a path for the diffusion of fluorine residues, leading to an exacerbation of the leakage current phenomenon caused by fluorine residue damage. For example Figure 1 in [], 120 can be the hydrogen ions (H Figure 1 after the remaining F in the fluorine residues exacerbated by cracks 122 and cracks 124 forms new Si-F bonds). + )

[0111] Referring again to Figure 5 and Figure 7 , in Figure 5 the embodiment shown, the second part 504 of the contact structure 404 extends between the fourth conductive layer 7064 and the adjacent dielectric layer 7062 in the first region 7042 of the second stacked structure. Figure 9 Shown Figure 5 the schematic diagram of the junction of the contact structure and the high-speed path in []. As Figure 9As shown, the second portion 504 of the contact structure 404 can be the first conductive layer 410 (e.g., TiN), extending between the fourth conductive layer 7064 and the adjacent dielectric layer 7062, forming a connection portion similar to a "mortise and tenon structure". The second portion 504 of the contact structure 404 can extend up to the material layer 902 between the fourth conductive layer 7064 and the adjacent dielectric layer 7062. The implementation of the material layer 902 can be found in [reference needed]. Figures 13A to 14 .

[0112] According to the semiconductor structure provided in this disclosure, when the coefficients of thermal expansion of the material of the fourth conductive layer and the material of the second part of the contact structure (such as W and TiN mentioned above) differ significantly, by setting the second part of the contact structure to extend between the fourth conductive layer and the adjacent dielectric layer, a "mortise and tenon structure" can be formed at the "handshake" point between the second part of the contact structure and the high-speed path. This avoids cracks from forming at the "handshake" point between the second part of the contact structure and the fourth conductive layer due to their different thermal stresses, thereby increasing the structural stability at the "handshake" point between the contact structure and the high-speed path and mitigating the exacerbation of leakage current caused by fluorine residue damage.

[0113] In some embodiments, since the first part of the second stacked structure can be formed by alternating stacking of a fourth conductive layer and a dielectric layer, and the fourth conductive layer can have two adjacent dielectric layers, the second part of the contact structure can be configured to extend between the fourth conductive layer and the two adjacent dielectric layers. Figure 10 according to Figure 9 A schematic diagram shows the second portion of the contact structure extending between the fourth conductive layer and the two adjacent dielectric layers. (See diagram.) Figure 10 As shown, the dielectric layer 7062 of the first region 7042 of the second stacked structure 704 may include a first dielectric layer 70622 and a second dielectric layer 70624. The first dielectric layer 70622 and the second dielectric layer 70624 are respectively adjacent to the fourth conductive layer 7064. The second part 504 of the contact structure extends between the corresponding fourth conductive layer 7064 and the first dielectric layer 70622, and extends between the corresponding fourth conductive layer 7064 and the second dielectric layer 70624.

[0114] In some embodiments, refer to Figure 5 , Figure 9 and Figure 10 The second part 504 of the contact structure 404 includes a first conductive layer 410. The first conductive layer 410 in the second part 504 of the contact structure 404 extends between the corresponding fourth conductive layer 7064 and the adjacent dielectric layer 7062. The first conductive layer 410 in the second part 504 of the second contact structure 404 is connected to the corresponding fourth conductive layer 7064 along the second direction.

[0115] In other embodiments, the second portion of the contact structure may include a first conductive layer and a second conductive layer. Figure 11 A schematic diagram of the second part of another contact structure is shown. (See diagram below.) Figure 11 As shown, the second part 504' of the contact structure may include a first conductive layer 410' and a second conductive layer 412', and the second conductive layer 412' in the second part of the contact structure is connected to the corresponding fourth conductive layer 7064 along the second direction. Figure 11 The first conductive layer 410', the second conductive layer 412', the third conductive layer 413', and the insulating core 414' of the first part 502' of the contact structure in the middle Figure 5 The first conductive layer 410, the second conductive layer 412, the third conductive layer 413, and the insulating core 414 of the first part 502 of the contact structure are respectively corresponding, and will not be described in detail here.

[0116] Figure 12 Show Figure 11 A schematic diagram of the junction between the intermediate contact structure and the high-speed path. (See diagram below.) Figure 12 As shown, the first conductive layer 410' (e.g., TiN can be used) of the second part 504' of the contact structure extends between the fourth conductive layer 7064 and the adjacent dielectric layer 7062. The second conductive layer 412' in the second part of the contact structure is connected to the corresponding fourth conductive layer 7064 along the second direction. The "handshake" between the second part 504' of the contact structure and the fourth conductive layer 7064 forms a kind of "mortise and tenon structure".

[0117] In some embodiments, the thickness of the first conductive layer 410' and the thickness of the second conductive layer 412' in the second part 504' of the contact structure can be in a preset ratio. The size of this ratio can be set according to the relationship between the thermal expansion coefficients of the materials of the first conductive layer 410' and the second conductive layer 412', so as to balance the difference in volume expansion of the two materials during the heat treatment process.

[0118] According to the semiconductor structure provided in the embodiments of this disclosure, by providing a first conductive layer and a second conductive layer in the second part of the contact structure, extending the first conductive layer between the fourth conductive layer and the adjacent dielectric layer, and connecting the second conductive layer with the fourth conductive layer, the difference in structural changes between the contact structure and the fourth conductive layer caused by the different thermal stresses of different materials during the heat treatment process can be balanced by adjusting the thickness of the first conductive layer and the second conductive layer in the second part of the contact structure. This increases the structural stability of the contact structure at the "handshake" point with the high-speed path and reduces the aggravation of leakage current caused by fluorine residue damage.

[0119] In some embodiments, a material layer that serves as a barrier may also be provided between the fourth conductive layer of the stacked structure and its adjacent dielectric layer. Figure 13A according to Figure 1 and Figure 8 An embodiment of a material layer between a fourth conductive layer and its adjacent dielectric layer is shown. Figure 13A and Figure 8 In contrast, the difference lies in the fact that a high dielectric constant (HiK) dielectric layer 1302 and a fifth conductive layer 1304 may be provided between the conductive layer 1062 (corresponding to the fourth conductive layer) through which the virtual channel structure 108 penetrates and its adjacent dielectric layer 1064. The fifth conductive layer 1304 may include a first material. Both the high dielectric constant dielectric layer 1302 and the fifth conductive layer 1304 are connected to the second part of the contact structure, namely the conductive channel 110.

[0120] Taking the high dielectric constant dielectric layer 1302 made of alumina (Al2O3) and the fifth conductive layer made of TiN as an example, when the conductive channel 110 is made of TiN and the conductive layer 1062 is made of W, referring again to Table 1 above, since the coefficient of thermal expansion of TiN is much greater than that of W and the conductive layer 1062 is much thicker than the high dielectric constant dielectric layer 1302, even though the coefficient of thermal expansion of TiN is not much different from that of Al2O3 in the high dielectric constant dielectric layer 1302, the thermal stress F1' experienced by the conductive layer 1062 in the second region 8044 during heat treatment is different from the thermal stress F2' experienced by the conductive channel 110 in the first region 8042, and F1' <F2'。

[0121] Figure 13B according to Figure 13A An exemplary diagram illustrates a crack appearing at the junction of the contact structure and the high-speed path. (Refer to...) Figure 13B During the heat treatment process, the thermal stress F1' of the conductive layer 1062 in the second region 8044 is less than the thermal stress F2' of the conductive channel 110 in the first region 8042. This results in a crack 122' at the "handshake" point between the conductive channel 110 and the conductive layer 1062. The crack 122' may become a path for the diffusion of fluorine residues, thereby exacerbating the leakage current phenomenon caused by fluorine residue damage.

[0122] Figure 14 It is based on Figure 9 and Figure 13A , Figure 13B The diagram shown illustrates the junction of the contact structure with another high-speed path. Figure 14 The intermediate contact structure can be adopted Figure 9 Implementation methods of the contact structure, Figure 14 Medium and high-speed pathways can be adopted Figure 13A , Figure 13B Implementation methods for medium- and high-speed pathways. For example... Figure 14As shown, the second portion 504 of the contact structure 404 can be a first conductive layer 410 (e.g., TiN), extending between the fourth conductive layer 7064 and the adjacent dielectric layer 7062. A high-dielectric-constant dielectric layer 1302 and a fifth conductive layer 1304 may also be provided between the fourth conductive layer 7064 and the adjacent dielectric layer 7062. The fifth conductive layer 1304 can be disposed between the fourth conductive layer 7064 and the high-dielectric-constant dielectric layer 1302, and the high-dielectric-constant dielectric layer 1302 is connected to the first conductive layer 410 in the second portion of the contact structure.

[0123] According to the semiconductor structure provided in this disclosure, when the coefficients of thermal expansion of the material of the fourth conductive layer (e.g., W as described above) and the material of the second part of the contact structure (e.g., TiN as described above) differ significantly, by setting the second part of the contact structure to extend between the fourth conductive layer and the adjacent dielectric layer, and to be in contact with a high dielectric constant dielectric layer (e.g., Al2O3) between the adjacent dielectric layers, and with the coefficients of thermal expansion of the material of the second part of the contact structure being close to those of the high dielectric constant dielectric layer, a "mortise and tenon structure" can be formed at the "handshake" point between the second part of the contact structure and the high-speed path. This avoids cracks from forming at the "handshake" point between the second part of the contact structure and the fourth conductive layer due to their different thermal stresses, thereby increasing the structural stability at the "handshake" point between the contact structure and the high-speed path and mitigating the exacerbation of leakage current caused by fluorine residue damage.

[0124] Figure 15 It is based on Figures 11 to 13B A schematic diagram of another contact structure at the junction with the high-speed path is shown. Figure 15 The intermediate contact structure can be adopted Figure 11 , Figure 12 Implementation methods of the contact structure, Figure 15 Medium and high-speed pathways can be adopted Figure 13A , Figure 13B Implementation methods for medium- and high-speed pathways. For example... Figure 15 As shown, the second part 504' of the contact structure may include a first conductive layer 410' and a second conductive layer 412'. The second conductive layer 412' in the second part of the contact structure is connected to the fifth conductive layer 1304 outside the corresponding fourth conductive layer 7064 along the second direction. The first conductive layer 410' in the second part of the contact structure extends along the second direction between the fourth conductive layer 7064 and the adjacent dielectric layer 7062, until it is connected to the high dielectric constant dielectric layer 1302.

[0125] According to the semiconductor structure provided in the embodiments of this disclosure, by providing a first conductive layer and a second conductive layer in the second part of the contact structure, extending the first conductive layer between the fourth conductive layer and the adjacent dielectric layer and connecting it with the high dielectric constant dielectric layer between the adjacent dielectric layers, and connecting the second conductive layer with the fourth conductive layer, the difference in structural changes between the contact structure and the fourth conductive layer caused by the different thermal stresses of different materials during the heat treatment process can be balanced by adjusting the thickness of the first conductive layer and the second conductive layer in the second part of the contact structure. This increases the structural stability of the contact structure at the "handshake" point with the high-speed path and reduces the aggravation of leakage current caused by fluorine residue damage.

[0126] Figure 16 A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment of the present disclosure. Figure 16 and Figure 4 (and Figure 5 The difference in semiconductor structures lies in the fact that the conductive layer and insulating core included in the part of the contact structure that penetrates the stacked structure are different. Figure 16 As shown, the semiconductor structure may include a stacked structure 1602 and a contact structure 1604 penetrating at least a portion of the stacked structure 1602. The contact structure 1604 includes a first conductive layer 16042, a second conductive layer 16044, and an insulating core 16046, which are sequentially arranged from the outside to the inside. The insulating core is made of a non-oxide insulating material. (Refer to...) Figure 16 The stacking plane of the stacking structure 1602 can be parallel to the BC plane, and the contact structure 1604 can penetrate at least part of the stacking structure 1602 along the A direction.

[0127] In some embodiments, the second conductive layer 16044 can be the main conductive layer connecting the (gate) conductive layer, which serves as a conductive path to realize the channel structure, to the external circuit. The first conductive layer 16042 can serve as a barrier layer isolating the second conductive layer 16044 from the surrounding oxide, and can also serve as an adhesive layer bonding the second conductive layer 16044 to the sidewall of the contact hole. For example, the first conductive layer 16042 may include a first material, and the second conductive layer 412 may include a second material, wherein the first material is different from the second material. The first material may be at least one of tantalum nitride (TaN) or titanium nitride (TiN), for example, TiN.

[0128] In some embodiments, the material of the insulating core 16046 may be at least one of silicon nitride or polycrystalline silicon.

[0129] According to the semiconductor structure provided in this disclosure, by sequentially providing a first conductive layer, a second conductive layer, and an insulating core of non-oxide insulating material from the outside to the inside in the contact structure, damage to the insulating core by fluorine residues in the second conductive layer can be avoided when the second conductive layer is made of W material, thereby enhancing the stability of the structure.

[0130] Figure 17 A flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown. Figure 17 Method 170 in the middle may include, for example, forming Figure 4 The overall steps of the semiconductor structure are shown. (Refer to...) Figure 17 The method 170 provided in this embodiment may include the following steps S1702 to S1710.

[0131] Step S1702: Form a stacked structure.

[0132] In some embodiments, a multilayer thin film deposition technique can be used to deposit a silicon oxide (i.e., the aforementioned OX material) layer onto a silicon nitride (e.g., Si3N4 in Table 1, corresponding to...) layer. Figure 1 The dielectric layers (104) are stacked alternately to form the initial stacked structure. The silicon oxide layer serves as an isolation layer; the silicon nitride layer serves as a sacrificial layer for subsequent replacement with gate conductive structures such as word lines, and will be replaced by a conductive metal (e.g., the W material mentioned above) in subsequent processes to form the final stacked structure. The process for replacing silicon nitride can involve etching away the silicon nitride layer with phosphoric acid, and then filling the voids with a conductive metal material.

[0133] In other embodiments, a multilayer thin-film deposition technique can be used to deposit a silicon oxide (i.e., the aforementioned OX material) layer onto a polycrystalline silicon (e.g., Poly in Table 1, corresponding to...) layer. Figure 1 The dielectric layer 104) is stacked alternately.

[0134] In the embodiments disclosed herein, the scheme of alternating stacking of silicon oxide layer and silicon nitride layer is used as an example for illustration, but it is not limited thereto.

[0135] Step S1704: A contact hole is formed through the stacked structure.

[0136] In some embodiments, contact holes can be formed in the region where the contact structure target of the stacked structure is located (e.g., the second region 7044 corresponding to the second stacked structure 704) by using photolithography, etching processes to pattern and etch sequentially the upper surface layer of the initial stacked structure (along the A direction or the opposite direction of the A direction) and the underlying silicon oxide-silicon nitride layer, etc. For example, a photolithography process can be performed to pattern the opening of the contact hole using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) can be performed to penetrate the silicon oxide-silicon nitride layer to stop at the designated silicon nitride layer.

[0137] In some embodiments, before forming contact holes, channel structures 7082 and virtual channel structures 7086 corresponding to the electrical connections of each gate conductive layer (e.g., word line layer) can be formed in the core region of the stacked structure (corresponding to the first stacked structure 702) and around the region where the contact structure target is located (corresponding to the first region 7042 of the second stacked structure 704). When forming channel structures 7082 and virtual channel structures 7086, the gate conductive structure has already partially replaced the corresponding sacrificial layer. Therefore, when passing through the silicon oxide-silicon nitride layer to form contact holes, the connection can stop at the corresponding word line layer.

[0138] In some embodiments, a contact hole comprising a first portion extending through at least a portion of the stacked structure along the A direction and a second portion extending in the BC plane can be formed using the SCT (Use Stair Step (SS) Etch Process to accurately place a Contact Hole on each WL) process. Specific embodiments can be found in [reference needed]. Figure 21 .

[0139] Step S1706: A first conductive layer is formed in the contact hole.

[0140] In some embodiments, a first material thin film may be deposited in the contact hole to form a first conductive layer. Implementation of the first material can be found in [reference needed]. Figure 4 .

[0141] Step S1708: A second conductive layer is formed on the surface of the first conductive layer in the contact hole.

[0142] In some embodiments, a second material film may be deposited on the surface of the first material film in the contact hole to form a second conductive layer. Implementation of the second material can be found in [reference needed]. Figure 4 .

[0143] Step S1710: A third conductive layer is formed on the surface of the second conductive layer in the contact hole.

[0144] In some embodiments, a first material film may be deposited on the surface of the second material film in the contact hole to form a third conductive layer. An embodiment of the thickness of the deposited first material film can be found in [reference needed]. Figure 18 and Figure 19 .

[0145] Figure 18 It shows Figure 17 The step S1710 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 18 As shown in the present embodiment, step S1710 may further include step S1802.

[0146] Step S1802: A titanium nitride layer with a thickness between 10 nm and 30 nm is formed on the surface of the second conductive layer in the contact hole.

[0147] In some embodiments, a titanium nitride film with a thickness between 10 nm and 30 nm may be deposited on the surface of the second material film in the contact hole to form a third conductive layer.

[0148] Figure 19 It shows Figure 17 The step S1710 shown is a schematic diagram of the processing procedure in another embodiment. (See diagram below.) Figure 19 As shown in the present embodiment, step S1710 may further include step S1902.

[0149] Step S1902: A titanium nitride layer with a thickness of 20 nm is formed on the surface of the second conductive layer in the contact hole.

[0150] In some embodiments, a titanium nitride film with a thickness of 20 nm may be deposited on the surface of the second material film in the contact hole to form a third conductive layer.

[0151] According to the method provided in the embodiments of this disclosure, after forming a first conductive layer and a second conductive layer in the contact hole, a third conductive layer of a certain thickness is formed on the surface of the second conductive layer. In the case of an insulating core in the contact structure, the second conductive layer and the insulating core are isolated by the third conductive layer, avoiding direct contact between the second conductive layer and the insulating core. This avoids damage to the oxides in the insulating core by the fluorine residues in the second conductive layer during the heat treatment process, thereby enhancing the stability of the structure.

[0152] Figure 20 according to Figure 17 A flowchart illustrating another method for forming the semiconductor structure in an embodiment of this disclosure is shown. Figure 20 Method 200 and Figure 17 The difference in method 170 includes the step of forming an insulating core on the surface of the third conductive layer in the contact hole. (See reference) Figure 20 The method 200 provided in this embodiment may include the following steps S2002 to S2012.

[0153] Step S2002: Form a stacked structure.

[0154] Step S2004: A contact hole is formed through the stacked structure.

[0155] Step S2006: A first conductive layer is formed in the contact hole.

[0156] Step S2008: A second conductive layer is formed on the surface of the first conductive layer in the contact hole.

[0157] Step S2010: A third conductive layer is formed on the surface of the second conductive layer in the contact hole. Both the first conductive layer and the third conductive layer include a first material, and the second conductive layer includes a second material. The first material is different from the second material.

[0158] The implementation methods of steps S2002 to S2010 can refer to the implementation methods of steps S1702 to S1710.

[0159] Step S2012: Fill the surface of the third conductive layer in the contact hole with an insulating core.

[0160] In some embodiments, OX may be deposited on the surface of the first material film of the third conductive layer in the contact hole to fill the insulating core.

[0161] Reference Figure 4 , Figure 5 and Figure 7 The channel structure 7082 may be disposed on the first stacked structure 702, and the virtual channel structure 7086 is correspondingly connected to the gate conductive layer of the channel structure 7082. The virtual channel structure 7086 may be disposed on the first region 7042 of the second stacked structure 704. The contact structure 404 disposed on the second region 7044 of the second stacked structure 704 may include a first portion 502 that penetrates at least a portion of the second region 7044 of the second stacked structure 704 along a first direction, and a second portion 504 that includes a corresponding fourth conductive layer 7064 connected to the first region 7042 of the second stacked structure 704 along a second direction. Therefore, when forming a contact hole, a first portion that penetrates at least a portion of the stacked structure along the A direction and a second portion that extends on the BC plane may be correspondingly formed.

[0162] Figure 21 Show Figure 17 The steps S1702 and S1704 shown are schematic diagrams of the processing procedure in one embodiment. (See diagram for reference.) Figure 21As shown in the present embodiment, step S1702 may further include steps S2102 and S2104, and step S1704 may further include steps S2106 and S2108.

[0163] Step S2102: Alternately stack sacrificial layers and dielectric layers along the first direction.

[0164] Step S2104: A portion of the sacrificial layer is replaced with a fourth conductive layer to form a first region of the first stacked structure and the second stacked structure.

[0165] For specific implementation methods of steps S2102 and S2104, please refer to step S1702.

[0166] Step S2106: At least through the second region of the second stacked structure to the corresponding sacrificial layer along the first direction to form the first portion of the contact hole.

[0167] Step S2108: Remove the corresponding sacrificial layer in the second stacked structure from the first portion of the contact hole along the second direction to form the second portion of the contact hole.

[0168] Reference Figures 26 to 28 , Figures 26 to 28 A cross-sectional schematic diagram of a semiconductor structure is shown during the process from forming a contact hole to forming a contact structure. Figures 26 to 28 The cross section shown in the figure can be, for example, Figure 7 Section E_E in [the text]. (Refer to...) Figure 14 and Figure 15 In step S2108, when removing the corresponding sacrificial layer in the second stacked structure from the first part of the contact hole along the second direction, the removal can stop at the fifth conductive layer 1304 disposed between the fourth conductive layer 7064 and the high dielectric constant dielectric layer 1302 in the second region 7044 of the second stacked structure, exposing the fifth conductive layer 1304.

[0169] In some embodiments, refer to Figure 24 as well as Figure 14 and Figure 15 In step S2108, when removing the corresponding sacrificial layer in the second stacked structure from the first portion of the contact hole along the second direction to expose the fifth conductive layer 1304, a portion of the high dielectric constant (HiK) dielectric layer 1302 may also be removed simultaneously. The resulting second portion of the contact hole extends between the fourth conductive layer 7064 and the dielectric layer 7062, so that... Figure 27A and Figure 27B During the step of forming the first conductive layer in the contact hole, the first conductive layer is extended between the fourth conductive layer 7064 and the dielectric layer 7062.

[0170] In other embodiments, reference is made to Figure 13A and Figure 13B After removing the sacrificial layer from the first portion of the contact hole to expose the fifth conductive layer and simultaneously removing a portion of the high-dielectric-constant dielectric layer 1302, a high-dielectric-constant dielectric material is deposited again in the gap between the conductive layer 1062 and the dielectric layer 1064. The high-dielectric-constant dielectric material exceeding the boundary between the first region 8042 and the second region 8044 in this deposition is then removed, thus forming... Figure 13A and Figure 13B The high dielectric constant dielectric layer 1302 in the middle.

[0171] According to the method provided in this disclosure, by skipping the steps of redepositing high dielectric constant dielectric material and partially removing it in the gap between the fourth conductive layer and the dielectric layer, the first conductive layer of the second part of the formed contact structure can extend to the space between the fourth conductive layer and the adjacent dielectric layer. A "mortise and tenon structure" can be formed at the "handshake" point between the second part of the contact structure and the high-speed path, thereby increasing the structural stability at the "handshake" point between the contact structure and the high-speed path, reducing the exacerbation of leakage current caused by fluorine residue damage, reducing the number of forming process steps, and effectively reducing process costs.

[0172] Figure 26 A schematic cross-sectional view of a semiconductor structure after the formation of contact holes is shown according to an exemplary embodiment. Figure 26 As shown, after steps S2106 and S2108, a first portion 26042 and a second portion 26044 of the contact hole can be formed. The second portion 26044 of the contact hole can be formed by rotating and removing the sacrificial layer from the bottom of the first portion 26042 of the contact hole, while the remaining sacrificial layer 2606 in its area can be retained.

[0173] Reference Figure 9 and Figure 11 The second part of the contact structure may include only the first conductive layer, or it may include both the first conductive layer and the second conductive layer. Figure 22 and Figure 23 Two methods for forming the second part of the contact structure are shown respectively.

[0174] Figure 22 According to Figure 9 A method for forming a contact structure is shown. (Reference) Figure 22 The method provided in this disclosure may include the following steps S2202 to S2208.

[0175] Step S2202: A first conductive layer is formed in the first and second portions of the contact hole.

[0176] Figure 27A according to Figure 22 A cross-sectional schematic diagram of a semiconductor structure after forming a first conductive layer in a contact hole is shown. As shown in Figure 27, the first conductive layer 2702 can be formed in step S2202.

[0177] Step S2204: A second conductive layer is formed on the surface of the first conductive layer in the first part of the contact hole.

[0178] Figure 28 according to Figure 22 and Figure 27A A schematic cross-sectional view of a semiconductor structure is shown after a second conductive layer is formed on the surface of a first conductive layer in a contact hole. (See diagram below.) Figure 28 As shown, in step S2204, a second conductive layer 2802 may be formed on the surface of the first conductive layer 2702.

[0179] Step S2206: A third conductive layer is formed on the surface of the second conductive layer in the first part of the contact hole.

[0180] Figure 29 according to Figure 22 , Figure 27A and Figure 28 A schematic cross-sectional view of a semiconductor structure is shown after a third conductive layer is formed on the surface of a second conductive layer in a contact hole. (See diagram below.) Figure 29 As shown, step S2206 can form a third conductive layer 2902 on the surface of the second conductive layer 2802.

[0181] Step S2208: In the first part of the contact hole, the surface of the third conductive layer is filled with an insulating core, the material of which is at least one of silicon nitride or polycrystalline silicon.

[0182] Figure 30 according to Figure 22 , Figure 27A , Figure 28 and Figure 19 A schematic cross-sectional view of a semiconductor structure after filling the contact hole with an insulating core is shown. (See diagram below.) Figure 30 As shown, step S2208 may deposit OX on the surface of the third conductive layer 2902 to fill the insulating core 3002.

[0183] Figure 31 according to Figure 30 A schematic cross-sectional view of a semiconductor structure after chemical mechanical polishing of the surface following filling of contact holes with insulating cores is shown. Figure 31As shown, after depositing OX on the surface of the third conductive layer 2902, the upper surface of the entire stacked structure can be chemically mechanically polished (CMP) to remove OX3102 on the upper surface and expose the third conductive layer 2902 on the upper surface.

[0184] Figure 32 according to Figure 31 A schematic cross-sectional view of a semiconductor structure after undergoing further surface chemical mechanical polishing is shown. Figure 32 As shown, the upper surface of the entire stacked structure is subjected to chemical mechanical polishing (CMP) again to remove the third conductive layer 2902 exposed on the upper surface, as well as the second conductive layer 2802 and the first conductive layer 2702 (3202) below it.

[0185] According to the method provided in the embodiments of this disclosure, a W Ring is formed as the conductive part of the contact structure, omitting the process step of forming a W plug, which effectively reduces the process cost.

[0186] Figure 23 According to Figure 11 Another method for forming a contact structure is shown. (Reference) Figure 23 The method provided in this disclosure may include the following steps S2202 to S2208.

[0187] Step S2302: A first conductive layer is formed in the first and second portions of the contact hole.

[0188] Figure 27B according to Figure 23 A schematic cross-sectional view of a semiconductor structure after a first conductive layer has been formed in a contact hole is shown. Figure 27B As shown, in step S2302, the thickness of the first conductive layer 2702' is controlled so that there are gaps in the second part of the contact hole.

[0189] Step S2304: A second conductive layer is formed on the surface of the first conductive layer in the first part and the second part of the contact hole, and the thickness of the first conductive layer in the second part of the contact structure is in a preset ratio to the thickness of the second conductive layer.

[0190] In step S2304, the second conductive layer formed in the first portion of the contact hole can be referenced. Figure 22 In the embodiment, the second conductive layer formed in the second portion of the contact hole can be referred to Figure 11 .

[0191] Step S2306: A third conductive layer is formed on the surface of the second conductive layer in the first part of the contact hole.

[0192] Step S2308: In the first part of the contact hole, the surface of the third conductive layer is filled with an insulating core, the material of which is at least one of silicon nitride or polycrystalline silicon.

[0193] The results of steps S2306 and S2308 and subsequent processes are similar. Figures 28 to 33 This will not be elaborated upon here.

[0194] Figure 24 Show Figure 21 The step S2104 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 24 As shown in the present embodiment, step S2104 may further include steps S2402 to S2408.

[0195] Step S2402: Remove a portion of the sacrificial layer to form a groove in the sacrificial layer.

[0196] In some embodiments, after forming the via, a portion of the surrounding sacrificial layer may be removed along the via to form a groove for depositing the gate conductive layer.

[0197] Step S2404: Deposit a high dielectric constant dielectric layer on the surface of the dielectric layer adjacent to the sacrificial layer exposed in the groove.

[0198] Step S2406: Deposit a fifth conductive layer on the surface of the high dielectric constant dielectric layer. The materials of the high dielectric constant dielectric layer and the fifth conductive layer can refer to the aforementioned embodiments.

[0199] In step S2408, a fourth conductive layer is deposited on the surface of the fifth conductive layer. The fourth conductive layer is the gate conductive layer in this embodiment of the present disclosure.

[0200] use Figure 24 The method shown can form Figures 13A to 13B The virtual channel structure 108 shown penetrates the conductive layer 1062 (corresponding to the fourth conductive layer) and its adjacent dielectric layer 1064, between the high dielectric constant (HiK) dielectric layer 1302 and the fifth conductive layer 1304.

[0201] Figure 25 An embodiment of this disclosure illustrates a method for forming a channel structure. (See reference...) Figure 25 The method provided in this disclosure may include the following steps S2502 to S2506.

[0202] Step S2502: Form a channel hole by at least partially penetrating the first region of the first stacked structure and the second stacked structure along the first direction.

[0203] Step S2504: A portion of the sacrificial layer is replaced with a fourth conductive layer from the via to form a first region of the first stacked structure and the second stacked structure.

[0204] Step S2506: A channel structure is formed in the channel hole of the first stacked structure, and a virtual channel structure is formed in the channel hole of the first region of the second stacked structure.

[0205] Figures 26 to 32 In the middle, the virtual channel structure 7082 can be adopted Figure 25 The method shown is used to form it.

[0206] Figure 33 A flowchart of another method for forming a semiconductor structure according to an embodiment of this disclosure is shown. Figure 33 Method 330 in the middle may include, for example, forming Figure 16 The overall steps of the semiconductor structure are shown. (Refer to...) Figure 33 The method 330 provided in this embodiment may include the following steps S3302 to S3310.

[0207] Step S3302: Form a stacked structure.

[0208] Step S3304: Form a contact hole through the stacked structure.

[0209] Step S3306: A first conductive layer is formed in the contact hole.

[0210] Step S3308: A second conductive layer is formed on the surface of the first conductive layer in the contact hole.

[0211] Step S3310: Fill the surface of the second conductive layer in the contact hole with a non-oxide insulating material.

[0212] The implementation methods of steps S3302 to S3310 can be referred to the implementation methods of steps S1702 to S1708 and step S2012, and will not be repeated here.

[0213] The semiconductor structure provided in this disclosure can be a semiconductor device, such as a memory. Figure 34 A block diagram of an exemplary system with memory is shown according to an embodiment of this disclosure. System 340 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory.

[0214] like Figure 34As shown, system 340 may include host 348 and memory system 342, the memory system 342 having one or more memories 344 and a memory controller 346. Host 348 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. Host 348 may be configured to send data to or receive data from memory 344.

[0215] In this disclosure, memory 344 can be any memory, such as non-volatile memory. Non-volatile memory can be NAND flash memory (e.g., three-dimensional (3D) NAND flash memory).

[0216] In some embodiments, memory controller 346 is coupled to memory 344 and host 348 and is configured to control memory 344. Memory controller 346 can manage data stored in memory 344 and communicate with host 348.

[0217] In some embodiments, the memory controller 346 is configured to send commands to the memory 344 to cause the memory 344 to perform the memory operation methods provided in the embodiments of this disclosure.

[0218] In some embodiments, the memory controller 346 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0219] In some embodiments, the memory controller 346 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 346 can be configured to send commands to the memory 344 to cause the memory 344 to perform operations, such as read, erase, and program operations.

[0220] The memory controller 346 can also be configured to manage various functions related to data stored or to be stored in the memory 344, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0221] In some embodiments, the memory controller 346 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 344. The memory controller 346 may also perform any other suitable functions, such as formatting the memory 344. The memory controller 346 may communicate with an external device (e.g., a host 348) according to a specific communication protocol. For example, the memory controller 346 may communicate with the external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0222] The memory controller 346 and one or more memories 344 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 342 can be implemented and packaged into different types of end electronic products.

[0223] Figure 35A A block diagram of a memory system is shown as an example. Figure 35A As shown, the memory controller 346 and a single memory 344 can be integrated into the memory card 352. The memory card 352 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 352 may also include a connector for connecting the memory card 352 to a host computer (e.g., ...). Figure 34 The memory card connector 354 is coupled to the host 348.

[0224] Figure 35B A block diagram of another memory system is shown as an example. Figure 35B As shown, the memory controller 346 and multiple memories 344 can be integrated into the SSD 356. The SSD 356 may also include components for connecting the SSD 356 to a host computer (e.g., ...). Figure 1 The SSD connector 358 is coupled to the host 348. In some embodiments, the storage capacity and / or operating speed of the SSD 356 is greater than the storage capacity and / or operating speed of the memory card 352.

[0225] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a contact structure and a stack structure. The contact structure comprises a first conductive layer, a second conductive layer and a third conductive layer, which are arranged from outside to inside. The first conductive layer and the third conductive layer comprise a first material, and the second conductive layer comprises a second material.

2. The semiconductor structure of claim 1, wherein, The first material is titanium nitride.

3. The semiconductor structure of claim 2, wherein, The thickness of the third conductive layer is between 10 nm and 30 nm.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that The thickness of the third conductive layer is 20 nm.

5. The semiconductor structure of claim 4, wherein, The contact structure further comprises an insulating core, which is arranged from outside to inside together with the first conductive layer, the second conductive layer and the third conductive layer.

6. The semiconductor structure of claim 2 or 3, wherein, The contact structure comprises a first part, which penetrates at least part of the stack structure along a first direction.

7. The semiconductor structure of claim 6, wherein, In a cross section of an end of the first part of the contact structure along the first direction, the second conductive layer is annular, and the cross section is perpendicular to the first direction.

8. The semiconductor structure of claim 7, wherein, The stack structure comprises a first stack structure and a second stack structure.

9. The semiconductor structure according to claim 7 or 8, characterized in that The first stack structure comprises fourth conductive layers and dielectric layers which are alternately stacked along the first direction. The second stack structure is divided into a first region and a second region. The first region of the second stack structure comprises the fourth conductive layers and the dielectric layers which are alternately stacked along the first direction.

10. The semiconductor structure of claim 9, wherein, The second region of the second stack structure comprises the dielectric layers which are stacked along the first direction.

11. The semiconductor structure of claim 9 or 10, wherein, The contact structure is located in the second stack structure.

12. The semiconductor structure of claim 11, wherein, The second part of the contact structure connects the fourth conductive layers of the first region of the second stack structure along a second direction.

13. The semiconductor structure of claim 11, wherein, The second part of the contact structure extends between the fourth conductive layers and the dielectric layers adjacent to the fourth conductive layers in the first region of the second stack structure.

14. The semiconductor structure of claim 13, wherein, The dielectric layers in the first region of the second stack structure comprise a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer are adjacent to the fourth conductive layers, respectively. The second part of the contact structure extends between the corresponding fourth conductive layer and the first dielectric layer. The second part of the contact structure extends between the corresponding fourth conductive layer and the second dielectric layer. The second part of the contact structure comprises the first conductive layer. The first conductive layer in the second part of the contact structure extends between the corresponding fourth conductive layer and the dielectric layer adjacent to the fourth conductive layer. The first conductive layer in the second part of the contact structure connects the corresponding fourth conductive layer along the second direction. The second part of the contact structure further comprises the second conductive layer. The second conductive layer in the second part of the contact structure connects the corresponding fourth conductive layer along the second direction. The thickness of the first conductive layer in the second part of the contact structure is in a preset ratio to the thickness of the second conductive layer.

15. The semiconductor structure of any of claims 9 to 14, wherein, The channel structure is located in the first stack structure and penetrates at least part of the first stack structure along the first direction.

16. The semiconductor structure of any of claims 9 to 15, wherein, The first region of the second stack structure further comprises a high dielectric constant dielectric layer arranged between the fourth conductive layer and the dielectric layer adjacent thereto, and the high dielectric constant dielectric layer is connected with the first conductive layer in the second part of the contact structure.

17. The semiconductor structure of claim 16, wherein, The first region of the second stack structure further comprises a fifth conductive layer arranged between the fourth conductive layer and the high dielectric constant dielectric layer, and the fifth conductive layer comprises the first material and is connected with the first conductive layer in the second part of the contact structure.

18. The semiconductor structure of any of claims 9 to 17, wherein, The first direction is perpendicular to the second direction.

19. A semiconductor structure, characterized by Comprising: a stack structure; a contact structure penetrating at least part of the stack structure, the contact structure comprising a first conductive layer, a second conductive layer and an insulating core, the first conductive layer, the second conductive layer and the insulating core being arranged in sequence from outside to inside, wherein the material of the insulating core is a non-oxide insulating material.

20. The semiconductor structure of claim 19, wherein, The material of the insulating core is at least one of silicon nitride or polysilicon.

21. The semiconductor structure of claim 19 or 20, wherein, The first conductive layer comprises a first material, and the second conductive layer comprises a second material, and the first material is different from the second material.

22. A method of forming a semiconductor structure, comprising: Comprising: forming a stack structure; forming a contact hole penetrating the stack structure; forming a first conductive layer in the contact hole; forming a second conductive layer on the surface of the first conductive layer in the contact hole; forming a third conductive layer on the surface of the second conductive layer in the contact hole.

23. The method of claim 22, wherein, The first conductive layer and the third conductive layer each comprise a first material, and the second conductive layer comprises a second material, and the first material is different from the second material.

24. The method of claim 23, wherein, The first material is titanium nitride.

25. The method of any one of claims 22-24, wherein, Forming a third conductive layer on the surface of the second conductive layer in the contact hole comprises: forming a third conductive layer with a thickness of 10nm-30nm on the surface of the second conductive layer in the contact hole.

26. The method of claim 25, wherein, Forming a third conductive layer on the surface of the second conductive layer in the contact hole comprises: forming a third conductive layer with a thickness of 20nm on the surface of the second conductive layer in the contact hole.

27. The method of claim 23 or 24, wherein, Further comprising: filling an insulating core on the surface of the third conductive layer in the contact hole.

28. The method of claim 27, wherein, The stack structure comprises a first stack structure and a second stack structure, and the contact hole comprises a first part; forming a stack structure comprises: alternately stacking a sacrificial layer and a dielectric layer along a first direction; replacing part of the sacrificial layer with a fourth conductive layer to form a first region of the first stack structure and the second stack structure; forming a contact hole penetrating the stack structure comprises: forming a first part of the contact hole by penetrating at least the second region of the second stack structure to the corresponding sacrificial layer along the first direction.

29. The method of claim 28, wherein, The contact hole further comprises a second part; forming a contact hole penetrating the stack structure further comprises: forming a second part of the contact hole by removing the corresponding sacrificial layer in the second stack structure along a second direction from the first part of the contact hole; forming a first conductive layer in the contact hole comprises: forming a first conductive layer in the first and second portions of the contact hole.

30. The method of claim 29, wherein, forming a second conductive layer on a surface of the first conductive layer in the contact hole, including: forming a second conductive layer on a surface of the first conductive layer in the first and second portions of the contact hole.

31. The method of claim 29, wherein, forming a second conductive layer on a surface of the first conductive layer in the first and second portions of the contact hole.

32. The method of claim 30 or 31, wherein, forming a second conductive layer on a surface of the first conductive layer in the first and second portions of the contact hole. forming a third conductive layer on a surface of the second conductive layer in the contact hole, including:

33. The method of claim 32, wherein, forming a third conductive layer on a surface of the second conductive layer in the first portion of the contact hole. filling an insulating core on a surface of the third conductive layer in the contact hole, including:

34. The method of any one of claims 28-33, wherein, filling an insulating core on a surface of the third conductive layer in the first portion of the contact hole. replacing a portion of the sacrificial layer with a fourth conductive layer, including: removing a portion of the sacrificial layer to form a recess in the sacrificial layer; depositing a high-k dielectric layer on a surface of the dielectric layer exposed in the recess adjacent to the sacrificial layer; depositing a fifth conductive layer on a surface of the high-k dielectric layer; 35. The method of any one of claims 28-34, wherein, depositing the fourth conductive layer on a surface of the fifth conductive layer. further comprising: forming a channel hole at least partially through the first and second stack structures in the first direction; replacing a portion of the sacrificial layer with a fourth conductive layer to form a first region of the first stack structure and the second stack structure, including: replacing a portion of the sacrificial layer with a fourth conductive layer from the channel hole to form a first region of the first stack structure and the second stack structure; the method further comprising:

36. The method of any one of claims 29-33, wherein, forming a channel structure in the channel hole of the first stack structure and a dummy channel structure in the first region channel hole of the second stack structure.

37. A method of forming a semiconductor structure, comprising: the first direction is perpendicular to the second direction. including: forming a stack structure; forming a contact hole through the stack structure; forming a first conductive layer in the contact hole; forming a second conductive layer on a surface of the first conductive layer in the contact hole; 38. A semiconductor device, comprising: filling a non-oxide insulating material on a surface of the second conductive layer in the contact hole.

39. A storage system, comprising: including the semiconductor structure of any one of claims 1-18 or 19-21. including the semiconductor device of claim 38 and a controller coupled to the semiconductor device, the controller configured to control the semiconductor device.

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