Packaging structure, packaging method and electronic equipment
By forming redistribution layers on both sides of the chip and arranging multiple second chips on the packaging substrate, the fan-out technology solves the problem of excessive packaging area, achieving a smaller packaging area and higher chip integration, thereby improving I/O density and packaging flexibility.
Patent Information
- Application Number
- CN202511362830.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2025-12-30
AI Technical Summary
As chip integration and performance requirements increase, more and more chips are integrated into the packaging structure, leading to a continuous increase in the area of silicon interposer boards, which increases the difficulty and cost of subsequent manufacturing processes.
Fan-out technology is used to replace silicon interposer interconnect bridging technology. By forming redistribution layers on both sides of the first chip and arranging multiple second chips on the packaging substrate, chip interconnection is achieved, reducing the packaging area.
While meeting the interconnection requirements of chip packaging, it reduces the package area, increases chip integration, improves I/O density, and enhances packaging flexibility.
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Figure CN121237777A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of semiconductor packaging, and in particular to a packaging structure, a packaging method and an electronic device. BACKGROUND
[0002] With the increasing requirements for chip integration and performance, more and more chips are integrated in the packaging structure, and the size and function requirements for the silicon interposer are also increasing, and the area of the silicon interposer is increasing, which leads to the increasing of the packaging area, and increases the difficulty and cost of subsequent process manufacturing. Therefore, how to provide a packaging structure to reduce the packaging area has become a technical problem that technicians in the field need to solve. SUMMARY
[0003] Therefore, embodiments of the present application provide a packaging structure, a packaging method and an electronic device, which can reduce the packaging area.
[0004] To achieve the above object, embodiments of the present application provide the following technical solutions.
[0005] In a first aspect, embodiments of the present application provide a packaging structure, which comprises:
[0006] a packaging substrate;
[0007] a first chip module connected to the packaging substrate, the first chip module comprising at least a first chip, a first redistribution layer fanned out from a first surface of the first chip, and a second redistribution layer fanned out from a second surface of the first chip, the first surface being opposite to the second surface; wherein the first chip is connected to the packaging substrate through the second redistribution layer;
[0008] a plurality of second chips arranged above the first redistribution layer, the second chips being interconnected with the first chip through the first redistribution layer.
[0009] Optionally, the plurality of second chips are arranged above the first redistribution layer, and the plurality of second chips comprise: edge-side second chips located at the edge side, and at least one second chip between the edge-side second chips.
[0010] The edge-side second chips extend beyond the first chip module.
[0011] Optionally, the edge-side second chips comprise: a signal area and a non-signal area, and the at least one second chip between the edge-side second chips comprises: a signal area and a non-signal area.
[0012] The signal area of the edge-side second chip and the signal area of at least one second chip between the edge-side second chips are connected to the first redistribution layer through the first connecting structure, the signal areas are interconnected through the first redistribution layer and connected to the packaging substrate through the first redistribution layer, and the non-signal area of at least one second chip between the edge-side second chips is connected to the first redistribution layer through the first connecting structure and connected to the packaging substrate through the first redistribution layer.
[0013] Optionally, the non-signal area of the edge-side second chip is located outside the range of the first chip module, and the non-signal area of the edge-side second chip is connected to the packaging substrate through the second connecting structure.
[0014] Optionally, the packaging method further comprises:
[0015] The first filling layer is located between the second chip and the first redistribution layer, and the first connecting structure for connecting the signal area and the first redistribution layer is arranged in the first filling layer.
[0016] Optionally, the packaging method further comprises:
[0017] The second filling layer fills the gap between the non-signal area of the edge-side second chip and the packaging substrate, and the second connecting structure for connecting the non-signal area of the edge-side second chip and the packaging substrate is arranged in the second filling layer.
[0018] Optionally, the packaging method further comprises:
[0019] The plastic encapsulation layer is located between the first redistribution layer and the second redistribution layer and on both sides of the first chip module.
[0020] The through hole structure is arranged in the first chip and the plastic encapsulation layer, and the first redistribution layer and the second redistribution layer are interconnected through the through hole structure in the first chip and / or the through hole structure in the plastic encapsulation layer.
[0021] Optionally, the first connecting structure is a solder ball, and the second connecting structure is a bump structure.
[0022] In a second aspect, the embodiments of the present application provide a packaging method, which comprises:
[0023] Providing a first chip;
[0024] Fan-out processing the first chip to form a first chip module, the first chip module comprising the first chip, a first redistribution layer fan-out from a first surface of the first chip, and a second redistribution layer fan-out from a second surface of the first chip, the first surface being opposite to the second surface;
[0025] arranging a plurality of second chips above the first redistribution layer, and connecting the second chips and the first chip through the first redistribution layer;
[0026] connecting the second redistribution layer and the package substrate.
[0027] In a third aspect, an electronic device is provided, and the electronic device comprises the package structure.
[0028] It can be seen that the package structure provided by the embodiments of the present application comprises a first chip module connected to a package substrate, the first chip module comprising at least a first chip, a first redistribution layer fanned out from a first surface of the first chip, a second redistribution layer fanned out from a second surface of the first chip, wherein the first surface is opposite to the second surface, and a plurality of second chips arranged above the first redistribution layer; and further, the first chip can be connected to the package substrate through the second redistribution layer, and the second chips and the first chip can be interconnected through the first redistribution layer. That is, the package structure provided by the embodiments of the present application can process the first chip in a plurality of chips (for example, the first chip and the plurality of second chips) which need to be packaged and interconnected through a fan-out technology, form the first redistribution layer by fanning out from the first surface of the first chip, and form the second redistribution layer by fanning out from the second surface of the first chip, so that the first chip can realize the role of switching while realizing its own function, that is, the first chip and the package substrate are connected through the second redistribution layer, and the plurality of second chips arranged above the first redistribution layer and the first chip are interconnected through the first redistribution layer, thereby reducing the packaging area and increasing the integration of the chips while meeting the demand of chip packaging and interconnection. BRIEF DESCRIPTION OF DRAWINGS
[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.
[0030] Figure 1 is an example diagram of a package structure provided by the embodiments of the present application;
[0031] Figure 2 is a flowchart of a packaging method provided by the embodiments of the present application;
[0032] Figures 3 to 8 is an example diagram of a package structure corresponding to each step in the packaging method provided by the embodiments of the present application. DETAILED DESCRIPTION
[0033] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.
[0034] In the field of modern electronic manufacturing, chip packaging is a crucial step. Chip packaging is to package a semiconductor die, that is, an integrated circuit manufactured on a silicon wafer, in a protective shell to facilitate circuit connection, heat dissipation, and physical installation in electronic devices.
[0035] As the chip integration is getting higher and higher, and the process node is almost reaching the process limit, how to further improve the performance of the chip has become a problem to be solved. At present, an existing advanced packaging scheme is to use a silicon interposer interconnection bridge technology to flexibly combine different types and different processes of chip IPs (Intellectual Property) together to realize heterogeneous structure packaging. The silicon interposer in the bridge interconnection is a passive device and plays a role in interconnection. The chips interconnected by the silicon interposer can be chips of different types and different processes, or can be a chip set interconnected by TSV (Through Silicon Via) technology.
[0036] However, as the requirements for chip integration and performance are getting higher and higher, more and more chips are integrated in the packaging structure, and the size requirement for the silicon interposer is getting higher and higher, which leads to the continuous increase of the area of the silicon interposer, thereby increasing the difficulty and cost of subsequent process manufacturing.
[0037] Therefore, the embodiments of the present application provide a packaging structure which can reduce the packaging area and increase the integration of chips. Figure 1 is an example of a packaging structure shown by the embodiments of the present application, referring to Figure 1 The packaging structure can include: a packaging substrate 100; a first chip module 200 connected to the packaging substrate, the first chip module 200 including at least a first chip 210, a first redistribution layer 211 fanned out from a first surface of the first chip, and a second redistribution layer 212 fanned out from a second surface of the first chip, the first surface being opposite to the second surface; wherein the first chip 210 is connected to the packaging substrate 100 through the second redistribution layer 212; a plurality of second chips 220 arranged above the first redistribution layer 211, the second chips 220 being interconnected with the first chip 210 through the first redistribution layer 211.
[0038] The packaging substrate 100 can serve as a carrier for semiconductor chip packaging, providing electrical connection, support, protection, heat dissipation, and other functions for the chip.
[0039] Fan-out is a semiconductor manufacturing technique that redistributes chip pins based on redistribution layer technology, with the array area bounded by the new pins being larger than the original chip area. Fan-out technology can increase the number of external connection points, thereby improving I / O (input / output) density and packaging flexibility. Therefore, the embodiments of this application use fan-out technology to replace silicon interposer interconnection bridging technology, which can effectively reduce the package area and increase the chip integration while realizing the interconnection of multiple different chips.
[0040] In this embodiment of the application, the first chip module 200 includes at least a first chip 210, a first rewiring layer 211 fanned out from a first side of the first chip, and a second rewiring layer 212 fanned out from a second side of the first chip, wherein the first side and the second side are opposite to each other.
[0041] In an optional embodiment, refer to Figure 1 The first surface can be the top surface of the first chip 210, and the second surface can be the bottom surface of the first chip 210. The area of the first redistribution layer 211 fanned out from the first surface of the first chip 210 is larger than the area of the first chip 210, and the area of the second redistribution layer 212 fanned out from the second surface of the first chip 210 is larger than the area of the first chip 210, thereby increasing the external connection points of the first chip 210 and improving the I / O density of the first chip 210. In this embodiment, the first chip 210 can be an active chip, which refers to an electronic chip that requires an external power supply to achieve its intended function. These chips contain active components that can actively amplify, regulate, or control signals. Using an active chip as an adapter board can achieve smaller spacing and higher I / O density, which is crucial for achieving high-bandwidth, low-latency applications.
[0042] The plurality of second chips 220 are multiple chips that need to be interconnected with the first chip 210. They can be arranged on the first wiring layer 211, and thus interconnected with the first chip 210 through the first wiring layer 211.
[0043] In an optional implementation, the plurality of second chips are arranged above the first redistribution layer, and the plurality of second chips may include: a side-side second chip located on the side, and at least one second chip between the side-side second chips; the range of the side-side second chip extends beyond the first chip module.
[0044] In an optional example, refer to Figure 1This application uses three second chips as an example for illustration. The plurality of second chips 220 may include: chip 221, chip 222 and chip 223, wherein chip 221 and chip 223 are side-side second chips located on the side, chip 222 is a second chip between two side-side second chips, and the range of side-side second chips 221 and 223 both extends beyond the first chip module 200.
[0045] Furthermore, both the side-side second chips 221 and 223 include signal regions and non-signal regions. At least one second chip 222 located between the side-side second chips includes a signal region and a non-signal region. The signal region refers to the area on the chip used for signal transmission and processing, including input / output pins for signal transmission between the chip and external devices, logic circuits for signal processing and control, etc. The non-signal region refers to the area on the chip that does not directly participate in signal transmission and processing, including wiring for providing power and ground lines to ensure that each part of the chip can obtain a stable power supply, etc. The signal regions of the side-side second chips and the signal regions of at least one second chip between the side-side second chips can be connected to the first rewiring layer through the first connection structure 231. Thus, each signal region can be interconnected through the first rewiring layer and connected to the packaging substrate through the first rewiring layer.
[0046] In this embodiment of the application, for the side-side second chip, the non-signal area of the side-side second chip is located beyond the range of the first chip module. The non-signal area of the side-side second chip (e.g., chip 221 and chip 223) is directly connected to the packaging substrate 100 through the second connection structure 232, and is directly powered by the packaging substrate 100.
[0047] For at least one second chip (e.g., chip 222) between the side second chips, including a signal area and a non-signal area, both the signal area and the non-signal area can be connected to the first redistribution layer 211 through the first connection structure 231. The signal area of at least one second chip between the side second chips can be interconnected through the first redistribution layer 211 and connected to the packaging substrate 100 through the first redistribution layer 211. The non-signal area of at least one second chip between the side second chips can be connected to the packaging substrate through the first redistribution layer 211.
[0048] In other words, whether it is the second chip on the side or at least one second chip located between the second chips on the side, the signal area is connected to the first redistribution layer through the first connection structure to achieve interconnection with the first chip and perform signal transmission and processing. For the non-signal area of at least one second chip located between the second chips on the side, the non-signal area can be connected to the first redistribution layer through the first connection structure to connect with the first chip through the first redistribution layer, and then connected to the packaging substrate for power supply through the second redistribution layer fanned out from the second side of the first chip; for the non-signal area of the second chip on the side, the non-signal area of the second chip on the side can be directly connected to the packaging substrate for power supply. Thus, the embodiments of this application can achieve chip interconnection and meet power supply requirements while making reasonable layouts and reducing the waste of space resources.
[0049] In an optional example, the first connection structure 231 can be a solder ball, and the second connection structure 232 can be a bump structure, such as a copper pillar.
[0050] In an optional implementation, the packaging structure may further include: a first filling layer 241 located between the second chip 220 and the first redistribution layer 211, wherein a first connection structure 231 is provided in the first filling layer 241 for connecting the signal area of the second chip and the first redistribution layer 211.
[0051] The first filler layer 241 can be a bottom filler adhesive, used to protect the first connection structure and chip from physical impact and wear, and reduce damage caused by mechanical stress such as vibration.
[0052] In an optional implementation, the packaging structure further includes: a second filling layer 242 that fills the gap between the non-signal area of the side-side second chip and the packaging substrate; a second connection structure 232 that connects the non-signal area of the side-side second chip and the packaging substrate 100 is located within the second filling layer 242; the non-signal area of the side-side second chip is directly connected to the packaging substrate 100 through the second connection structure 232 and is directly powered by the packaging substrate.
[0053] In an optional example, the material of the second filling layer 242 and the material of the first filling layer 241 can be the same.
[0054] Furthermore, continue to refer to Figure 1The packaging structure further includes a molding compound 250, which is located between the first redistribution layer 211 and the second redistribution layer 212, and on both sides of the first chip module 200; wherein, both the molding compound 250 and the first chip 210 are provided with through-hole structures 233, and the first redistribution layer 211 and the second redistribution layer 212 are interconnected through the through-hole structures in the first chip 210 and / or the through-hole structures in the molding compound 250.
[0055] The molding compound 250 can be used to fix and protect the first chip 210, while supporting and connecting the first rewiring layer 211 and the second rewiring layer 212 fanned out from the first chip 210. Specifically, the connection can be made through the through-hole structure 233 provided in the molding compound 250 and / or the through-hole structure in the first chip 210. The through-hole structure 233 has a metal layer deposited in it to achieve electrical connection.
[0056] As can be seen, the packaging structure provided in this application includes a first chip module connected to the packaging substrate. The first chip module includes at least a first chip, a first rewiring layer fanned out from a first side of the first chip, and a second rewiring layer fanned out from a second side of the first chip, wherein the first side and the second side are opposite to each other; and a plurality of second chips arranged on the first rewiring layer. Furthermore, the first chip can be connected to the packaging substrate through the second rewiring layer, and the second chips and the first chip can be interconnected through the first rewiring layer. In other words, the packaging structure provided in this application can process the first chip among multiple chips (e.g., a first chip and multiple second chips) that need to be packaged and interconnected through fan-out technology, forming a first rewiring layer on the first side of the first chip and a second rewiring layer on the second side of the first chip. This allows the first chip to perform its own function while also achieving a transition function through the rewiring layers fanned out from both sides of the first chip. That is, the connection between the first chip and the packaging substrate is achieved through the second rewiring layer, and the interconnection between the multiple second chips arranged on the first rewiring layer and the first chip is achieved through the first rewiring layer. Thus, while meeting the chip packaging interconnection requirements, the packaging area is reduced and the chip integration is increased.
[0057] Accordingly, embodiments of this application also provide a packaging method. Figure 2 This is a flowchart of a packaging method provided in an embodiment of this application. Figures 3 to 8 This is a schematic diagram of the packaging structure corresponding to each step in the packaging method provided in the embodiments of this application, with reference to... Figure 2 The encapsulation method may include the following steps.
[0058] Step S201: Provide the first chip.
[0059] Reference Figure 3The first chip 210 is provided. In this embodiment, the first chip 210 can be an active chip. An active chip refers to an electronic chip that requires an external power supply to achieve the expected function. These chips contain active components that can actively amplify, adjust or control signals. Using an active chip as an adapter board can achieve smaller spacing and higher I / O density, which is crucial for achieving high bandwidth and low latency applications.
[0060] In an optional implementation, the first chip 210 has a via structure 233, such as a TSV, so that the two subsequent redistribution layers can be connected through the via structure in the first chip and / or the via structure in the molding compound.
[0061] The bottom surface of the first chip is provided with a bonding structure 300, which can be a copper pad for temporary bonding or connection in subsequent processes.
[0062] Step S202: Perform fan-out processing on the first chip to form a first chip module. The first chip module includes a first chip, a first rewiring layer fanned out from a first side of the first chip, and a second rewiring layer fanned out from a second side of the first chip, with the first side and the second side facing each other.
[0063] Fan-out is a semiconductor manufacturing technique that redistributes chip pins based on redistribution layer technology, with the array area bounded by the new pins being larger than the original chip area. Fan-out technology can increase the number of external connection points, thereby improving I / O (input / output) density and packaging flexibility.
[0064] In this embodiment of the application, in order to achieve interconnection between the first chip and multiple second chips while reducing the packaging area, the first chip can be processed using fan-out technology.
[0065] Optionally, combined Figures 3 to 7 The step of fanning out the first chip to form the first chip module may include: cutting the first chip; mounting the cut first chip onto a carrier board; encapsulating the first chip to form a plastic-encapsulated first chip; processing the through-hole structure of the plastic-encapsulated first chip; fanning out a first super-wiring layer on a first side of the plastic-encapsulated first chip; flipping the plastic-encapsulated first chip with the first super-wiring layer formed thereon; and fanning out a second super-wiring layer on a second side of the plastic-encapsulated first chip.
[0066] The specific steps for forming the first chip module are described in detail below with reference to the accompanying drawings.
[0067] Reference Figures 3 to 4To facilitate the fan-out process of the first chip, the first chip 210 needs to be preprocessed first. Specifically, the first chip 210 is cut and reconstructed to prepare for the formation of redistribution layers on both sides of the first chip 210.
[0068] Continue to refer to Figure 4 The first chip 210, after being cut, is mounted onto the carrier board 100A, and the first chip 210 is encapsulated to form an encapsulated first chip.
[0069] The carrier board 100A serves as a temporary support platform during the packaging process, providing mechanical support to help position and move the packaged chip and support the entire packaging assembly. In this embodiment, a wafer bonding film 101 can be disposed between the carrier board 100A and the first chip 210. The wafer bonding film is a thin film material used to fix the chip on the carrier board, ensuring the physical connection between the chip and the carrier board.
[0070] Furthermore, after the first chip is cut, it needs to be encapsulated after being cut and mounted on the carrier board to fix and protect the first chip after cutting.
[0071] In an optional implementation, the specific steps of molding the first chip 210 to form a molded first chip may include: depositing molding layer material 400 on the first surface and both sides of the first chip 210 to form a molded first chip;
[0072] After completing the molding process of the first chip 210, the connection structure of the molded first chip needs to be processed first, so that redistribution layers can be formed on both sides of the first chip in the future.
[0073] Reference Figure 5 In an optional implementation, the processing of the via structure of the first molded chip includes: thinning the first molded chip to expose the via structure 233 in the first chip; and forming the via structure 233 in the molding layer 250 on both sides of the first chip. Combined with... Figure 5 After the first molded chip is thinned, it has a molding layer 250 located on both sides of the first chip. Furthermore, after thinning the first molded chip, through-hole structures 233, such as TSVs, can be formed in the molding layer 250 by drilling holes in it.
[0074] Furthermore, referring to Figure 6 After processing the via structure of the first molded chip, the first redistribution layer 211 can be formed by fanning out on the first side of the first molded chip.
[0075] In a specific implementation, the through-hole structure 233 formed in the molding layer 250 can be electroplated to deposit a metal layer in the through-hole, so as to realize the electrical connection between the first and second wiring layers.
[0076] In an optional embodiment, the first surface can be the top surface of the first chip 210, and the second surface can be the bottom surface of the first chip 210; through a fan-out process, a first rewiring layer 211 is formed on the first surface of the first chip 210 by rewiring, for subsequently placing multiple second chips on the first rewiring layer and interconnecting with the first chip; see reference. Figure 6 In this embodiment of the application, the area of the first redistribution layer 211 fanned out from the first side of the first chip 210 is larger than the area of the first chip 210, thereby increasing the external connection points of the first chip 210 and improving the I / O density of the first chip 210.
[0077] Furthermore, in this embodiment, the first superwiring layer 211 can be used to interconnect the first chip 210 and a plurality of second chips; after the first superwiring layer is formed on the first surface, a second superwiring layer needs to be formed on the second surface opposite to the first surface to facilitate subsequent connection of the packaging substrate for power supply.
[0078] In the optional implementation, refer to Figure 7 The first encapsulated chip with the first super-wiring layer 211 formed is flipped 180° and temporarily bonded to the carrier board 100A. Then, the second super-wiring layer 212 can be formed on the second side of the first encapsulated chip to facilitate subsequent connection to the packaging substrate.
[0079] Step S203: Arrange a plurality of second chips on the first rewiring layer and interconnect the second chips with the first chip through the first rewiring layer.
[0080] After the first and second wiring layers are formed, the first chip module is formed; then, multiple second chips that need to be interconnected with the first chip can be connected to the first chip module.
[0081] In an optional implementation, after the second secondary wiring layer is formed by fanning out on the second side of the first encapsulated chip, and before multiple second chips are arranged on the first wiring layer, the combination is... Figure 7 and Figure 8 The packaging method further includes: flipping the first encapsulated chip with the second super-wiring layer 212 and the first super-wiring layer 211 formed by 180° and rebonding it onto the carrier board 100A. After flipping, the first super-wiring layer 211, which is used to connect with multiple second chips 220, faces upward, so as to facilitate the mounting process of the second chips 220.
[0082] In this embodiment of the application, the process of flip-chipping multiple second chips 220 on the first redistribution layer 211 includes, but is not limited to, flip-chip, thermo-bonding and hybrid bonding processes.
[0083] Continue to refer to Figure 8 The plurality of second chips 220 are arranged on the first redistribution layer 211. The plurality of second chips 220 may include: a side second chip located on the side, and at least one second chip between the side second chips; the range of the side second chip extends beyond the first chip module.
[0084] In an optional example, this application uses three second chips as an example. The plurality of second chips 220 may include: chip 221, chip 222 and chip 223, wherein chip 221 and chip 223 are side-side second chips located on the side, chip 222 is a second chip between two side-side second chips, and the range of the side-side second chips (e.g. chip 221 and chip 223) extends beyond the first chip module 200.
[0085] In this embodiment, the side-side second chips 221 and 223 include signal regions and non-signal regions, and at least one second chip 222 located between the side-side second chips includes signal regions and non-signal regions. The signal region refers to the area on the chip used for signal transmission and processing, including input / output pins for signal transmission between the chip and external devices, and logic circuits for signal processing and control. The non-signal region refers to the area on the chip that does not directly participate in signal transmission and processing, including wiring for providing power and ground lines to ensure a stable power supply to various parts of the chip. The signal regions of the side-side second chips and the signal regions of at least one second chip between the side-side second chips can be connected to the first rewiring layer via a first connection structure. Furthermore, each signal region can be interconnected via the first rewiring layer and connected to the packaging substrate via the first rewiring layer. For the non-signal regions of the side-side second chips, they can be directly connected to the packaging substrate and powered directly by the packaging substrate. For the non-signal regions of at least one second chip between the side-side second chips, they can be directly connected to the packaging substrate via the first rewiring layer.
[0086] Furthermore, after arranging multiple second chips on the first wiring layer and before connecting the second wiring layer to the packaging substrate, the method further includes: forming a first filling layer 241 between the second chip 220 and the first wiring layer 211, wherein a first connection structure 231 is provided in the first filling layer 241, and the signal area of the side second chip and the signal area and non-signal area of at least one second chip between the side second chips are respectively connected to the first wiring layer 211 through the first connection structure 231.
[0087] In an optional embodiment, the first connection structure 231 may be a solder ball, and the first filler layer 241 may be an underfill adhesive, used to protect the first connection structure and the chip from physical impact and wear, and reduce damage caused by mechanical stress such as vibration.
[0088] Step S204: Connect the second wiring layer to the packaging substrate.
[0089] Furthermore, continue to refer to Figure 8 A second connection structure 232 is formed between the non-signal area of the second chip on the side and the carrier board 100A.
[0090] In this embodiment of the application, for the side-side second chip, the non-signal area of the side-side second chip is located beyond the range of the first chip module, and the non-signal area of the side-side second chip is connected to the packaging substrate 100 through the second connection structure 232;
[0091] For at least one second chip between the side second chips, including a signal area and a non-signal area, both the signal area and the non-signal area can be connected to the first redistribution layer 211 through the first connection structure 231, and then directly connected to the packaging substrate through the first redistribution layer 211.
[0092] In other words, whether it is the second chip on the side or at least one second chip located between the second chips on the side, the signal area is connected to the first redistribution layer 211 through the first connection structure 231 to achieve interconnection with the first chip and perform signal transmission and processing. For the non-signal area of the second chip on the side, the non-signal area of the second chip on the side can be directly connected to the packaging substrate through the second connection structure 232, and the packaging substrate directly supplies power. Thus, the embodiments of this application can achieve chip interconnection and meet power supply requirements while making reasonable layout and reducing the waste of space resources.
[0093] In an optional example, the second connection structure 232 can be a bump structure, such as a copper pillar.
[0094] Furthermore, please combine Figure 1 After forming a second connection structure 232 between the non-signal area of the second chip (e.g., chips 221 and 223) on the side and the carrier board 100A, the method further includes: removing the carrier board 100A and the wafer bonding film 101, and connecting the already connected first chip module and the overall package structure of multiple second chips to the package substrate 100. Specifically, this can be achieved by connecting the second redistribution layer 212 to the package substrate 100.
[0095] Next, a second filling layer 242 is formed by filling the gap between the non-signal area of the second chip on the side and the packaging substrate 100. The second connection structure 232 connecting the non-signal area of the second chip on the side and the packaging substrate 100 is located in the second filling layer 242 to protect the second connection structure and the chip from damage.
[0096] Finally, balls can be implanted at the bottom of the packaging substrate 100 (e.g., ...). Figure 1 The solder balls shown are 800, which are used to facilitate subsequent connection to external circuits.
[0097] As can be seen, the packaging structure provided in this application includes a first chip module connected to the packaging substrate. The first chip module includes at least a first chip, a first rewiring layer fanned out from a first side of the first chip, and a second rewiring layer fanned out from a second side of the first chip, wherein the first side and the second side are opposite to each other; and a plurality of second chips arranged on the first rewiring layer. Furthermore, the first chip can be connected to the packaging substrate through the second rewiring layer, and the second chips and the first chip can be interconnected through the first rewiring layer. In other words, the packaging structure provided in this application can process the first chip among multiple chips (e.g., a first chip and multiple second chips) that need to be packaged and interconnected through fan-out technology, forming a first rewiring layer on the first side of the first chip and a second rewiring layer on the second side of the first chip. This allows the first chip to perform its own function while also achieving a transition function through the rewiring layers fanned out from both sides of the first chip. That is, the connection between the first chip and the packaging substrate is achieved through the second rewiring layer, and the interconnection between the multiple second chips arranged on the first rewiring layer and the first chip is achieved through the first rewiring layer. Thus, while meeting the chip packaging interconnection requirements, the packaging area is reduced and the chip integration is increased.
[0098] This application provides an electronic device, such as a terminal device or a server device, which includes the packaging structure described in the foregoing embodiments.
[0099] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.
[0100] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A package structure, characterized by, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
2. The package structure of claim 1, wherein, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
3. The package structure of claim 2, wherein, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
4. The package structure of claim 3, wherein, The application relates to a chip module and a manufacturing method thereof.
5. The package structure of claim 3, wherein, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
6. The package structure of claim 4, wherein, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
7. The package structure of claim 6, wherein, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
8. The package structure of claim 5 or 6, wherein, The application relates to a chip module and a manufacturing method thereof.
9. A packaging method, characterized by, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof.
10. The packaging method according to claim 9, wherein, The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module and a manufacturing method thereof. The application relates to a chip module cutting the first chip; mounting the first chip after cutting on a carrier board; forming a plastic package first chip by performing a plastic package process on the first chip; processing a via structure of the plastic package first chip; forming the first redistribution layer on the first surface of the plastic package first chip; turning over the plastic package first chip with the first redistribution layer formed thereon; forming the second redistribution layer on the second surface of the plastic package first chip.
11. The packaging method according to claim 10, characterized in that, The forming a plastic package first chip by performing a plastic package process on the first chip comprises: depositing plastic package layer material on the first surface and two sides of the first chip to form a plastic package first chip, the plastic package first chip having a plastic package layer; The processing a via structure of the plastic package first chip comprises: performing a thinning process on the plastic package first chip to expose the via structure in the first chip; forming a via structure in the plastic package layer on the two sides of the first chip.
12. The packaging method of claim 10, wherein, After forming the second redistribution layer on the second surface of the plastic package first chip, before arranging a plurality of second chips on the first redistribution layer, the packaging method further comprises: turning over the plastic package first chip with the second redistribution layer and the first redistribution layer formed thereon.
13. The packaging method of claim 9, wherein, The plurality of second chips arranged on the first redistribution layer comprises: edge side second chips located on the edges, and at least one second chip between the edge side second chips; the range of the edge side second chips exceeds the first chip module; The edge side second chips comprise: a signal area and a non-signal area, and the at least one second chip between the edge side second chips comprises: a signal area and a non-signal area; wherein the non-signal area of the edge side second chips is located in the range of the edge side second chips exceeding the first chip module; The method further comprises: forming a second connection structure connected between the non-signal area of the edge side second chips and the carrier board.
14. The packaging method according to claim 13, characterized in that, After arranging the plurality of second chips on the first redistribution layer, before forming the second connection structure, the method further comprises: forming a first filling layer between the second chips and the first redistribution layer, the first filling layer being provided with a first connection structure, and the signal area of the edge side second chips and the signal area and the non-signal area of the at least one second chip between the edge side second chips being connected to the first redistribution layer through the first connection structure.
15. The packaging method of claim 13, wherein, After forming the second connection structure connected between the non-signal area of the edge side second chips and the carrier board, the method further comprises: removing the carrier board, and connecting the second redistribution layer and the packaging substrate; filling a second filling layer in the gap between the non-signal area of the edge side second chips and the packaging substrate, and the second connection structure connecting the non-signal area of the edge side second chips and the packaging substrate being located in the second filling layer.
16. An electronic device, comprising: The packaging structure comprises any one of claims 1-8.