Quick-start and self-adaptive load charge pump circuit

Abstract

The invention discloses a quick-start and self-adaptive load charge pump circuit, which comprises a loop control module, a clock signal generation module, a cross-coupling charge pump module and an establishment indication module, and is characterized in that the first output end of the loop control module is connected with the first input end of the establishment indication module; the second output end of the loop control module is connected with the input end of the clock signal generation module, the first output end of the clock signal generation module is connected with the first input end of the cross coupling charge pump module, and the second output end of the clock signal generation module is connected with the second input end of the cross coupling charge pump module. And the output end of the cross coupling charge pump module is connected with the second input end of the establishment indication module and the input end of the loop control module. The charge pump circuit has the advantages of being high in starting speed, high in driving capacity and low in implementation cost.

Description

Technical Field

[0001] This invention relates to a charge pump circuit, and more particularly to a fast-start and adaptive load-carrying charge pump circuit, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] A charge pump, also known as a switched capacitor voltage converter, is a DC-DC converter that uses a pumping capacitor as an energy storage device and controls the charging and discharging of the capacitor through a clock to achieve the required output voltage. Due to its inductance-free nature, ease of integration, and low electromagnetic interference, it is widely used in the power management systems of various driver chips.

[0003] Traditional charge pump circuits are extensions of the Dickson structure. Their basic principle is to use diodes or diode-connected MOSFETs to restrict the unidirectional flow of charge, utilizing the energy storage of the charge to raise or lower the reference voltage, thereby outputting the desired voltage. However, this type of charge pump has weak driving capability, a large pumping capacitor area, high implementation cost, and the charge pumping process suffers from voltage loss due to the threshold voltage of diodes.

[0004] For example, Chinese Patent Publication No. CN111371313A discloses a high-voltage charge pump circuit that designs a novel boost unit. It utilizes the voltage isolation characteristics of the isolated low-voltage PMOS device to reduce charge loss during the voltage boosting process, thereby indirectly reducing the number of stages required for series connection and effectively reducing the circuit area. However, this type of boost charge pump still belongs to the Dickson structure topology and cannot avoid the transmission voltage loss due to the threshold voltage of the diode-connected MOS transistor.

[0005] The high-voltage charge pump and its soft-start method disclosed in Chinese Patent Publication No. CN114977786A adopts a dual-channel cross-coupled charge pump structure, which completely eliminates the voltage loss caused by the threshold of the MOS transistor, and its flexible and configurable start-up time is sufficient to meet the application fields such as EEPROM. However, its fastest start-up speed is at the 100μs level, which cannot meet the needs of some application scenarios that require high voltage and rapid establishment.

[0006] The PMOS positive high voltage charge pump disclosed in Chinese Patent Publication No. CN102751867A uses a gate control auxiliary branch to reduce backflow current, improve the charge conduction capability of the MOS tube, thereby increasing the overall voltage rise slope and reducing the output voltage settling time. However, the charge pump with this structure has a relatively weak load-carrying capacity.

[0007] Therefore, it can be seen that the existing technology has not been able to achieve the advantages of fast start-up speed, strong driving capability and low implementation cost in charge pump circuit. Summary of the Invention

[0008] This invention relates to a charge pump circuit that is fast-starting and adaptive to load, which has the advantages of fast start-up speed, strong driving capability and low implementation cost.

[0009] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A fast-start and adaptive load-carrying charge pump circuit includes a loop control module, a clock signal generation module, a cross-coupled charge pump module, and a setup indicator module. The first output of the loop control module is connected to the first input of the setup indicator module and generates a bias voltage VBP_H. The second output of the loop control module is connected to the input of the clock signal generation module and generates a current IB_OSC. The first output of the clock signal generation module is connected to the first input of the cross-coupled charge pump module and generates a clock signal CLK. The second output of the clock signal generation module is connected to the second input of the cross-coupled charge pump module and generates an inverted clock signal. The output of the cross-coupled charge pump module is connected to the second input of the setup indicator module and the input of the loop control module to generate the target high voltage CP_OUT. The output of the setup indicator module generates the charge pump setup completion indication signal CP_OK.

[0010] Furthermore, the loop control module includes NMOS transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, LDNMOS high-voltage transistors D0, D1, D2, D3, D4, and D5. 5. Capacitors C0, C1, and C2, and Zener transistor Z0, the drain of NMOS transistor M0, one end of the reference current source IREF, the gates of NMOS transistors M0, M2, M3, M5, M6, M7, M8, M9, and M10 are connected. The other end of the reference current source IREF is connected to the power supply VDD. The sources of NMOS transistors M0, M2, M3, M4, M5, and M10 are grounded. PMOS transistor M1... The source, one end of capacitor C0, the cathode of Zener transistor Z0, and one end of capacitor C2 are connected and used as the input terminal of the loop control module, connected to the target high voltage CP_OUT. The drain of PMOS transistor M1, the gate of PMOS transistor M1, the other end of capacitor C0, and the drain of LDNMOS high-voltage transistor D0 are connected and used as the first output terminal of the loop control module to generate the bias voltage VBP_H. The gates of LDNMOS high-voltage transistors D0, D1, D4, and D5 are connected to the enable signal EN. The source of LDNMOS high-voltage transistor D0 is connected to the drain of NMOS transistor M2. One end of capacitor C1, the source of LDPMOS high-voltage transistor D2, and the other end of capacitor C0 are connected to the drain of LDPMOS high-voltage transistor D2. The source, source, source, source, and source of PMOS transistors M11, M12, M13, and M14 are connected to the power supply VCC. The other end of capacitor C1 is connected to the drain, gate, and gate of LDPMOS transistors D2 and D3, and the drain of LDNMOS transistor D1. The source of LDNMOS transistor D1 is connected to the drain of NMOS transistor M3. The anode of Zener transistor Z0 is connected to the source of LDPMOS transistor D3. The drain of LDPMOS transistor D3 is connected to the drain, gate, source, and drain of NMOS transistors M4 and M5.The other end of capacitor C2 is connected to the drain of PMOS transistor M11, the gate of PMOS transistor M11, the gate of PMOS transistor M12, and the drain of LDNMOS high-voltage transistor D4. The drain of PMOS transistor M12 is connected to the drain of PMOS transistor M18 and serves as the output terminal of the loop control module, generating current IB_OSC. The drain of PMOS transistor M13 is connected to the gates of PMOS transistors M13, M14, M15, M16, M17, and M18, and the drain of LDNMOS high-voltage transistor D5. The source of transistor D5 is connected to the drain of NMOS transistor M6; the source of NMOS transistor M6 is connected to the drain of NMOS transistor M7; the source of NMOS transistor M7 is connected to the drain of NMOS transistor M8; the source of NMOS transistor M8 is connected to the drain of NMOS transistor M9; the source of NMOS transistor M9 is connected to the drain of NMOS transistor M10; the drain of PMOS transistor M14 is connected to the source of PMOS transistor M15; the drain of PMOS transistor M15 is connected to the source of PMOS transistor M16; the drain of PMOS transistor M16 is connected to the source of PMOS transistor M17; and the drain of PMOS transistor M17 is connected to the source of PMOS transistor M18.

[0011] Furthermore, the NMOS transistors M0, M2, M3, M5, M6, M7, M8, M9, and M10 constitute the first NMOS current mirror.

[0012] Furthermore, PMOS transistors M11 and M12 constitute a first PMOS current mirror, and PMOS transistors M13, M14, M15, M16, M17, and M18 constitute a second PMOS current mirror.

[0013] Further, the clock signal generation module includes PMOS transistors M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, and M30; a D flip-flop (DFF); NOR gates Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7; and PMOS transistors M31, M32, M33, M34, M35, and M36. The sources of transistors M36, M37, M38, M19, M23, M25, M27, M29, M31, M33, M35, and M37 are connected to the power supply VCC. The gate of PMOS transistor M19 is connected to the gate of NMOS transistor M22 and the Reset terminal of the D flip-flop DFF, which is connected to the enable signal EN. The drain of PMOS transistor M19 is connected to the drain of PMOS transistor M20 and the drain of NMOS transistor M21. The gate of PMOS transistor M23 is connected to the gate of NMOS transistor M24. The source of PMOS transistor M20 serves as the input terminal of the clock signal generation module, connected to the current IB_OSC. The gate of PMOS transistor M20 is connected to the gate of NMOS transistor M21, the drain of PMOS transistor M29, the drain of NMOS transistor M30, and the clk terminal of the D flip-flop DFF. The source of NMOS transistor M21 is connected to the drain of NMOS transistor M22. The sources of NMOS transistors M22, M24, M26, M28, M30, and M32 are also connected. The sources of NMOS transistors M34, M36, and M38 are grounded. The drain of PMOS transistor M23 is connected to the drain of NMOS transistor M24, the gate of PMOS transistor M25, and the gate of NMOS transistor M26. The drain of PMOS transistor M25 is connected to the drain of NMOS transistor M26, the gate of PMOS transistor M27, and the gate of NMOS transistor M28. The drain of PMOS transistor M27 is connected to the drain of NMOS transistor M28, the gate of PMOS transistor M29, and the gate of NMOS transistor M30. The Q terminal of D flip-flop DFF is connected to the first input terminal of NOR gate Y0. The output of NOR gate Y0 is connected to the D terminal of the D flip-flop DFF and the second input terminal of NOR gate Y1. The output terminal of NOR gate Y0 is connected to the input terminal of NOT gate Y2. The output terminal of NOT gate Y2 is connected to the input terminal of NOT gate Y4. The output terminal of NOT gate Y4 is connected to the input terminal of NOT gate Y6 and the first input terminal of NOR gate Y1. The output terminal of NOT gate Y6 is connected to the gate of PMOS transistor M31 and the gate of NMOS transistor M32. The output terminal of NOR gate Y1 is connected to the input terminal of NOT gate Y3. The output terminal of NOT gate Y3 is connected to the input terminal of NOT gate Y5. The output terminal of NOT gate Y5 is connected to the input terminal of NOT gate Y7 and the second input terminal of NOR gate Y0. The output terminal of NOT gate Y7 is connected to the PMOS transistor... The gate of transistor M33 is connected to the gate of NMOS transistor M34. The drain of PMOS transistor M31 is connected to the drain of NMOS transistor M32, and the gate of PMOS transistor M35 is connected to the gate of NMOS transistor M36. The drain of PMOS transistor M33 is connected to the drain of NMOS transistor M34, and the gate of PMOS transistor M37 is connected to the gate of NMOS transistor M38. The drain of PMOS transistor M35 is connected to the drain of NMOS transistor M36 and serves as the first output terminal of the clock signal generation module to generate the clock signal CLK. The drain of PMOS transistor M37 is connected to the drain of NMOS transistor M38 and serves as the second output terminal of the clock signal generation module to generate the inverted clock signal. .

[0014] Further, the cross-coupled charge pump module includes NMOS transistors M39, M40, M41, M42, M43, M44, M45, M46, M47, M48, M49, and M50, as well as capacitors C3, C4, C5, C6, C7, and C8. One end of capacitor C3 is connected to one end of capacitors C5 and C7 and serves as the first input terminal of the cross-coupled charge pump module, connected to the clock signal CLK. One end of capacitor C4 is connected to one end of capacitors C6 and C8 and serves as the second input terminal of the cross-coupled charge pump module, connected to the inverted clock signal. The other end of capacitor C3 is connected to the source of NMOS transistor M39, the drain of PMOS transistor M40, the gate of NMOS transistor M41, and the gate of PMOS transistor M42. The other end of capacitor C4 is connected to the gate of NMOS transistor M39, the gate of PMOS transistor M40, the source of NMOS transistor M41, and the drain of PMOS transistor M42. The drains of NMOS transistors M39 and M41 are connected to the power supply VCC. The sources of PMOS transistors M40 and M42 are connected to the drains of NMOS transistors M43 and M45. The other end of capacitor C5 is connected to the source of NMOS transistor M43, the drain of PMOS transistor M44, the gate of NMOS transistor M45, and the gate of PMOS transistor M46. The other end of capacitor C6 is connected to the NMOS transistor M42. The gate of transistor M43, the gate of PMOS transistor M44, the source of NMOS transistor M45, and the drain of PMOS transistor M46 are connected. The source of PMOS transistor M44 and the source of PMOS transistor M46 are connected to the drain of NMOS transistor M47 and the drain of NMOS transistor M49. The other end of capacitor C7 is connected to the source of NMOS transistor M47, the drain of PMOS transistor M48, the gate of NMOS transistor M49, and the gate of PMOS transistor M50. The other end of capacitor C8 is connected to the gate of NMOS transistor M47, the gate of PMOS transistor M48, the source of NMOS transistor M49, and the drain of PMOS transistor M50. The source of PMOS transistor M48 and the source of PMOS transistor M50 are connected and serve as the output terminal of the cross-coupled charge pump module to generate the target high voltage CP_OUT.

[0015] Further, the establishment indication module includes PMOS transistors M51, M52, M53, M54, NMOS transistors M55, M56, M57, M58, M59, M60, M61, M62, LDPMOS high-voltage transistors D6, D7, DDNMOS high-voltage transistors D8, D9, resistor R0, capacitor C9, Schmitt trigger Y8, NOT gate Y9, NOT gate Y10, Schmitt trigger Y11, and NOT gate Y12. The gate of PMOS transistor M51 is connected to the gate of PMOS transistor M52 and functions as... To establish the first input terminal of the indicator module connected to the bias voltage VBP_H, the source of PMOS transistor M51 is connected to the source of PMOS transistor M52, one end of capacitor C9, the source of LDPMOS high-voltage transistor D6, and the source of LDPMOS high-voltage transistor D7, and this serves as the second input terminal of the indicator module connected to the target high voltage CP_OUT. The drain of PMOS transistor M51 is connected to the source of PMOS transistor M53. The gate of PMOS transistor M53 is connected to the drain of PMOS transistor M53 and the source of PMOS transistor M54. The gate of PMOS transistor M54 is connected to the drain of PMOS transistor M54, the drain of NMOS transistor M55, the gate of NMOS transistor M55, and the gate of NMOS transistor M56. The source of OS transistor M55 and the source of NMOS transistor M56 are connected to power supply VCC. The drain of PMOS transistor M52, one end of resistor R0, and the drain of NMOS transistor M56 are connected to node B. The other end of resistor R0, the other end of capacitor C9, and the input of Schmitt trigger Y8 are connected. The output of Schmitt trigger Y8 is connected to the input of NOT gate Y9. The output of NOT gate Y9 is connected to the gate of LDPMOS transistor D6 and the input of NOT gate Y10. The output of NOT gate Y10 is connected to the gate of LDPMOS transistor D7. The drain of LDPMOS transistor D6 is connected to the drain of LDNMOS transistor D8. The drain of LDPMOS transistor D7 is connected to the drain of LDNMOS transistor D8. The drain of transistor D9 is connected to the enable signal EN. The source of transistor D8 is connected to the drain of NMOS transistor M57, the gate of NMOS transistor M58, and the gate of NMOS transistor M61 at node C. The source of transistor D9 is connected to the drain of NMOS transistor M58, the gate of NMOS transistor M57, and the gate of NMOS transistor M62 at node D. The source of PMOS transistor M59 and the source of PMOS transistor M60 are connected to the power supply VDD. The gate of PMOS transistor M59 is connected to the drain of PMOS transistor M60, the input of Schmitt trigger Y11, and the drain of NMOS transistor M62 at node F.The gate of PMOS transistor M60 is connected to the drain of PMOS transistor M59 and the drain of NMOS transistor M61 at node E. The sources of NMOS transistors M57, M58, M61, and M62 are grounded. The output of Schmitt trigger Y11 is connected to the input of NOT gate Y12. The output of NOT gate Y12 serves as the output of the setup indicator module, generating the charge pump setup completion indicator signal CP_OK.

[0016] Furthermore, the PMOS transistor M1, together with PMOS transistors M51 and M52, constitutes a third PMOS current mirror.

[0017] Furthermore, the NMOS transistors M55 and M56 constitute a second NMOS current mirror.

[0018] Compared with existing technologies, this invention has the following advantages and effects: This invention provides a fast-starting and adaptively load-carrying charge pump circuit, employing a cross-coupled charge pump structure to completely eliminate the transmission voltage loss caused by the threshold voltage of the diode-connected MOS transistor; this invention uses a multi-stage series cross-coupled charge pump structure to output voltage at a series stage number far exceeding the target voltage, and obtains the target high voltage through Zener diode clamping. This significantly improves the start-up speed of the charge pump, enabling extremely fast high voltage output, with the entire process not exceeding 10µs. Compared to the settling time of traditional charge pumps, the settling time of this invention can be tens of times faster; this invention uses a clock whose frequency adapts to load feedback, which can enhance the driving capability by increasing the clock frequency to meet heavy-load scenarios. Compared to traditional charge pumps, for the same area of ​​pumping capacitor, it can improve the load-carrying capacity by several times. Attached Figure Description

[0019] Figure 1 This is a circuit diagram of the loop control module of a fast-start and adaptive load-carrying charge pump circuit according to the present invention.

[0020] Figure 2 This is a circuit diagram of the clock signal generation module of the present invention.

[0021] Figure 3 This is a circuit diagram of the cross-coupled charge pump module of the present invention.

[0022] Figure 4 This is a circuit diagram of the establishment instruction module of the present invention. Detailed Implementation

[0023] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0024] This invention discloses a fast-start and adaptive load-carrying charge pump circuit, comprising a loop control module, a clock signal generation module, a cross-coupled charge pump module, and a setup indicator module. The first output terminal of the loop control module is connected to the first input terminal of the setup indicator module and generates a bias voltage VBP_H. The second output terminal of the loop control module is connected to the input terminal of the clock signal generation module and generates a current IB_OSC. The first output terminal of the clock signal generation module is connected to the first input terminal of the cross-coupled charge pump module and generates a clock signal CLK. The second output terminal of the clock signal generation module is connected to the second input terminal of the cross-coupled charge pump module and generates an inverted clock signal. The output of the cross-coupled charge pump module is connected to the second input of the setup indicator module and the input of the loop control module to generate the target high voltage CP_OUT. The output of the setup indicator module generates the charge pump setup completion indication signal CP_OK.

[0025] like Figure 1As shown, the loop control module includes NMOS transistors M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, LDNMOS high-voltage transistors D0, D1, D2, D3, D4, and D5, and an electrical... Capacitors C0, C1, and C2, and Zener transistor Z0, the drain of NMOS transistor M0 is connected to one end of the reference current source IREF, the gates of NMOS transistors M0, M2, M3, M5, M6, M7, M8, M9, and M10. The other end of the reference current source IREF is connected to the power supply VDD. The sources of NMOS transistors M0, M2, M3, M4, M5, and M10 are grounded. The source of PMOS transistor M1 is connected to... One end of capacitor C0, the cathode of Zener transistor Z0, and one end of capacitor C2 are connected and used as the input terminal of the loop control module, connected to the target high voltage CP_OUT. The drain of PMOS transistor M1 and the gate of PMOS transistor M1, the other end of capacitor C0 and the drain of LDNMOS high voltage transistor D0 are connected and used as the first output terminal of the loop control module to generate the bias voltage VBP_H. The gates of LDNMOS high voltage transistors D0, D1, D4, and D5 are connected to the enable signal EN. The source of LDNMOS high voltage transistor D0 is connected to the drain of NMOS transistor M2. One end of capacitor C1 and the source of LDPMOS high voltage transistor D2 are connected to the source of NMOS transistor D2. The sources of PMOS transistors M11, M12, M13, and M14 are connected to the power supply VCC. The other end of capacitor C1 is connected to the drain, gate, and gate of LDPMOS transistors D2 and D3, and the drain of LDNMOS transistor D1. The source of LDNMOS transistor D1 is connected to the drain of NMOS transistor M3. The anode of Zener transistor Z0 is connected to the source of LDPMOS transistor D3. The drain of LDPMOS transistor D3 is connected to the drain, gate, source, and drain of NMOS transistors M4 and M5.The other end of capacitor C2 is connected to the drain of PMOS transistor M11, the gate of PMOS transistor M11, the gate of PMOS transistor M12, and the drain of LDNMOS high-voltage transistor D4. The drain of PMOS transistor M12 is connected to the drain of PMOS transistor M18 and serves as the output terminal of the loop control module, generating current IB_OSC. The drain of PMOS transistor M13 is connected to the gates of PMOS transistors M13, M14, M15, M16, M17, and M18, and the drain of LDNMOS high-voltage transistor D5. The source of transistor D5 is connected to the drain of NMOS transistor M6; the source of NMOS transistor M6 is connected to the drain of NMOS transistor M7; the source of NMOS transistor M7 is connected to the drain of NMOS transistor M8; the source of NMOS transistor M8 is connected to the drain of NMOS transistor M9; the source of NMOS transistor M9 is connected to the drain of NMOS transistor M10; the drain of PMOS transistor M14 is connected to the source of PMOS transistor M15; the drain of PMOS transistor M15 is connected to the source of PMOS transistor M16; the drain of PMOS transistor M16 is connected to the source of PMOS transistor M17; and the drain of PMOS transistor M17 is connected to the source of PMOS transistor M18.

[0026] NMOS transistors M0, M2, M3, M5, M6, M7, M8, M9, and M10 constitute the first NMOS current mirror.

[0027] PMOS transistors M11 and M12 form the first PMOS current mirror, while PMOS transistors M13, M14, M15, M16, M17, and M18 form the second PMOS current mirror.

[0028] NMOS transistors M2 and M3 provide bias as current sources. LDNMOS high-voltage transistors D0 and D1 withstand high voltage to prevent damage to the low-voltage transistors. The diode-connected PMOS transistor M1 generates a voltage bias VBP_H, which is output to the charge pump to establish an indicator circuit. Capacitors C0 and C1 act as voltage regulators, coupling the charge pump output CP_OUT and the high-voltage power supply VCC, respectively. LDPMOS high-voltage transistors D2 and D3, along with Zener diode Z0, constitute a current comparator. If the comparator input satisfies the following conditions:

[0029] Among them, V ZIf the voltage is the breakdown voltage of the Zener diode, then the gate-source voltage of the LDPMOS high-voltage diode D3 is greater than that of the LDPMOS high-voltage diode D2. Considering that the NMOS diodes M3 and M5 have the same dimensions, the pull-up capability of the LDPMOS high-voltage diode D3 is stronger than that of the NMOS diode M5. According to Kirchhoff's laws, the current equation at node A is:

[0030] Among them, I D3 I represents the current flowing through the LDNMOS high-voltage transistor D3. D4 I represents the current flowing through the LDNMOS high-voltage transistor D3. M3 I represents the current flowing through NMOS transistor M3. M4 This represents the current flowing through NMOS transistor M4. NMOS transistor M3 is an inverting ratio transistor, only turning on when the pull-up capability of the high-voltage LDPMOS transistor D3 is much stronger than the pull-down capability of NMOS transistor M5. This clamps the voltage at node A, preventing the low-voltage transistor M5 from being damaged by the high voltage, and also enhancing the system's transient response. Therefore, I... M4 This can be ignored; in this case, the current equation at node A can be rewritten as:

[0031] For a fixed current source I M5 I D4 The pull-up capability of LDNMOS high-voltage transistor D3 will decrease as its current pull-up capability increases. LDNMOS high-voltage transistors D4 and D5 also serve to withstand high voltage. Capacitor C2 feeds forward the disturbance of charge pump CP_OUT to the first PMOS current mirror, which plays a role in loop compensation and ensures stable system operation. The first PMOS current mirror and the second PMOS current mirror jointly output current bias IB_OSC to the clock generation module.

[0032] like Figure 2As shown, the clock signal generation module includes PMOS transistors M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, and M30; a D flip-flop (DFF); NOR gates Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7; and PMOS transistors M31, M32, M33, M34, and M35. The sources of transistors M36, M37, M38, M19, M23, M25, M27, M29, M31, M33, M35, and M37 are connected to the power supply VCC. The gate of PMOS transistor M19 is connected to the gate of NMOS transistor M22 and the Reset terminal of the D flip-flop DFF, which is connected to the enable signal EN. The drain of PMOS transistor M19 is connected to the drain of PMOS transistor M20, the drain of NMOS transistor M21, and PM. The gate of OS transistor M23 is connected to the gate of NMOS transistor M24. The source of PMOS transistor M20 serves as the input terminal of the clock signal generation module and is connected to the current IB_OSC. The gate of PMOS transistor M20 is connected to the gate of NMOS transistor M21, the drain of PMOS transistor M29, the drain of NMOS transistor M30, and the clk terminal of the D flip-flop DFF. The source of NMOS transistor M21 is connected to the drain of NMOS transistor M22. The sources of NMOS transistors M22, M24, M26, M28, M30, and M32 are also connected. The sources of NMOS transistors M34, M36, and M38 are grounded. The drain of PMOS transistor M23 is connected to the drain of NMOS transistor M24, the gate of PMOS transistor M25, and the gate of NMOS transistor M26. The drain of PMOS transistor M25 is connected to the drain of NMOS transistor M26, the gate of PMOS transistor M27, and the gate of NMOS transistor M28. The drain of PMOS transistor M27 is connected to the drain of NMOS transistor M28, the gate of PMOS transistor M29, and the gate of NMOS transistor M30. The Q terminal of D flip-flop DFF is connected to the first input terminal of NOR gate Y0. The output of NOR gate Y0 is connected to the D terminal of the D flip-flop DFF and the second input terminal of NOR gate Y1. The output terminal of NOR gate Y0 is connected to the input terminal of NOT gate Y2. The output terminal of NOT gate Y2 is connected to the input terminal of NOT gate Y4. The output terminal of NOT gate Y4 is connected to the input terminal of NOT gate Y6 and the first input terminal of NOR gate Y1. The output terminal of NOT gate Y6 is connected to the gate of PMOS transistor M31 and the gate of NMOS transistor M32. The output terminal of NOR gate Y1 is connected to the input terminal of NOT gate Y3. The output terminal of NOT gate Y3 is connected to the input terminal of NOT gate Y5. The output terminal of NOT gate Y5 is connected to the input terminal of NOT gate Y7 and the second input terminal of NOR gate Y0. The output terminal of NOT gate Y7 is connected to the PMOS transistor... The gate of transistor M33 is connected to the gate of NMOS transistor M34. The drain of PMOS transistor M31 is connected to the drain of NMOS transistor M32, and the gate of PMOS transistor M35 is connected to the gate of NMOS transistor M36. The drain of PMOS transistor M33 is connected to the drain of NMOS transistor M34, and the gate of PMOS transistor M37 is connected to the gate of NMOS transistor M38. The drain of PMOS transistor M35 is connected to the drain of NMOS transistor M36 and serves as the first output terminal of the clock signal generation module to generate the clock signal CLK. The drain of PMOS transistor M37 is connected to the drain of NMOS transistor M38 and serves as the second output terminal of the clock signal generation module to generate the inverted clock signal. .

[0033] PMOS transistors M19 and M20, along with NMOS transistors M21, M22, M23, M24, M25, M26, M27, M28, M29, and M30, constitute a ring oscillator with enable control. When enable EN is high, the clock is turned on, and the clock frequency output by the ring oscillator increases with the increase of the current bias IB_OSC. If enable EN is low, the entire... With the oscillator off, the clock generation circuit no longer outputs a clock signal. The oscillator output is connected to the CLK terminal of the D flip-flop (DFF) in a frequency divide-by-two manner. This, along with NOR gates Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, PMOS transistors M31, M32, M33, M34, M35, M36, M37, and M38, generates a set of non-overlapping, out-of-phase clock signals. and The output is supplied to the pumping capacitor of the cross-coupled charge pump. PMOS transistor M31, along with NMOS transistors M32, M33, M34, M35, M36, M37, and M38, form a buffer stage. The purpose is to enhance the driving capability of the clock signal and ensure that the boost voltage of each cycle meets expectations.

[0034] like Figure 3 As shown, the cross-coupled charge pump module includes NMOS transistors M39, M40, M41, M42, M43, M44, M45, M46, M47, M48, M49, and M50, as well as capacitors C3, C4, C5, C6, C7, and C8. One end of capacitor C3 is connected to one end of capacitors C5 and C7, serving as the first input terminal of the cross-coupled charge pump module and connected to the clock signal CLK. One end of capacitor C4 is connected to one end of capacitors C6 and C8, serving as the second input terminal of the cross-coupled charge pump module and connected to the inverted clock signal. The other end of capacitor C3 is connected to the source of NMOS transistor M39, the drain of PMOS transistor M40, the gate of NMOS transistor M41, and the gate of PMOS transistor M42. The other end of capacitor C4 is connected to the gate of NMOS transistor M39, the gate of PMOS transistor M40, the source of NMOS transistor M41, and the drain of PMOS transistor M42. The drains of NMOS transistors M39 and M41 are connected to the power supply VCC. The sources of PMOS transistors M40 and M42 are connected to the drains of NMOS transistors M43 and M45. The other end of capacitor C5 is connected to the source of NMOS transistor M43, the drain of PMOS transistor M44, the gate of NMOS transistor M45, and the gate of PMOS transistor M46. The other end of capacitor C6 is connected to the NMOS transistor M42. The gate of transistor M43, the gate of PMOS transistor M44, the source of NMOS transistor M45, and the drain of PMOS transistor M46 are connected. The source of PMOS transistor M44 and the source of PMOS transistor M46 are connected to the drain of NMOS transistor M47 and the drain of NMOS transistor M49. The other end of capacitor C7 is connected to the source of NMOS transistor M47, the drain of PMOS transistor M48, the gate of NMOS transistor M49, and the gate of PMOS transistor M50. The other end of capacitor C8 is connected to the gate of NMOS transistor M47, the gate of PMOS transistor M48, the source of NMOS transistor M49, and the drain of PMOS transistor M50. The source of PMOS transistor M48 and the source of PMOS transistor M50 are connected and serve as the output terminal of the cross-coupled charge pump module to generate the target high voltage CP_OUT.

[0035] Assuming that after the initial transient, the cross-coupled charge pump reaches a steady state: in the first half of the cycle, , Because the voltage difference across a capacitor cannot change abruptly, the voltage across the lower plate of capacitors C3, C5, and C7 is raised. At this time, NMOS transistors M39, M42, M43, M46, M47, and M50 are turned off, while NMOS transistors M41, M40, M45, M44, M49, and M48 are turned on. The input high-voltage power supply VCC charges the upper plate of capacitor C4 through NMOS transistor M41, reaching VCC when stable. The lower plate of capacitor C3 outputs high voltage through PMOS transistor M40, which serves as the input and the second stage charge. When the pumps are connected, the first-stage charge pump output voltage is 2VCC-HGND when stable. This output voltage charges the upper plate of capacitor C6 through NMOS transistor M45, reaching 2VCC-HGND when stable. The lower plate of capacitor C5 outputs high voltage through PMOS transistor M44, which is then connected as input to the third-stage charge pump. When stable, the second-stage charge pump output voltage is 3VCC-2HGND. This output voltage charges the upper plate of capacitor C8 through NMOS transistor M45, reaching 3VCC-2HGND when stable. The lower plate of capacitor C7 supplies power to the output through PMOS transistor M48 and acts as the charge pump output CP_OUT. In the second half of the cycle… , During the first half-cycle, the voltages of the upper plates of capacitors C4, C6, and C8 have stabilized at VCC, 2VCC-HGND, and 3VCC-2HGND, respectively. Due to the characteristics of capacitors, the voltages of the upper plates of capacitors C4, C6, and C8 are also raised to VCC-HGND. At this time, NMOS transistors M39, M42, M43, M46, M47, and M50 are turned on, while NMOS transistors M41, M40, M45, M44, M49, and M48 are turned off. The input high-voltage power supply VCC charges the upper plate of capacitor C3 through NMOS transistor M39, reaching VCC when stable. The lower plate of capacitor C4 is charged through PMOS transistor M42, M43, M44, M49, and M48. The first stage charge pump outputs a high voltage, which is then connected to the second stage charge pump as an input. When the output is stable, the first stage charge pump outputs a voltage of 2VCC-HGND. The first stage charge pump output voltage charges the upper plate of capacitor C6 through NMOS transistor M43, reaching 2VCC-HGND when stable. The lower plate of capacitor C5 outputs a high voltage through PMOS transistor M46, which is then connected to the third stage charge pump as an input. When the output is stable, the second stage charge pump outputs a voltage of 3VCC-2HGND. The second stage charge pump output voltage charges the upper plate of capacitor C8 through NMOS transistor M47, reaching 3VCC-2HGND when stable. The lower plate of capacitor C7 supplies power to the output through PMOS transistor M50 and acts as the charge pump output CP_OUT. This process repeats until the output stabilizes at 4VCC-3HGND.

[0036] like Figure 4As shown, the establishment instruction module includes PMOS transistors M51, M52, M53, M54, NMOS transistors M55, M56, M57, M58, M59, M60, M61, M62, LDPMOS high-voltage transistors D6, D7, DDNMOS high-voltage transistors D8, D9, resistor R0, capacitor C9, Schmitt trigger Y8, NOT gate Y9, NOT gate Y10, Schmitt trigger Y11, and NOT gate Y12. The gate of PMOS transistor M51 is connected to the gate of PMOS transistor M52 and serves as the establishment... The first input terminal of the indicator module is connected to the bias voltage VBP_H. The source of PMOS transistor M51 is connected to the source of PMOS transistor M52, one end of capacitor C9, the source of LDPMOS high-voltage transistor D6, and the source of LDPMOS high-voltage transistor D7, and serves as the second input terminal of the indicator module, connected to the target high voltage CP_OUT. The drain of PMOS transistor M51 is connected to the source of PMOS transistor M53. The gate of PMOS transistor M53 is connected to the drain of PMOS transistor M53 and the source of PMOS transistor M54. The gate of PMOS transistor M54 is connected to the drain of PMOS transistor M54, the drain of NMOS transistor M55, the gate of NMOS transistor M55, and the gate of NMOS transistor M56. The source of transistor M55 and the source of NMOS transistor M56 are connected to power supply VCC. The drain of PMOS transistor M52, one end of resistor R0, and the drain of NMOS transistor M56 are connected to node B. The other end of resistor R0, the other end of capacitor C9, and the input of Schmitt trigger Y8 are connected. The output of Schmitt trigger Y8 is connected to the input of NOT gate Y9. The output of NOT gate Y9 is connected to the gate of LDPMOS high-voltage transistor D6 and the input of NOT gate Y10. The output of NOT gate Y10 is connected to the gate of LDPMOS high-voltage transistor D7. The drain of LDPMOS high-voltage transistor D6 is connected to the drain of LDNMOS high-voltage transistor D8. The drain of LDPMOS high-voltage transistor D7 is connected to the drain of LDNMOS high-voltage transistor D9. The drain of LDNMOS transistor D8 and the gate of LDNMOS transistor D9 are connected to the enable signal EN. The source of LDNMOS transistor D8 is connected to the drain of NMOS transistor M57, the gate of NMOS transistor M58, and the gate of NMOS transistor M61 at node C. The source of LDNMOS transistor D9 is connected to the drain of NMOS transistor M58, the gate of NMOS transistor M57, and the gate of NMOS transistor M62 at node D. The source of PMOS transistor M59 and the source of PMOS transistor M60 are connected to the power supply VDD. The gate of PMOS transistor M59 is connected to the drain of PMOS transistor M60, the input of Schmitt trigger Y11, and the drain of NMOS transistor M62 at node F.The gate of PMOS transistor M60 is connected to the drain of PMOS transistor M59 and the drain of NMOS transistor M61 at node E. The sources of NMOS transistors M57, M58, M61, and M62 are grounded. The output of Schmitt trigger Y11 is connected to the input of NOT gate Y12. The output of NOT gate Y12 serves as the output of the setup indicator module, generating the charge pump setup completion indicator signal CP_OK.

[0037] PMOS transistors M1, M51, and M52 form the third PMOS current mirror. NMOS transistors M55 and M56 form the second NMOS current mirror.

[0038] PMOS transistor M51, along with PMOS transistors M52, M53, M54, and NMOS transistors M55 and M56, form a voltage comparator. PMOS transistor M51 is twice the size of PMOS transistor M52, while NMOS transistors M55 and M56 are the same size. When the charge pump enable signal goes high, the charge pump begins to build up, and the charge pump output CP_OUT continuously increases. When the charge pump output CP_OUT is raised to:

[0039] in, It is the drain-source voltage of PMOS transistor M51. It is the gate-source voltage of the PMOS transistor M53. It is the gate-source voltage of the PMOS transistor M54. This is the gate-source voltage of NMOS transistor M55. At this time, NMOS transistors M55 and M56 are turned on. Since the pull-down capability of NMOS transistor M56 is stronger than the pull-up capability of PMOS transistor M52, node B is pulled low to VCC. Resistor R0 and capacitor C9 form a first-order filter to avoid glitches. The low level VCC is output to the gate of LDPMOS high-voltage transistor D6 through Schmitt trigger Y8 and inverter Y9. Its inverted signal is output to the high level CP_OUT of LDPMOS high-voltage transistor D7 through inverter Y10. Since the sources of LDPMOS high-voltage transistors D6 and D7 are both connected to the high-voltage power supply CP_OUT, LDPMOS high-voltage transistor D6 is turned on, while LDPMOS high-voltage transistor D7 is turned off. Node C is pulled high, NMOS transistor M58 is turned on, node D is pulled low, NMOS transistor M61 is turned on, NMOS transistor M62 is turned off, node E is pulled low to GND, PMOS transistor M60 is turned on, and node F... Pulled up to VDD, the cross-coupled pairs consisting of NMOS transistors M57 and M58 and PMOS transistors M59 and M60 are used to accelerate node establishment through their positive feedback. The high level VDD of node F is passed through Schmitt trigger Y11 and inverter Y12, which makes the charge pump establishment indicator signal CP_OK go high, indicating that the charge pump establishment is complete.

[0040] The overall working principle of the fast-start and adaptive load-carrying charge pump circuit of the present invention is as follows: When the enable EN is low, the charge pump circuit is off; when the enable EN is high, the charge pump operates normally. The pumping capacitor of the cross-coupled charge pump circuit, in conjunction with the clock signal, raises the charge pump output voltage CP_OUT. Ignoring charge loss, based on the above analysis, CP_OUT should eventually stabilize at 4VCC-3HGND. However, the system uses a Zener transistor Z0 to clamp the maximum value of CP_OUT, causing it to be raised to a maximum of VCC+V. Z The target voltage is achieved by connecting multiple charge pumps in series, which lowers the voltage required at the nodes between each stage and increases the setup speed, thereby improving the start-up speed of the charge pump and enabling rapid output of the desired high voltage.

[0041] Furthermore, its adaptive load function is achieved by dynamically changing the current flowing through the LDPMOS high-voltage transistor D3 according to the load: Since the current provided by the NMOS transistor M5 is fixed, when the load increases, CP_OUT is pulled low, and the source of the LDPMOS high-voltage transistor D3 also decreases, reducing the current flowing through D3. This increases the bias current IB_OSC flowing into the oscillator, speeding up the output clock signal frequency and replenishing the charge lost due to the increased load. CP_OUT then rises back to the target value. Conversely, when the load decreases, CP_OUT is charged high, and the source of the LDPMOS high-voltage transistor D3 also rises, increasing the current flowing through D3. This reduces the bias current IB_OSC flowing into the oscillator, slowing down the output clock signal frequency. Its charging capacity is insufficient to replenish the charge lost due to the load. CP_OUT decreases back to the target value. When the load is zero, since NMOS transistors M3 and M5 are the same size, the current flowing through LDPMOS high-voltage transistor D3 is the same as the current flowing through NMOS transistor M5. Therefore, the oscillator bias current IB_OSC only contains a small current source composed of PMOS transistors M14, M15, M16, M17, and M18. This current is the minimum bias current required by the clock generation circuit to maintain the normal operation of the charge pump establishment indicator circuit and to reduce power consumption during pumping. In this way, no matter how the load changes, the system can adaptively output a stable target high voltage. Moreover, due to its adaptive load characteristics, for the same area of ​​pumping capacitor, the load-carrying capacity of the charge pump proposed in this invention is much stronger than that of the traditional charge pump.

[0042] As the output voltage CP_OUT of the charge pump is gradually raised to the target voltage, the charge pump setup is complete when the setup indicator signal CP_OK goes high.

[0043] This invention provides a fast-start and adaptive charge pump circuit. It employs a cross-coupled charge pump structure, completely eliminating the transmission voltage loss caused by the threshold voltage of the diode-connected MOSFET. The invention utilizes a multi-stage series cross-coupled charge pump structure, outputting a voltage with a series stage number far exceeding the target voltage. The target high voltage is obtained through Zener diode clamping, significantly improving the charge pump's startup speed and enabling extremely fast high voltage output. The entire process takes less than 10µs, which is tens of times faster than the setup time of traditional charge pumps. Furthermore, the invention uses a clock whose frequency adapts to load feedback. Increasing the clock frequency enhances the driving capability, meeting the needs of heavy-load scenarios. Compared to traditional charge pumps, it can increase the load-carrying capacity several times over for the same pumping capacitor area.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A fast-starting and self-adapting charge pump circuit, characterized by: The application comprises a loop control module, a clock signal generation module, a cross-coupled charge pump module and a setup indication module. The first output end of the loop control module is connected with the first input end of the setup indication module and generates a bias voltage VBP_H. The second output end of the loop control module is connected with the input end of the clock signal generation module and generates a current IB_OSC. The first output end of the clock signal generation module is connected with the first input end of the cross-coupled charge pump module and generates a clock signal CLK. The second output end of the clock signal generation module is connected with the second input end of the cross-coupled charge pump module and generates a reverse clock signal . The output end of the cross-coupled charge pump module is connected with the second input end of the setup indication module and the input end of the loop control module and generates a target high voltage CP_OUT. The output end of the setup indication module generates a charge pump setup completion indication signal CP_OK.

2. A fast-starting, self-adapting charge-pump circuit according to claim 1, characterized in that: The loop control module comprises NMOS tube M0, PMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, NMOS tube M6, NMOS tube M7, NMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube M12, PMOS tube M13, PMOS tube M14, PMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, LDNMOS high-voltage tube D0, LDNMOS high-voltage tube D1, LDPMOS high-voltage tube D2, LDPMOS high-voltage tube D3, LDNMOS high-voltage tube D4, LDNMOS high-voltage tube D5, capacitor C0, capacitor C1, capacitor C2 and Zener tube Z0, the drain of NMOS tube M0 is connected with one end of reference current source IREF, the gate of NMOS tube M0, the gate of NMOS tube M2, the gate of NMOS tube M3, the gate of NMOS tube M5, the gate of NMOS tube M6, the gate of NMOS tube M7, the gate of NMOS tube M8, the gate of NMOS tube M9 and the gate of NMOS tube M10, the other end of reference current source IREF is connected with power supply VDD, the source of NMOS tube M0, the source of NMOS tube M2, the source of NMOS tube M3, the source of NMOS tube M4, the source of NMOS tube M5 and the source of NMOS tube M10 are grounded, the source of PMOS tube M1, one end of capacitor C0, the cathode of Zener tube Z0 and one end of capacitor C2 are connected and connected with target high voltage CP_OUT as the input end of the loop control module, the drain of PMOS tube M1 is connected with the gate of PMOS tube M1, the other end of capacitor C0 and the drain of LDNMOS high-voltage tube D0 and generates bias voltage VBP_H as the first output end of the loop control module, the gates of LDNMOS high-voltage tube D0, LDNMOS high-voltage tube D1, LDNMOS high-voltage tube D4 and LDNMOS high-voltage tube D5 are connected with enable signal EN, the source of LDNMOS high-voltage tube D0 is connected with the drain of NMOS tube M2, one end of capacitor C1, the source of LDPMOS high-voltage tube D2, the source of PMOS tube M11, the source of PMOS tube M12, the source of PMOS tube M13 and the source of PMOS tube M14 are connected with power supply VCC, the other end of capacitor C1 is connected with the drain of LDPMOS high-voltage tube D2, the gate of LDPMOS high-voltage tube D2, the gate of LDPMOS high-voltage tube D3 and the drain of LDNMOS high-voltage tube D1, the source of LDNMOS high-voltage tube D1 is connected with the drain of NMOS tube M3, the anode of Zener tube Z0 is connected with the source of LDPMOS high-voltage tube D3, the drain of LDPMOS high-voltage tube D3 is connected with the drain of NMOS tube M4, the gate of NMOS tube M4, the source of LDNMOS high-voltage tube D4 and the drain of NMOS tube M5,The other end of the capacitor C2 is connected with the drain of the PMOS transistor M11, the gate of the PMOS transistor M11, the gate of the PMOS transistor M12 and the drain of the LDNMOS high voltage tube D4, the drain of the PMOS transistor M12 is connected with the drain of the PMOS transistor M18 and serves as the output end of the loop control module and generates the current IB_OSC, the drain of the PMOS transistor M13 is connected with the gate of the PMOS transistor M13, the gate of the PMOS transistor M14, the gate of the PMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17, the gate of the PMOS transistor M18 and the drain of the LDNMOS high voltage tube D5, the source of the LDNMOS high voltage tube D5 is connected with the drain of the NMOS transistor M6, the source of the NMOS transistor M6 is connected with the drain of the NMOS transistor M7, the source of the NMOS transistor M7 is connected with the drain of the NMOS transistor M8, the source of the NMOS transistor M8 is connected with the drain of the NMOS transistor M9, the source of the NMOS transistor M9 is connected with the drain of the NMOS transistor M10, the drain of the PMOS transistor M14 is connected with the source of the PMOS transistor M15, the drain of the PMOS transistor M15 is connected with the source of the PMOS transistor M16, the drain of the PMOS transistor M16 is connected with the source of the PMOS transistor M17, the drain of the PMOS transistor M17 is connected with the source of the PMOS transistor M18.

3. A fast-starting, self-adapting charge pump circuit according to claim 2, characterized in that: The NMOS transistor M0, the NMOS transistor M2, the NMOS transistor M3, the NMOS transistor M5, the NMOS transistor M6, the NMOS transistor M7, the NMOS transistor M8, the NMOS transistor M9 and the NMOS transistor M10 constitute a first NMOS current mirror.

4. The start-up fast and self-adapting load current of charge pump circuit according to claim 2, wherein: The PMOS transistor M11 and the PMOS transistor M12 constitute a first PMOS current mirror, the PMOS transistor M13, the PMOS transistor M14, the PMOS transistor M15, the PMOS transistor M16, the PMOS transistor M17 and the PMOS transistor M18 constitute a second PMOS current mirror.

5. The start-up fast and self-adapting load current charge pump circuit of claim 1, wherein: The clock signal generation module includes PMOS transistors M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, M29, and M30; a D flip-flop (DFF); NOR gates Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7; and PMOS transistors M31, M32, M33, M34, M35, and M6.

36. The sources of PMOS transistors M37, M38, M19, M23, M25, M27, M29, M31, M33, M35, and M37 are connected to the power supply VCC. The gate of PMOS transistor M19 is connected to the gate of NMOS transistor M22 and the Reset terminal of the D flip-flop DFF, which is connected to the enable signal EN. The drain of PMOS transistor M19 is connected to the drain of PMOS transistor M20, the drain of NMOS transistor M21, and PM. The gate of OS transistor M23 is connected to the gate of NMOS transistor M24. The source of PMOS transistor M20 serves as the input terminal of the clock signal generation module and is connected to the current IB_OSC. The gate of PMOS transistor M20 is connected to the gate of NMOS transistor M21, the drain of PMOS transistor M29, the drain of NMOS transistor M30, and the clk terminal of the D flip-flop DFF. The source of NMOS transistor M21 is connected to the drain of NMOS transistor M22. The sources of NMOS transistors M22, M24, M26, M28, M30, and M32 are also connected. The sources of NMOS transistors M34, M36, and M38 are grounded. The drain of PMOS transistor M23 is connected to the drain of NMOS transistor M24, the gate of PMOS transistor M25, and the gate of NMOS transistor M26. The drain of PMOS transistor M25 is connected to the drain of NMOS transistor M26, the gate of PMOS transistor M27, and the gate of NMOS transistor M28. The drain of PMOS transistor M27 is connected to the drain of NMOS transistor M28, the gate of PMOS transistor M29, and the gate of NMOS transistor M30. The Q terminal of D flip-flop DFF is connected to the first input terminal of NOR gate Y0. The second input end of the NOR gate Y1 is connected with the D end of the D flip-flop DFF, and the output end of the NOR gate Y0 is connected with the input end of the NOR gate Y2, the output end of the NOR gate Y2 is connected with the input end of the NOR gate Y4, the output end of the NOR gate Y4 is connected with the input end of the NOR gate Y6 and the first input end of the NOR gate Y1, the output end of the NOR gate Y6 is connected with the gate of the PMOS tube M31 and the gate of the NMOS tube M32, the output end of the NOR gate Y1 is connected with the input end of the NOR gate Y3, the output end of the NOR gate Y3 is connected with the input end of the NOR gate Y5, the output end of the NOR gate Y5 is connected with the input end of the NOR gate Y7 and the second input end of the NOR gate Y0, the output end of the NOR gate Y7 is connected with the gate of the PMOS tube M33 and the gate of the NMOS tube M34, the drain of the PMOS tube M31 is connected with the drain of the NMOS tube M32, the gate of the PMOS tube M35 and the gate of the NMOS tube M36, the drain of the PMOS tube M33 is connected with the drain of the NMOS tube M34, the gate of the PMOS tube M37 and the gate of the NMOS tube M38, the drain of the PMOS tube M35 is connected with the drain of the NMOS tube M36 and generates the clock signal CLK as the first output end of the clock signal generating module, the drain of the PMOS tube M37 is connected with the drain of the NMOS tube M38 and generates the inverse clock signal as the second output end of the clock signal generating module .

6. The fast-start and self-adapting load-banked charge pump circuit of claim 1, wherein: The cross-coupled charge pump module comprises NMOS tube M39, PMOS tube M40, NMOS tube M41, PMOS tube M42, NMOS tube M43, PMOS tube M44, NMOS tube M45, PMOS tube M46, NMOS tube M47, PMOS tube M48, NMOS tube M49, PMOS tube M50, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7 and capacitor C8, one end of the capacitor C3 is connected with one end of the capacitor C5 and one end of the capacitor C7, and when the one end of the capacitor C3 is connected with the clock signal CLK as the first input end of the cross-coupled charge pump module, one end of the capacitor C4 is connected with one end of the capacitor C6 and one end of the capacitor C8, and the inverted clock signal is connected as the second input end of the cross-coupled charge pump module, the other end of the capacitor C3 is connected with the source of the NMOS tube M39, the drain of the PMOS tube M40, the gate of the NMOS tube M41 and the gate of the PMOS tube M42, the other end of the capacitor C4 is connected with the gate of the NMOS tube M39, the gate of the PMOS tube M40, the source of the NMOS tube M41 and the drain of the PMOS tube M42, the drain of the NMOS tube M39 and the drain of the NMOS tube M41 are connected with the power supply VCC, the source of the PMOS tube M40 and the source of the PMOS tube M42 are connected with the drain of the NMOS tube M43 and the drain of the NMOS tube M45, the other end of the capacitor C5 is connected with the source of the NMOS tube M43, the drain of the PMOS tube M44, the gate of the NMOS tube M45 and the gate of the PMOS tube M46, the other end of the capacitor C6 is connected with the gate of the NMOS tube M43, the gate of the PMOS tube M44, the source of the NMOS tube M45 and the drain of the PMOS tube M46, the source of the PMOS tube M44 and the source of the PMOS tube M46 are connected with the drain of the NMOS tube M47 and the drain of the NMOS tube M49, the other end of the capacitor C7 is connected with the source of the NMOS tube M47, the drain of the PMOS tube M48, the gate of the NMOS tube M49 and the gate of the PMOS tube M50, the other end of the capacitor C8 is connected with the gate of the NMOS tube M47, the gate of the PMOS tube M48, the source of the NMOS tube M49 and the drain of the PMOS tube M50, and the source of the PMOS tube M48 and the source of the PMOS tube M50 are connected and generate the target high voltage CP_OUT as the output end of the cross-coupled charge pump module.

7. The fast-start and self-adapting load-banked charge pump circuit of claim 1, wherein: The establishing indication module comprises PMOS M51, PMOS M52, PMOS M53, PMOS M54, NMOS M55, NMOS M56, NMOS M57, NMOS M58, PMOS M59, PMOS M60, NMOS M61, NMOS M62, LDPMOS high voltage tube D6, LDPMOS high voltage tube D7, LDNMOS high voltage tube D8, LDNMOS high voltage tube D9, resistor R0, capacitor C9, Schmitt trigger Y8, NOT gate Y9, NOT gate Y10, Schmitt trigger Y11 and NOT gate Y12, the gate of PMOS M51 is connected with the gate of PMOS M52 and is connected with bias voltage VBP_H as the first input end of the establishing indication module, the source of PMOS M51 is connected with the source of PMOS M52, one end of capacitor C9, the source of LDPMOS high voltage tube D6 and the source of LDPMOS high voltage tube D7 and is connected with target high voltage CP_OUT as the second input end of the establishing indication module, the drain of PMOS M51 is connected with the source of PMOS M53, the gate of PMOS M53 is connected with the drain of PMOS M53 and the source of PMOS M54, the gate of PMOS M54 is connected with the drain of PMOS M54, the drain of NMOS M55, the gate of NMOS M55 and the gate of NMOS M56, the source of NMOS M55 and the source of NMOS M56 are connected with power supply VCC, the drain of PMOS M52 is connected with one end of resistor R0 and the drain of NMOS M56 at node B, the other end of resistor R0 is connected with the other end of capacitor C9 and the input end of Schmitt trigger Y8, the output end of Schmitt trigger Y8 is connected with the input end of NOT gate Y9, the output end of NOT gate Y9 is connected with the gate of LDPMOS high voltage tube D6 and the input end of NOT gate Y10, the output end of NOT gate Y10 is connected with the gate of LDPMOS high voltage tube D7, the drain of LDPMOS high voltage tube D6 is connected with the drain of LDNMOS high voltage tube D8, the drain of LDPMOS high voltage tube D7 is connected with the drain of LDNMOS high voltage tube D9, the gate of LDNMOS high voltage tube D8 and the gate of LDNMOS high voltage tube D9 are connected with enable signal EN, the source of LDNMOS high voltage tube D8 is connected with the drain of NMOS M57, the gate of NMOS M58 and the gate of NMOS M61 at node C, the source of LDNMOS high voltage tube D9 is connected with the drain of NMOS M58, the gate of NMOS M57 and the gate of NMOS M62 at node D, the source of PMOS M59 and the source of PMOS M60 are connected with power supply VDD, the gate of PMOS M59 is connected with the drain of PMOS M60, the input end of Schmitt trigger Y11 and the drain of NMOS M62 at node F,The gate of the PMOS transistor M60 is connected to the drain of the PMOS transistor M59 and the drain of the NMOS transistor M61 at a node E, the source of the NMOS transistor M57, the source of the NMOS transistor M58, the source of the NMOS transistor M61 and the source of the NMOS transistor M62 are grounded, the output of the Schmitt trigger Y11 is connected to the input of the NOT gate Y12, and the output of the NOT gate Y12 generates a charge pump setup completion indication signal CP_OK as the output of the establishment indication module.

8. A fast-starting, self-adapting charge-pump circuit according to claim 7, characterized in that: The PMOS transistor M1, the PMOS transistor M51 and the PMOS transistor M52 constitute a third PMOS current mirror.

9. The fast-start and self-adaptive load-banked charge pump circuit of claim 7, wherein: The NMOS transistor M55 and the NMOS transistor M56 constitute a second NMOS current mirror.

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