A via-in-via substrate stack utilizing a resin plug

Abstract

This invention discloses a via-in-via substrate stack using resin-filled vias, comprising: a glass core layer having a through-hole, the through-hole being filled with a first via-filling ink layer; an add-on structure laminated to the upper and lower surfaces of the glass core layer, the add-on structure comprising at least one layer of dielectric material; a second through-hole located in the add-on structure, the diameter of the second through-hole being smaller than the diameter of the first through-hole, and the second through-hole being coaxially arranged with the first through-hole; the second through-hole being filled with a second via-filling ink layer; the upper and lower surfaces of the substrate are respectively provided with differentiated circuit structures, wherein the line width and line spacing of the upper surface circuit are smaller than those of the lower surface circuit, and the copper thickness of the upper surface circuit is smaller than that of the lower surface circuit; through the asymmetric stack design of the glass core layer and the add-on structure, the differentiated circuit layout, and the coaxial dual-hole filling process, the warping problem caused by the difference in thermal expansion of the substrate is effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging substrate manufacturing technology, and more particularly to a via-in-via substrate stack using resin-filled vias. Background Technology

[0002] As AI chips evolve towards higher computing power, larger size, and higher power consumption, the symmetrical stacked design of traditional ball grid array (BGA) packaging substrates is gradually revealing the following shortcomings:

[0003] 1. Warping and Deformation: Organic substrates are prone to thermal expansion coefficient mismatch during high temperature and high pressure processes, which can lead to substrate warping, affect the reliability of solder ball connections, and cause pillow effect or cracks.

[0004] 2. Crosstalk problem: In symmetrical stacked structures, the distance between the chip and the PCB is relatively large, which can easily cause crosstalk during high-frequency signal transmission;

[0005] 3. Layer limit: To meet the needs of high-density cabling, the number of layers needs to be increased, which leads to increased costs and increased process complexity.

[0006] The aforementioned defects severely restrict the packaging performance and reliability of high-performance chips. To address these issues, existing technologies urgently need to propose new stacked designs for packaging substrates. Summary of the Invention

[0007] The purpose of this invention is to provide a via-in-via substrate stack using resin-filled vias. Through the asymmetric stack design of the glass core layer and the add-on structure, the differentiated circuit layout, and the coaxial dual-via filling process, the warping problem caused by the difference in thermal expansion of the substrate is effectively reduced, the distance between the chip and the PCB is shortened to avoid crosstalk, and the number of layers required is reduced.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0009] A via-to-via substrate stack using resin-filled vias, comprising:

[0010] A glass core layer having a through-hole, the through-hole being filled with a first plugging ink layer;

[0011] An add-on structure pressed onto the upper and lower surfaces of the glass core layer, the add-on structure comprising at least one layer of dielectric material;

[0012] The second through hole is located in the added-layer structure. The diameter of the second through hole is smaller than that of the first through hole, and the second through hole is coaxially arranged with the first through hole. The second through hole is filled with a second plugging ink layer.

[0013] The upper and lower surfaces of the substrate are respectively provided with differentiated circuit structures, wherein the line width and line spacing of the upper surface are smaller than those of the lower surface, and the copper thickness of the upper surface is smaller than that of the lower surface.

[0014] As a preferred embodiment of the hole-in-hole substrate stacked structure utilizing resin-filled holes described in this invention, wherein:

[0015] The diameter of the first through hole is ≥0.2mm, the diameter of the second through hole is ≤100μm, and the thickness of the glass core layer is ≥1.0mm.

[0016] As a preferred embodiment of the hole-in-hole substrate stacked structure utilizing resin-filled holes described in this invention, wherein:

[0017] The thickness of the first and second through-hole plugging inks after curing is 10~50μm, and the pore diameter of the first through-hole is 400μm, and the pore diameter of the second through-hole is 100μm.

[0018] As a preferred embodiment of the hole-in-hole substrate stacked structure utilizing resin-filled holes described in this invention, wherein:

[0019] The line width / spacing of the upper surface layer is 8 / 10 μm, and the copper thickness is 12 μm;

[0020] The line width / spacing of the lower surface layer is 50 / 50μm, and the copper thickness is 35μm.

[0021] As a preferred embodiment of the hole-in-hole substrate stacked structure utilizing resin-filled holes described in this invention, wherein:

[0022] The dielectric material of the added-layer structure is at least one of ABF or Prepreg, and the thickness of the dielectric material after single-layer lamination is ≥50μm.

[0023] A method for fabricating a through-hole substrate stack using resin-plugged vias, comprising the following steps:

[0024] Step S1: Open a first through hole in the glass substrate, fill it with first hole-plugging ink and cure it to obtain a pretreated glass core layer;

[0025] Step S2: Press the glass core layer and the dielectric material together to form an added-layer structure, and open a second through hole at the position corresponding to the first through hole;

[0026] Step S3: Fill the second through hole with second plugging ink and remove the overflow from the upper and lower surfaces of the substrate;

[0027] Step S4: Differentiated circuits are fabricated on the upper and lower surfaces of the added-layer structure to produce a semi-finished substrate;

[0028] Step S5: After stacking and pressing the two semi-finished substrates together, separate them to obtain independent asymmetric packaging substrates.

[0029] As a preferred embodiment of the method for fabricating a through-hole substrate stack using resin-plugged vias according to the present invention, wherein:

[0030] In step S2, the second through hole is formed by mechanical drilling or laser melting.

[0031] As a preferred embodiment of the method for fabricating a through-hole substrate stack using resin-plugged vias according to the present invention, wherein:

[0032] In step S3, before filling the second hole-sealing ink, the substrate is electroplated to achieve conductivity between the upper and lower surfaces.

[0033] As a preferred embodiment of the method for fabricating a through-hole substrate stack using resin-plugged vias according to the present invention, wherein:

[0034] In step S5, the dielectric material of the contact layer of the two semi-finished substrates is composed of different dielectric materials.

[0035] As a preferred embodiment of the method for preparing a hole-in-hole substrate stack using resin plugging according to the present invention, in step S4, the differentiated lines are formed by laser blind hole processing.

[0036] The beneficial effects of this invention are:

[0037] This application provides a via-in-via substrate stack using resin-filled vias. Through the asymmetric stack design of the glass core layer and the add-on structure, the differentiated circuit layout, and the coaxial dual-via filling process, it effectively reduces the warping problem caused by the difference in thermal expansion of the substrate, shortens the distance between the chip and the PCB to avoid crosstalk, and reduces the number of layers required. It has the advantages of improving the matching of the substrate's thermal expansion coefficient, improving the stability of high-frequency signal transmission, and reducing process complexity. Attached Figure Description

[0038] Figure 1 This invention provides a schematic diagram of a hole-in-hole substrate stacked structure utilizing resin-filled holes;

[0039] Figure 2 This invention provides a schematic diagram of the fabrication process of a hole-in-hole substrate stack using resin-filled holes. Attached image description:

[0041] 100. Glass core layer; 200. Add-on structure; 300. Circuit structure;

[0042] 110. First through hole; 120. First plug ink layer;

[0043] 210, Dielectric material; 220, Second through-hole; 230, Second plug ink layer. Detailed Implementation

[0044] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0045] In existing technologies, traditional ball grid array (BGA) packaging substrates generally employ a symmetrical stacked design. The difference in thermal expansion coefficients between the upper and lower layers' circuitry and dielectric material 210 leads to frequent substrate warping during high-temperature, high-pressure processes. Furthermore, the larger spacing between the chip and the PCB in symmetrical structures easily generates crosstalk issues during high-frequency signal transmission. In addition, to meet the requirements of high-density wiring, the number of layers needs to be increased, significantly increasing process complexity and cost. For example, in AI chip packaging scenarios, large-size substrates experience localized deformation due to uneven thermal stress distribution, thus affecting solder joint reliability. To address these issues, a new stacked structure needs to be designed to balance thermal stress distribution while optimizing signal transmission paths.

[0046] Therefore, refer to Figure 1 This invention provides a via-in-via substrate stack using resin plugging, comprising: a glass core layer 100 having a through-hole 110, the through-hole 110 being filled with a first plugging ink layer 120; an add-on structure 200 laminated to the upper and lower surfaces of the glass core layer 100, the add-on structure 200 including at least one dielectric material 210; a second through-hole 220 located in the add-on structure 200, the diameter of the second through-hole 220 being smaller than the diameter of the first through-hole 110, and the second through-hole 220 being coaxially arranged with the first through-hole 110; the second through-hole 220 being filled with a second plugging ink layer 230; and differentially designed circuit structures 300 respectively provided on the upper and lower surfaces of the substrate, wherein the line width and line spacing of the circuits on the upper surface are smaller than those on the lower surface, and the copper thickness of the upper surface is smaller than that of the lower surface.

[0047] Specifically, the glass core layer 100 serves as the basic carrier, providing mechanical support. Using glass as the core layer of the packaging substrate eliminates limitations in drilling tools and equipment, allowing for the fabrication of smaller diameter, high-density vias with multiple glass core layer thicknesses. Simultaneously, the ink filling the first via 110 forms a stable interconnect channel. The second via 220 in the add-on structure 200 is coaxially aligned with the first via 110, forming a hierarchical conductive path and avoiding the space occupied by large-diameter vias in wiring. The filling ink can be made of resin material. The upper surface layer employs a fine circuit design to match the requirements of high-frequency signal transmission, while the lower surface layer enhances current carrying capacity through widened line spacing and increased copper thickness. The two circuit layers achieve impedance matching through different dielectric materials 210, forming an asymmetrical signal transmission system.

[0048] Compared to existing technologies, this solution achieves thermal stress balance through the combination of a glass core layer 100 and organic additive materials, naturally forms electromagnetic shielding through a hierarchical via structure, and integrates different functional circuits within the same layer through differentiated circuit design. Through the above technical solutions, this application using a glass core layer 100 effectively alleviates substrate warping issues. Simultaneously, the asymmetric stacked design formed by differentiated circuits effectively reduces impedance abrupt changes in high-frequency signal transmission paths, while the hierarchical via structure reduces the number of layers required to achieve hybrid wiring. The hierarchical via structure optimizes interlayer interconnect density, achieving high-density wiring within a limited number of layers. The asymmetric circuit design also facilitates the design and layout of fan-out circuits, mitigating crosstalk issues caused by the core layer.

[0049] This application further proposes that the diameter of the first through hole 110 is ≥0.2mm, the diameter of the second through hole 220 is ≤100μm, and the thickness of the glass core layer 100 is ≥1.0mm.

[0050] Here, linewidth / spacing refers to the width of the conductor and the distance between adjacent conductors in the same circuit layer, while copper thickness refers to the thickness of the copper layer in the circuit layer. Specifically, the upper surface layer circuitry achieves high-density wiring through smaller linewidths and spacings, thereby reducing the length differences in signal transmission paths and avoiding crosstalk caused by path impedance mismatch during high-frequency signal transmission. At the same time, the thinner copper thickness reduces the weight and thermal expansion coefficient differences of the surface layer circuitry, alleviating local stress concentration on the substrate caused by temperature changes. The lower surface layer circuitry uses wider linewidths and spacings to enhance mechanical support capabilities, while the thicker copper layer improves current carrying capacity and heat dissipation efficiency, ensuring the structural stability of the substrate during the packaging process.

[0051] Compared with existing technologies, this application can effectively reduce the warping deformation of the substrate caused by thermal stress, reduce electromagnetic interference in the high-frequency signal transmission path, and avoid the increase in cost and process complexity caused by excessively increasing the number of layers, thus achieving the high reliability and high integration requirements of high computing power chip packaging substrates.

[0052] This application further proposes that the linewidth / spacing of the upper surface layer is 8 / 10 μm, and the copper thickness is 12 μm; the linewidth / spacing of the lower surface layer is 50 / 50 μm, and the copper thickness is 35 μm. The layered structure formed after the first via-filling ink cures serves to support the glass core layer 100 and isolate it from the external environment. The layered structure formed after the second via-filling ink cures serves to reduce signal transmission loss and enhance mechanical strength. The cured thickness refers to the thickness of the stable layer formed after heat treatment following ink filling; this thickness range can balance the stress distribution within the via and the surface flatness.

[0053] Specifically, L1 on the substrate requires a smaller opening for connecting small solder balls to the chip, while L6 connects to a larger solder ball without requiring a small opening. This design reduces crosstalk from the Core layer. After ink filling, a uniform resin layer is formed through thermosetting, creating a support interface within the vias of the glass core layer 100 and the build-up structure 200. When the cured ink thickness is above 10 μm, it effectively covers the inner walls of the vias and avoids voids caused by insufficient filling; when the thickness is below 50 μm, it prevents surface unevenness caused by ink overflow or excessive accumulation. This thickness range allows the resin layer to form a stable bond with the dielectric material 210 during thermosetting, while reducing localized stress concentration caused by thickness differences.

[0054] Compared with the prior art, this application solves the problems of substrate warping and circuit processing defects caused by uneven resin layer thickness, reduces the risk of interlayer peeling caused by ink shrinkage or expansion, and ensures the processing compatibility between high-density circuit areas and thick copper layers.

[0055] This application further proposes that the thickness of the first and second via-filling inks after curing is 10~50μm. The thickness of the dielectric material 210 after single-layer lamination is defined as the actual thickness of the material after the lamination process, which can be achieved by adjusting the initial thickness of the prepreg and the lamination parameters. This thickness control ensures the mechanical support of the interlayer structure.

[0056] Specifically, when ABF is used as the dielectric material 210 in the add-on structure 200, its low dielectric loss characteristics can effectively reduce energy loss during high-speed signal transmission, while its thin film morphology facilitates more precise circuit fabrication. By setting the thickness of the single-layer dielectric material 210 to no less than 50 μm, the reliability of interlayer insulation is ensured, and sufficient physical support space is provided for subsequent circuit fabrication, avoiding the process complexity caused by the stacking of multiple thin dielectric layers.

[0057] Compared to existing technologies, traditional solutions typically use a single type of dielectric material (210) with unclear layer thickness control, resulting in significant high-frequency signal attenuation or insufficient mechanical strength. This solution, however, utilizes differentiated applications of ABF and Prepreg to enhance structural strength while ensuring signal integrity. Combined with clear thickness control standards, it offers significant advantages in reducing interlayer thermal expansion differences.

[0058] Through the above technical solution, this application effectively solves the problem of thermal stress concentration caused by insufficient dielectric layer thickness in high-performance chip packaging, and simultaneously improves the quality of high-frequency signal transmission through the optimized combination of dielectric material 210. In specific implementation, the high-density wiring capability of ABF material reduces the number of layers required.

[0059] This application further proposes that the dielectric material 210 of the add-on structure 200 is at least one of ABF or Prepreg, and the thickness of the dielectric material 210 after single-layer lamination is ≥50μm. ABF is suitable for high-frequency signal transmission scenarios and can realize the fabrication of micro-circuits. The thickness of the dielectric material 210 after single-layer lamination is defined as the actual thickness of the material after the lamination process, which can be achieved by adjusting the initial thickness of the prepreg and the lamination parameters. This thickness control ensures the mechanical support of the interlayer structure.

[0060] Specifically, when ABF is used as the dielectric material 210 in the add-on structure 200, its low dielectric loss characteristics can effectively reduce energy loss during high-speed signal transmission, while its thin film morphology facilitates more precise circuit fabrication. By setting the thickness of the single-layer dielectric material 210 to no less than 50 μm, the reliability of interlayer insulation is ensured, and sufficient physical support space is provided for subsequent circuit fabrication, avoiding the process complexity caused by the stacking of multiple thin dielectric layers.

[0061] Compared with the prior art, this application effectively solves the problem of thermal stress concentration caused by insufficient dielectric layer thickness in high computing power chip packaging, and improves the quality of high frequency signal transmission through the optimized combination of dielectric material 210.

[0062] Reference Figure 2This application proposes a method for fabricating a through-hole substrate stack using resin-filled vias, which is used to manufacture the aforementioned through-hole substrate stack using resin-filled vias, comprising the following steps: Step S1, forming a first through-hole 110 in a glass substrate, filling it with a first via-filling ink and curing it to obtain a pretreated glass core layer 100; Step S2, pressing the glass core layer 100 with a dielectric material 210 to form a layered structure 200, and forming a second through-hole 220 at a position corresponding to the first through-hole 110; Step S3, filling the second through-hole 220 with a second via-filling ink, and removing excess material from the upper and lower surfaces of the substrate; Step S4, fabricating differentiated circuits on the upper and lower surfaces of the layered structure 200 to form a semi-finished substrate; Step S5, stacking and pressing the two semi-finished substrates together and then separating them to obtain independent asymmetric packaging substrates.

[0063] The first through-hole 110 refers to a through-hole structure formed on the glass substrate, which can be represented as a TGV through-hole. It can be achieved through laser drilling or chemical etching processes. The first plugging ink, after curing, is used to support the structural stability of the glass core layer 100. The add-on structure 200 consists of at least one layer of dielectric material 210, which can be formed using ABF or Prepreg materials through a lamination process. Differentiated circuitry refers to conductive lines with different linewidths, spacings, and copper thicknesses formed on the upper and lower surfaces of the substrate.

[0064] Specifically, the glass core layer 100, after forming a mechanical support structure by filling with resin ink, is laminated with the dielectric material 210 to form a composite substrate. The second through-hole 220 is coaxially formed with the first through-hole 110 and is filled with secondary resin to form a hole-in-hole structure. The upper and lower surface layer circuits adopt an asymmetrical design, which is achieved during the manufacturing process through pattern transfer with different line widths and spacings and differentiated electroplating parameters.

[0065] Compared with existing technologies, this application can effectively reduce the difference in thermal expansion of the substrate during high-temperature lamination and suppress substrate warping deformation. The asymmetric circuit structure 300 design reduces the path length of high-frequency signal transmission and reduces the risk of signal crosstalk. The symmetric lamination and splitting process, while ensuring the accuracy of the circuit layers, achieves the production of double-sided asymmetric substrates in a single lamination, simplifying the production process.

[0066] This application further proposes that in step S2, the second through-hole 220 is formed by mechanical drilling or laser ablation, and the diameter of the first through-hole 110 is 400 μm, while the diameter of the second through-hole 220 is 100 μm. Mechanical drilling refers to a processing method that forms a through-hole by rotating a drill bit. Laser ablation refers to using a high-energy laser beam to locally melt and vaporize the material to form a through-hole. The first through-hole 110 (TGV through-hole) refers to a through-hole structure penetrating the glass core layer 100, which can be formed by chemical etching or laser processing. Its diameter directly affects the lamination compatibility of the subsequent add-on structure 200. The second through-hole 220 refers to a secondary through-hole opened in the add-on structure 200, and its diameter must be smaller than that of the TGV through-hole. Specifically, different diameter hole-in-hole structures can be achieved through staged processing. Specifically, after the glass core layer 100 and the dielectric material 210 are laminated, the drilling method is selected based on the thickness of the add-on structure 200 and the characteristics of the dielectric material 210.

[0067] Compared with existing technologies, this application solves the warping problem of high-performance chip packaging substrates caused by differences in thermal expansion coefficients during high-temperature and high-pressure processes. The stepped aperture structure, through a combination of mechanical drilling and laser melting processes, achieves efficient fabrication of vias of different sizes, reducing interlayer stress accumulation. Simultaneously, precise aperture control ensures the alignment accuracy between the add-on structure 200 and the glass core layer 100, avoiding crosstalk problems caused by signal transmission path misalignment, and providing a reliable physical support structure for high-density wiring.

[0068] This application further proposes that, in step S3, before filling the second via with the sealing ink, an electroplating process is performed on the substrate to achieve conductivity between the upper and lower surfaces. The electroplating process refers to the process of forming a conductive metal layer on the substrate surface and via walls through chemical deposition. Its function is to form a stable conductive path before resin filling, reducing the risk of line misalignment due to material expansion differences during subsequent hot-pressing. The conductivity between the upper and lower surfaces refers to the electrical connection formed between the conductive layers at the upper and lower ends of the substrate through metallized vias. Its function is to provide a stable current transmission channel for subsequent differentiated circuits, avoiding impedance discontinuities caused by resin filling.

[0069] Specifically, before filling the second through-hole 220 with resin, the substrate is placed in an electroplating solution environment, where a uniform metal plating layer is formed on the inner wall of the through-hole and the surface of the substrate through a chemical reduction reaction. This metal layer covers the interface area between the glass core layer 100 and the build-up structure 200, and can compensate for the thermal expansion differences between the different materials during high-temperature pressing. Through the pre-established conductive path, the subsequently filled resin material only serves as a structural support medium and will not affect the already formed metal interconnect network.

[0070] Compared with existing technologies, this application effectively solves the problem of internal stress concentration caused by the thermal expansion difference of multilayer materials in the substrate, while ensuring reliable electrical connection between high-density lines and thick copper lines. The metal plating layer can play a buffering role during the high-temperature pressing stage, suppressing the misalignment tendency between the glass core layer 100 and the added-layer structure 200, thereby avoiding signal transmission failures caused by structural deformation.

[0071] This application further proposes that in step S5, the dielectric material 210 of the contact layer of the two semi-finished substrates is composed of different dielectric materials 210. Compared with the prior art, traditional symmetrical stacked structures usually use a single dielectric material 210, resulting in a large difference in the thermal expansion coefficient between layers, which can easily cause the overall substrate to warp. By selecting materials differently, such as ABF and PP, it is possible to reduce interlayer stress concentration, improve interlayer bonding strength, and avoid signal transmission loss or structural deformation caused by the single material properties.

[0072] This application further proposes that in step S4, the differentiated circuitry is formed by laser blind via fabrication. The differentiated circuitry refers to conductive lines with different linewidths, spacings, and copper thicknesses on the upper and lower surfaces of the substrate. Specifically, this can be achieved by adjusting the laser parameters and mask pattern to control the circuitry precision. Its function is to reduce thermal stress accumulation through an asymmetric structure, while simultaneously meeting the dual requirements of high-frequency signal transmission and mechanical support. Laser blind via fabrication refers to the technique of using a high-energy laser beam to ablate and form micro-holes on the surface of the dielectric material 210.

[0073] Specifically, when fabricating differentiated circuitry on the surface of the add-on structure 200, a blind via structure is first formed by ablation of the substrate material using a laser beam. Subsequently, chemical copper plating and electroplating processes are performed to fill the blind vias and form interconnects. By adjusting the laser energy density and scanning path, finer linewidths and denser spacing can be formed on the upper surface of the same substrate, while supporting lines with greater linewidth and copper thickness can be formed on the lower surface. This process avoids the material thermal expansion differences caused by traditional full-board etching through precise localized processing, while the non-contact nature of laser processing reduces mechanical impact on the substrate stack.

[0074] Compared with existing technologies, this application can effectively reduce the risk of substrate warping during high-temperature lamination, and shorten the signal transmission path and reduce signal crosstalk through asymmetric circuit design. In addition, the laser blind via processing avoids the multiple lamination steps required for traditional interlayer conduction, simplifies the fabrication process of high-density circuits, and reduces manufacturing costs.

[0075] Those skilled in the art will understand that embodiments of the present invention can provide methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0076] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A via-hole substrate stack using resin-filled holes, characterized in that, include: A glass core layer (100) has a through-hole (110) and the through-hole (110) is filled with a first plug ink layer (120). The layered structure (200) is pressed onto the upper and lower surfaces of the glass core layer (100), and the layered structure (200) includes at least one layer of dielectric material (210). The second through hole (220) is located in the added layer structure (200). The diameter of the second through hole (220) is smaller than that of the first through hole (110), and the second through hole (220) is coaxially arranged with the first through hole (110). The second through hole (220) is filled with a second plug ink layer (230). The upper and lower surfaces of the substrate are respectively provided with differentiated circuit structures (300), wherein the line width and line spacing of the upper surface circuit are smaller than those of the lower surface circuit, and the copper thickness of the upper surface circuit is smaller than that of the lower surface circuit.

2. The through-hole substrate stack structure utilizing resin-filled holes as described in claim 1, characterized in that: The diameter of the first through hole (110) is ≥0.2mm, the diameter of the second through hole (220) is ≤100μm, and the thickness of the glass core layer (100) is ≥1.0mm.

3. The through-hole substrate stack structure utilizing resin-filled holes according to claim 2, characterized in that: The thickness of the first and second through-hole inks after curing is 10~50μm, and the diameter of the first through-hole (110) is 400μm, and the diameter of the second through-hole (220) is 100μm.

4. The through-hole substrate stack structure utilizing resin-filled holes as described in claim 1, characterized in that: The line width / spacing of the upper surface layer is 8 / 10 μm, and the copper thickness is 12 μm; The line width / spacing of the lower surface layer is 50 / 50μm, and the copper thickness is 35μm.

5. The through-hole substrate stack structure utilizing resin-filled holes according to claim 1, characterized in that: The dielectric material (210) of the layered structure (200) is at least one of ABF or Prepreg, and the thickness of the dielectric material (210) after single-layer lamination is ≥50μm.

6. A method for fabricating a through-hole substrate stack using resin-plugged vias, used to manufacture the through-hole substrate stack using resin-plugged vias according to any one of claims 1 to 5, characterized in that, Includes the following steps: Step S1: Open a first through hole (110) in the glass substrate, fill it with first plugging ink and cure it to obtain a pretreated glass core layer (100). Step S2: Press the glass core layer (100) and the dielectric material (210) together to form a layered structure (200), and open a second through hole (220) at the position corresponding to the first through hole (110). Step S3: Fill the second through hole (220) with second plugging ink and remove the overflow from the upper and lower surfaces of the substrate; Step S4: Differentiated circuits are fabricated on the upper and lower surfaces of the added-layer structure (200) to form a semi-finished substrate; Step S5: After stacking and pressing the two semi-finished substrates together, separate them to obtain independent asymmetric packaging substrates.

7. The method for fabricating a through-hole substrate stack using resin-plugged vias according to claim 6, characterized in that: In step S2, the second through hole (220) is formed by mechanical drilling or laser melting.

8. The method for preparing a through-hole substrate stack using resin-plugged vias according to claim 6, characterized in that: In step S3, before filling the second hole-sealing ink, the substrate is electroplated to achieve conductivity between the upper and lower surfaces.

9. The method for preparing a through-hole substrate stack using resin-plugged vias according to claim 6, characterized in that: In step S5, the dielectric material (210) of the contact layer of the two semi-finished substrates is composed of different dielectric materials (210).

10. The method for preparing a through-hole substrate stack using resin-plugged vias according to claim 6, characterized in that: In step S4, the differentiated circuit is formed by laser blind hole processing.

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