Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The manufacturing method of the semiconductor device comprises the following steps: sequentially forming a first conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer on one side of a substrate; a dual damascene process is adopted for the second dielectric layer, the second conducting layer and the first dielectric layer, a plurality of holes with the bottoms exposed out of the first conducting layer are formed, and the holes are distributed in an array mode in the first direction and the second direction; and sequentially forming an initial semiconductor layer, an initial gate insulating layer and an initial gate at the side, far away from the substrate, of the second dielectric layer and at the position corresponding to the hole, and removing a part of the initial semiconductor layer, a part of the initial gate insulating layer and a part of the initial gate layer by adopting a chemical mechanical polishing method so as to form a semiconductor layer, a gate insulating layer and a gate. The manufacturing method of the semiconductor device provided by the invention can effectively improve the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, relates to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can effectively improve the performance of the device.

[0005] The embodiments of the present application provide a manufacturing method of a semiconductor device, which comprises: providing a substrate; forming a first conductive layer, a first dielectric layer and a second conductive layer on one side of the substrate in sequence, the first conductive layer extends along a first direction and is spaced apart along a second direction, and the second conductive layer extends along the second direction and is spaced apart along the first direction; manufacturing a second dielectric layer on the side of the second conductive layer away from the substrate; adopting a double-damascene process on the second dielectric layer, the second conductive layer and the first dielectric layer to form a plurality of holes with the bottom exposed to the first conductive layer, and the holes are arrayed along the first direction and the second direction; depositing an initial semiconductor layer on the second dielectric layer, the initial semiconductor layer covers the second dielectric layer and covers the side wall and bottom wall of the holes, and does not fill the holes; depositing an initial gate insulating layer on the initial semiconductor layer, the initial gate insulating layer covers the initial semiconductor layer and does not fill the holes; depositing an initial gate layer on the initial gate insulating layer, the initial gate layer covers the initial gate insulating layer and fills the holes; adopting a chemical mechanical polishing method to remove part of the initial semiconductor layer, part of the initial gate insulating layer and part of the initial gate layer, and retaining the initial semiconductor layer, the initial gate insulating layer and the initial gate layer at the positions of the holes to form the semiconductor layer, the gate insulating layer and the gate.

[0006] In some embodiments, the double-Damascene process is used to form the second dielectric layer, the second conductive layer and the first dielectric layer, including: forming a hard mask layer and a first photoresist layer on the side of the second dielectric layer away from the substrate, the hard mask layer covering the second dielectric layer, and the first photoresist layer having a plurality of first openings, the first openings having a projection on the substrate overlapping the projection of the first conductive layer on the substrate; forming a first opening through the first conductive layer using the first photoresist layer as a mask and an etching process; forming a second photoresist layer covering the hard mask layer after the first opening is formed, and the second photoresist layer having a second opening at the position of the first opening, the second opening having an outer contour larger than that of the first opening; forming a second opening through the second conductive layer using the second photoresist layer as a mask and an etching process, the second opening being in communication with the first opening, and the first opening and the second opening forming the hole.

[0007] In some embodiments, the chemical mechanical polishing method is used to remove part of the initial semiconductor layer, part of the initial gate insulating layer and part of the initial gate layer, including: polishing the initial semiconductor layer, the initial gate insulating layer and the initial gate layer using a polishing liquid to form the semiconductor layer, the gate insulating layer and the gate at the position of the hole; wherein: the polishing rate of the polishing liquid on the initial semiconductor layer and the initial gate insulating layer is greater than that on the initial gate, so that the surface of the gate formed protrudes from the surface of the second dielectric layer.

[0008] In some embodiments, the material of the semiconductor layer is indium gallium zinc oxide; the material of the gate is indium zinc oxide, or titanium nitride, or indium zinc oxide and titanium nitride; the material of the gate insulating layer is a high-k dielectric layer.

[0009] The embodiments of the present application provide a semiconductor device formed by any of the above embodiments, including: a substrate; a first conductive layer located on one side of the substrate, extending in a first direction and spaced apart in a second direction; a second conductive layer located on the side of the first conductive layer away from the substrate, extending in the second direction and spaced apart in the first direction; a first dielectric layer located between the first conductive layer and the second conductive layer; a second dielectric layer located on a side of the second conductive layer away from the substrate; a plurality of holes arrayed along the first direction and the second direction, each of the holes penetrating the second dielectric layer, the second conductive layer and the first dielectric layer to expose the first conductive layer; a gate located in the hole; a gate insulating layer located in the hole and covering a side wall and a bottom wall of the gate; a semiconductor layer located in the hole and covering a side wall and a bottom wall of the gate insulating layer, and in contact with the first conductive layer, the first dielectric layer, the second conductive layer and the second dielectric layer, respectively.

[0010] In some embodiments, the gate has a T-shaped cross section perpendicular to the substrate. An angle between a side wall of the gate and a plane where the substrate is located is 70 degrees to 90 degrees. A transistor includes the gate, the semiconductor layer and the gate insulating layer, and the transistor is arrayed along the first direction and the second direction.

[0011] In some embodiments, a surface of the semiconductor layer is flush with a surface of the second dielectric layer, a surface of the gate insulating layer is flush with the surface of the second dielectric layer, and a surface of the gate protrudes from the surface of the second dielectric layer.

[0012] In some embodiments, at a position corresponding to the hole, along the second direction, an opening size of the second dielectric layer is a first size, an opening size of the second conductive layer is a second size, and an opening size of the first dielectric layer is a third size. The second size is equal to the third size, and the first size is greater than the second size.

[0013] In some embodiments, the semiconductor device further includes a third dielectric layer located between the substrate and the first conductive layer and covering the substrate. The material of the first dielectric layer, the material of the second dielectric layer and the material of the third dielectric layer are the same.

[0014] Embodiments of the present application provide an electronic device including the semiconductor device described in any of the above embodiments.

[0015] The technical solutions provided by the embodiments of the present application have at least the following beneficial effects: In the semiconductor device fabrication method provided in this application embodiment, a hole is formed on the second dielectric layer, the second conductive layer, and the first dielectric layer using a double damask process. The shape of the hole is the same as the shape of the gate to be formed. In this application embodiment, the shape of the gate to be formed is formed by using a patterning process on the second dielectric layer, the second conductive layer, and the first dielectric layer, and the gate can be formed by using a chemical mechanical polishing method. There is no need to perform a patterning process (including etching process) on the film layer for forming the gate. Therefore, the production cost can be reduced, and the tilt angle of the formed gate can reach a right angle or a near right angle, thereby improving the performance of the semiconductor device.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A flowchart illustrating a method for fabricating a semiconductor device, as provided in an embodiment of this application; Figures 2-9 This application provides a schematic diagram illustrating the structure at different stages of semiconductor device fabrication. Figure 10 This is a top view of a semiconductor device provided in an embodiment of this application.

[0018] Figure label: 111-Substrate; 112-First conductive layer; 113-First dielectric layer; 114-Second conductive layer; 115-Second dielectric layer; 116-Third dielectric layer; 117-Hard mask layer; 118-First photoresist layer; 1181-First opening; 119-First aperture; 120-Second photoresist layer; 1201-Second opening; 121-Hole; 122-Initial semiconductor layer; 123-Initial gate insulating layer; 124-Initial gate layer; 125-Semiconductor layer; 126-Gate insulating layer; 127-Gate; 131-Bit line; 132-Word line. Detailed Implementation

[0019] This application is described in detail below. Examples of embodiments of this application are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Furthermore, detailed descriptions of known technologies that are unnecessary for the features of this application are omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0021] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0022] Semiconductor devices, such as memory devices, include multiple transistors. Each transistor includes a semiconductor layer, a source, a drain, and a gate. The semiconductor layer can be made of indium gallium zinc oxide (IGZO), and the gate can be made of indium zinc oxide (IZO) or titanium nitride (TiN). The gate is formed by deposition followed by etching.

[0023] The etching of IZO thin films requires special etching equipment, and the tilt angle of the gate sidewall formed after etching can only reach a maximum of 85 degrees. This is not conducive to improving the performance of semiconductor devices, and the use of special etching equipment will lead to higher production costs.

[0024] To address the aforementioned issues, this application provides a novel method for fabricating transistor gates. This method applies a double damask process to the gate fabrication process and combines it with a chemical mechanical polishing (CMP) method to form the gate. When fabricating the gate using this method, no special etching equipment is required, which can reduce production costs. Furthermore, the tilt angle of the fabricated gate can reach a right angle or near a right angle, thereby improving the performance of the semiconductor device.

[0025] This application provides a semiconductor device, which can be a memory or other type of integrated circuit. Taking a memory as an example, the memory can be a 3D DRAM.

[0026] The embodiments of this application will now be described with reference to the accompanying drawings.

[0027] This application provides a method for fabricating a semiconductor device, such as... Figure 1 As shown, the manufacturing method includes: S101, Provide a substrate; S102. A first conductive layer, a first dielectric layer and a second conductive layer are sequentially formed on one side of the substrate. The first conductive layer extends along a first direction and is spaced apart along a second direction. The second conductive layer extends along a second direction and is spaced apart along the first direction. The first direction and the second direction intersect. S103. A second dielectric layer is formed on the side of the second conductive layer away from the substrate; S104. The second dielectric layer, the second conductive layer and the first dielectric layer are processed by a double damask process to form a number of holes with the bottom exposed to the first conductive layer. The holes are distributed in an array along the first direction and the second direction. S105. Deposit an initial semiconductor layer on the second dielectric layer. The initial semiconductor layer covers the second dielectric layer and covers the sidewalls and bottom wall of the hole, but does not fill the hole completely. S106. Deposit an initial gate insulating layer on the initial semiconductor layer, wherein the initial gate insulating layer covers the initial semiconductor layer but does not fill the vias; S107. Deposit an initial gate layer on the initial gate insulating layer, the initial gate layer covering the initial gate insulating layer and filling the vias; S108. A portion of the initial semiconductor layer, a portion of the initial gate insulating layer, and a portion of the initial gate layer are removed by chemical mechanical polishing, while retaining the initial semiconductor layer, the initial gate insulating layer, and the initial gate layer at the hole location, in order to form a semiconductor layer, a gate insulating layer, and a gate.

[0028] It should be noted that the substrate can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or it can be a glass substrate or a ceramic substrate, or it can be other types of substrates. In the embodiments of this application, the substrate can be a silicon substrate; the substrate can provide support for the film layer to be fabricated subsequently.

[0029] It should be noted that the cross-sectional shape of the hole formed by the double damask process along the direction perpendicular to the substrate is T-shaped, that is, the hole has a first part away from the substrate and a second part close to the substrate, and the size of the first part is larger than the size of the second part.

[0030] It should be noted that the principle of chemical mechanical polishing (CMP) is a processing technology that combines chemical etching and mechanical removal. In the embodiments of this application, when forming semiconductor layers, gate insulating layers and gates using chemical mechanical polishing, the initially formed semiconductor layers, gate insulating layers and gates can be polished by a combination of polishing slurry and physical mechanical polishing to form semiconductor layers, gate insulating layers and gates.

[0031] The semiconductor device fabrication method provided in this application includes using a double damascene process on a second dielectric layer, a second conductive layer, and a first dielectric layer to form a plurality of holes with the bottom exposed to the first conductive layer, and using a chemical mechanical polishing method to sequentially fabricate a semiconductor layer, a gate insulating layer, and a gate at the corresponding positions of the holes on the side of the second dielectric layer away from the substrate. Therefore, in this application embodiment, the fabrication of the gate no longer requires a special etching machine or an etching method. Instead, the double damascene process is applied to the gate fabrication process, and the gate is formed in conjunction with a chemical mechanical polishing method, thereby reducing production costs. Furthermore, the tilt angle of the fabricated gate can reach a right angle or a near right angle, thereby improving the performance of the semiconductor device.

[0032] In the semiconductor device fabrication method provided in this application embodiment, a double damask process is used to form a hole in the second dielectric layer, the second conductive layer, and the first dielectric layer. The shape of the hole is the same as the shape of the gate to be formed. In this way, this application embodiment forms the shape of the gate to be formed by using a patterning process for the second dielectric layer, the second conductive layer, and the first dielectric layer, and then forms the gate by using a chemical mechanical polishing method. It is no longer necessary to perform a patterning process (including etching process) on the film layer for forming the gate, so as to reduce the production cost. Moreover, the tilt angle of the sidewall of the formed gate can reach a right angle or a near right angle, thereby improving the performance of the semiconductor device.

[0033] Specifically, such as Figure 2 As shown, in the semiconductor device fabrication method provided in this application embodiment, a first conductive layer 112, a first dielectric layer 113, and a second conductive layer 114 are first sequentially formed on one side of a substrate 111. The first conductive layer 112 extends along a first direction and is spaced apart along a second direction. The second conductive layer 114 extends along the second direction and is spaced apart along the first direction. The first direction and the second direction intersect, for example, they can be perpendicular to each other. The specific fabrication methods of the first conductive layer 112, the first dielectric layer 113, and the second conductive layer 114 are similar to those in the prior art and will not be described in detail here.

[0034] Next, as Figure 3As shown, a second dielectric layer 115 is formed on the side of the second conductive layer 114 away from the substrate 111. The material of the second dielectric layer 115 can be the same as that of the first dielectric layer 113, and the fabrication method of the second dielectric layer 115 can also be the same as that of the first dielectric layer 113. In addition, before fabricating the first conductive layer 112, a third dielectric layer 116 can be formed on the substrate 111. The third dielectric layer 116 can be formed by physical deposition, for example. The material of the third dielectric layer 116 can also be the same as that of the first dielectric layer 113. The third dielectric layer 116 can serve to insulate the substrate 111 and the first conductive layer 112, and can prevent ions in the first conductive layer 112 from diffusing into the substrate 111.

[0035] In one specific embodiment, a double damask process is used for the second dielectric layer, the second conductive layer, and the first dielectric layer, including: forming a hard mask layer and a first photoresist layer sequentially on the side of the second dielectric layer away from the substrate, the hard mask layer covering the second dielectric layer, the first photoresist layer having a plurality of first openings, the orthographic projection of the first openings on the substrate overlapping the orthographic projection of the first conductive layer on the substrate; using the first photoresist layer as a mask, forming a first opening penetrating to the first conductive layer using an etching process; forming a second photoresist layer, the second photoresist layer covering the hard mask layer after the first opening is formed, and at the location of the first opening, the second photoresist layer having a second opening, the outer contour of the second opening being larger than the outer contour of the first opening; using the second photoresist layer as a mask, forming a second opening penetrating to the second conductive layer using an etching process, the second opening communicating with the first opening, and the first and second openings forming a hole.

[0036] Specifically, such as Figure 3 As shown, a hard mask layer 117 and a first photoresist layer 118 are sequentially formed on the side of the second dielectric layer 115 away from the substrate 111. The hard mask layer 117 covers the second dielectric layer 115. The first photoresist layer 118 has a plurality of first openings 1181. The orthographic projection of the first openings 1181 on the substrate 111 overlaps with the orthographic projection of the first conductive layer 112 on the substrate 111. The first openings 1181 extend along a first direction and are spaced apart along a second direction.

[0037] It should be noted that the orthogonal projection of the hard mask layer 117 onto the substrate 111 overlaps with the substrate. The hard mask layer 117 includes two film layers with different materials. The material of one of the film layers in the mask layer 117 can be selected from materials such as silicon oxynitride (SiON), silicon nitride (SiN), and silicon oxide (SiO2). The specific arrangement of the mask layer 117 is similar to that of the prior art and will not be described in detail here.

[0038] Next, as Figure 3 and Figure 4As shown, using the first photoresist layer 118 as a mask, an etching process is used to form a first opening 119 that penetrates to the first conductive layer 112. The first opening 119 penetrates the hard mask layer 117, the second dielectric layer 115, the second conductive layer 114 and the first dielectric layer 113, exposing the first conductive layer 112.

[0039] After that, as Figure 5 As shown, a second photoresist layer 120 is formed, which covers the hard mask layer 117 after the first opening is formed. At the location of the first opening 119, the second photoresist layer 120 has a second opening 1201, the outer contour of which is larger than the outer contour of the first opening 119. Specifically, the size of the second opening 1201 along the second direction is larger than the size of the first opening 119 along the second direction, and the orthogonal projection area of ​​the second opening 1201 on the substrate 111 covers the orthogonal projection area of ​​the first opening 119 on the substrate 111.

[0040] Next, as Figure 5 and Figure 6 As shown, using the second photoresist layer 120 as a mask, an etching process is used to form a second opening that penetrates to the second conductive layer 114. Then, the second photoresist layer 120 and the hard mask layer 117 are removed. The second opening is connected to the first opening, and the first opening and the second opening form a hole 121. The cross-sectional shape of the hole 121 along the third direction is T-shaped.

[0041] In one specific embodiment, a semiconductor layer, a gate insulating layer, and a gate are sequentially fabricated on the side of the second dielectric layer away from the substrate and at the location corresponding to the hole. This includes: depositing an initial semiconductor layer on the second dielectric layer, the initial semiconductor layer covering the second dielectric layer and covering the sidewalls and bottom wall of the hole, but not filling the hole; depositing an initial gate insulating layer on the initial semiconductor layer, the initial gate insulating layer covering the initial semiconductor layer, but not filling the hole; depositing an initial gate layer on the initial gate insulating layer, the initial gate layer covering the initial gate insulating layer, and filling the hole; and removing a portion of the initial semiconductor layer, a portion of the initial gate insulating layer, and a portion of the initial gate layer using a chemical mechanical polishing method, retaining the initial semiconductor layer, the initial gate insulating layer, and the initial gate layer at the hole location to form the semiconductor layer, the gate insulating layer, and the gate.

[0042] Specifically, such as Figure 6 and Figure 7As shown, after forming the hole 121, an initial semiconductor layer 122 is deposited on the second dielectric layer 115. The initial semiconductor layer 122 covers the second dielectric layer 115 and covers the sidewalls and bottom wall of the hole 121, but does not fill the hole 121. Then, an initial gate insulating layer 123 is deposited on the initial semiconductor layer 122. The initial gate insulating layer 123 covers the initial semiconductor layer 122, but does not fill the hole 121. Then, an initial gate layer 124 is deposited on the initial gate insulating layer 123. The initial gate layer 124 covers the initial gate insulating layer 123 and fills the hole 121. The initial semiconductor layer 122 is connected to the first conductive layer 112 and the second conductive layer 114, respectively. The initial gate insulating layer 123 is used to insulate the initial semiconductor layer 122 and the initial gate layer 124.

[0043] Next, as Figure 8 and Figure 9 As shown, a portion of the initial semiconductor layer 122, a portion of the initial gate insulating layer 123, and a portion of the initial gate layer 124 are removed using a chemical mechanical polishing method, while retaining the initial semiconductor layer 122, the initial gate insulating layer 123, and the initial gate layer 124 at the location of the via 121, to form a semiconductor layer 125, a gate insulating layer 126, and a gate 127. The surface of the formed semiconductor layer 125 is flush with the surface of the second dielectric layer 115, the surface of the formed gate insulating layer 126 is flush with the surface of the second dielectric layer 115, and the surface of the formed gate 127 can be flush with the surface of the second dielectric layer 115 (e.g., ...). Figure 9 As shown), it can also protrude from the second dielectric layer 115 (e.g. Figure 8 As shown, when the surface of the formed gate 127 protrudes beyond the second dielectric layer 115, it is easier to connect with the subsequent metal layer and prevent short circuits.

[0044] In one specific embodiment, the semiconductor layer 125 is made of indium gallium zinc oxide (IGZO); the gate 127 is made of indium zinc oxide (IZO), or titanium nitride (TiN), or a combination of indium zinc oxide (IZO) and titanium nitride (TiN); and the gate insulating layer 126 is made of a high-k dielectric layer.

[0045] It should be noted that the material of the semiconductor layer 125 in this embodiment is not limited to IGZO, but can also be other metal oxides. For example, the material of the semiconductor layer 125 can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, etc., as long as the leakage current of the transistor can meet the requirements. The specific materials can be adjusted according to the actual situation.

[0046] It should be noted that the material of the gate insulating layer 126 is a high-k dielectric layer. For example, the material of the gate insulating layer 126 may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0047] In one specific embodiment, such as Figure 8 As shown, when the surface of the formed gate 127 protrudes beyond the second dielectric layer 115, a portion of the initial semiconductor layer, a portion of the initial gate insulating layer, and a portion of the initial gate layer are removed by a chemical mechanical polishing method. This includes polishing the initial semiconductor layer 122, the initial gate insulating layer 123, and the initial gate layer 124 with a polishing slurry to form a semiconductor layer 125, a gate insulating layer 126, and a gate 127 at the hole location. The polishing rate of the polishing slurry on the initial semiconductor layer 122 and the initial gate insulating layer 123 is greater than that on the initial gate 124, so that the surface of the formed gate 127 protrudes beyond the surface of the second dielectric layer 115.

[0048] Based on the same inventive concept, embodiments of this application provide a semiconductor device fabricated using the semiconductor device fabrication method provided in any of the above embodiments, such as... Figure 8 and Figure 9As shown, it includes: a substrate 111, a first conductive layer 112, a second conductive layer 114, a first dielectric layer 113, a second dielectric layer 115, a gate 127, a gate insulating layer 126, and a semiconductor layer 125; the first conductive layer 112 is located on one side of the substrate 111, extends along a first direction and is spaced apart along a second direction; the second conductive layer 114 is located on the side of the first conductive layer 112 away from the substrate 111, extends along the second direction and is spaced apart along the first direction; the first dielectric layer 113 is located between the first conductive layer 112 and the second conductive layer 114; the second dielectric layer 115 is located between the second conductive layer 111 and the second conductive layer 114. 14. On the side away from the substrate 111; a plurality of holes 121 are arrayed along the first direction and the second direction, and each hole 121 penetrates the second dielectric layer 115, the second conductive layer 114 and the first dielectric layer 113, exposing the first conductive layer 112; a gate 127 is located in the hole 121; a gate insulating layer 126 is located in the hole 121 and covers the sidewall and bottom wall of the gate 127; a semiconductor layer 125 is located in the hole 121 and covers the sidewall and bottom wall of the gate insulating layer 126, and is in contact with the first conductive layer 112, the first dielectric layer 113, the second conductive layer 114 and the second dielectric layer 115 respectively.

[0049] Since the semiconductor device provided in this application embodiment is fabricated using the semiconductor device fabrication method provided in any of the above embodiments, the tilt angle of the fabricated gate sidewall can reach a right angle or approximately a right angle, thereby improving the performance of the semiconductor device.

[0050] In one specific embodiment, the gate 127 formed in this application embodiment has a T-shaped cross-section along the direction perpendicular to the substrate 111; the angle between the sidewall of the gate 127 and the plane where the substrate 111 is located is 70 degrees to 90 degrees; thus, the gate 127 formed in this application embodiment can improve the performance of the semiconductor device.

[0051] This application uses a semiconductor device as an example for illustration, and the planar structure of the fabricated memory is as follows. Figure 10 As shown, the memory includes a plurality of transistors, a plurality of bit lines 131 and a plurality of source lines 132. The transistors include a gate 127, a semiconductor layer 125 and a gate insulating layer 126 formed in the manner described in the embodiments of this application. The transistors are arranged in an array along a first direction and a second direction, and a row of transistors (first direction) shares a bit line 131, that is, the first conductive layer corresponding to a row of transistors can be used as a bit line. A column of transistors (second direction) shares a source line 132, that is, the second conductive layer corresponding to a column of transistors can be used as a source line.

[0052] Specifically, the first conductive layer 112 includes at least one of various conductive materials. For example, the conductive material may include one of the following: a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten, titanium, tantalum, etc.), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0053] Specifically, the material of the second conductive layer 114 can be the same as the material of the first conductive layer 112, and the second conductive layer 114 can also include at least one of various conductive materials.

[0054] Specifically, the materials of the first dielectric layer 113 and the second dielectric layer 115 can be the same, for example, they can be formed from at least one of metal oxides (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide) or perovskite dielectric materials (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT), or include at least one of the above-mentioned materials. The materials of the first dielectric layer 113 and the second dielectric layer 115 can also be formed from at least one of silicon oxide, silicon nitride, or silicon nitride, or include at least one of silicon oxide, silicon nitride, or silicon nitride.

[0055] Specifically, the gate insulating layer 126 may be formed of at least one of a high-k dielectric material, silicon oxide, silicon nitride, or silicon nitride, or may include at least one of a high-k dielectric material, silicon oxide, silicon nitride, or silicon nitride, and may have a single-layer or multi-layer structure. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0056] Specifically, the material of the gate 127 can be indium zinc oxide (IZO), titanium nitride (TiN), or a combination of indium zinc oxide (IZO) and titanium nitride (TiN); the material of the semiconductor layer 125 can be indium gallium zinc oxide (IGZO).

[0057] In one specific embodiment, such as Figure 8 As shown, the surface of the semiconductor layer 125 is flush with the surface of the second dielectric layer 115, the surface of the gate insulating layer 126 is flush with the surface of the second dielectric layer 115, and the surface of the gate 127 protrudes from the surface of the second dielectric layer 115. The protrusion of the gate 127 from the surface of the second dielectric layer 115 facilitates connection with subsequent metal layers and prevents short circuits.

[0058] In one specific embodiment, such as Figure 8 and Figure 9 As shown, at the corresponding position of hole 121 (i.e. Figure 8 and Figure 9 At the location where the gate 127 is formed, along the second direction, the opening size of the second dielectric layer 115 is the first size, the opening size of the second conductive layer 114 is the second size, and the opening size of the first dielectric layer 113 is the third size; the second size and the third size are equal, and the first size is larger than the second size; this structural design forms a double damask structure, which enables the double damask process to be applied to the gate fabrication process, and combined with chemical mechanical polishing to form the gate, thereby reducing production costs.

[0059] In one specific embodiment, such as Figure 8 and Figure 9 As shown, the semiconductor device further includes a third dielectric layer 116, which is located between the substrate 111 and the first conductive layer 112 and covers the substrate 111; the materials of the first dielectric layer 113, the second dielectric layer 115 and the third dielectric layer 116 are the same.

[0060] Based on the same inventive concept, embodiments of this application provide an electronic device, including a semiconductor device as provided in any of the above embodiments.

[0061] The electronic device includes the aforementioned semiconductor device, and therefore has the same beneficial effects as the aforementioned semiconductor device, which will not be repeated here.

[0062] Specifically, electronic devices include storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks.

[0063] In summary, by applying the embodiments of this application, at least the following beneficial effects can be achieved: In the semiconductor device fabrication method provided in this application embodiment, a hole is formed on the second dielectric layer, the second conductive layer, and the first dielectric layer using a double damask process. The shape of the hole is the same as the shape of the gate to be formed. In this application embodiment, the shape of the gate to be formed is formed by using a patterning process on the second dielectric layer, the second conductive layer, and the first dielectric layer, and the gate can be formed by using a chemical mechanical polishing method. There is no need to perform a patterning process (including etching process) on the film layer for forming the gate. Therefore, the production cost can be reduced, and the tilt angle of the formed gate can reach a right angle or a near right angle, thereby improving the performance of the semiconductor device.

[0064] In addition, the surface of the gate of the semiconductor device provided in this application embodiment can protrude from the surface of the second dielectric layer; this design makes it easier to connect with subsequent metal layers and prevent short circuits.

[0065] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0066] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0067] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0068] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: providing a substrate; forming a first conductive layer, a first dielectric layer and a second conductive layer on one side of the substrate in sequence, the first conductive layer extends along a first direction and is spaced along a second direction, the second conductive layer extends along the second direction and is spaced along the first direction; forming a second dielectric layer on the side of the second conductive layer away from the substrate; forming a plurality of holes exposing the first conductive layer by a double-damascene process on the second dielectric layer, the second conductive layer and the first dielectric layer, the holes are arrayed along the first direction and the second direction; depositing an initial semiconductor layer on the second dielectric layer, the initial semiconductor layer covers the second dielectric layer and the sidewall and bottom wall of the holes and does not fill the holes; depositing an initial gate insulating layer on the initial semiconductor layer, the initial gate insulating layer covers the initial semiconductor layer and does not fill the holes; depositing an initial gate layer on the initial gate insulating layer, the initial gate layer covers the initial gate insulating layer and fills the holes; removing part of the initial semiconductor layer, part of the initial gate insulating layer and part of the initial gate layer by a chemical mechanical polishing method, and retaining the initial semiconductor layer, the initial gate insulating layer and the initial gate layer at the positions of the holes to form the semiconductor layer, the gate insulating layer and the gate.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The double-damascene process on the second dielectric layer, the second conductive layer and the first dielectric layer comprises the following steps: forming a hard mask layer and a first photoresist layer on the side of the second dielectric layer away from the substrate in sequence, the hard mask layer covers the second dielectric layer, and the first photoresist layer has a plurality of first openings, the orthogonal projection of the first openings on the substrate overlaps the orthogonal projection of the first conductive layer on the substrate; forming first openings penetrating to the first conductive layer by an etching process with the first photoresist layer as a mask; forming a second photoresist layer, the second photoresist layer covers the hard mask layer after the first openings are formed, and at the positions of the first openings, the second photoresist layer has second openings, the outer contour of the second openings is larger than the outer contour of the first openings; forming second openings penetrating to the second conductive layer by an etching process with the second photoresist layer as a mask, the second openings communicate with the first openings, and the first openings and the second openings form the holes.

3. The method of manufacturing a semiconductor device according to Claim 1, wherein The chemical mechanical polishing method for removing part of the initial semiconductor layer, part of the initial gate insulating layer and part of the initial gate layer comprises the following steps: polishing the initial semiconductor layer, the initial gate insulating layer and the initial gate layer by a polishing liquid to form the semiconductor layer, the gate insulating layer and the gate at the positions of the holes; wherein: the polishing rate of the polishing liquid to the initial semiconductor layer and the initial gate insulating layer is greater than the polishing rate to the initial gate, so that the surface of the gate protrudes from the surface of the second dielectric layer.

4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein The material of the semiconductor layer is indium gallium zinc oxide. The material of the gate is indium zinc oxide, or is titanium nitride, or is indium zinc oxide and titanium nitride; The material of the gate insulation layer is a high-k dielectric layer.

5. A semiconductor device produced by the method according to any one of claims 1 to 4, characterized by Comprise: a substrate; a first conductive layer on one side of the substrate, extending along a first direction and spaced along a second direction; a second conductive layer on a side of the first conductive layer away from the substrate, extending along the second direction and spaced along the first direction; a first dielectric layer between the first conductive layer and the second conductive layer; a second dielectric layer on a side of the second conductive layer away from the substrate; a plurality of holes arrayed along the first direction and the second direction, and each of the holes penetrates the second dielectric layer, the second conductive layer and the first dielectric layer, exposing the first conductive layer; a gate in the hole; a gate insulation layer in the hole and covering the side wall and bottom wall of the gate; a semiconductor layer in the hole and covering the side wall and bottom wall of the gate insulation layer, and respectively in contact with the first conductive layer, the first dielectric layer, the second conductive layer and the second dielectric layer.

6. The semiconductor device of claim 5, wherein, The cross-sectional shape of the gate along the direction perpendicular to the substrate is T-shaped; The angle between the side wall of the gate and the plane of the substrate is 70 to 90 degrees; The transistor comprises the gate, the semiconductor layer and the gate insulation layer, and the transistor is arrayed along the first direction and the second direction.

7. The semiconductor device of claim 6, wherein, The surface of the semiconductor layer is flush with the surface of the second dielectric layer, the surface of the gate insulation layer is flush with the surface of the second dielectric layer, and the surface of the gate protrudes from the surface of the second dielectric layer.

8. The semiconductor device of claim 5, wherein, At the corresponding position of the hole, along the second direction, the opening size of the second dielectric layer is a first size, the opening size of the second conductive layer is a second size, and the opening size of the first dielectric layer is a third size; The second size is equal to the third size, and the first size is greater than the second size.

9. The semiconductor device according to any one of claims 5 to 8, wherein Further comprising a third dielectric layer between the substrate and the first conductive layer, and covering the substrate; The material of the first dielectric layer, the material of the second dielectric layer and the material of the third dielectric layer are the same.

10. An electronic device, comprising: Comprise the semiconductor device as claimed in any one of claims 5 to 9.

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