Manufacturing method of capacitor structure

Abstract

The invention provides a manufacturing method of a capacitor structure. The method comprises the following steps: sequentially forming a first conductive layer, a capacitor dielectric layer and a second conductive layer on a substrate; a protection mask is formed on the second conductive layer before a subsequent processing process in a flash memory device manufacturing process is executed by adding a special photoetching process once. The protective mask shields and protects the capacitor structure in a subsequent processing process, so that the top surface of the capacitor structure is prevented from being affected, and the flatness of the capacitor structure is maintained. According to the method, only one photoetching mask needs to be added, the damage of chemical mechanical planarization and other processes to the flatness of the capacitor structure can be effectively avoided, and therefore the capacitor structure higher in stability and precision is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for manufacturing a capacitor structure. BACKGROUND

[0002] In the field of semiconductor memory technology, non-volatile memory (NVM) is widely used due to its ability to retain data after power-off, and Flash Memory is one of the most important categories. In the manufacturing process of a Flash Memory device, especially for NORD type Flash Memory, the Oxide-Nitride-Oxide (ONO) structure is a key multi-layer dielectric stack. It is usually used as the Inter-Poly Dielectric (IPD) layer between the Floating Gate and the Control Gate, and the excellent charge blocking ability of the silicon nitride layer is used to trap or store charges, so as to realize the writing and erasing of data, and ensure the long-term reliable retention of data.

[0003] Since the film quality, thickness uniformity and interface characteristics of the ONO stack have a decisive influence on the coupling ratio, data retention time, endurance of erasing and writing, and other key performance indicators of the Flash Memory cell, it is crucial to accurately monitor the electrical characteristics of the ONO stack during the production process. A commonly used monitoring method in the industry is to manufacture a test capacitor structure with the same or similar ONO stack as the memory cell in the scribe lane or a specific test area of the chip. By measuring the capacitance value (C-V characteristics), leakage current (I-V characteristics) and other parameters of the test capacitor, the process stability and electrical quality of the ONO film can be effectively evaluated and monitored.

[0004] However, in advanced Flash Memory process platforms (for example, 90 nm node NORD type Flash Memory process), the manufacture of the ONO capacitor for process monitoring faces severe challenges. The existing process flow is extremely complex, involving multiple chemical mechanical planarization (CMP), dry / wet etching, ion implantation and heat treatment steps. When the ONO capacitor structure is integrated into the standard Flash Memory manufacturing process, the capacitor structure will inevitably be affected by these complex process steps.

[0005] For example, CMP process is often used to achieve global planarization, but its inherent "dishing effect" will cause the inconsistent grinding rate in different layout density areas, thus forming a depression on the top electrode surface of the ONO capacitor, destroying its flatness, causing uneven electrode thickness, and further affecting the accuracy of the capacitance measurement. In addition, when performing patterned etching on other areas on the chip (such as logic area or peripheral circuit of memory array), if the ONO capacitor structure is not effectively protected, its top electrode or dielectric layer may be over-etched or damaged, resulting in variation of the capacitor structure, performance degradation or even failure. These process variations ultimately make the manufactured monitoring capacitor structure unstable, low in precision, and the measurement results cannot truly and reliably reflect the real state of the ONO thin film in the core memory unit, bringing great difficulty to process monitoring and yield improvement.

[0006] Therefore, there is an urgent need in the art for a new manufacturing method that can be well compatible with the existing flash memory manufacturing process without significantly increasing the process complexity and cost, and can manufacture an ONO capacitor structure with flat structure, stable performance and high precision to solve the above technical problems. SUMMARY

[0007] The purpose of the present application is to solve the technical problem in the prior art that the test capacitor structure integrated in the complex flash memory manufacturing process is easily affected by other process steps, resulting in uneven structure, unstable performance and low precision, thus failing to effectively monitor the process stability.

[0008] To achieve the above purpose, the present application provides a manufacturing method of a capacitor structure integrated in the manufacturing process of a flash memory device, the method comprising sequentially forming a first conductive layer serving as a lower electrode, a capacitor dielectric layer and a second conductive layer serving as an upper electrode on a substrate, and the method further comprising:

[0009] Step one, forming a protection mask on the second conductive layer by adding a dedicated lithography process in the manufacturing process of the flash memory device;

[0010] Step two, performing subsequent processing technology in the manufacturing process of the flash memory device, wherein the protection mask shields and protects the capacitor structure composed of the first conductive layer, the capacitor dielectric layer and the second conductive layer, so as to keep the top surface of the second conductive layer from being affected by the subsequent processing technology, thereby maintaining the flatness of the second conductive layer;

[0011] Step three, removing the protection mask after the subsequent processing technology is performed;

[0012] Step four, forming a contact structure electrically connected with the first conductive layer and the second conductive layer respectively.

[0013] Preferably, before step one, the manufacturing process of the flash memory device further comprises: sequentially forming a coupling dielectric layer, a first conductive layer, a capacitor dielectric layer, a second conductive layer and a hard mask layer covering the second conductive layer on the substrate.

[0014] Preferably, before step one, the manufacturing process of the flash memory device further comprises: selectively removing the hard mask layer in the capacitor structure region and the peripheral logic device region of the flash memory device by a lithography and etching process to expose the underlying second conductive layer.

[0015] Preferably, the first conductive layer is a floating gate polysilicon layer and the second conductive layer is a control gate polysilicon layer.

[0016] Preferably, the capacitor dielectric layer is an oxide-nitride-oxide stack structure.

[0017] Preferably, in step one, the dedicated lithography process is an I-line lithography process and the protection mask is a photoresist layer.

[0018] Preferably, in step two, the subsequent processing process comprises a dry etching process.

[0019] Preferably, in step two, the subsequent processing process further comprises: etching to remove the coupling dielectric layer, the first conductive layer, the capacitor dielectric layer and the second conductive layer in the peripheral logic device region to expose the substrate.

[0020] Preferably, after step three, the manufacturing process of the flash memory device further comprises: sequentially depositing a gate dielectric layer and a gate polysilicon layer on the exposed substrate in the logic device region and on the second conductive layer in the capacitor structure region.

[0021] Preferably, after depositing the gate polysilicon layer, the manufacturing process of the flash memory device further comprises: depositing a protection mask layer on the gate polysilicon layer.

[0022] Preferably, in step four, forming the contact structure electrically connected to the second conductive layer comprises: performing a one-time patterning etching process to simultaneously form a gate structure in the peripheral logic device region and form an opening in a partial region of the capacitor structure region to lead out the second conductive layer.

[0023] Preferably, in step four, forming the contact structure electrically connected to the first conductive layer comprises the following steps:

[0024] Step A, forming a patterned photoresist layer, wherein the patterned photoresist layer defines an etching region for leading out the first conductive layer in the capacitor structure region;

[0025] Step B, etching through the second conductive layer and the capacitor dielectric layer to expose the first conductive layer with the patterned photoresist layer as a mask.

[0026] Preferably, in step A, the patterned photoresist layer also simultaneously defines an etching region of the flash memory stripe region.

[0027] Preferably, in step B, the etching also simultaneously etches away the hard mask layer in the flash memory strip area.

[0028] Preferably, after performing the patterned etching process and the etching, the method further comprises forming a side wall on the sidewall of the gate structure in the logic device area, on the sidewall of the memory cell in the memory array area of the flash memory device, and on the sidewall of the opening formed by the etching in the capacitor structure area.

[0029] Preferably, after forming the side wall, the method further comprises forming a metal silicide layer on the exposed surface of the first conductive layer, on the exposed surface of the second conductive layer, on the exposed surface of the gate structure in the logic device area, and on the surface of the substrate exposed in the memory array area and the peripheral logic device area of the flash memory device, by using a self-aligned silicidation process.

[0030] Preferably, after forming the metal silicide layer, the method further comprises depositing an interlayer dielectric layer covering the device structure, and forming a contact via structure in the interlayer dielectric layer to electrically connect with the metal silicide layer formed on the first conductive layer and the second conductive layer, respectively.

[0031] Preferably, in step B, the etching is a controlled gate self-aligned contact etching process.

[0032] Preferably, the manufacturing process of the flash memory device is a 90nm NORD type flash memory process flow.

[0033] As described above, the method for manufacturing the capacitor structure of the present application has the following beneficial effects:

[0034] The present application can effectively protect the integrity of the capacitor structure and the flatness of the upper surface by adding only one special photolithography process to form a protection mask in the manufacturing process of the flash memory device, when performing the subsequent complex patterned etching process and the like. The present application avoids the damage to the capacitor structure caused by the dishing effect of the CMP process and other etching processes, and can manufacture a test capacitor with stable structure and higher precision, thereby providing a reliable means for performance monitoring of the flash memory process. Meanwhile, the method of the present application is highly compatible with the existing flash memory process, and the added cost is low, thus having high practical value. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 shows a flowchart of a method for manufacturing a capacitor structure of the present application;

[0036] Figure 2 shows a cross-sectional view of the method for manufacturing a capacitor structure of the present application after forming an initial stack structure in an embodiment;

[0037] Figure 3Fig. 6 shows a cross-sectional view of a capacitor structure after a photoresist layer is formed to define the lower electrode in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0038] Figure 4 Fig. 7 shows a cross-sectional view of a capacitor structure after the hard mask layer is selectively removed in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0039] Figure 5 Fig. 8 shows a cross-sectional view of a capacitor structure after a protective mask layer is formed and a stack etch is performed on the peripheral logic device area in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0040] Figure 6 Fig. 9 shows a cross-sectional view of a capacitor structure after a gate dielectric layer and a gate poly layer are deposited in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0041] Figure 7 Fig. 10 shows a cross-sectional view of a capacitor structure after a protective mask layer is deposited in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0042] Figure 8 Fig. 11 shows a cross-sectional view of a capacitor structure after a photoresist layer is formed to define the gate structure in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0043] Figure 9 Fig. 12 shows a cross-sectional view of a capacitor structure after the gate structure is formed and the upper electrode is formed in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0044] Figure 10 Fig. 13 shows a cross-sectional view of a capacitor structure after a photoresist layer is formed to define the lower electrode in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0045] Figure 11 Fig. 14 shows a cross-sectional view of a capacitor structure after the lower electrode is formed in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0046] Figure 12 Fig. 15 shows a cross-sectional view of a capacitor structure after a sidewall is formed in an embodiment of a method of fabricating a capacitor structure according to the present application;

[0047] Figure 13 Fig. 16 shows a cross-sectional view of a capacitor structure after a protective mask layer is formed and a stack etch is performed on the peripheral logic device area in an embodiment of a method of fabricating a capacitor structure according to the present application; DETAILED DESCRIPTION

[0048] Following, specific embodiments of the present application are described in detail, and the skilled in the art can easily understand other advantages and effects of the present application from the disclosure of the present specification. The present application can also be implemented or applied by other different embodiments, and the details in the present specification can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0049] Referring to Figure 1 , Figure 1 is a flow chart of a method for fabricating a capacitor structure in an embodiment of the present application. The detailed steps of the method will be described in detail below with reference to the device cross-sectional structure schematic diagrams at different process stages shown in Figures 2 to 13 .

[0050] The present application provides a method for fabricating a capacitor structure, which is integrated in the fabrication process of a flash memory device. The method comprises sequentially forming a first conductive layer 103 serving as a lower electrode, a capacitor dielectric layer 104, and a second conductive layer 105 serving as an upper electrode on a substrate 101. The method further comprises:

[0051] In some embodiments, before step one, referring to Figure 2 , the fabrication process of the flash memory device further comprises sequentially forming a coupling dielectric layer 102, the first conductive layer 103, the capacitor dielectric layer 104, the second conductive layer 105, and a hard mask layer 106 covering the second conductive layer 105 on the substrate 101. The substrate 101 is usually a P-type or N-type (100) single crystal silicon substrate doped with boron or phosphorus, or a silicon-on-insulator (SOI) substrate, so as to improve the isolation performance of the device and reduce parasitic effects. The coupling dielectric layer 102 can be a layer of high-quality thermal oxide silicon with low interface defect density, which is grown at high temperature (e.g. 800-1000°C) by dry or wet oxygen method. The hard mask layer 106 is usually a material such as silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON) formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), which has a good etching selectivity ratio relative to oxide and polysilicon, and is used to accurately transfer patterns and protect the underlying stack structure in subsequent patterning and etching processes.

[0052] In some embodiments, the first conductive layer 103 is a floating gate polysilicon layer and the second conductive layer 105 is a control gate polysilicon layer. These conductive layers are typically formed by low pressure chemical vapor deposition (LPCVD) using silane (SiH4) or disilane (Si2H6) as precursors to achieve excellent step coverage and thickness uniformity. Doping can be achieved by subsequent ion implantation (e.g. implanting phosphorous or arsenic ions) and annealing activation of amorphous or polysilicon layers, or by in-situ doping during deposition. Depending on device performance requirements, these conductive layers can also be formed using amorphous silicon or metal gate materials (e.g. titanium nitride TiN, tantalum nitride TaN, tungsten W formed by physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD)) according to process requirements.

[0053] In some embodiments, the capacitor dielectric layer 104 is an oxide-nitride-oxide (ONO) stack structure. This ONO structure is typically formed by a sequential LPCVD process, e.g. the bottom oxide (O) layer can be deposited using tetraethyl orthosilicate (TEOS) as the source gas, the middle nitride (N) layer can be deposited by reacting dichlorosilane (SiH2Cl2) and ammonia (NH3), and the top oxide (O) layer can also be deposited using TEOS. This structure is effective in blocking charge leakage. Of course, the method of the present application is also applicable to protecting capacitor structures using other high-k materials as the capacitor dielectric layer, e.g. hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3) or their composite layers formed by atomic layer deposition (ALD), which is capable of achieving atomic level thickness control and excellent conformality by alternating precursor and reaction gases.

[0054] In some embodiments, prior to step one, please refer to Figure 4 It also includes selectively removing the hard mask layer 106 in the capacitor structure area and the peripheral logic device area of the flash memory device by photolithography and etching processes to expose the underlying second conductive layer 105. This step can use hot phosphoric acid (H3PO4) wet etching, which has high selectivity to silicon nitride and little etching to polysilicon and silicon oxide; or a reactive ion etching (RIE) process based on fluorocarbon compounds (e.g. CF4 / O2 / CHF3). This step prepares for the subsequent formation of a dedicated protection mask directly on the second conductive layer, ensuring that the protection mask can be in good contact with a clean surface.

[0055] Step one, please refer to Figure 5 A dedicated photolithography process is added in the manufacturing flow of the flash memory device to form a protection mask 108 on the second conductive layer 105;

[0056] In some embodiments, in step one, the dedicated photolithography process is an i-line photolithography process, and the protective mask 108 is a photoresist layer. The process includes standard wafer cleaning, adhesion promoter coating, photoresist spin coating, soft bake to remove solvent, exposure by an i-line stepper, and post exposure bake and development. By adding only one relatively low-cost i-line photolithography mask, the sensitive capacitor structure can be completely isolated and protected in the subsequent complex process flow, achieving the effect of significant process optimization at a lower cost. In addition to photoresist, the protective mask can also be other materials that can be temporarily deposited and removed, such as spin-coatable carbon-based hard mask materials.

[0057] In step two, subsequent processing in the flash memory device manufacturing flow is performed, wherein the protective mask 108 shields and protects the capacitor structure composed of the first conductive layer 103, the capacitor dielectric layer 104, and the second conductive layer 105, so that the top surface of the second conductive layer 105 is not affected by the subsequent processing, thereby maintaining the flatness of the second conductive layer 105.

[0058] In some embodiments, in step two, the subsequent processing includes a dry etching process.

[0059] In some embodiments, referring to Figure 3 and Figure 5 , in step two, the subsequent processing further includes: in the peripheral logic device area, etching to remove the coupling dielectric layer 102, the first conductive layer 103, the capacitor dielectric layer 104, and the second conductive layer 105 to expose the substrate 101. Figure 3 In the flash memory area, for example, a patterning process such as forming the word line 107 is shown, while in Figure 5 , a multi-layer etching of the peripheral logic device area is shown. The etching process is usually carried out in an inductively coupled plasma (ICP) etcher or a magnetically enhanced reactive ion etcher, using a multi-step etching recipe: for example, using HBr / Cl2-based plasma to etch the polysilicon layer, and then switching to fluorocarbon gas (such as C4F8 / O2 / Ar) based plasma to etch the dielectric layer, to obtain a highly anisotropic etching profile. Since the capacitor structure is completely covered by the protective mask 108, the upper electrode (second conductive layer 105) and the underlying structure of the capacitor structure are not affected by plasma bombardment or chemical corrosion when deep etching of multiple layers of materials in the peripheral logic area. This fundamentally avoids the possible disc-shaped effect caused by chemical mechanical planarization (CMP) process, as well as the possible surface damage or thickness thinning caused by etching processes in other areas. Ultimately, this method can manufacture a capacitor structure with highly flat and parallel electrode plates, which is very beneficial for ensuring the accuracy and stability of the capacitor measurement, as well as improving the consistency of the device-to-device parameters.

[0060] Step three, after performing the subsequent processing, removing the protection mask 108;

[0061] In some embodiments, referring to Figure 6 After step three, further comprising: sequentially depositing a gate dielectric layer 109 and a gate polysilicon layer 110 on the exposed substrate 101 in the logic device region and on the second conductive layer 105 in the capacitor structure region.

[0062] In some embodiments, referring to Figure 7 After depositing the gate polysilicon layer 110, further comprising: depositing a protection mask layer 111 on the gate polysilicon layer 110.

[0063] Step four, forming contact structures electrically connected to the first conductive layer 103 and the second conductive layer 105 respectively.

[0064] In some embodiments, referring to Figure 8 And Figure 9 In step four, forming the contact structure electrically connected to the second conductive layer 105 comprises: performing a one-time photolithography and etching process to simultaneously form gate structures in the peripheral logic device region and form openings in part of the capacitor structure region to lead out the second conductive layer 105. Figure 8 Fig. 4 shows the use of a patterned photoresist layer 112 to define the etching area, while Figure 9 Fig. 5 shows the structure after etching is completed. This integrated approach of sharing one lithography and etching process simplifies the overall process flow, reduces the number of mask plates used, and helps reduce production costs and shorten manufacturing cycle.

[0065] In some embodiments, in step four, forming the contact structure electrically connected to the first conductive layer 103 comprises the following steps:

[0066] Step A, referring to Figure 10 Forming a patterned photoresist layer 113, wherein the patterned photoresist layer 113 defines an etching area for leading out the first conductive layer 103 in the capacitor structure region;

[0067] In some embodiments, in step A, the patterned photoresist layer 113 also simultaneously defines an etching area for the flash memory strip region.

[0068] Step B, referring to Figure 11 Etching through the second conductive layer 105 and the capacitor dielectric layer 104 to expose the first conductive layer 103, using the patterned photoresist layer 113 as a mask.

[0069] In some embodiments, in step B, the etching also simultaneously etches and removes the hard mask layer 106 in the flash memory strip region.

[0070] In some embodiments, in step B, the etching is a controlled gate self-aligned contact etching process. By precisely controlling the kind and ratio of etching gases, for example, by tuning the plasma chemical environment to a high carbon-fluorine ratio, a high selectivity etching of oxide and nitride over polysilicon can be achieved, ensuring minimal damage to the first conductive layer 103 as the etch stop layer while removing the overlying layers, thus creating a good condition for the subsequent formation of low resistance ohmic contacts.

[0071] In some embodiments, referring to Figure 12 After the patterning and etching processes are performed, a sidewall 114 is formed on the sidewalls of the gate structures in the logic device region, the sidewalls of the memory cells in the memory array region of the flash memory device, and the sidewalls of the openings formed by the etching in the capacitor structure region. The sidewall is formed using a standard process, i.e., a layer of dielectric material (such as silicon nitride or silicon oxide) is first conformally deposited on the entire device surface by chemical vapor deposition (CVD) or the like, and then anisotropic reactive ion etching (RIE) is performed to etch back the dielectric material, which preferentially removes the dielectric material on the horizontal surfaces, leaving only the dielectric material on the vertical sidewalls to form the sidewall structure. The sidewall structure has multiple functions in different regions: in the logic device region, it is used to define the lightly doped drain (LDD) and subsequent source / drain implant regions; in the memory array region, the sidewall protects the stacked gate structure of the memory cells and provides electrical isolation; in the capacitor structure region, it provides lateral electrical isolation and physical protection for the openings.

[0072] In some embodiments, referring to Figure 13After the formation of the sidewall 114, a metal silicide layer 116 is formed on the exposed surface of the first conductive layer 103, the exposed surface of the second conductive layer 105, the exposed surface of the gate structure in the logic device region, and the surface of the substrate 101 exposed in the memory array region and the logic device region of the flash memory device, by a self-aligned silicidation process. The detailed steps of the self-aligned silicidation process (Salicide) can include: first, by a dilute hydrofluoric acid (dHF) wet cleaning or in-situ argon plasma sputter cleaning, to effectively remove the native oxide layer on all exposed silicon surfaces, which is necessary for forming a low resistance interface; then, by a physical vapor deposition (PVD) method, a thin film of metal, such as nickel (Ni), cobalt (Co), or nickel platinum (NiPt) or nickel titanium (NiTi) alloy for improved thermal stability, is deposited on the entire wafer surface; subsequently, a first rapid thermal annealing (RTA) is performed, usually at a lower temperature (e.g., 300-500 °C), to cause the metal to react only with the silicon surfaces in direct contact, forming a high-resistivity metal-rich phase (e.g., Ni2Si); then, by a selective wet etching process, such as using a sulfuric acid-hydrogen peroxide mixture (SPM) or a specific acidic solution, the metal deposited on the dielectric surface that did not participate in the reaction is completely removed; finally, a second RTA is performed at a higher temperature (e.g., 450-600 °C) to drive the phase transition of the metal-rich phase to the final desired stoichiometric stable phase (e.g., NiSi) with low resistivity. The metal silicide layer, with a much lower resistivity than doped polysilicon, its formation can effectively reduce the series resistance of the capacitor electrode and the source-drain contact resistance of the transistor, thereby improving the frequency response characteristics and driving ability of the device.

[0073] In some embodiments, referring to Figure 13After forming the metal silicide layer 116, the process further includes: depositing an interlayer dielectric layer 115 covering the device structure; and forming contact lead-out structures 117 in the interlayer dielectric layer 115 to electrically connect with the metal silicide layer 116 formed on the first conductive layer 103 and the second conductive layer 105, respectively. The interlayer dielectric layer 115 is typically deposited using a high-density plasma chemical vapor deposition (HDP-CVD) method to deposit silicon oxide-based materials, such as undoped silicon glass (USG) or fluorinated silicate glass (FSG), to obtain good trench filling capability, and is subsequently typically required to perform global planarization by chemical mechanical planarization (CMP). The formation of the contact lead-out structure 117 begins with etching a high aspect ratio contact hole in the interlayer dielectric layer 115 using photolithography and reactive ion etching. Next, a multilayer film composed of titanium (Ti) and / or titanium nitride (TiN) is conformally deposited in the contact hole using physical vapor deposition (PVD) or atomic layer deposition (ALD). This multilayer film serves as a barrier layer to prevent tungsten from reacting directly with silicon or silicides and as an adhesion layer to enhance the adhesion of subsequent filler metal. Then, tungsten (W) metal is deposited on the entire wafer surface using chemical vapor deposition (CVD) with tungsten hexafluoride (WF6) as a precursor to completely fill the contact hole. Finally, excess tungsten metal on the wafer surface is removed using a chemical mechanical planarization (CMP) process, leaving tungsten only in the contact hole, thus forming an independent contact plug, which is the final electrical contact structure.

[0074] The method of this invention can be applied to 90nm NORD flash memory process flow. Furthermore, the idea disclosed in this invention—isolation of sensitive test structures by adding a dedicated protective mask—can also be flexibly applied to other more advanced or different types of semiconductor process platforms, exhibiting good scalability.

[0075] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a capacitor structure integrated in a manufacturing flow of a flash memory device, the method comprising forming successively on a substrate (101) a first conductive layer (103) serving as a lower electrode, a capacitor dielectric layer (104) and a second conductive layer (105) serving as an upper electrode, characterized in that, At least comprising: Step one, forming a protection mask (108) on the second conductive layer (105) by adding a dedicated lithography process in the manufacturing process of the flash memory device; Step two, performing subsequent processing in the manufacturing process of the flash memory device, wherein the protection mask (108) shields and protects the capacitor structure composed of the first conductive layer (103), the capacitor dielectric layer (104) and the second conductive layer (105), so that the top surface of the second conductive layer (105) is not affected by the subsequent processing, thereby maintaining the flatness of the second conductive layer (105); Step three, removing the protection mask (108) after the subsequent processing is performed; Step four, forming contact structures respectively electrically connected with the first conductive layer (103) and the second conductive layer (105).

2. The method of manufacturing a capacitive structure according to claim 1, wherein: Before step one, the manufacturing process of the flash memory device further comprises: sequentially forming a coupling dielectric layer (102), the first conductive layer (103), the capacitor dielectric layer (104), the second conductive layer (105) and a hard mask layer (106) covering the second conductive layer (105) on the substrate (101).

3. The method of fabricating a capacitive structure of claim 2, wherein: Before step one, it further comprises: selectively removing the hard mask layer (106) in the capacitor structure region and the peripheral logic device region of the flash memory device by lithography and etching process, to expose the underlying second conductive layer (105).

4. The method of fabricating a capacitive structure of claim 2, wherein: The first conductive layer (103) is a floating gate polysilicon layer, and the second conductive layer (105) is a control gate polysilicon layer.

5. The method of fabricating a capacitive structure of claim 4, wherein: The capacitor dielectric layer (104) is an oxide-nitride-oxide stack structure.

6. The method of fabricating a capacitive structure of claim 1, wherein: In step one, the dedicated lithography process is an I-line lithography process, and the protection mask (108) is a photoresist layer.

7. The method of fabricating a capacitive structure of claim 1, wherein: In step two, the subsequent processing includes a dry etching process.

8. The method of fabricating a capacitive structure of claim 7, wherein: In step two, the subsequent processing further comprises: in the peripheral logic device region, etching to remove the coupling dielectric layer (102), the first conductive layer (103), the capacitor dielectric layer (104) and the second conductive layer (105), to expose the substrate (101).

9. The method of fabricating a capacitive structure of claim 8, wherein: After step three, it further comprises: on the exposed substrate (101) in the peripheral logic device region and the second conductive layer (105) in the capacitor structure region, depositing a gate dielectric layer (109) and a gate polysilicon layer (110) in sequence.

10. The method of fabricating a capacitive structure of claim 9, wherein: After depositing the gate polysilicon layer (110), it further comprises: depositing a protection mask layer (111) on the gate polysilicon layer (110).

11. The method of fabricating a capacitive structure of claim 10, wherein: In step four, forming contact structures electrically connected with the second conductive layer (105) comprises: performing a patterned etching process to simultaneously form gate structures in the peripheral logic device region and form openings in part of the capacitor structure region to lead out the second conductive layer (105).

12. The method of fabricating a capacitive structure of claim 1, wherein: In step four, the forming the contact structure electrically connected with the first conductive layer (103) comprises the following steps: step A, forming a patterned photoresist layer (113), wherein the patterned photoresist layer (113) defines an etching area for leading out the first conductive layer (103) in the capacitor structure region; step B, etching through the second conductive layer (105) and the capacitor dielectric layer (104) with the patterned photoresist layer (113) as a mask to expose the first conductive layer (103).

13. The method of fabricating a capacitive structure of claim 12, wherein: In step A, the patterned photoresist layer (113) also simultaneously defines an etching area of the flash memory strip region.

14. The method of fabricating a capacitive structure of claim 13, wherein: In step B, the etching also simultaneously etches away the hard mask layer (106) in the flash memory strip region.

15. The method of manufacturing a capacitive structure according to claim 11 or 14, characterized in that: After the patterned etching process and the etching are performed, it further comprises forming a side wall (114) on the sidewall of the gate structure in the peripheral logic device region, on the sidewall of the memory cell in the memory array region of the flash memory device, and on the sidewall of the opening formed by the etching in the capacitor structure region.

16. The method of fabricating a capacitive structure of claim 15, wherein: After the side wall (114) is formed, it further comprises forming a metal silicide layer (116) on the exposed surface of the first conductive layer (103), on the exposed surface of the second conductive layer (105), on the exposed surface of the gate structure in the peripheral logic device region, and on the surface of the substrate (101) exposed in the memory array region and the peripheral logic device region of the flash memory device by using a self-aligned silicidation process.

17. The method of fabricating a capacitive structure of claim 16, wherein: After the metal silicide layer (116) is formed, it further comprises depositing an interlayer dielectric layer (115) covering the device structure, and forming a contact leading-out structure (117) in the interlayer dielectric layer (115) to be electrically connected with the metal silicide layer (116) formed on the first conductive layer (103) and the second conductive layer (105) respectively.

18. The method of fabricating a capacitive structure of claim 14, wherein: In step B, the etching is a controlled gate self-aligned contact etching process.

19. The method of fabricating a capacitive structure of claim 1, wherein: The manufacturing process of the flash memory device is a 90nm NORD type flash memory process flow.

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