Method of forming semiconductor device

Abstract

Various examples related to a shallow trench isolation (STI) protection structure formed on an STI region of a nanostructured field effect transistor (NSFET) device are disclosed. The STI protection structure protects the STI region (e.g., a portion directly below the dummy gate structure) during a subsequent selective etch process. The STI protection structure includes a liner layer and a hard mask layer formed on the liner layer. In a first set of examples, the hard mask layer on the liner layer is controlled by various processing steps to achieve different profiles (e.g., concave, convex, or flat) for the upper surface of the STI protection structure. A second set of examples is disclosed for enhancing the quality of the liner layer of the STI protection structure by different plasma processes, thereby making the liner layer more resistant to subsequent etch processes. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers and semiconductor material layers over a semiconductor substrate and patterning each of the material layers using photolithography to form electrical circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the smallest component that can be fabricated, allowing more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that should be addressed. SUMMARY

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure comprises a fin and a layer stack above the fin, wherein the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming shallow trench isolation regions on opposite sides of the fin structure; forming a shallow trench isolation protection structure on an upper surface of the shallow trench isolation regions, comprising: forming a liner layer along a top surface of the layer stack, along sidewalls of the layer stack, and along the upper surface of the shallow trench isolation regions; forming a hard mask layer on the liner layer, wherein the hard mask layer is formed to have a first portion along the top surface of the layer stack, a second portion along the sidewalls of the layer stack, and a third portion along the upper surface of the shallow trench isolation regions, wherein the first and third portions of the hard mask layer have a higher density than the second portion of the hard mask layer; removing the first and second portions of the hard mask layer; and after removing the first and second portions of the hard mask layer, removing the liner layer from the top surface of the layer stack and the sidewalls of the layer stack; after forming the shallow trench isolation protection structure, forming a dummy gate structure above the fin structure and the shallow trench isolation protection structure; forming source / drain regions above the fin and on opposite sides of the dummy gate structure; and after forming the source / drain regions, replacing the dummy gate structure with a replacement gate structure.

[0005] Another embodiment of the present application provides a method of forming a semiconductor device, the method comprising: forming a fin structure protruding above a shallow trench isolation region, wherein the shallow trench isolation region is located above a substrate and on opposite sides of the fin structure, wherein the fin structure comprises a fin and a layer stack above the fin, wherein the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation protection structure on an upper surface of the shallow trench isolation region, comprising: forming a liner layer along a top surface of the layer stack, along sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; forming a hard mask layer on the liner layer, comprising: forming a first material layer on the liner layer; and performing an anisotropic plasma process to process the first material layer, wherein the anisotropic plasma process transforms the first material layer into a second material layer having a different material composition than the first material layer; removing the hard mask layer from the top surface of the layer stack and the sidewalls of the layer stack; and after removing the hard mask layer, removing the liner layer from the top surface of the layer stack and the sidewalls of the layer stack, wherein after removing the liner layer, a remaining portion of the liner layer and a remaining portion of the hard mask layer cover the upper surface of the shallow trench isolation region; forming a dummy gate structure above the fin structure and the shallow trench isolation protection structure; forming source / drain regions on opposite sides of the dummy gate structure; and after forming the source / drain regions, replacing the dummy gate structure with a replacement gate structure.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a fin structure protruding over a shallow trench isolation region, wherein the shallow trench isolation region is located above a substrate and on opposite sides of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation region, comprising: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; processing the pad layer with a plasma process; and, after processing the pad layer, applying a protective layer to the substrate. A hard mask layer is formed on the pad layer; and the hard mask layer and the pad layer are removed from the top surface and the sidewalls of the layer stack; a dummy gate structure is formed above the fin structure and the shallow trench isolation protection structure; a source / drain opening is formed on the opposite side of the dummy gate structure, wherein the source / drain opening exposes a first portion of the first semiconductor material disposed below the dummy gate structure; the first portion of the first semiconductor material is replaced with a sacrificial material; after the replacement, a source / drain region is formed in the source / drain opening; and after forming the source / drain region, the sacrificial material is removed and the dummy gate structure is replaced with a replacement gate structure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] FIG. 1 Examples of nanostructured field-effect transistor (NSFET) devices are shown in three-dimensional views according to some embodiments.

[0009] FIG. 2 , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 11A , FIG. 11B , FIG. 12A, FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A , FIG. 15B , FIG. 16A , FIG. 16B , FIG. 16C , FIG. 17A , FIG. 17B , FIG. 17C , FIG. 18A , FIG. 18B , FIG. 18C , FIG. 19A , FIG. 19B , FIG. 19C , FIG. 20A , FIG. 20B , FIG. 20C , FIG. 21A , FIG. 21B , FIG. 21C , FIG. 22A , FIG. 22B , FIG. 22C , FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A and FIG. 25B This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device according to an embodiment at various manufacturing stages.

[0010] FIG. 2 , FIG. 2 , FIG. 2 , FIG. 3A , FIG. 3B and FIG. 4A This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device according to another embodiment at various manufacturing stages.

[0011] FIG. 4B , FIG. 5A , FIG. 5B and FIG. 6A This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device according to yet another embodiment at various manufacturing stages.

[0012] FIG. 6B and FIG. 7A A flowchart of a method for forming a semiconductor device in some embodiments is also shown.

[0013] FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B ,FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A and FIG. 15B This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device according to an embodiment at various manufacturing stages.

[0014] FIG. 16A and FIG. 16B This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device according to another embodiment.

[0015] FIG. 16C and FIG. 17A A flowchart of a method for forming a semiconductor device in some embodiments is also shown. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact.

[0017] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed using the same or similar materials and the same or similar forming processes. Furthermore, figures with the same reference numerals but different letters (e.g., FIG. 17B The diagram shows different views of the same device at the same processing stage.

[0018] The disclosed embodiments relate to shallow trench isolation (STI) protection structures formed on the STI regions of an NSFET device. The STI protection structure protects the STI regions (e.g., the portion directly beneath a dummy gate structure) during selective etching of a disposable material used in a disposable oxide interposer (DOI) process for forming the NSFET device. The STI protection structure includes a pad layer and a hard mask layer formed on the pad layer. A first set of embodiments for forming STI protection structures with concave, convex, or flat upper surfaces is disclosed. In the first set of embodiments, the hard mask layer on the pad layer is controlled through various processing steps to achieve different profiles (e.g., concave, convex, or flat) for the upper surface of the STI protection structure. A second set of embodiments for enhancing the quality of the pad layer of the STI protection structure through different plasma processes, thereby making the pad layer more resistant to subsequent etching processes.

[0019] FIG. 17C An example of a nanostructured field-effect transistor (NSFET) device 30 is shown in a three-dimensional view according to some embodiments. The NSFET device 30 includes a semiconductor fin 90 (also referred to as a fin) protruding above a substrate 50. A gate electrode 122 (e.g., a metal gate) is disposed above the fin, and source / drain regions 112 are formed on opposite sides of the gate electrode 122. A plurality of nanostructures 54 (e.g., nanowires or nanosheets) are formed above the fin 90 and between the source / drain regions 112. An isolation region 96 is formed on opposite sides of the fin 90. A gate dielectric layer 120 is formed around the nanostructures 54. The gate electrode 122 is located above and around the gate dielectric layer 120.

[0020] FIG. 18A Reference cross sections used in later figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 122 and in a direction, for example, perpendicular to the direction of current between the source / drain regions 112 of the NSFET device 30. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 90, in a direction, for example, the direction of current between the source / drain regions 112 of the NSFET device. Cross section CC is parallel to cross section BB and is located between two adjacent fins 90. Cross section DD is parallel to cross section AA and extends through the source / drain regions 112 of the NSFET device. For clarity, the following figures may refer to these reference cross sections.

[0021] FIG. 18B , FIG. 18C , FIG. 19A , FIG. 19B , FIG. 19C , FIG. 20A , FIG. 20B , FIG. 20C , FIG. 21A , FIG. 21B ,FIG. 21C , FIG. 22A , FIG. 22B , FIG. 22C , FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A , FIG. 25B , FIG. 2 , FIG. 2 , FIG. 2 , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 10B , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 12B , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A , FIG. 15B , FIG. 16A , FIG. 16B , FIG. 16C , FIG. 17A and FIG. 17B This is a cross-sectional view of a portion of the nanostructured field-effect transistor (NSFET) device 100 according to an embodiment at various manufacturing stages.

[0022] exist FIG. 17C A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 includes: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0023] A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. FIG. 18A In the process, the layers formed by the first semiconductor material 52 are labeled as 52A, 52B and 52C, and the layers formed by the second semiconductor material 54 are labeled as 54A, 54B and 54C. FIG. 18B The number of layers formed from the first semiconductor material and the second semiconductor material shown is merely a non-limiting example. Other numbers of layers are also possible and are fully intended to be included within the scope of embodiments of this disclosure.

[0024] In some embodiments, the first semiconductor material 52 is a first type of epitaxial material, such as silicon germanium (Si). x Ge 1-x (where x can be in the range of 0 to 1), and the second semiconductor material 54 is a second type of epitaxial material, such as silicon. A multilayer stack 64 (which may also be referred to as an epitaxial material stack) is patterned to form the channel region of the NSFET in a subsequent process. Specifically, the multilayer stack 64 is patterned and etched to form nanostructures (e.g., nanosheets or nanowires), wherein the resulting NSFET channel region comprises multiple horizontally extending nanostructures.

[0025] The multilayer stack 64 can be formed by an epitaxial growth process performed in a growth chamber. During the epitaxial growth process, in some embodiments, the growth chamber is cyclically exposed to a first precursor set for selectively growing a first semiconductor material 52, and then exposed to a second precursor set for selectively growing a second semiconductor material 54. The first precursor set includes a precursor for the first semiconductor material (e.g., silicon-germanium), and the second precursor set includes a precursor for the second semiconductor material (e.g., silicon). In some embodiments, the first precursor set includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germanane), and the second precursor set includes a silicon precursor but omits the germanium precursor. Thus, the epitaxial growth process can include continuously enabling the silicon precursor to flow into the growth chamber, and then cyclically: (1) enabling the germanium precursor to flow into the growth chamber when growing the first semiconductor material 52; and (2) preventing the germanium precursor from flowing into the growth chamber when growing the second semiconductor material 54. The cyclic exposure can be repeated until a target number of layers are formed.

[0026] FIG. 18C , FIG. 19A , FIG. 19B , FIG. 19C , FIG. 20A , FIG. 20B , FIG. 20C , FIG. 21A , FIG. 21B ,FIG. 21C , FIG. 22A , FIG. 22B , FIG. 22C , FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A , FIG. 25B , FIG. 3A , FIG. 4A , FIG. 5A , FIG. 6A , FIG. 7A , FIG. 8A , FIG. 9A , FIG. 10A , FIG. 11A , FIG. 12A , FIG. 13A , FIG. 14A , FIG. 15A , FIG. 16A , FIG. 17A , FIG. 18A , FIG. 19A , FIG. 20A , FIG. 21A , FIG. 22A , FIG. 23A , FIG. 24A , FIG. 25A , FIG. 1 , FIG. 3B , FIG. 4B , FIG. 5B , FIG. 6B , FIG. 7B , FIG. 8B , FIG. 9B , FIG. 10B , FIG. 11B and FIG. 12B This is a cross-sectional view of the NSFET device 100 according to an embodiment during a subsequent manufacturing stage. FIG. 13B , FIG. 14B , FIG. 15B , FIG. 16C , FIG. 17C , FIG. 18C , FIG. 19C , FIG. 20C , FIG. 21C , FIG. 22C , FIG. 23B , FIG. 24B , FIG. 25B , FIG. 1 , FIG. 16B , FIG. 17B , FIG. 18B , FIG. 19B , FIG. 20B , FIG. 21B , FIG. 22B , FIG. 1 and FIG. 3A It is along FIG. 3B The cross-sectional view of section BB in the diagram. FIG. 3A, FIG. 3B , FIG. 3A , FIG. 3B , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 4A , FIG. 4B , FIG. 7B , FIG. 5A , FIG. 5B , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ , ​ and ​ It is along ​ The cross-sectional view of section AA in the diagram. ​ , ​ , ​ , ​ , ​ , ​ and ​ It is along ​ The figure shows a cross-sectional view of section DD. The number of fins and gate structures shown in the figure are merely non-limiting examples, and it should be understood that other numbers of fins and other numbers of gate structures can also be formed.

[0027] exist ​ and ​ In the process, fin structures 91 are formed protruding above the substrate 50. Each fin structure 91 includes a semiconductor fin 90 (also referred to as a fin) and a layer stack 92 located above the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 can be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The layer stack 92 and the semiconductor fin 90 can be formed by the same etching process.

[0028] The fin structure 91 can be patterned using any suitable method. For example, the fin structure 91 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern, for example, the fin structure 91.

[0029] In some embodiments, the remaining spacers are used to pattern mask 94, which is then used to pattern fin structure 91. Mask 94 may be a single-layer mask or a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and the second mask layer 94B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to suitable techniques. The first mask layer 94A and the second mask layer 94B are different materials with high etch selectivity. For example, the first mask layer 94A may be silicon oxide, and the second mask layer 94B may be silicon nitride. Mask 94 may be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etch process. Mask 94 may then be used as an etch mask to etch substrate 50 and multilayer stack 64. Etching may be any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. In some embodiments, etching is an anisotropic etching process. Following the etching process, patterned multilayer stack 64 forms layer stack 92, and patterned portions of the substrate 50 form fins 90 (e.g., 90A or 90B), such as... ​ and ​ As shown in the diagram. The remaining (e.g., unpatterned) portion of substrate 50 is in ​ and ​ And referred to as substrate 50 in the following figures. Therefore, in the illustrated embodiment, the layer stack 92 also includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. The fin 90 is formed of the same material as the substrate 50. ​ and ​ In this example, fins 90A and 90B are formed to extend parallel to each other.

[0030] Next step, in ​ and ​ In this embodiment, a shallow trench isolation (STI) region 96 is formed above the substrate 50 and on the opposite side of the fin structure 91. As an example of forming the STI region 96, an insulating material can be formed above the substrate 50. The insulating material can be an oxide such as silicon oxide, a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process can be performed after the formation of the insulating material.

[0031] In some embodiments, the insulating material is formed such that an excess of insulating material covers the fin structure 91. In some embodiments, a liner (not shown) is first formed along the surface of the substrate 50 and the fin structure 91, and a filler material, such as those discussed above, is formed over the liner. In some embodiments, the liner is omitted.

[0032] Next, a removal process is applied to the insulating material to remove excess insulating material disposed above the fin structure 91. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, may be utilized. The planarization process exposes the layer stack 92, such that the top surface of the layer stack 92 and the insulating material are flush after the planarization process is completed. Next, the insulating material is recessed to form STI regions 96. The insulating material is recessed such that the layer stack 92 protrudes between adjacent STI regions 96. The top portion of the semiconductor fin 90 may also protrude between adjacent STI regions 96. Furthermore, the top surface of the STI region 96 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof, as shown. The top surface of the STI region 96 may be formed as flat, convex, and / or concave by appropriate etching. The STI region 96 may be recessed using acceptable etching processes, such as etching processes that are selective to the material of the insulating material (e.g., etching the material of the insulating material at a rate faster than the materials of the fin 90 and the layer stack 92). For example, it can be removed using chemical oxides with a suitable etchant such as dilute hydrofluoric acid (dHF).

[0033] Still referencing ​ and ​ A pad layer 61 is formed over the layer stack 92 and over the STI region 96. The pad layer 61 can be a suitable dielectric material, such as silicon oxide, and can be formed using suitable deposition methods, such as CVD, atomic layer deposition (ALD), etc. In some embodiments, the pad layer 61 protects the layer stack 92 from damage caused by subsequent etching processes used to form the STI protection structure 68. The pad layer 61 may also be referred to as an oxide pad layer. Other suitable materials besides silicon oxide may also be used, such as dielectric materials that provide high etch selectivity relative to the layer stack 92 and the subsequently formed hard mask layers (e.g., 63, 65, 71). In the illustrated embodiment, the pad layer 61 is a conformal layer with a substantially uniform thickness.

[0034] Next, a hard mask layer 66 is formed on the padding layer 61 (see example). ​The hard mask layer 66 is formed by a suitable deposition process, such as an ALD process, a conformal CVD process, etc. In some embodiments, the hard mask layer 66 is formed by a deposition process comprising multiple deposition cycles (e.g., a plasma-enhanced ALD (PEALD) process), wherein each of the multiple deposition cycles forms a sublayer 66S of the hard mask layer 66. ​ , ​ , FIG. 6A and FIG. 6B The processing steps of the deposition cycle for forming the sublayer 66S of the hard mask layer 66 are shown. FIG. 7A and FIG. 7B The hard mask layer 66 is shown after the deposition process (e.g., the PEALD process) is completed.

[0035] The hard mask layer 66 is formed of a different material than the pad layer 61 and the STI region 96. In some embodiments, the material of the hard mask layer 66 is selected to provide high etch selectivity relative to the material of the STI region 96, such that the hard mask layer 66 protects the STI region 96 from loss during subsequent wafer-forming processes (e.g., etching processes) that form nanostructures (e.g., nanosheets). In an embodiment, the STI region 96 comprises silicon oxide, and the hard mask layer 66 comprises silicon nitride. Other suitable materials besides silicon nitride, such as silicon oxynitride, silicon carbonitride, etc., may also be used for the hard mask layer 66.

[0036] In some embodiments, the hard mask layer 66 is formed using the PEALD process disclosed herein. The PEALD process includes multiple deposition cycles, each including multiple processing steps performed sequentially in a process chamber. In some embodiments, the multiple processing steps in a deposition cycle include a first processing step and a second processing step performed sequentially. After each of the first and second processing steps, unused precursors, plasma generated during the processing step, and / or byproducts of the processing step (if any) are removed from the process chamber (e.g., cleaned or pumped out). For ease of discussion, the layer of material formed after each deposition cycle of the PEALD process is completed is referred to as a sublayer 66S of the hard mask layer 66.

[0037] FIG. 5A and FIG. 5BA first processing step in the deposition cycle is illustrated. In the illustrated embodiment, the first processing step forms a first material layer 62 on a lower layer (e.g., a previously formed sublayer 66S of the pad layer 61 or hard mask layer 66). In this embodiment, a silicon-containing precursor, such as dichlorosilane (SiH2Cl2), is supplied to the process chamber and adsorbed onto the surface of the lower layer, thus forming the first material layer 62 (e.g., a layer of chemically bonded precursor molecules, which may also be referred to as an adsorbed precursor layer). After the first processing step, unused precursors and / or byproducts (if any) are discharged from the process chamber.

[0038] FIG. 6A and FIG. 6B A second processing step in the deposition cycle is illustrated. In this second processing step, an anisotropic plasma process 69 is performed to process the first material layer 62 and transform the first material layer 62 into a second material layer 66S (e.g., a sublayer 66S). In an embodiment, the anisotropic plasma process 69 is performed using a gas source comprising nitrogen (N2). The gas source is ignited into plasma by an RF power source, and the N2 plasma reacts with the first material layer 62, transforming the first material layer 62 into the second material layer 66S. The first material layer 62 (which comprises SiH2Cl2 and / or SiH...) x Cl y The chemical reaction between the substance and the nitrogen plasma produces silicon nitride (e.g., SiN) and volatile byproducts (e.g., HCl). After the second processing step is completed, unused gas sources, plasma, and / or byproducts (if any) are discharged from the process chamber.

[0039] Due to the anisotropy of the anisotropic plasma process 69, the horizontal portion of the first material layer 62 (e.g., the portion disposed along the top surface of the fin structure 91 and the upper surface of the STI region 96) is subjected to more nitrogen plasma than the vertical portion of the first material layer 62 (e.g., the portion disposed along the sidewall of the fin structure 91). Therefore, the second material layer 66S is formed having a horizontal portion 63S and a vertical portion 65S, which have different material compositions and / or physical properties. The horizontal portion 63S is disposed along the top surface of the fin structure 91 and the upper surface of the STI region 96, and the vertical portion 65S is disposed along the sidewall of the fin structure 91. The material composition of the horizontal portion 63S has a higher percentage of silicon nitride than that of the vertical portion 65S. For example, all or most of the SiH2Cl2 and / or SiH2Cl2 in the horizontal portion of the first material layer 62. x Cl y The material is nitrided and transformed into silicon nitride, while a smaller percentage of SiH2Cl2 and / or SiH in the vertical portion of the first material layer 62 x Cl yThe material is nitrided and transformed into silicon nitride. Therefore, in some embodiments, the horizontal portion 63S primarily comprises silicon nitride, with a small percentage or no SiH2Cl2 or SiH x Cl y The material, and the vertical portion 65S includes a smaller percentage of silicon nitride, but a higher percentage of SiH2Cl2 or SiH than the horizontal portion 63S. x Cl y Material. Furthermore, the horizontal portion 63S has a higher density than the vertical portion 65S, and exhibits a slower etch rate (e.g., more etch-resistant) in the subsequent etch process performed to remove the sidewall portions of the hard mask layer 66. The deposition cycle described above is repeated to continuously form multiple sublayers 66S on the pad layer 61 to form the hard mask layer 66. The PEALD process is stopped when the thickness of the hard mask layer 66 reaches the target value.

[0040] FIG. 7A and FIG. 7B The hard mask layer 66 is shown after the PEALD process is completed. Similar to... FIG. 6A and FIG. 6B The hard mask layer 66 includes horizontal portions 63 and vertical portions 65, which are formed by the horizontal portions 63S and vertical portions 65S of all sublayers 66S, respectively. For ease of discussion, the horizontal portion 63 disposed along the top surface of the fin structure 91 may also be referred to as the top portion 63, the horizontal portion 63 disposed along the upper surface of the STI region 96 may also be referred to as the bottom portion 63, and the vertical portion 65 may also be referred to as the sidewall portion 65. The material composition and / or physical properties of the horizontal portions 63 and vertical portions 65 are the same as or similar to those of the horizontal portions 63S and vertical portions 65S, respectively, and therefore details will not be repeated.

[0041] It should be noted that the use of silicon nitride as a material for hard mask layer 66 in the above examples is a non-limiting example. Other suitable materials, such as silicon oxynitride, silicon carbonitride, etc., may also be used for hard mask layer 66, and the deposition methods disclosed above (e.g., the PEALD process) can be adapted to form different materials for hard mask layer 66, as will be readily understood by those skilled in the art. In embodiments, a silicon oxide (e.g., SiO) layer is formed in the first processing step of the deposition cycle. Various methods are possible for forming the silicon oxide layer in the first processing step. For example, precursors already containing Si-O bonds, such as tetraethyl orthosilicate (TEOS), may be used in the first processing step. The precursor may be decomposed to form a SiO-like substance on the surface of the underlying layer (e.g., liner layer 61, or the previously formed sublayer 66S). As another example, in the first processing step, silicon-containing precursors, such as silanes (SiH4) or dichlorosilanes (SiH2Cl2), may be used in conjunction with oxygen plasma or oxygen-containing plasma. Plasma energy can help decompose the precursor and form Si-O bonds. Then, in the second processing step, the N2 plasma converts silicon oxide into silicon oxynitride. In another embodiment, the first processing step forms a silicon carbide layer, and the N2 plasma in the second processing step converts the silicon carbide into silicon carbonitride.

[0042] Next step, in FIG. 8A and FIG. 8B In this process, a mask layer 67 is formed above the hard mask layer 66. In some embodiments, the mask layer 67 is a bottom antireflective coating (BARC) layer, typically used in three-layer photoresist. As an example, the BARC layer can be a carbon-containing material, such as spin-coated glass (SOG) carbon. Therefore, in the discussion herein, the mask layer 67 may also be referred to as BARC layer 67, and it should be understood that other suitable materials may also be used. FIG. 8A and FIG. 8B As shown, the BARC layer 67 fills the grooves between adjacent fin structures 91 and covers the top surface of the fin structure 91.

[0043] Next step, in FIG. 9A and FIG. 9B In this process, the BARC layer 67 is etched back to expose the top portion 63 of the hard mask layer 66. Suitable etching processes, such as dry etching, wet etching, or combinations thereof, can be performed to etch back the BARC layer 67. The etching process can be a timed process that etchs back the BARC layer 67 by a predetermined amount. In some embodiments, the etching process is performed using an etchant that is selective to the material of the BARC layer 67 (e.g., has a higher etch rate thereto), thereby removing the BARC layer 67 without substantially eroding the hard mask layer 66.

[0044] Next step, in FIG. 10A and FIG. 10BIn this process, the exposed top portion 63 of the hard mask layer 66 is removed by an etching process. For example, a dry etching process using a gas source, such as a fluorine-based etching gas, can be implemented to remove the exposed top portion 63 of the hard mask layer 66. As an example, the gas source may include NF3 and H2. As another example, a wet etching process using, for example, phosphoric acid (H3PO4) can be implemented to remove the exposed top portion 63 of the hard mask layer 66. FIG. 10A and FIG. 10B In the illustrated example, the etching process also recesses the BARC layer 67 and removes the upper portion of the sidewall portion 65 of the hard mask layer 66. Due to the etch selectivity between the pad layer 61 and the BARC layer 67 / hard mask layer 66, the pad layer 61 remains substantially unetched and covers the sidewalls and top surface of the fin structure 91. Therefore, the pad layer 61 protects the stacked layer 92 (and the subsequently formed nanostructure 54) from damage caused by the etching process used to form the STI protective structure 68.

[0045] Next step, in FIG. 11A and FIG. 11B In this process, the remaining portion of the BARC layer 67 is removed by an etching process. The etching process can be dry etching, wet etching, a combination thereof, etc. In some embodiments, the etching process is a plasma etching process performed using a gas source including H2 and N2 gases. After the remaining portion of the BARC layer 67 is removed, the remaining portion of the hard mask layer 66 is exposed. The remaining portion of the hard mask layer 73 includes a sidewall portion 65 along the sidewall of the fin structure 91 and a bottom portion 63 along the upper surface of the STI region 96.

[0046] Next step, in FIG. 12A and FIG. 12B In this process, the sidewall portions 65 of the hard mask layer 66 are removed by an etching process (e.g., an isotropic etching process). The etching process can be a dry etching process, a wet etching process, a combination thereof, etc. In some embodiments, a dry etching process is performed using a fluorine-based etching gas, such as HF, NF3, or a combination thereof, to remove the sidewall portions 65 of the hard mask layer 66. In some embodiments, a wet etching process is performed to remove the sidewall portions 65 of the hard mask layer 66. In an embodiment, the wet etching process is performed by: etching for a first duration using a first etchant (e.g., H3PO4); and then etching for a second duration using a second etchant (e.g., SC1, which is a mixture of deionized water, ammonia, and hydrogen peroxide).

[0047] Recall that the sidewall portion 65 of the hard mask layer 66 has a faster etch rate than the bottom portion 63 of the hard mask layer 66 (e.g., due to its lower density and / or less percentage of silicon nitride). Therefore, the sidewall portion 65 is removed (e.g., completely removed) from the sidewall of the fin structure 91 by an etching process (e.g., an isotropic etching process), while the bottom portion 63 remains and covers the upper surface of the STI region 96, but with a reduced thickness due to the etching process. FIG. 12A and FIG. 12B As shown, the remaining bottom portion 63 has a convex upper surface. The remaining bottom portion 63 forms part of the subsequently formed STI protective structure 68. For ease of discussion, the remaining bottom portion 63 may also be referred to hereinafter as the hard mask layer 63.

[0048] Next step, in FIG. 13A and FIG. 13B In this process, a hard mask layer 71 is formed (e.g., conformally) on the pad layer 61 and the hard mask layer 63. The hard mask layer 71 fills the space between the hard mask layer 63 and the pad layer 61 at the corner region where the upper surface of the STI region 96 intersects with the sidewall of the fin 90. The hard mask layer 71 can be formed by a suitable deposition method, such as an ALD process or a conformal CVD process. In some embodiments, the dielectric material of the hard mask layer 71 is selected based on its etch rate relative to the etch rate of the hard mask layer 63 to achieve a target profile (e.g., a concave upper surface or a flat upper surface) for the subsequently formed STI protection structure 68. FIGS. 13A-15B In one example, hard mask layer 71 has the same density as hard mask layer 63 or slightly lower density (e.g., less than 10%). Additionally, or alternatively, for... FIG. 14A and FIG. 14B In the subsequent etching process, the hard mask layer 71 has the same etching rate as the hard mask layer 63, or a slightly slower etching rate (e.g., less than 10%), and therefore, the subsequently formed STI protection structure 68 has a flat upper surface (see, for example...). FIG. 15B In another embodiment, for FIG. 14A and FIG. 14B In subsequent etching processes, hard mask layer 71 has a higher density than hard mask layer 63, and / or a slower etching rate than hard mask layer 63, and therefore, the subsequently formed STI protection structure 68 has a concave upper surface (see, for example...). FIG. 27B ).

[0049] In some embodiments, hard mask layer 63 may be or include a material selected from the group consisting of silicon nitride, silicon oxynitride, and silicon carbonitride, and hard mask layer 71 may be or include a material selected from the group consisting of silicon nitride and silicon oxide. As an example, hard mask layer 63 and hard mask layer 71 may include different materials (e.g., one including silicon oxynitride and the other including silicon nitride) to achieve different etch rates. As another example, hard mask layer 63 and hard mask layer 71 may include the same material (e.g., silicon nitride) but with different densities and etch rates. For example, hard mask layer 71 may be a silicon nitride layer formed using a CVD deposition process, and hard mask layer 63 may be a silicon nitride layer formed using a PEALD deposition process, whereby the CVD deposition process can produce silicon nitride with a higher density than silicon nitride formed by the PEALD deposition process.

[0050] Next step, in FIG. 14A and FIG. 14B In this process, an etching process is performed to remove the hard mask layer 71 from the top surface of the stack 92, the sidewalls of the stack 92, and the upper surface of the hard mask layer 63. Suitable etching processes, such as dry etching, wet etching, or combinations thereof, can be performed. In this embodiment, the etching process is a wet etching process performed using a fluorine-based etchant (such as HF). After the etching process, a portion of the hard mask layer 71 remains at the corner region where the upper surface of the STI region 96 intersects with the sidewall of the fin 90. For example, the remaining portion of the hard mask layer 71 is laterally disposed between the pad layer 61 and the hard mask layer 63. FIG. 14A and FIG. 14B In this example, the upper surface of the remaining portion of the hard mask layer 71 is flush with the upper surface of the hard mask layer 63.

[0051] Next step, in FIG. 15A and FIG. 15B In this process, the portion of the pad layer 61 disposed above the remaining portions of the hard mask layers 63 and 71 is removed by an etching process. Suitable etching processes, such as dry etching, wet etching, or combinations thereof, can be used to remove the portion of the pad layer 61. In this embodiment, the portion of the pad layer 61 is removed by a wet etching process performed using a mixture of HF and SC1. After the etching process, the remaining portions of the pad layer 61, the hard mask layers 63 and 71 form the STI protective structure 68. FIG. 15A and FIG. 15B As shown, the STI protection structure 68 covers (e.g., contacts and extends thereto) the upper surface of the STI region 96. The STI protection structure 68 protects (e.g., shields) the STI region 96 in subsequent wafer fabrication processes to prevent or reduce the loss of the STI region 96 located directly beneath the dummy gate structure.

[0052] existFIG. 15B In this structure, the padding layer 61 of the STI protective structure 68 extends along the sidewalls of the remaining portion of the hard mask layer 71 and along the bottom surface of the hard mask layer 63. FIG. 15B In one example, the STI protection structure 68 has a flat upper surface away from the substrate 50. In some embodiments, the STI protection structure 68 has a concave upper surface away from the substrate 50, such as... FIG. 27B As shown and discussed below. In some embodiments, the STI protection structure 68 has a convex upper surface, such as... FIG. 29B As shown and discussed below. These and other variations are entirely intended to be included within the scope of embodiments disclosed herein.

[0053] In advanced semiconductor manufacturing processes, the aspect ratio of trenches between adjacent fin structures 91 increases significantly, making it increasingly challenging for etching processes to reach the bottom of these trenches. Therefore, it is difficult to control the profile of structures (e.g., STI protection structures) located at the bottom of trenches using etching processes alone. Embodiments of this disclosure allow for precise control of the profile of the STI protection structure 68 (e.g., the shape of its upper surface), which provides manufacturing advantages. For example, the material of the STI protection structure 68 (e.g., 61, 63, 71) undergoes various etching processes, such as subsequent etching processes for removing dummy gate structures. Etching processes can etch (e.g., remove) the material of the STI protection structure 68 in different ways. For example, some dry etching processes (e.g., plasma etching) tend to remove material at a faster rate in the central region of the trench, and some wet etching processes tend to remove material at the corner regions of the trench at a faster rate. To compensate for the additional etching at the central region and to prevent etching through the STI protection structure 68 in the central region, a convex upper surface for the STI protection structure 68 may be advantageous because the central region of the STI protection structure 68 is thicker. Conversely, to compensate for the additional etching at the corner regions, a concave upper surface for the STI protection structure 68 may be advantageous, as the corner regions of the STI protection structure 68 are thicker. Without the currently disclosed method, the STI protection structure 68 may be damaged by the etching process (e.g., etch-through) and may fail to protect the underlying structures (e.g., fins, STI regions) from the etching process, thus causing device failure. The current disclosure provides the ability to control the contour of the STI protection structure 68, thereby preventing the STI protection structure 68 from damage caused by subsequent etching processes (e.g., etch-through) and improving production yield.

[0054] Next step, in FIGS. 16A-16CIn this embodiment, a pseudo-dielectric layer 97 is formed above the STI protection structure 68 and above the sidewalls and top surface of the fin structure 91. The pseudo-dielectric layer 97 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. In this embodiment, a silicon layer is conformally formed above the layer stack 92 and above the upper surface of the STI protection structure 68, and a thermal oxidation process is performed to convert the deposited silicon layer into an oxide layer as the pseudo-dielectric layer 97.

[0055] Next, a dummy gate 102 is formed over the fin structure 91. To form the dummy gate 102, a dummy gate layer can be formed over the dummy dielectric layer 97. The dummy gate layer can be deposited over the dummy dielectric layer 97 and then planarized, for example, by CMP. The dummy gate layer can be amorphous silicon, polysilicon, poly-SiGe, etc. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art.

[0056] A mask 104 is then formed over the dummy gate layer. The mask 104 can be formed of silicon nitride, silicon oxynitride, combinations thereof, etc., and can be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). The pattern of the mask 104 is then transferred to the dummy gate layer using an acceptable etching technique to form a dummy gate 102, and then transferred to a dummy dielectric layer using an acceptable etching technique to form a dummy gate dielectric 97. The dummy gate 102 covers the corresponding channel regions of the stack 92. The pattern of the mask 104 can be used to physically separate each of the dummy gates 102 from adjacent dummy gates. The dummy gates 102 can also have a longitudinal direction substantially perpendicular to the longitudinal direction of the fin structure 91. The dummy gates 102 and the dummy gate dielectric 97 are collectively referred to as the dummy gate structure.

[0057] Next, a gate spacer layer 108 is formed by conformally depositing an insulating material over the layer stack 92, the STI protection structure 68, and the dummy gate 102. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, etc. In some embodiments, the gate spacer layer 108 includes multiple sublayers. For example, a first sublayer (sometimes referred to as a gate sealing spacer layer) may be formed by thermal oxidation or deposition, and a second sublayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first sublayer.

[0058] FIG. 16B and FIG. 16C They are shown respectively FIG. 16A NSFET device 100 in FIG. 16A The cross-sectional views of sections EE and FF are shown. Sections EE and FF correspond to...FIG. 1 Sections DD and AA in the diagram. It should be noted that... FIG. 16A A cross-sectional view along the longitudinal direction (e.g., the current direction) of one of the fins 90 is shown; cross-sectional views along the longitudinal direction (e.g., the current direction) of the other fins 90 are the same or similar, unless otherwise stated. Furthermore, FIG. 16A Two dummy gates 102 are shown as a non-limiting example, and the number of dummy gates 102 above the fin 90 can be any suitable number.

[0059] Next step, in FIGS. 17A-17C In this process, the gate spacer layer 108 is etched using an anisotropic etching process to form the gate spacer 108. The anisotropic etching process can remove the horizontal portion of the gate spacer layer 108 (e.g., the portion above the STI region 96 and the dummy gate 102), wherein the remaining vertical portion of the gate spacer layer 108 along the sidewalls of the dummy gate 102 and the dummy gate dielectric 97 forms the gate spacer 108. Furthermore, the remaining vertical portion of the gate spacer layer 108 along the sidewalls of the fin 90 forms the fin spacer 108F (see example...). FIG. 17B ).

[0060] After forming the gate spacer 108, implantation for the lightly doped source / drain (LDD) region (not shown) can be performed. An appropriate type of impurity (e.g., p-type or n-type) can be implanted into the exposed layer stack 92 and / or semiconductor fins 90. The n-type impurity can be any suitable n-type impurity, such as phosphorus, arsenic, antimony, etc., and the p-type impurity can be any suitable p-type impurity, such as boron, BF2, indium, etc. The lightly doped source / drain region can have a depth of approximately 10. 15 cm -3 To about 10 16 cm -3 The concentration of impurities. Annealing can be used to activate the injected impurities.

[0061] Next, an opening 110 (which may also be referred to as a groove or source / drain opening) is formed in the layer stack 92. The opening 110 may extend through the layer stack 92 and into the fin 90. The opening 110 may be formed by an anisotropic etching process using, for example, a dummy gate 102 and a gate spacer 108 as an etching mask. The upper surface 90U of the fin 90 is exposed at the bottom of the opening 110. The sidewalls of the opening 110 expose a first semiconductor material 52 and a second semiconductor material 54.

[0062] exist FIG. 17B In one example, the anisotropic etching process used to form the source / drain opening 110 removes the portion of the STI protection structure 68 that extends beyond the sidewall of the fin spacer 108F, and also removes a portion of the underlying STI region 96, thereby creating a groove in the STI region 96.FIG. 17B The curved (e.g., concave) upper surface 96U of the STI region 96, resulting from the etching of the STI region 96, is shown. It should be noted that the portion of the STI protection structure 68 located below (e.g., directly below) the dummy gate 102 is shielded from the anisotropic etching process and thus remains intact.

[0063] like FIG. 17B As shown, a portion of the STI protection structure 68 remains beneath the fin spacer 108F and is referred to as the remaining portion of the STI protection structure 68. The remaining portion of the STI protection structure 68 protects the fin 90 from over-etching caused by the anisotropic etching process used to form the source / drain openings 110. Without the remaining portion of the STI protection structure 68, over-etching caused by the anisotropic etching process could expose and / or remove portions of the fin 90 disposed beneath the fin spacer 108F. During subsequent source / drain region formation processes, accidental removal of portions of the fin 90 by over-etching could cause the fin 90 to collapse, and / or could cause epitaxial source / drain material to grow unintentionally from the unintentionally exposed portions of the fin 90. Unintentional growth of epitaxial source / drain material between adjacent fins 90 could cause electrical short circuits between adjacent source / drain regions, thus resulting in device failure. The method disclosed herein (with the remaining portion of the STI protection structure 68) avoids the aforementioned over-etching-related problems, thereby preventing or reducing the likelihood of device failure and improving production yield. This demonstrates another advantage of currently publicly available content.

[0064] Next step, in FIGS. 18A-18C In this process, the first semiconductor material 52 located below the dummy gate 102 and exposed by the opening 110 is removed. The first semiconductor material 52 can be removed by performing an isotropic etching process (such as wet etching) using an etchant selective for the material of the first semiconductor material 52, while the second semiconductor material 54, fin 90, STI region 96, and STI protection structure 68 remain relatively unetched compared to the first semiconductor material 52. In embodiments where the first semiconductor material 52 comprises, for example, SiGe and the second semiconductor material 54 comprises, for example, Si or SiC, the first semiconductor material 52 can be selectively removed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. After removing the first semiconductor material 52, gaps 56 (e.g., spacers) are formed between adjacent layers of the second semiconductor material 54 and between the fin 90 and the bottommost layer of the second semiconductor material 54.

[0065] Next step, in FIGS. 19A-19CIn this process, a disposable material 57 (also referred to as a sacrificial material) is deposited in the opening 110 to line the sidewalls and bottom of the opening 110. The disposable material 57 also fills the gap 56. The disposable material 57 can be deposited using conformal deposition processes such as CVD, ALD, etc. In some embodiments, the disposable material 57 is a dielectric material. In some embodiments, the disposable material 57 comprises one or more layers of silicon oxide (SiO), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc. These materials are selected for their properties, such as etch selectivity, which allows for precise removal during the manufacturing process without adversely affecting adjacent and underlying structures. The selection of the disposable material 57 can depend on the specific requirements of the semiconductor device being manufactured and the desired electrical and physical properties of the final product.

[0066] Next step, in FIGS. 20A-20C In the process, the disposable material 57 disposed outside the gap 56 is removed, and the sidewall of the remaining portion of the disposable material 57 is recessed relative to the corresponding sidewall 54S of the second semiconductor material 54 to form a sidewall groove 58.

[0067] In some embodiments, an anisotropic etching process, such as a dry etching process like plasma etching, is performed to remove the disposable material 57 disposed outside the gap 56. Next, an isotropic etching process, such as a wet etching process, is performed to recess the remaining portion of the disposable material 57 to form a sidewall groove 58. Both the dry and wet etching processes can use etchants selective for the disposable material 57, thereby etching the disposable material 57 without substantially corroding other materials and / or structures. In some embodiments, multiple etching cycles are performed, each including a dry etching process followed by a wet etching process to remove the disposable material 57 and to form the sidewall groove 58. The etching cycles are repeated until the sidewalls of the disposable material 57 are recessed beyond the sidewalls 54S of the second semiconductor material 54. In some embodiments, the disposable material 57 is etched using a wet etching process employing hydrogen fluoride, diluted hydrogen fluoride, another fluorine-based etchant, etc., as the etchant. The wet etching process is performed until the sidewalls of the disposable material 57 are recessed beyond the sidewalls 54S of the second semiconductor material 54. The remaining portion of the primary material 57 (interspersed between layers of the second semiconductor material 54 or between fin 90 and the bottommost layer of the second semiconductor material 54) can be referred to as a primary oxide interposer (DOI). In a subsequent wafer fabrication process, the DOI is selectively removed to release layers of the second semiconductor material 54 to form a nanostructure 54 (e.g., a nanosheet or nanowire). This process can be referred to as the DOI process.

[0068] Replacing the first semiconductor material 52 with a disposable material 57 in a DOI process can offer advantages. To understand these advantages, consider a reference manufacturing process where the first semiconductor material 52 is not replaced with the disposable material 57. In subsequent source / drain formation steps, one or more high-temperature processes can be performed to, for example, activate dopants in the source / drain regions. When the first semiconductor material 52 (e.g., SiGe) is exposed to high temperatures, germanium in the first semiconductor material 52 can diffuse into and mix with the second semiconductor material 54 (e.g., Si), a process referred to as mixing between germanium and silicon. Mixing can increase the roughness at the interface between the first semiconductor material 52 and the second semiconductor material 54 and can cause manufacturing defects that degrade the performance of the resulting device. By replacing the first semiconductor material 52 with the disposable material 57 prior to high-temperature processes (e.g., source / drain annealing), mixing is avoided, manufacturing defects can be reduced, and device performance can be improved. Furthermore, the material of the DOI (e.g., SiO) provides excellent etch selectivity (e.g., above 10,000) relative to the material of the second semiconductor material 54 (e.g., Si), thus allowing selective removal of the DOI in the wafer forming process with little or no damage to the nanostructure 54.

[0069] Next step, in FIGS. 21A-21C In this process, an internal spacer 55 is formed in the sidewall recess 58. In some embodiments, to form the internal spacer 55, an internal spacer layer is formed (e.g., conformally) in the opening 110. The internal spacer layer also fills the sidewall recess 58 of the sacrificial material 57. The internal spacer layer can be a suitable dielectric material, such as silicon carbonitride (SiCN), silicon carbonitride oxycarbonitrile (SiOCN), etc., formed by a suitable deposition method such as PVD, CVD, ALD, etc. Next, an etching process, such as anisotropic etching, is performed to remove the portion of the internal spacer layer disposed outside the sidewall recess 58 of the sacrificial material 57. The remaining portion of the internal spacer layer (e.g., the portion disposed inside the sidewall recess 58) forms the internal spacer 55. FIG. 21A As shown, the opening 110 exposes the sidewalls of the second semiconductor material 54 and the upper surface 90U of the fin 90.

[0070] Next step, in FIGS. 22A-22CIn the diagram, a source / drain region 112 is formed in the opening 110. In the discussion herein, the source / drain region may refer to either the source or the drain, individually or collectively, depending on the context. In the illustrated embodiment, the source / drain region 112 is formed of an epitaxial material and therefore may also be referred to as an epitaxial source / drain region 112. In some embodiments, the epitaxial source / drain region 112 is formed in the opening 110 to apply stress to the respective channel regions of the formed NSFET device, thereby improving performance. In some embodiments, the epitaxial source / drain region 112 is formed such that a dummy gate 102 is disposed between respective adjacent pairs of the epitaxial source / drain regions 112. In some embodiments, a gate spacer 108 is used to separate the epitaxial source / drain regions 112 from the dummy gate 102 by an appropriate lateral distance such that the epitaxial source / drain regions 112 do not short-circuit the gate subsequently formed in the resulting NSFET device.

[0071] The epitaxial source / drain region 112 is epitaxially grown in the opening 110. The epitaxial source / drain region 112 can include any acceptable material, such as materials suitable for n-type or p-type devices. For example, when forming an n-type device, the epitaxial source / drain region 112 can include a material that applies tensile strain to the channel region, such as silicon, SiC, SiCP, SiP, etc. Similarly, when forming a p-type device, the epitaxial source / drain region 112 can include a material that applies compressive strain to the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The epitaxial source / drain region 112 can have a surface protruding from the corresponding surface of the fin 90 and can have a facet.

[0072] The epitaxial source / drain regions 112 and / or fins 90 can be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a dopant content of approximately 10. 19 cm -3 Peace Treaty 10 21 cm -3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 112 can be doped in situ during growth.

[0073] Due to the epitaxial process used to form the epitaxial source / drain regions 112, the upper surface of the epitaxial source / drain regions 112 has small planes that extend laterally outward beyond the sidewalls of the fins 90. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 112 above adjacent fins 90 remain separated, such as... FIG. 22B As shown in the diagram. In other embodiments, these facets cause adjacent epitaxial source / drain regions 112 to merge.

[0074] Next, a contact etch stop layer (CESL) 116 is formed (e.g., conformally) over the source / drain region 112 and over the dummy gate 102, and then a first interlayer dielectric (ILD) 114 is deposited over the CESL 116. The CESL 116 is formed of a material having a different etch rate than the first ILD 114, and can be formed from silicon nitride using PECVD, but other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof can optionally be used, as well as alternative techniques for forming the CESL 116 such as low-voltage CVD (LPCVD), PVD, etc.

[0075] The first ILD 114 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, PECVD, or FCVD. The dielectric material used for the first ILD 114 can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can also be used.

[0076] FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A and FIG. 25B A subsequent gate replacement process is illustrated, in which the dummy gate structures (e.g., 102 and 97) are removed and replaced by a replacement gate structure 123 (e.g., a metal gate structure). In some embodiments, for the gate replacement process, no corresponding [details omitted]. FIG. 22B The cross-sectional view, because such a cross-sectional view is consistent with... FIG. 22B same.

[0077] Next step, in FIG. 23A and FIG. 23B In the etching step, the dummy gate 102 is removed, thereby forming a groove 103 (also referred to as a gate trench) between the respective gate spacers 108. In some embodiments, the dummy gate 102 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 102 without etching the first ILD 114 and the gate spacers 108. During the removal of the dummy gate 102, the dummy gate dielectric 97 can be used as an etch stop layer while the dummy gate 102 is being etched. Then, after the removal of the dummy gate 102, the dummy gate dielectric 97 can be removed.

[0078] Next step, in FIG. 24A and FIG. 24BIn this process, the primary material 57 is removed to release the second semiconductor material 54; this can be referred to as a wafer fabrication process. After the primary material 57 is removed, the second semiconductor material 54 (e.g., the portion located below the dummy gate 102 before its removal) forms a plurality of horizontally extending (e.g., parallel to the main upper surface of the substrate 50) nanostructures 54. The nanostructures 54 can be collectively referred to as the channel region 93 or channel layer 93 of the NSFET device 100. FIG. 24A and FIG. 24B As shown, gaps 53 (e.g., spatial dividers) are formed between nanostructures 54 and between the bottommost nanostructure 54 and the fin 90 by removing disposable material 57. In some embodiments, the nanostructures 54 are nanosheets or nanowires, depending on, for example, the size (e.g., size and / or aspect ratio) of the nanostructures 54.

[0079] In some embodiments, the disposable material 57 is removed by a selective etching process using an etchant that is selective to the disposable material 57 (e.g., has a higher etching rate), thereby removing the disposable material 57 without substantially corroding the second semiconductor material 54. In some embodiments, an isotropic etching process, such as a wet etching process, is performed to remove the disposable material 57. In embodiments where the disposable material 57 comprises, for example, SiO2 and the second semiconductor material 54 comprises, for example, Si or SiC, hydrogen fluoride, diluted hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the disposable material 57.

[0080] In some embodiments, a high etch selectivity of 10,000 or more is achieved between the primary material 57 and the second semiconductor material 54. In other words, the primary material 57 is removed by an isotropic etching process at an etch rate 10,000 times or more higher than that of the second semiconductor material 54. Therefore, the etching process (e.g., a wafer forming process) used to remove the primary material 57 causes little or no damage to the nanostructure 54.

[0081] In some embodiments, both the disposable material 57 and the STI region 96 are formed of oxide (e.g., silicon oxide). Without the STI protection structure 68, the wafer fabrication process can remove the upper portion of the STI region 96 located below the opening 103, thus causing the STI region 96 to be recessed. Recessing the STI region 96 reduces the distance between the subsequently formed replacement gate structure and the substrate. Furthermore, during the wafer fabrication process, the corner regions of the STI region 96 (e.g., the area of ​​the upper surface of the STI region 96 that contacts the sidewall of the fin 90) can be removed (e.g., etched away) at a faster rate than other regions of the STI region 96. When the subsequently formed replacement gate structure fills the removed corner regions of the STI region 96, a protrusion of the replacement gate structure occurs. The reduced distance between the replacement gate structure and the substrate, as well as the protrusion of the replacement gate structure, increases the parasitic capacitance of the replacement gate structure. Embodiments of this disclosure (by forming the STI protection structure 68) prevent or reduce the possibility of STI region loss during the wafer fabrication process, thus reducing the parasitic capacitance of the formed NSFET device and improving device performance.

[0082] Next step, in FIGS. 25A-25B In this process, a gate dielectric layer 120 and a gate electrode 122 are formed to form an alternative gate structure 123. In some embodiments, the gate dielectric material 120 is conformally deposited in the recess 103 (such as on the top surface and sidewalls of the fin 90, on the sidewalls of the gate spacer 108, and on the STI protection structure 68). The gate dielectric material 120 may also be formed on the top surface of the first ILD 114. It should be noted that the gate dielectric material 120 is formed as an encapsulation of the nanostructure 54. According to some embodiments, the gate dielectric material 120 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric material 120 comprises a high-k dielectric material, and in these embodiments, the gate dielectric material 120 may have a dielectric constant (e.g., a K value) greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb or combinations thereof. Methods for forming the gate dielectric material 120 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0083] Next, gate electrode material 122 is deposited over and around the gate dielectric material 120 to fill the remaining portion of the trench 103. The gate electrode material may include metallic materials such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode material 122 is shown, the gate electrode material 122 may include any number of pad layers (e.g., barrier layers), any number of work function adjustment layers, and filler metallic material. After filling the gate electrode material 122, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric material 120 and the gate electrode material 122 located above the top surface of the first ILD 114. Thus, the remaining portions of the gate electrode material 122 and the gate dielectric material 120 form the gate electrode 122 and the gate dielectric layer 120 of the replacement gate structure 123 of the NSFET device 100, respectively. Each gate electrode 122 and the corresponding gate dielectric layer 120 may be collectively referred to as gate stack 123, replacement gate structure 123, metal gate structure 123, or gate structure 123. Each gate structure 123 extends around the corresponding nanostructure 54.

[0084] Additional processing steps can be implemented to complete the fabrication of the NSFET device 100, as will be readily understood by those skilled in the art. For example, a second ILD can be formed over a first ILD 114. Gate contact plugs and source / drain contact plugs can be formed to extend through the second ILD and / or the first ILD 114 to electrically couple to the gate structure 123 and the source / drain region 112. Next, an interconnect structure including multiple dielectric layers and conductive components (e.g., vias and wires) formed in the multiple dielectric layers is formed to interconnect the underlying electrical components (e.g., NSFETs) to form functional circuitry. Next, external connections (e.g., copper pillars, conductive bumps) can be formed to electrically couple to the interconnect structure to provide electrical connections to external electrical devices. Dicing can be performed to separate the multiple NSFET devices into individual, independent devices. Details are not discussed here.

[0085] FIG. 26A , FIG. 26B , FIG. 27A , FIG. 27B , FIG. 28A and FIG. 28B This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device 100A according to another embodiment at various manufacturing stages. The NSFET device 100A is similar to the NSFET device 100, but has a concave upper surface for the STI protection structure 68.

[0086] FIG. 26A and FIG. 26B The processing shown follows FIG. 13A andFIG. 13B The process shown involves forming a hard mask layer 71. It should be noted that in the embodiment of the NSFET device 100A, the material of the hard mask layer 71 has a higher density and / or a slower etch rate than the material of the hard mask layer 63. FIG. 26A and FIG. 26B In China, implementation and FIG. 14A and FIG. 14B The same or similar etching process is used to remove the hard mask layer 71 from the top surface and sidewalls of the stack 92 and from the upper surface of the hard mask layer 63. The remaining portion of the hard mask layer 71 is disposed above the corner region of the STI region 96 and laterally between the pad layer 61 and the hard mask layer 63. Due to the density and / or etching rate of the hard mask layers 71 relative to those of the hard mask layers 63, the remaining portion of the hard mask layer 71 is thicker (e.g., extending further from the substrate) than the hard mask layer 63. Therefore, at the bottom of the trench between adjacent fin structures 91, the remaining portion of the hard mask layer 71 and the portion of the hard mask layer 63 disposed between them form a structure with a concave upper surface.

[0087] Next step, in FIG. 27A and FIG. 27B In this process, the portion of the pad layer 61 disposed above the hard mask layer 63 and the remaining portion of the hard mask layer 71 are removed by an etching process. The etching process can be combined with... FIG. 15A and FIG. 15B The etching process is the same or similar, so details will not be repeated. After the etching process, the remaining portion of the pad layer 61, the remaining portion of the hard mask layer 63, and the remaining portion of the hard mask layer 71 form the STI protection structure 68. It should be noted that in FIG. 27B In the middle, the upper surface of the STI protective structure 68 is a concave upper surface.

[0088] Next step, implementation FIGS. 16A-16C , FIGS. 17A-17C , FIGS. 18A-18C , FIGS. 19A-19C , FIGS. 20A-20C , FIGS. 21A-21C , FIGS. 22A-22C , FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A and FIG. 25B The processing steps shown are used to form the NSFET device 100A. FIG. 28A and FIG. 28B A cross-sectional view of the NSFET device 100A after the replacement gate structure 123 is formed is shown. In other words, FIG. 28A and FIG. 28B The processing steps correspond to FIG. 25A and FIG. 25B The processing steps. For example...FIG. 28B As shown, the gate dielectric layer 120 contacts the concave upper surface of the STI protection structure 68 and extends along the concave upper surface of the STI protection structure 68.

[0089] FIG. 29A , FIG. 29B , FIG. 30A and FIG. 30B This is a cross-sectional view of a portion of a nanostructured field-effect transistor (NSFET) device 100B according to yet another embodiment at various manufacturing stages. The NSFET device 100B is similar to the NSFET device 100, but has a convex upper surface for the STI protection structure 68.

[0090] FIG. 29A and FIG. 29B The processing shown follows FIG. 12A and FIG. 12B The process shown is as described. It should be noted that the hard mask layer 71 of the NSFET device 100 is omitted in the fabrication process of the NSFET device 100. Implementation with... FIG. 15A and FIG. 15B An etching process similar to or the same as the etching process is used to remove the pad layer 61 from the top surface and sidewalls of the stacked component 92. The remaining portion of the pad layer 61 and the hard mask layer 63 forms the STI protective structure 68. FIG. 29B As shown, in some embodiments, the STI protection structure 68 has a convex upper surface, which is formed because the bottom portion 63 of the hard mask layer 66 has a higher density and / or a lower etch rate, as discussed above.

[0091] Next step, implementation FIGS. 16A-16C , FIGS. 17A-17C , FIGS. 18A-18C , FIGS. 19A-19C , FIGS. 20A-20C , FIGS. 21A-21C , FIGS. 22A-22C , FIG. 23A , FIG. 23B , FIG. 24A , FIG. 24B , FIG. 25A and FIG. 25B The processing steps shown are used to form the NSFET device 100B. FIG. 30A and FIG. 30B A cross-sectional view of the NSFET device 100B after the replacement gate structure 123 is formed is shown. In other words, FIG. 30A and FIG. 30B The processing steps correspond to FIG. 25A and FIG. 25B The processing steps. For example... FIG. 30B As shown, the gate dielectric layer 120 contacts the convex upper surface of the STI protection structure 68 and extends along the convex upper surface of the STI protection structure 68.

[0092] FIG. 31A and FIG. 31B A flowchart of a method 1000 for forming a semiconductor device according to some embodiments is also shown. It should be understood that... FIG. 31A and FIG. 31B The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, options, and modifications. For example, additions, deletions, substitutions, rearrangements, or repetitions may be made. FIG. 31A and FIG. 31B The steps shown are as follows.

[0093] refer to FIG. 31A and FIG. 31B In block 1010, a fin structure protruding above the substrate is formed, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material. In block 1020, a shallow trench isolation (STI) region is formed on opposite sides of the fin structure. In block 1030, an STI protection structure is formed on the upper surface of the STI region, including: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the STI region; forming a hard mask layer on the pad layer, wherein the hard mask layer is formed having a first portion along the top surface of the layer stack, a second portion along the sidewalls of the layer stack, and a third portion along the upper surface of the STI region, wherein the first and third portions of the hard mask layer have a higher density than the second portion of the hard mask layer; removing the first and second portions of the hard mask layer; and removing the pad layer from the top surface and sidewalls of the layer stack after removing the first and second portions of the hard mask layer. In block 1040, after forming the STI protection structure, a dummy gate structure is formed above the fin structure and the STI protection structure. In block 1050, source / drain regions are formed above the fin and on the opposite side of the dummy gate structure. In block 1060, after forming the source / drain regions, the dummy gate structure is replaced by a replacement gate structure.

[0094] As discussed above, the STI protection structure 68 disclosed herein protects the STI region 96 disposed beneath the dummy gate structure during the wafer fabrication process and prevents or reduces the loss of the STI region 96. Further improvements to the STI protection structure 68 are possible, for example, by improving the quality and / or etch resistance of the pad layer 61. Various embodiments are disclosed below.

[0095] FIG. 32A , FIG. 32B , FIG. 33A , FIG. 33B , FIG. 34A , FIG. 34B , FIG. 35A ,FIG. 35B , FIG. 36A , FIG. 36B , FIG. 36C , FIG. 37A , FIG. 37B , FIG. 38A , FIG. 38B , FIG. 39A and FIG. 39B This is a cross-sectional view of a portion of the nanostructured field-effect transistor (NSFET) device 200 according to an embodiment at various manufacturing stages. NSFET device 200 is similar to NSFET device 100, but has a different fabrication process for the STI protection structure 68. For brevity, the following discussion focuses on the differences between NSFET devices 100 and 200, and details of the processing steps common to NSFET devices 100 and 200 will not be repeated.

[0096] FIG. 32A , FIG. 33A , FIG. 34A , FIG. 35A , FIG. 36A , FIG. 37A , FIG. 38A and FIG. 39A It is along FIG. 1 The cross-sectional view of section BB in the diagram. FIG. 32B , FIG. 33B , FIG. 34B , FIG. 35B , FIG. 36C , FIG. 37B , FIG. 38B and FIG. 39B It is along FIG. 1 The cross-sectional view of section AA in the diagram. FIG. 36B It is along FIG. 1 The cross-sectional view of section DD in the diagram.

[0097] FIG. 32A and FIG. 32B The processing follows FIG. 3A and FIG. 3B The processing. In FIG. 32A and FIG. 32B In the middle, in the formation FIG. 4A and FIG. 4B Following the same or similar process as that used for STI region 96, STI region 96 is formed. Next, a pad layer 61' is formed over the layer stack 92 and over STI region 96. Pad layer 61' can be a suitable dielectric material, such as silicon oxide, and can be formed using a suitable deposition method, such as CVD, ALD, etc.

[0098] Next step, in FIG. 33A and FIG. 33BIn this process, the padding layer 61' is treated by a plasma process 74. The plasma process 74 alters or enhances the properties of the padding layer 61' and transforms the padding layer 61' into the padding layer 61.

[0099] In this embodiment, plasma process 74 is an isotropic plasma process implemented using an oxygen-containing gas source, such as a gas source comprising oxygen (O2) or carbon dioxide gas (CO2). The gas source may include a carrier gas, such as argon. The gas source is ignited into plasma by an RF power source, and the plasma is used to process the substrate layer 61'. The process conditions of plasma process 74 are adjusted to achieve isotropy. In some embodiments, the plasma from the gas source is filtered by an ion filter, and oxygen ions pass through the ion filter and are used to process the substrate layer 61'. In some embodiments, the substrate layer 61' (e.g., silicon oxide) has defects, such as dangling bonds (Si-O dangling bonds) at the surface of the substrate layer 61', and oxygen ions repair the dangling bonds to form higher quality (e.g., less defective) silicon oxide, which is more resistant to subsequent etching processes, such as wafer forming processes. Carbon in the plasma (e.g., carbon ions) can be used to control the reaction rate of the isotropic plasma process.

[0100] In some embodiments, the isotropic plasma process is performed at a temperature between about 75°C and about 390°C. The pressure of the isotropic plasma process can be between about 2 Torr and about 5 Torr. The power of the RF power source can be between about 15 W and about 500 W, and the processing time of the isotropic plasma process can be between about 10 seconds and about 60 seconds.

[0101] In an embodiment, plasma process 74 is an anisotropic plasma process implemented using a nitrogen-containing gas source, such as a gas source including nitrogen (N2) or ammonia (NH3). The gas source may include a carrier gas, such as argon. The gas source is ignited into plasma by an RF power source, and the plasma is used to process the pad layer 61'. The process conditions of plasma process 74 are adjusted to achieve anisotropy. In some embodiments, the plasma from the gas source is used to nitride the pad layer 61' (e.g., silicon oxide) and transform the pad layer 61' into pad layer 61, which is a nitride layer (e.g., silicon oxynitride). Pad layer 61 is more resistant (e.g., has a lower etch rate) to subsequent etching processes than pad layer 61'.

[0102] In some embodiments, the anisotropic plasma process is performed at a temperature between about 260°C and about 450°C. The pressure of the anisotropic plasma process can be between about 3.5 Torr and about 8 Torr. The power of the RF power source can be between about 500 W and about 1300 W, and the processing time of the anisotropic plasma process can be between about 20 seconds and about 3 minutes.

[0103] In this embodiment, plasma process 74 is an ion implantation process. Nitrogen ions (e.g., N+ ions) are implanted into the pad layer 61', transforming the pad layer 61' into the pad layer 61 (e.g., silicon oxynitride). In other words, the ion implantation process nitrides the pad layer 61'.

[0104] In some embodiments, the implantation process is carried out using nitrogen ions having energies between about 0.8 keV and about 1.2 keV. The dose of the ion implantation process is about 10. 15 cm -2 and 3×10 15 cm -2 The implantation angle is between approximately 0.5 degrees and approximately 3 degrees. After the ion implantation process, an annealing process (such as spike annealing) can be performed at a temperature between approximately 800°C and approximately 900°C for a duration between approximately 20 seconds and approximately 60 seconds.

[0105] Next step, in FIG. 34A and FIG. 34B In this process, a hard mask layer 73 is formed (e.g., conformally) above the backing layer 61. The hard mask layer 73 can be formed of silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, etc., and can be formed by a suitable formation method, such as CVD, ALD, etc.

[0106] Next, multiple etching processes are performed to recess the pad layer 61 and the hard mask layer 73, for example, by removing the pad layer 61 and the hard mask layer 73 from the top surface and sidewalls of the layer stack 92. For example, this can be achieved with... FIGS. 8A-12B The same or similar processing steps are then performed to recess the hard mask layer 73. The padding layer 61, which lies on the remaining portion of the hard mask layer 73, is then removed by an etching process. The remaining portion of the hard mask layer 73 and the remaining portion of the padding layer 61 form the STI protective structure 68. FIG. 35B In one example, the STI protection structure 68 has a flat upper surface.

[0107] Next step, in FIGS. 16A-22C Following the same or similar processing steps, a dummy gate 102 and a dummy gate dielectric 97 are formed above the fin structure 91. A gate spacer 108 is formed to extend along the sidewall of the dummy gate 102. A sacrificial material 57 is formed to replace the first semiconductor material 52 disposed below the dummy gate 102. An internal spacer 55 is formed at the opposite ends of the sacrificial material 57. A source / drain region 112 is formed on the opposite sides of the dummy gate 102. A CESL 116 and a first ILD 114 are formed above the source / drain region 112 and the dummy gate 102. FIGS. 36A-36CA cross-sectional view of the NSFET device 200 after the formation of CESL 116 and the first ILD 114 is shown.

[0108] Next step, implementation FIGS. 37A-39B The replacement gate process shown is used to replace the dummy gate structure with replacement gate structure 123. The details are the same as or similar to those discussed above, and therefore will not be repeated.

[0109] exist FIG. 37A and FIG. 37B In this process, the dummy gate structure is removed to form a groove 103 (e.g., a gate trench) between the gate spacers 108.

[0110] Next step, in FIG. 38A and FIG. 38B In the wafer fabrication process, sacrificial material 57 is removed to release second semiconductor material 54, thus forming nanostructure 54. Spacing 53 is formed at the location where sacrificial material 57 was previously located. FIG. 38B In one example, after the etching process used in the wafer formation process, the pad layer 61 has a sloping upper surface 61S. The sloping upper surface 61S of the pad layer 61 extends further from the substrate 50 than the upper surface of the remaining portion of the hard mask layer 73.

[0111] FIG. 38B The tilted, higher upper surface 61S of the STI protection structure 68 in the disclosed embodiment demonstrates an advantage. Without the plasma process 74, the padding layer in the STI protection structure 68 would be padding layer 61', which is typically an oxide (e.g., silicon oxide). Because silicon oxide is less etch-resistant than the material of the hard mask layer 73 (e.g., silicon nitride), padding layer 61' could become a weakness in the STI protection structure 68. During the wafer fabrication process, the padding layer (e.g., silicon oxide) at the corner regions of the STI protection structure 68 may be etched through, damaging the fins 90. When the subsequently formed replacement gate structure fills the space gap at the corner regions (left by the removed padding layer), a gate structure protrusion occurs, increasing the parasitic capacitance of the formed gate structure. The disclosed plasma process 74 improves the etch resistance of padding layer 61' and transforms padding layer 61' into a more etch-resistant padding layer 61. Therefore, the problems associated with weak padding layers discussed above are avoided or mitigated. After the wafer forming process, the higher upper surface 61S of the padding layer 61 of the STI protective structure 68 (such as...) FIG. 38B The effectiveness of plasma treatment (e.g., plasma process 74) for the liner layer 61' is demonstrated (as shown in the diagram).

[0112] Next step, in FIG. 39A and Figure 39BIn this process, a gate dielectric layer 120 is formed around the nanostructure 54, and a gate electrode 122 is formed around the gate dielectric layer 120 to form an alternative gate structure 123. The details have been discussed above, so they will not be repeated here.

[0113] Figure 40A and Figure 40B This is a partial cross-sectional view of a nanostructured field-effect transistor (NSFET) device 200A according to another embodiment. The NSFET device 200A is similar to the NSFET device 200, but in the final product, only the pad layer 61 of the STI protection structure 68 is retained. Figure 40B In the example, the padding layer 61 has an inclined upper surface 61S, similar to Figure 38B Those mentioned above. In some embodiments, the wafer fabrication process of the NSFET device 200A uses a wet etching process to remove the sacrificial material 57. The etchant used in the wet etching process (e.g., H3PO4) can etch away (e.g., completely remove) the hard mask layer 73 in the STI protective structure 68 (see...). Figure 39B Furthermore, the padding layer 61 of the STI structure 68 is retained in the NSFET device 200A, as shown below. Figure 40A and Figure 40B As shown. Conversely. Figure 38B The STI protection structure 68 still has a hard mask layer 73, which may be due to the etchants used in the wafer formation process for the NSFET device 200, such as diluted hydrofluoric acid (dHF), buffered HF (a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F)), or fluorinated peroxide mixture (FPM) (a mixture of hydrogen peroxide (H2O2) and hydrofluoric acid (HF)).

[0114] Figure 41A and Figure 41B A flowchart of a method 2000 for forming a semiconductor device in some embodiments is also shown. It should be understood that... Figure 41A and Figure 41B The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, options, and modifications. For example, additions, deletions, substitutions, rearrangements, or repetitions may be made. Figure 41A and Figure 41B The steps shown are as follows.

[0115] refer to Figure 41A and Figure 41BIn block 2010, a fin structure is formed protruding above a shallow trench isolation (STI) region, wherein the STI region is located above the substrate and on the opposite side of the fin structure. The fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material. In block 2020, an STI protection structure is formed on the upper surface of the STI region, including: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the STI region; processing the pad layer using a plasma process; forming a hard mask layer on the pad layer after processing the pad layer; and removing the hard mask layer and the pad layer from the top surface and sidewalls of the layer stack. In block 2030, a dummy gate structure is formed above the fin structure and the STI protection structure. In block 2040, a source / drain opening is formed on the opposite side of the dummy gate structure, wherein the source / drain opening exposes a first portion of the first semiconductor material disposed below the dummy gate structure. In block 2050, a first portion of the first semiconductor material is replaced with a sacrificial material. In block 2060, after the replacement, a source / drain region is formed in the source / drain opening. In block 2070, after the source / drain region is formed, the sacrificial material is removed, and the dummy gate structure is replaced with a replacement gate structure.

[0116] Advantages are achieved through the disclosed embodiments. For example, the use of the DOI process reduces mixing between germanium and silicon and provides significantly higher etch selectivity (e.g., >10000) between the primary material 57 and the secondary semiconductor material 54. Therefore, there is minimal or no damage to the nanostructure when the sacrificial material 57 is removed to form the nanostructure 54. As another example, the disclosed STI protection structure 68 protects the STI region 96 (e.g., the portion below the dummy gate) during the removal of the sacrificial material 57, and thus avoids or reduces the loss of the STI region 96, which reduces the parasitic capacitance of the replacement gate structure 123 and improves device performance. As yet another example, the remaining portion of the STI protection structure 68 below the fin spacer 108F prevents or reduces the possibility of fin 90 collapse or accidental growth / merging of source / drain materials due to over-etching of the STI region 96. Therefore, device failures are avoided and production yields are increased.

[0117] Variations and modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of the embodiments disclosed herein. Examples of NSFET devices 100, 100A, and 100B focus on a hard mask layer in the STI protection structure 68 to achieve various profiles for the upper surface of the STI protection structure, and examples of NSFET devices 200 and 200A focus on a pad layer that enhances the STI protection structure. Those skilled in the art will readily understand that various aspects of the disclosed embodiments can be combined. For example, the plasma process 74 for NSFET device 200 can be used to enhance the pad layer 61 of NSFET devices 100, 100A, and 100B, thereby producing a more etch-resistant pad layer 61 and simultaneously achieving various profiles for the STI protection structure 68 (e.g., concave / convex / flat upper surface).

[0118] In an embodiment, a method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a stack of layers above the fin, wherein the stack of layers includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation (STI) region on opposite sides of the fin structure; and forming an STI protection structure on the upper surface of the STI region, which includes: forming a pad layer along the top surface of the stack of layers, along the sidewalls of the stack of layers, and along the upper surface of the STI region; forming a hard mask layer on the pad layer, wherein the hard mask layer is formed having a first portion along the top surface of the stack of layers, a second portion along the sidewalls of the stack of layers, and a third portion along the upper surface of the STI region, wherein the first and third portions of the hard mask layer have a higher density than the second portion of the hard mask layer; removing the first and second portions of the hard mask layer; and removing the pad layer from the top surface of the stack of layers and the sidewalls of the stack of layers after removing the first and second portions of the hard mask layer. The method further includes: after forming the STI protection structure, forming a dummy gate structure above the fin structure and the STI protection structure; forming a source / drain region above the fin and on the opposite side of the dummy gate structure; and after forming the source / drain region, replacing the dummy gate structure with a replacement gate structure. In an embodiment, forming the source / drain region includes: forming a source / drain opening in the fin structure on the opposite side of the dummy gate structure, wherein the source / drain opening exposes a first semiconductor material and a second semiconductor material; and forming a source / drain region in the source / drain opening. In an embodiment, the method further includes: after forming the source / drain opening and before forming the source / drain region, replacing the first semiconductor material disposed below the dummy gate structure with a sacrificial material. In an embodiment, replacing the dummy gate structure includes: removing the dummy gate structure to expose a first portion of the sacrificial material and the second semiconductor material; removing the exposed sacrificial material, wherein after removing the exposed sacrificial material, the first portion of the second semiconductor material is retained to form a channel region of the semiconductor device; and forming a gate dielectric material and a gate electrode material around the channel region. In an embodiment, forming the hard mask layer includes performing multiple deposition cycles, each of which is performed by the following steps: depositing a first material layer on a pad layer; and processing the first material layer using an anisotropic plasma process, wherein the anisotropic plasma process transforms the first material layer into a second material layer, wherein the second material layer and the first material layer have different material compositions. In an embodiment, the first material layer comprises silicon, and the anisotropic plasma process is performed using a gas source comprising nitrogen. In an embodiment, after removing the pad layer, the remaining portion of the pad layer along the upper surface of the STI region and a third portion of the hard mask layer form an STI protection structure. In an embodiment, the STI protection structure has a convex upper surface remote from the substrate.In one embodiment, forming the STI protection structure further includes, after removing the first and second portions of the hard mask layer and before removing the pad layer: forming another hard mask layer along the top surface of the layer stack, along the sidewalls of the layer stack, along the sidewalls of the fin, and along the upper surface of the third portion of the hard mask layer; and performing an etching process to remove the other hard mask layer from the top surface of the layer stack, the sidewalls of the layer stack, and the upper surface of the third portion of the hard mask layer, wherein, after performing the etching process, the remaining portion of the other hard mask layer is laterally disposed between the pad layer and the third portion of the hard mask layer, wherein, after removing the pad layer, the remaining portion of the other hard mask layer, the third portion of the hard mask layer, and the remaining portion of the upper surface of the pad layer along the STI region are retained to form the STI protection structure. In one embodiment, the other hard mask layer has a higher density than the hard mask layer, and the STI protection structure has a concave upper surface away from the substrate. In another embodiment, the other hard mask layer has the same density as the hard mask layer, and the STI protection structure has a flat upper surface away from the substrate.

[0119] In an embodiment, a method of forming a semiconductor device includes: forming a fin structure protruding over a shallow trench isolation (STI) region, wherein the STI region is located above a substrate and on the opposite side of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; and forming an STI protection structure on the upper surface of the STI region, which includes: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the STI region; and forming a hardened protective structure on the pad layer. A mask layer includes: forming a first material layer on a pad layer; performing an anisotropic plasma process to process the first material layer, wherein the anisotropic plasma process transforms the first material layer into a second material layer having a material composition different from that of the first material layer; removing a hard mask layer from the top surface and sidewalls of a stacked layer; and after removing the hard mask layer, removing a pad layer from the top surface and sidewalls of the stacked layer, wherein after removing the pad layer, the remaining portions of the pad layer and the hard mask layer cover the upper surface of the STI region. The method further includes: forming a dummy gate structure over a fin structure and an STI protection structure; forming source / drain regions on opposite sides of the dummy gate structure; and after forming the source / drain regions, replacing the dummy gate structure with a replacement gate structure. In one embodiment, the hard mask layer is formed to include a first portion along the top surface of the layer stack, a second portion along the sidewalls of the layer stack, and a third portion along the upper surface of the STI region, wherein the first and third portions of the hard mask layer have a higher density than the second portion of the hard mask layer. In another embodiment, forming the STI protection structure further includes, after removing the hard mask layer and before removing the padding layer: forming another hard mask layer along the top surface of the layer stack, along the sidewalls of the layer stack, along the sidewalls of the fin, and along the upper surface of the remaining portion of the hard mask layer; and performing an etching process to remove the other hard mask layer from the top surface of the layer stack, the sidewalls of the layer stack, and the upper surface of the remaining portion of the hard mask layer, wherein, after performing the etching process, the remaining portion of the other hard mask layer is laterally disposed between the padding layer and the remaining portion of the hard mask layer. In another embodiment, after removing the padding layer, the remaining portion of the padding layer extends along the sidewalls of the fin and the upper surface of the STI region, wherein the remaining portion of the other hard mask layer, the remaining portion of the hard mask layer, and the remaining portion of the padding layer form the STI protection structure. In an embodiment, forming the source / drain region includes: forming a source / drain opening in a fin structure on the opposite side of the dummy gate structure; after forming the source / drain opening, replacing the first semiconductor material disposed below the dummy gate structure with a sacrificial material; and after the replacement, forming the source / drain region in the source / drain opening.In an embodiment, replacing the dummy gate structure includes: forming an interlayer dielectric (ILD) layer over a source / drain region surrounding the dummy gate structure; removing the dummy gate structure to form a gate trench in the ILD layer, wherein the gate trench exposes a first portion of a sacrificial material and a second semiconductor material; selectively removing the exposed sacrificial material, wherein, after selective removal, the first portion of the second semiconductor material is retained to form a nanostructure; and forming a gate dielectric material and a gate electrode material around the nanostructure.

[0120] In an embodiment, a method of forming a semiconductor device includes: forming a fin structure protruding over a shallow trench isolation (STI) region, wherein the STI region is located above a substrate and on the opposite side of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; and forming an STI protection structure on the upper surface of the STI region, which includes: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the STI region; processing the pad layer with a plasma process; forming a hard mask layer on the pad layer after processing the pad layer; and removing the hard mask layer and the pad layer from the top surface of the layer stack and the sidewalls of the layer stack. The method further includes: forming a dummy gate structure above the fin structure and the STI protection structure; forming source / drain openings on opposite sides of the dummy gate structure, wherein the source / drain openings expose a first portion of the first semiconductor material disposed below the dummy gate structure; replacing the first portion of the first semiconductor material with a sacrificial material; forming a source / drain region in the source / drain openings after replacement; and after forming the source / drain region, removing the sacrificial material and replacing the dummy gate structure with a replacement gate structure. In an embodiment, processing the pad layer includes processing the pad layer using an isotropic plasma process, which is implemented using an oxygen-containing gas source. In an embodiment, processing the pad layer includes processing the pad layer using an anisotropic plasma process, which is implemented using a nitrogen-containing gas source.

[0121] Some embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation region on opposite sides of the fin structure; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation region, comprising: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; forming a hard mask layer on the pad layer, wherein the hard mask layer is formed having a first portion along the top surface of the layer stack and a second portion along the sidewalls of the layer stack. The first and third portions of the hard mask layer are divided along the upper surface of the shallow trench isolation region, wherein the first and third portions of the hard mask layer have a higher density than the second portion of the hard mask layer; the first and second portions of the hard mask layer are removed; and after removing the first and second portions of the hard mask layer, the pad layer is removed from the top surface of the layer stack and the sidewalls of the layer stack; after forming the shallow trench isolation protection structure, a dummy gate structure is formed above the fin structure and the shallow trench isolation protection structure; a source / drain region is formed above the fin and on the opposite side of the dummy gate structure; and after forming the source / drain region, the dummy gate structure is replaced with a replacement gate structure.

[0122] In some embodiments, forming the source / drain region includes: forming a source / drain opening in the fin structure on the opposite side of the dummy gate structure, wherein the source / drain opening exposes the first semiconductor material and the second semiconductor material; and forming the source / drain region in the source / drain opening. In some embodiments, the method further includes replacing the first semiconductor material disposed below the dummy gate structure with a sacrificial material after forming the source / drain opening and before forming the source / drain region. In some embodiments, replacing the dummy gate structure includes: removing the dummy gate structure to expose a first portion of the sacrificial material and the second semiconductor material; removing the exposed sacrificial material, wherein after removing the exposed sacrificial material, the first portion of the second semiconductor material is retained to form a channel region of the semiconductor device; and forming a gate dielectric material and a gate electrode material around the channel region. In some embodiments, forming the hard mask layer includes performing a plurality of deposition cycles, wherein each of the plurality of deposition cycles is performed by the steps of: depositing a first material layer on the pad layer; and processing the first material layer using an anisotropic plasma process, wherein the anisotropic plasma process transforms the first material layer into a second material layer, wherein the second material layer and the first material layer have different material compositions. In some embodiments, the first material layer comprises silicon, and the anisotropic plasma process is performed using a gas source comprising nitrogen. In some embodiments, after removing the pad layer, the remaining portion of the pad layer along the upper surface of the shallow trench isolation region and the third portion of the hard mask layer form the shallow trench isolation protection structure. In some embodiments, the shallow trench isolation protection structure has a convex upper surface remote from the substrate. In some embodiments, forming the shallow trench isolation protection structure further includes, after removing the first and second portions of the hard mask layer and before removing the pad layer: forming another hard mask layer along the top surface of the layer stack, along the sidewalls of the layer stack, along the sidewalls of the fin, and along the upper surface of the third portion of the hard mask layer; and performing an etching process to remove the other hard mask layer from the top surface of the layer stack, the sidewalls of the layer stack, and the upper surface of the third portion of the hard mask layer, wherein, after performing the etching process, the remaining portion of the other hard mask layer is laterally disposed between the pad layer and the third portion of the hard mask layer, wherein, after removing the pad layer, the remaining portion of the other hard mask layer, the third portion of the hard mask layer, and the remaining portion of the pad layer along the upper surface of the shallow trench isolation region are retained to form the shallow trench isolation protection structure.In some embodiments, the other hard mask layer has a higher density than the hard mask layer, and the shallow trench isolation protection structure has a concave upper surface away from the substrate. In some embodiments, the other hard mask layer has the same density as the hard mask layer, and the shallow trench isolation protection structure has a flat upper surface away from the substrate.

[0123] Other embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a fin structure protruding over a shallow trench isolation region, wherein the shallow trench isolation region is located above a substrate and on opposite sides of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation region, comprising: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; forming a hard mask layer on the pad layer, comprising: forming a first material layer on the pad layer; and performing an anisotropic plasma process to process the first material layer. The anisotropic plasma process transforms the first material layer into a second material layer having a different material composition than the first material layer; removes the hard mask layer from the top surface and sidewalls of the layer stack; and after removing the hard mask layer, removes the pad layer from the top surface and sidewalls of the layer stack, wherein, after removing the pad layer, the remaining portion of the pad layer and the remaining portion of the hard mask layer cover the upper surface of the shallow trench isolation region; forms a dummy gate structure above the fin structure and the shallow trench isolation protection structure; forms source / drain regions on opposite sides of the dummy gate structure; and after forming the source / drain regions, replaces the dummy gate structure with a replacement gate structure.

[0124] In some embodiments, the hard mask layer is formed to include a first portion along the top surface of the layer stack, a second portion along the sidewalls of the layer stack, and a third portion along the upper surface of the shallow trench isolation region, wherein the first and third portions of the hard mask layer have a higher density than the second portion of the hard mask layer. In some embodiments, forming the shallow trench isolation protection structure further includes, after removing the hard mask layer and before removing the padding layer: forming another hard mask layer along the top surface of the layer stack, along the sidewalls of the layer stack, along the sidewalls of the fin, and along the upper surface of the remaining portion of the hard mask layer; and performing an etching process to remove the other hard mask layer from the top surface of the layer stack, the sidewalls of the layer stack, and the upper surface of the remaining portion of the hard mask layer, wherein, after performing the etching process, the remaining portion of the other hard mask layer is laterally disposed between the padding layer and the remaining portion of the hard mask layer. In some embodiments, after the pad layer is removed, the remaining portion of the pad layer extends along the sidewall of the fin and the upper surface of the shallow trench isolation region, wherein the remaining portion of the other hard mask layer, the remaining portion of the hard mask layer, and the remaining portion of the pad layer form the shallow trench isolation protection structure. In some embodiments, forming the source / drain region includes: forming a source / drain opening in the fin structure on the opposite side of the dummy gate structure; after forming the source / drain opening, replacing the first semiconductor material disposed below the dummy gate structure with a sacrificial material; and after the replacement, forming the source / drain region in the source / drain opening. In some embodiments, replacing the dummy gate structure includes: forming an interlayer dielectric layer over the source / drain regions surrounding the dummy gate structure; removing the dummy gate structure to form a gate trench in the interlayer dielectric layer, wherein the gate trench exposes the sacrificial material and a first portion of the second semiconductor material; selectively removing the exposed sacrificial material, wherein, after the selective removal, the first portion of the second semiconductor material is retained to form a nanostructure; and forming a gate dielectric material and a gate electrode material around the nanostructure.

[0125] Some embodiments of this application provide a method for forming a semiconductor device, the method comprising: forming a fin structure protruding over a shallow trench isolation region, wherein the shallow trench isolation region is located above a substrate and on opposite sides of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation protection structure on the upper surface of the shallow trench isolation region, comprising: forming a pad layer along the top surface of the layer stack, along the sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; processing the pad layer with a plasma process; and, after processing the pad layer, applying a protective layer to the substrate. A hard mask layer is formed on the pad layer; and the hard mask layer and the pad layer are removed from the top surface and the sidewalls of the layer stack; a dummy gate structure is formed above the fin structure and the shallow trench isolation protection structure; a source / drain opening is formed on the opposite side of the dummy gate structure, wherein the source / drain opening exposes a first portion of the first semiconductor material disposed below the dummy gate structure; the first portion of the first semiconductor material is replaced with a sacrificial material; after the replacement, a source / drain region is formed in the source / drain opening; and after forming the source / drain region, the sacrificial material is removed and the dummy gate structure is replaced with a replacement gate structure.

[0126] In some embodiments, processing the padding layer includes processing the padding layer using an isotropic plasma process, which is implemented using an oxygen-containing gas source. In some embodiments, processing the padding layer includes processing the padding layer using an anisotropic plasma process, which is implemented using a nitrogen-containing gas source.

[0127] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a fin structure protruding above a substrate, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming shallow trench isolation regions on opposite sides of the fin structure; forming a shallow trench isolation protection structure on an upper surface of the shallow trench isolation regions, including: forming a liner layer along a top surface of the layer stack, along sidewalls of the layer stack, and along the upper surface of the shallow trench isolation regions; forming a hardmask layer on the liner layer, wherein the hardmask layer is formed to have a first portion along the top surface of the layer stack, a second portion along the sidewalls of the layer stack, and a third portion along the upper surface of the shallow trench isolation regions, wherein the first and third portions of the hardmask layer have a higher density than the second portion of the hardmask layer; removing the first and second portions of the hardmask layer; and removing the liner layer from the top surface of the layer stack and the sidewalls of the layer stack after removing the first and second portions of the hardmask layer; forming a dummy gate structure above the fin structure and the shallow trench isolation protection structure after forming the shallow trench isolation protection structure; forming source / drain regions above the fin and on opposite sides of the dummy gate structure; and replacing the dummy gate structure with a replacement gate structure after forming the source / drain regions.

2. The method of claim 1, wherein, forming the source / drain regions includes: forming source / drain openings in the fin structure on the opposite sides of the dummy gate structure, wherein the source / drain openings expose the first semiconductor material and the second semiconductor material; and forming the source / drain regions in the source / drain openings.

3. The method of claim 2, further comprising, after forming the source / drain openings and before forming the source / drain regions, replacing the first semiconductor material disposed beneath the dummy gate structure with a sacrificial material.

4. The method of claim 3, wherein, replacing the dummy gate structure includes: removing the dummy gate structure to expose the sacrificial material and a first portion of the second semiconductor material; removing the exposed sacrificial material, wherein the first portion of the second semiconductor material remains to form a channel region of the semiconductor device after removing the exposed sacrificial material; and forming a gate dielectric material and a gate electrode material around the channel region.

5. The method of claim 1, wherein, forming the hardmask layer includes implementing a plurality of deposition cycles, wherein each deposition cycle of the plurality of deposition cycles is implemented by: depositing a first material layer on the liner layer; and processing the first material layer using an anisotropic plasma process, wherein the anisotropic plasma process transforms the first material layer into a second material layer, wherein the second material layer and the first material layer have different material compositions.

6. The method of claim 5, wherein, The first material layer includes silicon, and the anisotropic plasma process is performed using a gas source that includes nitrogen.

7. The method of claim 1, wherein, After the removal of the liner layer, a remaining portion of the liner layer and a remaining portion of the hard mask layer along the upper surface of the shallow trench isolation region form the shallow trench isolation protection structure.

8. The method of claim 7, wherein, The shallow trench isolation protection structure has a convex upper surface that is distanced from the substrate.

9. A method of forming a semiconductor device, the method comprising: forming a fin structure that protrudes above a shallow trench isolation region, wherein the shallow trench isolation region is located above a substrate and on opposite sides of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation protection structure on an upper surface of the shallow trench isolation region, including: forming a liner layer along a top surface of the layer stack, along sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; forming a hard mask layer on the liner layer, including: forming a first material layer on the liner layer; and performing an anisotropic plasma process to treat the first material layer, wherein the anisotropic plasma process transforms the first material layer into a second material layer having a different material composition than the first material layer; removing the hard mask layer from the top surface of the layer stack and the sidewalls of the layer stack; and after the removal of the hard mask layer, removing the liner layer from the top surface of the layer stack and the sidewalls of the layer stack, wherein, after the removal of the liner layer, a remaining portion of the liner layer and a remaining portion of the hard mask layer cover the upper surface of the shallow trench isolation region; forming a dummy gate structure above the fin structure and the shallow trench isolation protection structure; forming source / drain regions on opposite sides of the dummy gate structure; and after the formation of the source / drain regions, replacing the dummy gate structure with a replacement gate structure.

10. A method of forming a semiconductor device, the method comprising: forming a fin structure that protrudes above a shallow trench isolation region, wherein the shallow trench isolation region is located above a substrate and on opposite sides of the fin structure, wherein the fin structure includes a fin and a layer stack above the fin, wherein the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a shallow trench isolation protection structure on an upper surface of the shallow trench isolation region, including: forming a liner layer along a top surface of the layer stack, along sidewalls of the layer stack, and along the upper surface of the shallow trench isolation region; treating the liner layer with a plasma process; after the treatment of the liner layer, forming a hard mask layer on the liner layer; and removing the hard mask layer and the liner layer from the top surface of the layer stack and the sidewalls of the layer stack; forming a dummy gate structure above the fin structure and the shallow trench isolation protection structure; forming a source / drain opening on an opposite side of the dummy gate structure, wherein the source / drain opening exposes a first portion of the first semiconductor material disposed under the dummy gate structure; replacing the first portion of the first semiconductor material with a sacrificial material; after the replacing, forming a source / drain region in the source / drain opening; and after forming the source / drain region, removing the sacrificial material and replacing the dummy gate structure with a replacement gate structure.

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