Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor substrate layer; the first buffer layer, the second buffer layer, the third buffer layer and the drift layer are sequentially arranged on one side of the semiconductor substrate layer in the first direction; wherein the conductivity types of the semiconductor substrate layer, the first buffer layer, the second buffer layer, the third buffer layer and the drift layer are the same, and the doping concentration of the first buffer layer and the doping concentration of the drift layer are respectively smaller than the doping concentration of the semiconductor substrate layer; the doping concentration of the third buffer layer is larger than that of the drift layer and smaller than that of the first buffer layer; the doping concentration of the second buffer layer is smaller than that of the drift layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] The semiconductor power device includes unipolar semiconductor power device, such as MOSFET, JBS or SBD, which is the mainstream power device in the power market, showing great application potential and value.

[0003] How to improve the reverse recovery softness of the semiconductor power device is a technical problem to be solved.

[0004] SUMMARY

[0005] The technical problem of the present application includes how to improve the reverse recovery softness of the semiconductor power device.

[0006] The present application provides a semiconductor device, comprising: a semiconductor substrate layer; a first buffer layer, a second buffer layer, a third buffer layer and a drift layer arranged in sequence on one side of the semiconductor substrate layer in a first direction; wherein the semiconductor substrate layer, the first buffer layer, the second buffer layer, the third buffer layer and the drift layer have the same conductivity type; the doping concentration of the first buffer layer and the drift layer is less than the doping concentration of the semiconductor substrate layer; the doping concentration of the third buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and the doping concentration of the second buffer layer is less than the doping concentration of the drift layer.

[0007] Optionally, the doping concentration of the third buffer layer is 2 to 5 times the doping concentration of the drift layer.

[0008] Optionally, the doping concentration of the drift layer is 2 to 20 times the doping concentration of the second buffer layer.

[0009] Optionally, the thickness of the second buffer layer between the third buffer layer and the first buffer layer in the first direction is 1 to 4 microns.

[0010] Optionally, the thickness of the third buffer layer between the second buffer layer and the drift layer in the first direction is 2 to 5 microns.

[0011] Optionally, the second buffer layer comprises a plurality of second sub-buffer bodies arranged at intervals in a direction perpendicular to the first direction; wherein the semiconductor device further comprises a first additional buffer layer located between adjacent second sub-buffer bodies, the first additional buffer layer having the same conductivity type as the second sub-buffer body, and the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer.

[0012] Optionally, the first additional buffer layer and the third buffer layer are an integral structure.

[0013] Optionally, the third buffer layer includes a plurality of third sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; wherein, the semiconductor device further includes: a second additional buffer layer, the second additional buffer layer being located between adjacent third sub-buffer bodies, the second additional buffer layer having the same conductivity type as the third sub-buffer bodies, and the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer.

[0014] Optionally, the second additional buffer layer and the second buffer layer are an integral structure.

[0015] Optionally, the second buffer layer includes a plurality of second sub-buffer bodies spaced apart along a direction perpendicular to the first direction; the third buffer layer includes a plurality of third sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the semiconductor device further includes: a first additional buffer layer located between adjacent second sub-buffer bodies, the first additional buffer layer having the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and a second additional buffer layer located between adjacent third sub-buffer bodies, the second additional buffer layer having the same conductivity type as the third sub-buffer bodies, and the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer; wherein, the second sub-buffer bodies are located between the second additional buffer layer and the first buffer layer, and the first additional buffer layer is located between the third sub-buffer bodies and the first buffer layer.

[0016] Optionally, the first additional buffer layer and the third buffer layer are an integral structure, and the second buffer layer and the second additional buffer layer are an integral structure.

[0017] Optionally, the semiconductor device is a unipolar semiconductor power device.

[0018] This application also provides a method for fabricating a semiconductor device, comprising: sequentially forming a first buffer layer, a second buffer layer, a third buffer layer, and a drift layer on one side of a semiconductor substrate along a first direction; wherein the semiconductor substrate, the first buffer layer, the second buffer layer, the third buffer layer, and the drift layer have the same conductivity type; the doping concentration of the first buffer layer and the drift layer is less than the doping concentration of the semiconductor substrate; the doping concentration of the third buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and the doping concentration of the second buffer layer is less than the doping concentration of the drift layer.

[0019] Optionally, forming the second buffer layer includes forming a plurality of second sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the method for fabricating the semiconductor device further includes: forming a first additional buffer layer, the first additional buffer layer being located between adjacent second sub-buffer bodies, the first additional buffer layer having the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; wherein, forming the third buffer layer includes: forming the third buffer layer on the side of the second sub-buffer bodies and the first additional buffer layer opposite to the first buffer layer.

[0020] Optionally, the first additional buffer layer is formed during the formation of the second sub-buffer body.

[0021] Optionally, forming the third buffer layer includes: forming a plurality of third sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the method for fabricating the semiconductor device further includes: forming a second additional buffer layer on the side of the second buffer layer away from the first buffer layer, the second additional buffer layer having the same conductivity type as the third sub-buffer bodies, the second additional buffer layer being located between adjacent third sub-buffer bodies, and the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer.

[0022] Optionally, the second additional buffer layer is formed during the formation of the third sub-buffer.

[0023] Optionally, forming the second buffer layer includes forming a plurality of second sub-buffer bodies spaced apart along a direction perpendicular to the first direction; forming the third buffer layer includes forming a plurality of third sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the method for fabricating the semiconductor device further includes: forming a first additional buffer layer, the first additional buffer layer being located between adjacent second sub-buffer bodies, the first additional buffer layer having the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and forming a second additional buffer layer, the second additional buffer layer being located between adjacent third sub-buffer bodies, the second additional buffer layer having the same conductivity type as the third sub-buffer bodies, and the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer; wherein, the second sub-buffer bodies are located between the second additional buffer layer and the first buffer layer, and the first additional buffer layer is located between the third sub-buffer bodies and the first buffer layer.

[0024] Optionally, the first additional buffer layer is formed during the formation of the second sub-buffer body, and the second additional buffer layer is formed during the formation of the third sub-buffer body.

[0025] The technical solution of this invention has the following technical effects: The semiconductor device provided by this invention has a first buffer layer with a lower doping concentration than the semiconductor substrate. The first buffer layer alleviates lattice mismatch between the semiconductor substrate and the drift layer and improves structural defects such as dislocations. During reverse recovery, the depletion region extends from the drift layer towards the third buffer layer. The doping concentration of the third buffer layer is greater than that of the drift layer but less than that of the first buffer layer. Due to the higher doping concentration of the third buffer layer, it can prevent the depletion region from extending further towards the second buffer layer. This causes the electric field formed by the depletion region to stop inside the third buffer layer, in the drift layer on the side of the third buffer layer away from the semiconductor substrate, or at the boundary between the third buffer layer and the drift layer. The electric field formed by the depletion region will not exist in the second and first buffer layers. During reverse recovery, minority carriers are injected into the drift layer. When these minority carriers are transported to the third buffer layer, some recombine with majority carriers in the third buffer layer. Due to the higher doping concentration of the third buffer layer, a larger number of minority carriers recombine with majority carriers in the third buffer layer. Because the doping concentration of the second buffer layer is low, and the electric field of the aforementioned depletion region does not exist in the second buffer layer, when minority carriers are transported to the second buffer layer during the reverse recovery process, they are not affected by the electric field of the aforementioned depletion region and thus do not generate drift current. As a storage region for excess minority carriers, the second buffer layer removes minority carriers mainly by diffusion and recombination with majority carriers in the second buffer layer. Minority carriers are stored in the second buffer layer for a long time and disappear slowly in the second buffer layer, reducing the rate of change of minority carriers and slowing down the rate of change of minority carrier current, thereby significantly improving the reverse recovery softness of semiconductor devices. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a semiconductor device in one embodiment of this application; Figure 2 This is a schematic diagram of a semiconductor device according to another embodiment of this application; Figure 3 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 4 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 5 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 6 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 7 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 8 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 9 This is a schematic diagram of a semiconductor device in yet another embodiment of this application; Figure 10 This is a schematic diagram of a semiconductor device in yet another embodiment of this application. Figures 11-12 This is a schematic diagram of the fabrication process of a semiconductor device in one embodiment of this application; Figures 13-16 This is a schematic diagram of the fabrication process of a semiconductor device according to another embodiment of this application; Figures 17-20 This is a schematic diagram of the fabrication process of a semiconductor device according to another embodiment of this application; Figures 21-24 This is a schematic diagram of the fabrication process of a semiconductor device in another embodiment of this application. Detailed Implementation

[0028] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] One embodiment of this application provides a semiconductor device, with reference to... Figures 1-10 ,include: Semiconductor substrate layer 100; A first buffer layer 110, a second buffer layer 120, a third buffer layer 130, and a drift layer 140 are sequentially arranged on one side of the semiconductor substrate 100 in a first direction. The semiconductor substrate 100, the first buffer layer 110, the second buffer layer 120, the third buffer layer 130, and the drift layer 140 have the same conductivity type. The doping concentrations of the first buffer layer 110 and the drift layer 140 are respectively lower than the doping concentration of the semiconductor substrate 100. The doping concentration of the third buffer layer 130 is greater than the doping concentration of the drift layer 140 and less than the doping concentration of the first buffer layer 110. The doping concentration of the second buffer layer 120 is less than the doping concentration of the drift layer 140.

[0033] In this embodiment, the doping concentration of the first buffer layer 110 is less than that of the semiconductor substrate layer 100. The first buffer layer 110 is used to alleviate lattice mismatch between the semiconductor substrate layer and the drift layer and improve structural defects such as dislocations. During reverse recovery, the depletion region extends from the drift layer 140 toward the third buffer layer 130. The doping concentration of the third buffer layer 130 is greater than that of the drift layer 140 but less than that of the first buffer layer 110. Because the doping concentration of the third buffer layer 130 is relatively large, it can prevent the depletion region from continuing to extend toward the second buffer layer 120. This causes the electric field formed by the depletion region to stop inside the third buffer layer 130, or in the drift layer 140 on the side of the third buffer layer 130 away from the semiconductor substrate layer 100, or at the boundary between the third buffer layer 130 and the drift layer 140. The electric field formed by the depletion region will not exist in the second buffer layer 120 and the first buffer layer 110. During reverse recovery, minority carriers are injected into the drift layer 140. When these minority carriers travel to the third buffer layer 130, some recombine with majority carriers in the third buffer layer 130. Due to the high doping concentration of the third buffer layer 130, a significant number of minority carriers recombine with the majority carriers in the third buffer layer 130. Since the second buffer layer 120 has a lower doping concentration and the electric field of the aforementioned depletion region does not exist in the second buffer layer 120, minority carriers traveling to the second buffer layer 120 during reverse recovery are not affected by the electric field of the aforementioned depletion region and do not generate a drift current. The second buffer layer 120 serves as a storage region for excess minority carriers. Minority carriers are mainly removed through diffusion and recombination with majority carriers in the second buffer layer 120. The longer the minority carriers are stored in the second buffer layer 120, the slower they disappear, reducing the rate of change of minority carriers and slowing down the rate of change of minority carrier current, thereby significantly improving the reverse recovery softness of the semiconductor device.

[0034] Applying semiconductor devices to other circuits results in smaller voltage oscillations in those circuits, making the entire circuit safer and more reliable.

[0035] In this embodiment, the semiconductor device is a unipolar semiconductor power device, such as a MOSFET semiconductor device, a junction barrier Schottky diode (JBS), or a Schottky barrier diode (SBD).

[0036] In this embodiment, the semiconductor substrate 100, the first buffer layer 110, the second buffer layer 120, the third buffer layer 130, and the drift layer 140 have the same conductivity type. For example, the semiconductor substrate 100, the first buffer layer 110, the second buffer layer 120, the third buffer layer 130, and the drift layer 140 are all N-type.

[0037] In this embodiment, a SiC-based semiconductor device is used as an example for illustration. Accordingly, the semiconductor substrate 100 is silicon carbide (SiC) doped with conductive ions. Based on SiC, next-generation semiconductor devices possess higher reverse breakdown voltage, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance, and are therefore considered a new hope in the field of power conversion. It should be noted that in this embodiment, the material of the semiconductor substrate 100 is not limited.

[0038] In one embodiment, the semiconductor substrate 100 has an N-type conductivity.

[0039] In one embodiment, the conductivity type of the drift layer 140 is the same as that of the semiconductor substrate layer 100. The doping concentration of the drift layer 140 is lower than that of the semiconductor substrate layer 100.

[0040] In one embodiment, the drift layer 140 has an N-type conductivity, and further, the material of the drift layer 140 is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the drift layer can be made of other materials.

[0041] In one embodiment, the N-type conductive ion can be a phosphorus ion or a nitrogen ion.

[0042] In one embodiment, the doping concentration of the first buffer layer 110 is less than the doping concentration of the semiconductor substrate layer 100.

[0043] In one embodiment, the first buffer layer 110 is doped with an N-type conductivity, and further, the material of the first buffer layer 110 is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the material of the first buffer layer 110 may also be other materials.

[0044] In one embodiment, the second buffer layer 120 is doped with an N-type conductivity, and further, the material of the second buffer layer 120 is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the material of the second buffer layer 120 may also be other materials.

[0045] In one embodiment, the third buffer layer 130 is doped with an N-type conductivity, and further, the material of the third buffer layer 130 is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the material of the third buffer layer 130 may also be other materials.

[0046] In one embodiment, the doping concentration of the drift layer 140 is less than the doping concentration of the first buffer layer 110.

[0047] In one embodiment, the doping concentration of the drift layer 140 is 2 to 20 times that of the doping concentration of the second buffer layer 120, for example, 2, 5, 10, 15, or 20 times. If the doping concentration of the second buffer layer 120 is too high, the improvement of the minority carrier storage function of the second buffer layer 120 is limited, and the degree to which it slows down the rate of change of minority carrier current is limited; if the doping concentration of the second buffer layer 120 is too low, the impact on the forward conduction resistance increases.

[0048] In one embodiment, the doping concentration of the third buffer layer 130 is 2 to 5 times that of the drift layer 140, for example, 2, 3, 4, or 5 times. If the doping concentration of the third buffer layer 130 is too high, the rate of minority carrier recombination in the drift layer 140 and the rate of majority carrier recombination in the third buffer layer 130 are limited, thus limiting the improvement in the reverse recovery softness of the semiconductor device. If the doping concentration of the third buffer layer 130 is too low, the effect of blocking the electric field of the second buffer layer 120 and the depletion layer is weakened, limiting the degree of slowing down the rate of change of minority carrier current, and increasing the impact on the forward conduction resistance.

[0049] In one embodiment, the doping concentration of the first buffer layer 110 is 5E17atom / cm³. 3 ~3E18atom / cm 3 .

[0050] In one embodiment, the doping concentration of the semiconductor substrate 100 is 5E18 atom / cm². 3 ~1E20atom / cm 3 .

[0051] In one embodiment, the thickness of the second buffer layer 120 between the third buffer layer 130 and the first buffer layer 110 in the first direction is 1 micrometer to 4 micrometers, for example, 1 micrometer, 2 micrometers, 3 micrometers, or 4 micrometers. If the thickness of the second buffer layer 120 between the third buffer layer 130 and the first buffer layer 110 in the first direction is too small, the improvement of the minority carrier storage function of the second buffer layer 120 is limited, and the degree to which it slows down the rate of change of minority carrier current is limited; if the thickness of the second buffer layer 120 between the third buffer layer 130 and the first buffer layer 110 in the first direction is too large, the influence on the forward conduction resistance increases.

[0052] In one embodiment, the thickness of the third buffer layer 130 between the second buffer layer 120 and the drift layer 140 in the first direction is 2 micrometers to 5 micrometers, for example, 2 micrometers, 3 micrometers, 4 micrometers, or 5 micrometers. If the thickness of the third buffer layer 130 between the second buffer layer 120 and the drift layer 140 in the first direction is greater than 5 micrometers, the rate of minority carrier recombination in the drift layer 140 and the rate of majority carrier recombination in the third buffer layer 130 are limited, the degree to which the reverse recovery softness of the semiconductor device is improved is limited, and the impact on the forward conduction resistance is increased. If the thickness of the third buffer layer 130 between the second buffer layer 120 and the drift layer 140 in the first direction is less than 2 micrometers, the effect of blocking the electric field between the second buffer layer 120 and the depletion layer is weakened, and the degree to which the minority carrier current change rate is slowed down is limited.

[0053] In one embodiment, the doping concentration of the drift layer 140 is 2 to 20 times that of the second buffer layer 120; the doping concentration of the third buffer layer 130 is 2 to 5 times that of the drift layer 140; the thickness of the third buffer layer 130 between the second buffer layer 120 and the drift layer 140 in the first direction is 2 to 5 micrometers; and the thickness of the second buffer layer 120 between the third buffer layer 130 and the first buffer layer 110 in the first direction is 1 to 4 micrometers. These doping concentration and thickness settings effectively balance the performance of mitigating the minority carrier current change rate and reducing the forward conduction resistance.

[0054] In one embodiment, reference Figure 2 and Figure 6 The second buffer layer 120 includes a plurality of second sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; wherein, the semiconductor device further includes: a first additional buffer layer 131, the first additional buffer layer 131 being located between adjacent second sub-buffer bodies, the first additional buffer layer 131 having the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer 131 being greater than the doping concentration of the drift layer 140 and less than the doping concentration of the first buffer layer 110. Preferably, the first additional buffer layer 131 and the third buffer layer 130 are an integral structure. This further reduces the forward conduction resistance.

[0055] In one embodiment, the doping concentration of the first additional buffer layer 131 is 2 to 5 times that of the doping concentration of the drift layer 140, for example, 2, 3, 4 or 5 times.

[0056] In one embodiment, the thickness of the first additional buffer layer 131 in the first direction is 1 micrometer to 4 micrometers, for example, 1 micrometer, 2 micrometers, 3 micrometers or 4 micrometers.

[0057] In one embodiment, reference Figure 3 and Figure 7The third buffer layer 130 includes a plurality of third sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; wherein, the semiconductor device further includes a second additional buffer layer 121, the second additional buffer layer 121 being located between adjacent third sub-buffer bodies, the conductivity type of the second additional buffer layer 131 being the same as that of the third sub-buffer bodies, and the doping concentration of the second additional buffer layer 121 being less than the doping concentration of the drift layer 140; preferably, the second additional buffer layer 121 and the second buffer layer 120 are an integral structure.

[0058] In one embodiment, the doping concentration of the drift layer 140 is 2 to 20 times that of the doping concentration of the second additional buffer layer 121, for example, 2 times, 5 times, 10 times, 15 times or 20 times.

[0059] In one embodiment, the thickness of the second additional buffer layer 121 in the first direction is 2 micrometers to 5 micrometers, for example, 2 micrometers, 3 micrometers, 4 micrometers or 5 micrometers.

[0060] In one embodiment, reference Figure 4 and Figure 8 The second buffer layer includes a plurality of second sub-buffer bodies 1200 spaced apart along a direction perpendicular to the first direction; the third buffer layer includes a plurality of third sub-buffer bodies 1300 spaced apart along a direction perpendicular to the first direction; wherein, the semiconductor device further includes: a first additional buffer layer 131, the first additional buffer layer 131 being located between adjacent second sub-buffer bodies 1200, the doping concentration of the first additional buffer layer 131 being greater than the doping concentration of the drift layer 140 and less than the doping concentration of the first buffer layer 110; and a second additional buffer layer 121, the second additional buffer layer 121 being located between adjacent third sub-buffer bodies 1300, the doping concentration of the second additional buffer layer 121 being less than the doping concentration of the drift layer 140; wherein, the second sub-buffer bodies 1200 are located between the second additional buffer layer 121 and the first buffer layer 110, and the first additional buffer layer 131 is located between the third sub-buffer bodies 1300 and the first buffer layer 110. The first additional buffer layer 131 and the third sub-buffer 1300 are in contact, and the second sub-buffer 1200 and the second additional buffer layer 121 are in contact.

[0061] Preferably, the first additional buffer layer 131 and the third buffer layer are integral structures, and the second buffer layer and the second additional buffer layer 121 are integral structures.

[0062] In one embodiment, the doping concentration of the first additional buffer layer 131 is 2 to 5 times that of the doping concentration of the drift layer 140, for example, 2, 3, 4 or 5 times.

[0063] In one embodiment, the thickness of the first additional buffer layer 131 in the first direction is 1 micrometer to 4 micrometers, for example, 1 micrometer, 2 micrometers, 3 micrometers or 4 micrometers.

[0064] In one embodiment, the doping concentration of the drift layer 140 is 2 to 20 times that of the doping concentration of the second additional buffer layer 121, for example, 2 times, 5 times, 10 times, 15 times or 20 times.

[0065] In one embodiment, the thickness of the second additional buffer layer 121 in the first direction is 2 micrometers to 5 micrometers, for example, 2 micrometers, 3 micrometers, 4 micrometers or 5 micrometers.

[0066] In one embodiment, reference Figures 5-8 The semiconductor device is a MOSFET device. The semiconductor device further includes: a well region 150 located in a portion of the drift layer 140, the conductivity type of the well region 150 being opposite to that of the drift layer 140; a first source region 160 located in the well region 150, the doping concentration of the first source region 160 being greater than that of the drift layer 140; the drift layer 140 between adjacent well regions 150 being a JFET region; the conductivity type of the first source region 160 being opposite to that of the well region 150. In this embodiment, when the conductivity type of the well region 150 is P-type, the conductivity type of the first source region 160 is N-type. The semiconductor device also includes a gate structure 180, which covers the JFET region and a portion of the surface of the first source region 160 on both sides of the JFET region. The gate structure 180 includes a gate dielectric layer and a gate electrode layer, the gate electrode layer being located on the side of the gate dielectric layer facing away from the semiconductor substrate. The material of the gate dielectric layer includes silicon oxide, and the material of the gate electrode layer includes polysilicon. The semiconductor device also includes a second source region 170 located within the well region 150. The second source region 170 has the same conductivity type as the well region 150, but its doping concentration is higher. When the well region 150 has a P-type conductivity, the second source region 170 also has a P-type conductivity. The second source region 170 has the opposite conductivity type to the first source region 160; when the first source region 160 has an N-type conductivity, the second source region 170 also has a P-type conductivity. The semiconductor device also includes a front electrode in contact with the first source region 160; and a drain metal layer 190 located on the side surface of the semiconductor substrate layer 100 facing away from the drift layer 140. The semiconductor device also includes an isolation dielectric layer surrounding the side and top surfaces of the gate structure. The front electrode covers the gate structure, and the isolation dielectric layer isolates the front electrode from the gate structure. The material of the isolation dielectric layer includes silicon oxide.

[0067] In one embodiment, the conductivity type of the well region 150 is opposite to that of the drift layer 140. In this embodiment, when the conductivity type of the drift layer 140 is N-type, the conductivity type of the well region 150 is P-type.

[0068] In one embodiment, the semiconductor device is a MOSFET device. The semiconductor device further includes a current spreading layer located in the drift layer on the side of the well region and the JFET region facing the semiconductor substrate. The current spreading layer is in contact with both the well region and the JFET region. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0069] In one embodiment, reference Figure 9 The semiconductor device is a junction barrier Schottky diode (JBS). The semiconductor device also includes a doped layer 200, an anode metal layer 210, and a back metal layer 220. The doped layer 200 is located within a portion of the drift layer 140, and the conductivity type of the doped layer 200 is opposite to that of the drift layer 140. When the drift layer 140 has an N-type conductivity, the doped layer 200 has a P-type conductivity. The anode metal layer 210 is located on the side of the drift layer 140 and the doped layer 200 facing away from the third buffer layer 130; the back metal layer 220 is located on the side of the semiconductor substrate layer 100 facing away from the first buffer layer 110.

[0070] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The semiconductor device further includes a current spreading layer located in a drift layer on the side of the doped layer facing the semiconductor substrate. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0071] When the semiconductor device is a junction barrier Schottky diode (JBS), the first, second, and third buffer layers can also be... Figures 2-4 The first buffer layer, the second buffer layer, and the third buffer layer.

[0072] In one embodiment, reference Figure 10 The semiconductor device is a Schottky barrier diode (SBD). The semiconductor device also includes an anode metal layer 300 and a back metal layer 310. The anode metal layer 300 is located on the side of the drift layer 140 away from the third buffer layer 130; the back metal layer 310 is located on the side of the semiconductor substrate layer 100 away from the first buffer layer 110.

[0073] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD), and the semiconductor device further includes a current spreading layer located in a portion-thickness drift layer 140 and in contact with the anode metal layer 300. The current spreading layer is spaced from the third buffer layer 130 in a first direction.

[0074] When the semiconductor device is a Schottky barrier diode (SBD), the first, second, and third buffer layers can also be... Figures 2-4 The first buffer layer, the second buffer layer, and the third buffer layer.

[0075] This application also provides a method for fabricating a semiconductor device, comprising: sequentially forming a first buffer layer, a second buffer layer, a third buffer layer, and a drift layer on one side of a semiconductor substrate along a first direction; wherein the semiconductor substrate, the first buffer layer, the second buffer layer, the third buffer layer, and the drift layer have the same conductivity type; the doping concentration of the first buffer layer and the drift layer is less than the doping concentration of the semiconductor substrate; the doping concentration of the third buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and the doping concentration of the second buffer layer is less than the doping concentration of the drift layer.

[0076] Figures 11-12 This is a schematic diagram of the fabrication process of a semiconductor device in one embodiment of this application.

[0077] refer to Figure 11 A first buffer layer 110, a second buffer layer 120, a third buffer layer 130 and a drift layer 140 are sequentially formed on one side of the semiconductor substrate layer 100 along the first direction.

[0078] The semiconductor substrate layer is described with reference to the foregoing embodiments. The first buffer layer 110, the second buffer layer 120, the third buffer layer 130, and the drift layer 140 are described with reference to the foregoing embodiments.

[0079] In this embodiment, the process for forming the first buffer layer 110 includes an epitaxial process. The process for forming the second buffer layer 20 includes an epitaxial process. The process for forming the third buffer layer 130 includes an epitaxial process. The process for forming the drift layer 140 includes an epitaxial process.

[0080] In one embodiment, reference Figure 12The semiconductor device is a MOSFET device. The fabrication method further includes: forming a well region 150 in a portion of the drift layer 140, the conductivity type of the well region 150 being opposite to that of the drift layer 140; forming a first source region 160 in the well region 150, the doping concentration of the first source region 160 being greater than that of the drift layer 140; the drift layer 140 between adjacent well regions 150 being a JFET region; the conductivity type of the first source region 160 being opposite to that of the well region 150. The fabrication method further includes: forming a gate structure 180, the gate structure 180 covering the JFET region and a portion of the surface of the first source region 160 on both sides of the JFET region. The fabrication method further includes forming a second source region 170 in the well region 150. The conductivity type of the second source region 170 is the same as that of the well region, and the doping concentration of the second source region 170 is greater than that of the well region 150. The method for fabricating a semiconductor device further includes forming a front electrode that contacts a first source region 160; and forming a drain metal layer 190 located on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 140. The method also includes forming an isolation dielectric layer that surrounds the side and top surfaces of the gate structure. The front electrode covers the gate structure, and the isolation dielectric layer isolates the front electrode from the gate structure.

[0081] In one embodiment, the semiconductor device is a MOSFET device, and the fabrication method of the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in the drift layer on the side of the well region and the JFET region facing the semiconductor substrate, and the current spreading layer is in contact with the well region and the JFET region, respectively. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0082] It should be noted that Figure 12 In this example, a MOSFET device is used as a semiconductor device.

[0083] In other embodiments, the semiconductor device is a junction barrier Schottky diode (JBS). The method for fabricating the semiconductor device further includes forming a doped layer in a portion of the drift layer, forming an anode metal layer on the side of the drift layer away from the semiconductor substrate between the doped layer and adjacent doped layers, and forming a drain metal layer located on the surface of the semiconductor substrate 100 away from the drift layer. The conductivity type of the doped layer is opposite to that of the drift layer. When the drift layer has an N-type conductivity, the doped layer has a P-type conductivity.

[0084] In other embodiments, the semiconductor device is a junction barrier Schottky diode (JBS). The method for fabricating the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in a drift layer on the side of the doped layer facing the semiconductor substrate. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0085] In other embodiments, the semiconductor device is a Schottky barrier diode (SBD). The fabrication method of the semiconductor device further includes forming an anode metal layer and a back metal layer, wherein the anode metal layer is located on the side of the drift layer opposite to the third buffer layer; and the back metal layer is located on the side of the semiconductor substrate layer opposite to the first buffer layer.

[0086] In other embodiments, the semiconductor device is a Schottky barrier diode (SBD), and the fabrication method of the semiconductor device further includes a current spreading layer located in a drift layer of a certain thickness and in contact with the anode metal layer. The current spreading layer and the third buffer layer are spaced apart in a first direction.

[0087] Figures 13-16 This is a schematic diagram of the fabrication process of a semiconductor device in another embodiment of this application.

[0088] The difference between this application and the previous embodiment is that: forming the second buffer layer includes forming a plurality of second sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the method for fabricating the semiconductor device further includes: forming a first additional buffer layer, the first additional buffer layer being located between adjacent second sub-buffer bodies, the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; wherein, forming the third buffer layer includes: forming the third buffer layer on the side of the second sub-buffer bodies and the first additional buffer layer away from the first buffer layer.

[0089] refer to Figure 13 A first buffer layer 110 and a second buffer layer 120 are sequentially formed on one side of the semiconductor substrate layer 100 along the first direction.

[0090] The semiconductor substrate layer is described in the foregoing embodiments.

[0091] Forming the second buffer layer 120 includes forming a plurality of second sub-buffers spaced apart along a direction perpendicular to the first direction.

[0092] The method for fabricating a semiconductor device further includes forming a first additional buffer layer 131, wherein the first additional buffer layer 131 is located between adjacent second sub-buffer bodies. The doping concentration of the first additional buffer layer 131 is greater than the doping concentration of the subsequent drift layer but less than the doping concentration of the first buffer layer 110.

[0093] In one embodiment, the first additional buffer layer 131 is formed during the formation of the second sub-buffer body, simplifying the process. The process of forming the second sub-buffer body and the first additional buffer layer 131 includes an epitaxial process.

[0094] In other embodiments, a first additional buffer layer 131 is formed after the second sub-buffer body is formed; or, a second sub-buffer body is formed after the first additional buffer layer 131 is formed.

[0095] refer to Figure 14 This forms a third buffer layer 130.

[0096] The formation of the third buffer layer 130 includes forming the third buffer layer 130 on the side of the second sub-buffer body and the first additional buffer layer 131 away from the first buffer layer 110.

[0097] refer to Figure 15 A drift layer 140 is formed. The drift layer 140 is located on the side of the third buffer layer 130 away from the semiconductor substrate layer 100.

[0098] In one embodiment, reference Figure 16 The semiconductor device is a MOSFET device. The fabrication method further includes: forming a well region 150 in a portion of the drift layer 140, the conductivity type of the well region 150 being opposite to that of the drift layer 140; forming a first source region 160 in the well region 150, the doping concentration of the first source region 160 being greater than that of the drift layer 140; the drift layer 140 between adjacent well regions 150 being a JFET region; the conductivity type of the first source region 160 being opposite to that of the well region 150. The fabrication method further includes: forming a gate structure 180, the gate structure 180 covering the JFET region and a portion of the surface of the first source region 160 on both sides of the JFET region. The fabrication method further includes forming a second source region 170 in the well region 150. The conductivity type of the second source region 170 is the same as that of the well region, and the doping concentration of the second source region 170 is greater than that of the well region 150. The method for fabricating a semiconductor device further includes forming a front electrode that contacts a first source region 160; and forming a drain metal layer 190 located on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 140. The method also includes forming an isolation dielectric layer that surrounds the side and top surfaces of the gate structure. The front electrode covers the gate structure, and the isolation dielectric layer isolates the front electrode from the gate structure.

[0099] In one embodiment, the semiconductor device is a MOSFET device, and the fabrication method of the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in the drift layer on the side of the well region and the JFET region facing the semiconductor substrate, and the current spreading layer is in contact with the well region and the JFET region, respectively. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0100] It should be noted that Figure 16 In this example, a MOSFET device is used as a semiconductor device.

[0101] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The fabrication method of the semiconductor device further includes forming a doped layer in a portion of the drift layer, forming an anode metal layer on the side of the drift layer away from the semiconductor substrate between the doped layer and adjacent doped layers, and forming a drain metal layer located on the surface of the semiconductor substrate 100 away from the drift layer. The conductivity type of the doped layer is opposite to that of the drift layer. When the drift layer has an N-type conductivity, the doped layer has a P-type conductivity.

[0102] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The method for fabricating the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in a drift layer on the side of the doped layer facing the semiconductor substrate. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0103] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD). The method for fabricating the semiconductor device further includes forming an anode metal layer and a back metal layer, wherein the anode metal layer is located on the side of the drift layer away from the third buffer layer; and the back metal layer is located on the side of the semiconductor substrate layer away from the first buffer layer.

[0104] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD), and the fabrication method of the semiconductor device further includes a current spreading layer located in a drift layer of a certain thickness and in contact with the anode metal layer. The current spreading layer and the third buffer layer are spaced apart in a first direction.

[0105] Figures 17-20 This is a schematic diagram of the fabrication process of a semiconductor device in another embodiment of this application.

[0106] The difference between this application and the aforementioned embodiments is that: forming the third buffer layer includes: forming a plurality of third sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the method for fabricating the semiconductor device further includes: forming a second additional buffer layer on the side of the second buffer layer away from the first buffer layer, the second additional buffer layer being located between adjacent third sub-buffer bodies, and the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer.

[0107] refer to Figure 17 A first buffer layer 110 and a second buffer layer 120 are sequentially formed on one side of the semiconductor substrate layer 100 along the first direction.

[0108] refer to Figure 18 The formation of the third buffer layer 130 includes: forming a plurality of third sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; and forming a second additional buffer layer 121 on the side of the second buffer layer 120 away from the first buffer layer 110, wherein the second additional buffer layer 121 is located between adjacent third sub-buffer bodies.

[0109] In one embodiment, the second additional buffer layer 121 is formed during the formation of the third sub-buffer body, simplifying the process. The process for forming the third sub-buffer body and the second additional buffer layer 121 includes an epitaxial process.

[0110] In other embodiments, a second additional buffer layer 121 is formed after the third sub-buffer body is formed; or, a third sub-buffer body is formed after the second additional buffer layer 121 is formed.

[0111] refer to Figure 19 A drift layer 140 is formed. The drift layer 140 is located on the side of the second additional buffer layer 121 and the third sub-buffer layer away from the semiconductor substrate layer 100.

[0112] In one embodiment, reference Figure 20The semiconductor device is a MOSFET device. The fabrication method further includes: forming a well region 150 in a portion of the drift layer 140, the conductivity type of the well region 150 being opposite to that of the drift layer 140; forming a first source region 160 in the well region 150, the doping concentration of the first source region 160 being greater than that of the drift layer 140; the drift layer 140 between adjacent well regions 150 being a JFET region; the conductivity type of the first source region 160 being opposite to that of the well region 150. The fabrication method further includes: forming a gate structure 180, the gate structure 180 covering the JFET region and a portion of the surface of the first source region 160 on both sides of the JFET region. The fabrication method further includes forming a second source region 170 in the well region 150. The conductivity type of the second source region 170 is the same as that of the well region, and the doping concentration of the second source region 170 is greater than that of the well region 150. The method for fabricating a semiconductor device further includes forming a front electrode that contacts a first source region 160; and forming a drain metal layer 190 located on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 140. The method also includes forming an isolation dielectric layer that surrounds the side and top surfaces of the gate structure. The front electrode covers the gate structure, and the isolation dielectric layer isolates the front electrode from the gate structure.

[0113] In one embodiment, the semiconductor device is a MOSFET device, and the fabrication method of the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in the drift layer on the side of the well region and the JFET region facing the semiconductor substrate, and the current spreading layer is in contact with the well region and the JFET region, respectively. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0114] It should be noted that Figure 20 In this example, a MOSFET device is used as a semiconductor device.

[0115] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The fabrication method of the semiconductor device further includes forming a doped layer in a portion of the drift layer, forming an anode metal layer on the side of the drift layer away from the semiconductor substrate between the doped layer and adjacent doped layers, and forming a drain metal layer located on the surface of the semiconductor substrate 100 away from the drift layer. The conductivity type of the doped layer is opposite to that of the drift layer. When the drift layer has an N-type conductivity, the doped layer has a P-type conductivity.

[0116] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The method for fabricating the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in a drift layer on the side of the doped layer facing the semiconductor substrate. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0117] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD). The method for fabricating the semiconductor device further includes forming an anode metal layer and a back metal layer, wherein the anode metal layer is located on the side of the drift layer away from the third buffer layer; and the back metal layer is located on the side of the semiconductor substrate layer away from the first buffer layer.

[0118] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD), and the fabrication method of the semiconductor device further includes a current spreading layer located in a drift layer of a certain thickness and in contact with the anode metal layer. The current spreading layer and the third buffer layer are spaced apart in a first direction.

[0119] Figures 21-24 This is a schematic diagram of the fabrication process of a semiconductor device in another embodiment of this application.

[0120] The differences between this embodiment and the previous embodiments include: forming the second buffer layer includes forming a plurality of second sub-buffer bodies spaced apart along a direction perpendicular to the first direction; forming the third buffer layer includes forming a plurality of third sub-buffer bodies spaced apart along a direction perpendicular to the first direction; wherein, the semiconductor device fabrication method further includes: forming a first additional buffer layer, the first additional buffer layer being located between adjacent second sub-buffer bodies, the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and forming a second additional buffer layer, the second additional buffer layer being located between adjacent third sub-buffer bodies, the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer; wherein, the second sub-buffer bodies are located between the second additional buffer layer and the first buffer layer, and the first additional buffer layer is located between the third sub-buffer bodies and the first buffer layer.

[0121] refer to Figure 21 A first buffer layer 110 is formed on one side of the semiconductor substrate 100 along a first direction; forming a second buffer layer includes: forming a plurality of second sub-buffer bodies 1200 arranged at intervals along a direction perpendicular to the first direction on the side of the first buffer layer 110 away from the semiconductor substrate 100; forming a first additional buffer layer 131, the first additional buffer layer 131 being located between adjacent second sub-buffer bodies 1200.

[0122] The doping concentration of the first additional buffer layer 131 is greater than the doping concentration of the subsequent drift layer but less than the doping concentration of the first buffer layer 110.

[0123] In one embodiment, the first additional buffer layer 131 is formed during the formation of the second sub-buffer 1200, simplifying the process. The process of forming the second sub-buffer 1200 and the first additional buffer layer 131 includes an epitaxial process.

[0124] In other embodiments, the first additional buffer layer 131 is formed after the second sub-buffer 1200 is formed; or the second sub-buffer 1200 is formed after the first additional buffer layer 131.

[0125] refer to Figure 22 The formation of a third buffer layer includes: forming a plurality of third sub-buffer bodies 1300 spaced apart along a direction perpendicular to the first direction; and forming a second additional buffer layer 121 located between adjacent third sub-buffer bodies 1300.

[0126] The second sub-buffer 1200 is located between the second additional buffer layer 121 and the first buffer layer 110, and the first additional buffer layer 131 is located between the third sub-buffer 1300 and the first buffer layer 110.

[0127] The doping concentration of the second additional buffer layer 121 is lower than that of the subsequent drift layer.

[0128] In one embodiment, a second additional buffer layer 121 is formed during the formation of the third sub-buffer 1300. This simplifies the process. The process for forming the third sub-buffer 1300 and the second additional buffer layer 121 includes an epitaxial process.

[0129] In other embodiments, a second additional buffer layer 121 is formed after the third sub-buffer 1300 is formed; or, the third sub-buffer 1300 is formed after the second additional buffer layer 121.

[0130] refer to Figure 23 A drift layer 140 is formed. The drift layer 140 is located on the side of the second additional buffer layer 121 and the third sub-buffer 1300 away from the semiconductor substrate layer 100.

[0131] In one embodiment, reference Figure 24The semiconductor device is a MOSFET device. The fabrication method further includes: forming a well region 150 in a portion of the drift layer 140, the conductivity type of the well region 150 being opposite to that of the drift layer 140; forming a first source region 160 in the well region 150, the doping concentration of the first source region 160 being greater than that of the drift layer 140; the drift layer 140 between adjacent well regions 150 being a JFET region; the conductivity type of the first source region 160 being opposite to that of the well region 150. The fabrication method further includes: forming a gate structure 180, the gate structure 180 covering the JFET region and a portion of the surface of the first source region 160 on both sides of the JFET region. The fabrication method further includes forming a second source region 170 in the well region 150. The conductivity type of the second source region 170 is the same as that of the well region, and the doping concentration of the second source region 170 is greater than that of the well region 150. The method for fabricating a semiconductor device further includes forming a front electrode that contacts a first source region 160; and forming a drain metal layer 190 located on the side surface of the semiconductor substrate layer 100 opposite to the drift layer 140. The method also includes forming an isolation dielectric layer that surrounds the side and top surfaces of the gate structure. The front electrode covers the gate structure, and the isolation dielectric layer isolates the front electrode from the gate structure.

[0132] In one embodiment, the semiconductor device is a MOSFET device, and the fabrication method of the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in the drift layer on the side of the well region and the JFET region facing the semiconductor substrate, and the current spreading layer is in contact with the well region and the JFET region, respectively. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0133] It should be noted that Figure 24 In this example, a MOSFET device is used as a semiconductor device.

[0134] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The fabrication method of the semiconductor device further includes forming a doped layer in a portion of the drift layer, forming an anode metal layer on the side of the drift layer away from the semiconductor substrate between the doped layer and adjacent doped layers, and forming a drain metal layer located on the surface of the semiconductor substrate 100 away from the drift layer. The conductivity type of the doped layer is opposite to that of the drift layer. When the drift layer has an N-type conductivity, the doped layer has a P-type conductivity.

[0135] In one embodiment, the semiconductor device is a junction barrier Schottky diode (JBS). The method for fabricating the semiconductor device further includes forming a current spreading layer. The current spreading layer is located in a drift layer on the side of the doped layer facing the semiconductor substrate. The conductivity type of the current spreading layer is the same as that of the drift layer, and the doping concentration of the current spreading layer is greater than that of the drift layer.

[0136] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD). The method for fabricating the semiconductor device further includes forming an anode metal layer and a back metal layer, wherein the anode metal layer is located on the side of the drift layer away from the third buffer layer; and the back metal layer is located on the side of the semiconductor substrate layer away from the first buffer layer.

[0137] In one embodiment, the semiconductor device is a Schottky barrier diode (SBD), and the fabrication method of the semiconductor device further includes a current spreading layer located in a drift layer of a certain thickness and in contact with the anode metal layer. The current spreading layer and the third buffer layer are spaced apart in a first direction.

[0138] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a semiconductor substrate layer; a first buffer layer, a second buffer layer, a third buffer layer and a drift layer arranged in sequence on one side of the semiconductor substrate layer in a first direction; wherein the semiconductor substrate layer, the first buffer layer, the second buffer layer, the third buffer layer and the drift layer have the same conductivity type; the doping concentration of the first buffer layer and the drift layer is less than the doping concentration of the semiconductor substrate layer; the doping concentration of the third buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and the doping concentration of the second buffer layer is less than the doping concentration of the drift layer.

2. The semiconductor device according to claim 1, wherein The doping concentration of the third buffer layer is 2 to 5 times the doping concentration of the drift layer.

3. The semiconductor device of claim 1, wherein The doping concentration of the drift layer is 2 to 20 times the doping concentration of the second buffer layer.

4. The semiconductor device of claim 1, wherein The thickness of the second buffer layer between the third buffer layer and the first buffer layer in the first direction is 1 to 4 microns.

5. The semiconductor device of claim 1, wherein The thickness of the third buffer layer between the second buffer layer and the drift layer in the first direction is 2 to 5 microns.

6. The semiconductor device of claim 1, wherein The second buffer layer comprises a plurality of second sub-buffer bodies arranged at intervals in a direction perpendicular to the first direction. The semiconductor device further comprises a first additional buffer layer between adjacent second sub-buffer bodies, the first additional buffer layer has the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer. Preferably, the first additional buffer layer and the third buffer layer are in an integral structure.

7. The semiconductor device of claim 1, wherein The third buffer layer comprises a plurality of third sub-buffer bodies arranged at intervals in a direction perpendicular to the first direction. The semiconductor device further comprises a second additional buffer layer between adjacent third sub-buffer bodies, the second additional buffer layer has the same conductivity type as the third sub-buffer bodies, and the doping concentration of the second additional buffer layer is less than the doping concentration of the drift layer. Preferably, the second additional buffer layer and the second buffer layer are in an integral structure.

8. The semiconductor device of claim 1, wherein The second buffer layer comprises a plurality of second sub-buffer bodies arranged at intervals in a direction perpendicular to the first direction; and the third buffer layer comprises a plurality of third sub-buffer bodies arranged at intervals in a direction perpendicular to the first direction. The semiconductor device further comprises: a first additional buffer layer between adjacent second sub-buffer bodies, the first additional buffer layer has the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and a second additional buffer layer between adjacent third sub-buffer bodies, the second additional buffer layer has the same conductivity type as the third sub-buffer bodies, and the doping concentration of the second additional buffer layer is less than the doping concentration of the drift layer. The second sub-buffer body is located between the second additional buffer layer and the first buffer layer, and the first additional buffer layer is located between the third sub-buffer body and the first buffer layer. Preferably, the first additional buffer layer and the third buffer layer are an integral structure, and the second buffer layer and the second additional buffer layer are an integral structure.

9. The semiconductor device of claim 1, wherein, The semiconductor device is a unipolar semiconductor power device.

10. A method of manufacturing a semiconductor device according to any one of claims 1 to 9, characterized by, Comprise: A first buffer layer, a second buffer layer, a third buffer layer and a drift layer are sequentially formed on one side of a semiconductor substrate layer along a first direction; The semiconductor substrate layer, the first buffer layer, the second buffer layer, the third buffer layer and the drift layer have the same conductivity type; the doping concentration of the first buffer layer and the drift layer is less than the doping concentration of the semiconductor substrate layer; the doping concentration of the third buffer layer is greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and the doping concentration of the second buffer layer is less than the doping concentration of the drift layer.

11. The method for fabricating the semiconductor device according to claim 10, characterized in that, The second buffer layer is formed by forming a plurality of second sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; The method for manufacturing the semiconductor device further comprises: forming a first additional buffer layer, the first additional buffer layer being located between adjacent second sub-buffer bodies, the first additional buffer layer having the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; The third buffer layer is formed by forming a plurality of third sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; Preferably, the first additional buffer layer is formed in the process of forming the second sub-buffer body.

12. The method of fabricating a semiconductor device of claim 10, wherein, The third buffer layer is formed by forming a plurality of third sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; The method for manufacturing the semiconductor device further comprises: forming a second additional buffer layer on a side of the second buffer layer away from the first buffer layer, the second additional buffer layer having the same conductivity type as the third sub-buffer bodies, the second additional buffer layer being located between adjacent third sub-buffer bodies, and the doping concentration of the second additional buffer layer being less than the doping concentration of the drift layer; Preferably, the second additional buffer layer is formed in the process of forming the third sub-buffer body.

13. The method for fabricating the semiconductor device according to claim 10, characterized in that, The second buffer layer is formed by forming a plurality of second sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; and the third buffer layer is formed by forming a plurality of third sub-buffer bodies arranged at intervals along a direction perpendicular to the first direction; The method for manufacturing the semiconductor device further comprises: forming a first additional buffer layer, the first additional buffer layer being located between adjacent second sub-buffer bodies, the first additional buffer layer having the same conductivity type as the second sub-buffer bodies, and the doping concentration of the first additional buffer layer being greater than the doping concentration of the drift layer and less than the doping concentration of the first buffer layer; and forming a second additional buffer layer between adjacent third sub-buffer bodies, the second additional buffer layer having the same conductivity type as the third sub-buffer bodies, and a doping concentration less than that of the drift layer; wherein the second sub-buffer bodies are between the second additional buffer layer and the first buffer layer, and the first additional buffer layer is between the third sub-buffer bodies and the first buffer layer; Preferably, the first additional buffer layer is formed during formation of the second sub-buffer bodies, and the second additional buffer layer is formed during formation of the third sub-buffer bodies.

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