Semiconductor-on-insulator and method of making the same

Abstract

This disclosure provides a semiconductor-on-insulator (SOS) and its fabrication method. The SOS comprises, sequentially disposed: a substrate layer, a fusion layer, a trap-rich layer, a buried oxide layer, and a device layer. The fusion layer is located on one side of the substrate layer and includes migrating elements obtained by diffusion from elements in a compound of the substrate layer. The trap-rich layer is located on the side of the fusion layer away from the substrate layer. The buried oxide layer is located on the side of the trap-rich layer away from the substrate layer. The device layer is located on the side of the buried oxide layer away from the trap-rich layer. The migrating elements in the fusion layer of this SOS enhance the connection between the trap-rich layer and the substrate layer while ensuring that the resistivity of the substrate layer does not decrease, thereby improving the trap-rich layer's ability to trap impurities and reducing harmonic interference in radio frequency devices.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor on insulator, and more specifically to a semiconductor on insulator and a method for preparing the same. Background Technology

[0002] Devices are typically manufactured using wafers as substrates, with the wafers primarily serving a supporting role. However, as device integration density increases and performance requirements rise, the correlation between device performance and substrate characteristics becomes increasingly significant. This phenomenon is particularly pronounced in radio frequency (RF) devices. RF devices handle signal frequencies ranging from approximately 3kHz to 300GHz and are widely used in the telecommunications field, such as cellular phones, Wi-Fi, and Bluetooth. When high-frequency signals propagate through the device, the resulting electromagnetic fields penetrate deep into the substrate and interact with charge carriers within it. This interaction can lead to numerous problems, such as signal nonlinear distortion, signal energy loss, and inter-device interference. Summary of the Invention

[0003] The semiconductor-on-insulator disclosed herein enhances the connection between the rich trap layer and the substrate layer by means of a fusion layer, while ensuring that the resistivity of the substrate layer does not decrease. This improves the ability of the rich trap layer to trap impurities and reduces the harmonic effects in radio frequency devices. Thus, it solves the technical problem that the dielectric layer of existing semiconductor-on-insulators blocks the connection between the rich trap layer and the substrate layer, resulting in a decrease in the ability of the rich trap layer to trap impurities and making radio frequency devices susceptible to harmonic effects.

[0004] Some embodiments of this disclosure provide a semiconductor-on-insulator, comprising a substrate layer, a fusion layer, a trap-rich layer, a buried oxide layer, and a device layer disposed sequentially. The fusion layer is located on one side of the substrate layer and includes a migration element obtained by diffusion of an element from a compound formed on the substrate layer. The trap-rich layer is located on the side of the fusion layer away from the substrate layer. The buried oxide layer is located on the side of the trap-rich layer away from the substrate layer. The device layer is located on the side of the buried oxide layer away from the trap-rich layer.

[0005] For example, in some embodiments of the present disclosure, the lattice structure or surface structure of the fusion layer is configured to guide the growth of the trap-rich layer.

[0006] For example, in some embodiments of the present disclosure, the semiconductor-on-insulator layer comprises polysilicon, and the trap-rich layer comprises polysilicon.

[0007] For example, in some embodiments of the present disclosure, the grain size of the polysilicon in the fusion layer is smaller than the grain size of the polysilicon in the trap-rich layer.

[0008] For example, in some embodiments of the present disclosure of a semiconductor-on-insulator, the concentration of migrating elements on the side of the fusion layer closer to the substrate layer is greater than the concentration of migrating elements on the side of the fusion layer closer to the trap-rich layer.

[0009] For example, in some embodiments of the present disclosure, the semiconductor-on-insulator layer comprises monocrystalline silicon, the compound obtained based on the substrate layer is silicon oxide, and the migrating element is oxygen.

[0010] For example, in some embodiments of the present disclosure, the semiconductor-on-insulator has the migration elements distributed at the grain boundaries of the fusion layer.

[0011] For example, in some embodiments of the present disclosure, the thermal conductivity of the trap-rich layer is higher than that of the buried oxide layer.

[0012] For example, in some embodiments of the semiconductor-on-insulator provided in this disclosure, the trap-rich layer includes a dopant element, preferably boron; preferably, the doping amount of the dopant element is 1 × 10⁻⁶. 10 atmos / cm 3 ~5×10 10 atmos / cm 3 .

[0013] For example, in some embodiments of the present disclosure, the buried oxide layer has a thickness of 0.1 μm to 4 μm, and preferably, the device layer is monocrystalline silicon.

[0014] Some embodiments of this disclosure provide a method for fabricating a semiconductor-on-insulator, comprising: providing a first donor, the first donor comprising a substrate layer and a compound formed based on the substrate layer; forming a fusion layer based on migrating elements in the compound, and obtaining a trap-rich layer based on the fusion layer; providing a second donor as a device layer, forming a buried oxide layer on the surface of the second donor; and combining the trap-rich layer with the buried oxide layer to obtain the semiconductor-on-insulator.

[0015] For example, in the preparation method provided in some embodiments of this disclosure, the fusion layer is generated based on the compound, including: placing the first donor in a reaction chamber at a first temperature; and injecting a silicon source precursor into the reaction chamber at a second temperature, wherein the migrating elements in the compound diffuse and combine with the silicon source precursor to obtain the fusion layer.

[0016] For example, in the preparation method provided in some embodiments of this disclosure, the rich trap layer is obtained based on the fusion layer, including: raising the temperature of the reaction chamber from the second temperature to the third temperature, and continuing to inject silicon source precursor into the reaction chamber to obtain the rich trap layer based on the fusion layer.

[0017] For example, in the preparation methods provided in some embodiments of this disclosure, the first temperature is between 850°C and 1200°C, the second temperature is between 600°C and 800°C, and the third temperature is between 800°C and 1000°C.

[0018] For example, in some embodiments of the present disclosure, the preparation method further includes: after placing the first donor in a reaction chamber at a first temperature, injecting an inert gas that does not react with the compound into the reaction chamber to pretreat the first donor in the reaction chamber.

[0019] For example, in the preparation methods provided in some embodiments of this disclosure, the substrate layer includes monocrystalline silicon, the compound generated on the substrate layer is silicon oxide obtained by natural oxidation of the substrate layer, and the migrating element is oxygen.

[0020] For example, in the preparation method provided in some embodiments of this disclosure, the silicon source precursor includes trichlorosilane, the fusion layer and the trap-rich layer are polycrystalline silicon, and the grain size of the polycrystalline silicon in the fusion layer is smaller than the grain size of the polycrystalline silicon in the trap-rich layer.

[0021] For example, in some embodiments of the present disclosure, a second donor is provided as a device layer, and a buried oxide layer is formed on the surface of the second donor, including: forming the buried oxide layer on the surface of the second donor by a wet oxygen or dry oxygen process.

[0022] For example, in some embodiments of the present disclosure, the method of combining the trap-rich layer and the buried oxide layer to obtain the semiconductor-on-insulator includes: bonding the trap-rich layer and the buried oxide layer to obtain the semiconductor-on-insulator; or forming an oxide layer on the surface of the trap-rich layer and bonding the oxide layer and the buried oxide layer to obtain the semiconductor-on-insulator. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 A schematic diagram of a semiconductor-on-insulator structure is shown.

[0025] Figure 2 A schematic diagram of a semiconductor-on-insulator provided in at least one embodiment of the present disclosure is shown;

[0026] Figure 3 A schematic diagram of a semiconductor-on-insulator structure provided in another embodiment of this disclosure is shown;

[0027] Figure 4 A flowchart illustrating a method for fabricating a semiconductor on an insulator according to at least one embodiment of the present disclosure is shown;

[0028] Figure 5 A schematic diagram of a method for fabricating a semiconductor on an insulator according to at least one embodiment of the present disclosure is shown;

[0029] Figure 6 A flowchart illustrating a method for generating a fusion layer based on the diffusion of migrating elements from compounds, according to at least one embodiment of this disclosure, is shown; and

[0030] Figure 7 A schematic diagram of a microscopic fusion layer and a trap-rich layer provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0031] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention.

[0032] Any specific numerical values ​​disclosed herein (including the endpoints of numerical ranges) are not limited to their exact values, but should be understood to also include values ​​close to the exact value, such as all possible values ​​within ±5% of the exact value. Furthermore, with respect to the disclosed numerical ranges, one or more new numerical ranges can be obtained by arbitrarily combining the endpoint values ​​of the range, the endpoint values ​​with specific point values ​​within the range, and the specific point values ​​themselves; these new numerical ranges should also be considered as specifically disclosed herein.

[0033] The terminology used in this disclosure is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used in this disclosure are intended to include the plural forms as well. The terms “comprising,” “including,” “containing,” and “having” are inclusive and thus describe the presence of said features, elements, compositions, steps, integers, operations, and / or components, but do not exclude the presence or inclusion of one or more other features, integers, steps, operations, elements, components, and / or sets thereof. Although the open-ended term “comprising” should be understood as a non-limiting term used to describe and claim the various embodiments described in this disclosure, in some aspects it may instead be understood as a more restrictive and limiting term, such as “consisting of” or “substantially consisting of.” Thus, for any given embodiment describing a composition, material, component, element, feature, integer, operation, and / or process step, this disclosure also particularly includes embodiments consisting of or substantially consisting of such compositions, materials, components, elements, features, integers, operations, and / or process steps. In the case of “consisting of…”, the alternative embodiments exclude any additional compositions, materials, components, elements, features, integers, operations and / or process steps. In the case of “essentially composed of…”, any additional compositions, materials, components, elements, features, integers, operations and / or process steps that substantially affect the essential and novel characteristics are excluded from such embodiments. However, any compositions, materials, components, elements, features, integers, operations and / or process steps that do not substantially affect the essential and novel characteristics may be included in the embodiments.

[0034] Any method steps, processes, and operations described in this disclosure should not be construed as necessarily requiring them to be performed in a particular order as discussed or shown, unless explicitly specified. It should also be understood that additional or alternative steps may be used unless otherwise stated.

[0035] In this application, except where expressly stated, any matters or issues not mentioned are directly applicable to those known in the art without any modification. Furthermore, any implementation described in this disclosure may be freely combined with one or more other implementations described in this disclosure, and the resulting technical solutions or concepts shall be considered part of the original disclosure or original record of this application, and should not be regarded as new content not disclosed or anticipated in this disclosure, unless those skilled in the art consider the combination to be clearly unreasonable.

[0036] Unless otherwise stated, the terms used herein have the same meaning as commonly understood by those skilled in the art, and if a term is defined herein and its definition differs from the common understanding in the art, the definition herein shall prevail.

[0037] As mentioned above, device fabrication is becoming increasingly challenging and pushing towards the limits of physical possibility. One recent development in semiconductor technology is semiconductor-on-insulator (SOI) technology, a semiconductor manufacturing technique that involves forming a buried oxide layer on a silicon substrate (also known as the "substrate layer") and then growing a thin device layer on top of it. Specifically, SOI technology achieves isolation between the device layer and the silicon substrate by embedding a buried oxide layer between the device layer and the substrate layer. This reduces parasitic capacitance, improves device operating speed, lowers power consumption, and mitigates the problem of electromagnetic fields penetrating the substrate and interacting with charge carriers in the substrate when high-frequency signals propagate through the device. Therefore, SOI technology can provide semiconductor devices with better performance, lower power consumption, higher radiation resistance, and better compatibility, making it a promising technology for many applications, such as high-performance processors, wireless communication chips, and low-power mobile devices.

[0038] Figure 1 A schematic diagram of a semiconductor-on-insulator 100 is shown.

[0039] like Figure 1 As shown, the semiconductor-on-insulator 100 includes, in sequence: a substrate layer 11, a dielectric layer 15, a trap-rich layer 12, a buried oxide layer 13, and a device layer 14.

[0040] Substrate 11 is the "foundation" of the semiconductor-on-insulator 100 structure, providing mechanical strength and stability so that it can be transported, handled, and processed in subsequent semiconductor processes. Substrate 11 also undertakes part of the chip's heat dissipation function.

[0041] The trap-rich layer 12, for example, is a polycrystalline silicon layer. Through the trapping effect of grain boundary defects, it blocks the parasitic conductive path between the buried oxide layer 13 and the substrate layer 11, thereby significantly improving the radio frequency performance and electrical stability of the semiconductor on insulator. It can also actively modulate the electrical performance of SOI by trapping and releasing charges.

[0042] The buried oxide layer 13 is the main insulating layer of the semiconductor on insulator 100, which realizes the isolation between the device layer 14 and the substrate layer 11.

[0043] Device layer 14 serves as the active region of the device, where components such as transistors (e.g., CMOS), resistors, and capacitors are manufactured using processes such as photolithography, etching, and ion implantation in this thin layer of single-crystal silicon.

[0044] The dielectric layer 15 is located between the substrate layer 11 and the rich trap layer 12. It is used to reduce the requirements for growing the rich trap layer 12 on the substrate layer 11 and reduce the difficulty of obtaining the rich trap layer 12. The dielectric layer 15 is also used to block impurity invasion and isolate carrier injection to ensure that the resistivity of the substrate layer 11 does not decrease.

[0045] For example, if the device layer can be silicon and the substrate layer can be a silicon substrate, then the semiconductor on insulator is silicon on insulator.

[0046] The structure of the semiconductor-on-insulator 100 mitigates the problem of electromagnetic fields penetrating the substrate and interacting with charge carriers in the substrate when high-frequency signals propagate in the device through the buried oxide layer 13 and the trap-rich layer 12. However, the dielectric layer 15 in this structure blocks the connection between the trap-rich layer 12 and the substrate layer 11, resulting in a reduced impurity trapping capability of the trap-rich layer 12 and making the RF device susceptible to harmonic interference. In addition, the lattice size of the trap-rich layer 12 grown on the dielectric layer 15 is difficult to control, and the surface roughness is high, making it difficult to bond the trap-rich layer 12 to the buried oxide layer 13.

[0047] Based on this, some embodiments of this disclosure provide a semiconductor-on-insulator. The semiconductor-on-insulator includes a substrate layer, a fusion layer, a trap-rich layer, a buried oxide layer, and a device layer sequentially disposed therefrom. The fusion layer is located on one side of the substrate layer and includes a migrating element obtained by diffusion from elements in a compound formed on the substrate layer. The trap-rich layer is located on the side of the fusion layer away from the substrate layer. The buried oxide layer is located on the side of the trap-rich layer away from the substrate layer. The device layer is located on the side of the buried oxide layer away from the trap-rich layer. This semiconductor-on-insulator, through the fusion layer, enhances the connection between the trap-rich layer and the substrate layer while ensuring that the resistivity of the substrate layer does not decrease, thereby improving the trap-rich layer's ability to trap impurities and reducing harmonic interference in radio frequency devices.

[0048] Other embodiments of this disclosure provide a method for fabricating the above-described semiconductor-on-insulator. This method includes providing a first donor comprising a substrate layer and a compound formed based on the substrate layer; forming a fusion layer based on the compound, and obtaining a trap-rich layer based on the fusion layer; providing a second donor as a device layer, forming a buried oxide layer on the surface of the second donor; and bonding the trap-rich layer and the buried oxide layer to obtain a semiconductor-on-insulator. The semiconductor-on-insulator obtained by this method, through the fusion layer, enhances the connection between the trap-rich layer and the substrate layer while ensuring that the resistivity of the substrate layer does not decrease, thereby improving the trap-rich layer's ability to trap impurities and reducing harmonic interference in radio frequency devices.

[0049] Figure 2 A schematic diagram of a semiconductor-on-insulator 200 provided in at least one embodiment of the present disclosure is shown. Figure 2The semiconductor-on-insulator 200 shown can be, for example, a wafer or be fabricated as a wafer. As the substrate material for chips, individual chips are formed on the wafer surface through multiple processes such as photolithography, etching, doping, and dicing.

[0050] like Figure 2 As shown, the semiconductor-on-insulator 200 includes a substrate layer 21, a trap-rich layer 22, a buried oxide layer 23, a device layer 24, and a fusion layer 25 sequentially disposed therefrom. The fusion layer 25 is located on one side of the substrate layer 21 and includes migrating elements obtained by diffusion of elements from a compound formed on the substrate layer. The trap-rich layer 22 is located on the side of the fusion layer 25 away from the substrate layer 21; the buried oxide layer 23 is located on the side of the trap-rich layer 22 away from the substrate layer 21; and the device layer 24 is located on the side of the buried oxide layer 23 away from the trap-rich layer 22.

[0051] The fusion layer of the semiconductor-on-insulator 200 includes migrating elements that, compared to the dense dielectric layer in the semiconductor-on-insulator 100, enhance the connection between the trap-rich layer and the substrate while ensuring that the resistivity of the substrate does not decrease. This improves the trap-rich layer's ability to trap impurities and reduces harmonic effects in radio frequency devices.

[0052] For example, substrate 21 includes opposing first and second sides, and fusion layer 25 includes the first side located on substrate 21. For example, in Figure 2 In the structure shown, the first side of the substrate 21 is located above the second side of the substrate 21, that is, the fusion layer 25 is located above the substrate 21.

[0053] The fusion layer 25 includes a first side and a second side, the first side of which is, for example, the side in contact with the substrate layer 21; the second side of the fusion layer 25 is the side away from the substrate layer 21. For example, in Figure 2 In the example, the first side of the fusion layer 25 is located below the second side of the fusion layer 25. For example, the first side of the fusion layer 25 is located on the surface of the substrate layer 21, and the second side of the fusion layer 25 is located away from the substrate layer 21 and close to the trap-rich layer 22 relative to the first side of the fusion layer 25.

[0054] In some embodiments of this disclosure, the fusion layer 25 includes migration elements obtained by diffusion of elements from a compound generated in the substrate layer.

[0055] For example, the compound formed on the substrate layer may be obtained by reacting the substrate layer with chemical elements or substances. For instance, if the substrate layer is monocrystalline silicon, and monocrystalline silicon reacts with oxygen to form silicon oxide, then the compound is silicon oxide, and the migrating element is oxygen atoms. For silicon oxide (SiO2), under high-temperature processing conditions, oxygen atoms diffuse rapidly across the SiO2 interface and along grain boundaries via solid-state diffusion, thus acting as migrating elements in the fusion layer. Another example is silicon nitride obtained by reacting the substrate layer with nitrogen, where the migrating element is nitrogen atoms. Yet another example is silicon oxynitride obtained by reacting the substrate layer with nitrogen and oxygen, where the migrating elements are nitrogen atoms, oxygen atoms, etc.

[0056] In some embodiments of this disclosure, the fusion layer 25 may be formed based on a dielectric layer on the surface of the substrate silicon, since the dielectric layer is typically a compound derived from the substrate silicon. For example, in Figure 1 The semiconductor-on-insulator 100 shown includes a dielectric layer 15, which is, for example, silicon oxide (SiO2) obtained by natural oxidation of the substrate. A fusion layer can then be directly formed on this dielectric layer 15. In this embodiment, the fusion layer is formed directly based on the dielectric layer, thus eliminating the need for additional processes to remove the dielectric layer to grow the fusion layer, and also eliminating the need to change existing materials and processes for fabricating semiconductors-on-insulators.

[0057] return Figure 2 The trap-rich layer 22 includes a first side and a second side. For example, the first side of the trap-rich layer 22 is in contact with the fusion layer 25, and the second side of the trap-rich layer 22 is the side away from the substrate layer 21 or the fusion layer 25. Figure 2 In the example, the first side of the rich trap layer 22 is located below the second side of the rich trap layer 22.

[0058] The buried oxide layer 23 includes a first side and a second side, for example, the first side of the buried oxide layer 23 is in contact with the second side of the trap-rich layer 22. The second side of the buried oxide layer 23 is the side away from the trap-rich layer 22. For example, the device layer 24 is in contact with the second side of the buried oxide layer 23. Figure 2 In the example, the first side of the buried oxide layer 23 is located below the second side of the buried oxide layer 23. That is, the first side of the buried oxide layer 23 is closer to the trap-rich layer 22 relative to the second side. The second side of the buried oxide layer 23 is closer to the device layer 24 relative to the first side.

[0059] The following sections will describe the fusion layer 25, substrate layer 21, trap-rich layer 22, buried oxide layer 23, and device layer 24.

[0060] In some embodiments of this disclosure, the lattice structure or surface structure of the fusion layer 25 is configured to guide the growth of the trap-rich layer. In this embodiment, the fusion layer 25 acts as a seed layer, i.e., guiding the growth of the trap-rich layer 22. This allows for easier control of the grain size of the trap-rich layer 22 and reduces its surface roughness, making it easier for the trap-rich layer 22 to bond with the buried oxide layer 23. Therefore, the semiconductor-on-insulator 200 can enhance the connection between the trap-rich layer 22 and the substrate layer 21 while ensuring that the resistivity of the substrate layer 21 does not decrease, thereby improving the trap-rich layer 22's ability to trap impurities and reducing harmonic effects in radio frequency devices. It also allows for easier control of the grain size of the trap-rich layer 22 and reduces its surface roughness, making it easier for the trap-rich layer 22 to bond with the buried oxide layer 23.

[0061] For example, the substrate layer 21 is monocrystalline silicon. Monocrystalline silicon is very reactive and will form a dense SiO2 layer under natural conditions. This dense SiO2 film serves as a dielectric layer. A seed layer is grown on the basis of this SiO2 film. At the same time as the seed layer is grown, the SiO2 film is annealed and melted at high temperature to form a fusion layer.

[0062] In some embodiments of this disclosure, the concentration of migrating elements on the side of the fusion layer closer to the substrate is greater than the concentration of migrating elements on the side of the fusion layer closer to the trap-rich layer. For example, during the formation of the fusion layer by high-temperature annealing of the SiO2 film while growing the seed layer, oxygen atoms in the SiO2 film migrate from the side closer to the substrate to the side farther from the substrate. The oxygen atom concentration is higher on the side closer to the substrate and decreases with increasing distance from the substrate. For example, oxygen atoms can be observed under a microscope at the location of the fusion layer close to the substrate, while oxygen atoms are absent at the location of the fusion layer farther from the substrate, consisting only of polycrystalline silicon (i.e., the conventional seed layer).

[0063] For example, the lattice structure of the fusion layer 25 matches the lattice structure of the trap-rich layer 22. For example, the fit between the lattice structure of the fusion layer 25 and the lattice structure of the trap-rich layer 22 is less than 5%.

[0064] For example, the surface structure of the fusion layer 25 can guide the growth of the trap-rich layer 22 by exposing specific crystal planes or by its own preferred orientation. Alternatively, the fusion layer 25 can guide the growth of the trap-rich layer 22 by allowing atoms to preferentially nucleate at active sites on the surface of the seed layer through surface chemisorption.

[0065] For example, the fusion layer 25 comprises polycrystalline silicon, and the trap-rich layer 22 comprises polycrystalline silicon. The fact that the fusion layer 25 and the trap-rich layer 22 are made of the same material (polycrystalline silicon) makes it easier for the lattices of the fusion layer 25 and the trap-rich layer 22 to match, and easier to guide the growth of the trap-rich layer 22.

[0066] In some embodiments of this disclosure, the grain size of the polysilicon in the fusion layer 25 is smaller than the grain size of the polysilicon in the trap-rich layer 22. This embodiment utilizes controllable lattice differences in the same material (polysilicon) to introduce compressive stress, thereby improving carrier mobility, optimizing device electrical performance, and guiding grain orientation to reduce defect density.

[0067] In some embodiments of this disclosure, migrating elements are distributed at the grain boundaries of the fusion layer 25. For example, the fusion layer 25 comprises polysilicon, and the migrating elements are located within the grain boundaries of the polysilicon. In other embodiments of this disclosure, the migrating elements may also be located within the grains.

[0068] In some embodiments of this disclosure, for example, a fusion layer 25 is obtained by reacting trichlorosilane with silicon oxide (SiO2) at a high temperature, wherein the fusion layer 25 is polycrystalline silicon including oxygen atoms.

[0069] In other embodiments of this disclosure, the compound is silicon nitride, and the migrating element is nitrogen atoms. In this embodiment, the fusion layer is, for example, polycrystalline silicon comprising nitrogen atoms. For example, polycrystalline silicon is obtained based on trichlorosilane, and nitrogen atoms in the silicon nitride diffuse into the grain boundaries of the polycrystalline silicon at high temperature, thereby obtaining the fusion layer.

[0070] In some embodiments of this disclosure, the substrate layer 21 is used to provide support. The substrate layer 21 may be, for example, any one of high-resistivity polycrystalline silicon, high-resistivity monocrystalline silicon, low-resistivity polycrystalline silicon, and low-resistivity monocrystalline silicon.

[0071] As the bottom layer of the wafer, substrate 21 needs to meet requirements such as high mechanical strength, stable electrical performance, and minimal interference to top-layer devices. Therefore, in some embodiments of this disclosure, substrate 21 may have a high-resistivity silicon substrate, which reduces the electrical interference of the substrate itself and synergistically improves device performance with the trap-rich layer 22 and buried oxide layer 23. For example, the resistivity of substrate 21 is greater than 5000 ohm·cm. High-resistivity silicon substrates are beneficial for achieving characteristics such as low parasitic effects, high insulation isolation, and resistance to radiation interference, making them suitable for device scenarios with stringent electrical performance requirements. For example, the resistivity of the substrate layer 21 can be any value from 5500 ohm·cm, 6000 ohm·cm, 6500 ohm·cm, 7000 ohm·cm, 7500 ohm·cm, 8000 ohm·cm, 8500 ohm·cm, 9000 ohm·cm, 9500 ohm·cm, or 10000 ohm·cm, or any value within a range of any two values.

[0072] In some embodiments of this disclosure, the substrate 21 can be monocrystalline silicon. For example, the substrate 21 can be monocrystalline silicon doped with P-type impurities, i.e., the substrate 21 is P-type monocrystalline silicon. The embodiments of this disclosure do not specifically limit the P-type impurities; for example, the P-type impurity can be boron, etc. P-type monocrystalline silicon can be directly used to manufacture basic devices such as diodes and transistors, and has good compatibility with traditional processes such as photolithography and etching, reducing the difficulty of process development.

[0073] In some embodiments of this disclosure, the thickness of the substrate layer 21 is 400 μm to 800 μm. Exemplarily, the thickness of the substrate layer 21 may be any one of 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, or 750 μm, or any value within a range of any two values. If the thickness of the substrate layer 21 is too large (e.g., greater than 800 μm), the resulting semiconductor-on-insulator may experience problems such as photolithography defocusing, thermal stress warping, increased material and manufacturing costs, extended process time, and reduced equipment compatibility in subsequent processes. If the thickness of the substrate layer 21 is too small (e.g., less than 400 μm), the resulting semiconductor-on-insulator will have lower mechanical strength due to its lower overall thickness, resulting in problems such as easy breakage of the overall wafer structure, severe warping, prominent thermal stress problems, difficulty in transport processing, the need for special support (e.g., including but not limited to temporary bonding), high packaging difficulty, and high risks in the thinning process. Therefore, setting the thickness of the substrate layer 21 in the range of 400~800μm can alleviate the occurrence of the above-mentioned adverse phenomena.

[0074] Although high-resistivity silicon itself has high resistivity, at high frequencies (such as above GHz), the parasitic conductive layer formed by parasitic surface charges (such as fixed oxide charges and interface states) leads to a decrease in effective resistivity (known as the "trap-poor" effect), increasing the coupling loss of substrate layer 21. A trap-rich layer 22 is introduced below the buried oxide layer (BOX) 23 to trap parasitic charges through high-density grain boundaries and defect states, suppressing the formation of surface conductive channels. Combined with the high-resistivity substrate, the high effective resistivity of the substrate can be maintained (even at high frequencies), significantly reducing substrate losses in signal transmission (such as insertion loss and crosstalk). Furthermore, fluctuations in parasitic charges cause substrate impedance to change with frequency or voltage, introducing nonlinear distortion (such as harmonics and intermodulation distortion); the trap-rich layer 22 acts as a charge buffer layer, stabilizing the interface potential and reducing nonlinear changes in substrate impedance, making it particularly suitable for RF devices requiring high linearity (such as power amplifiers and switches). The charge trapping effect of the trap-rich layer 22 suppresses parasitic current paths in the substrate and reduces crosstalk between adjacent devices (such as the isolation between the receiver and transmitter in an RF chip). In mixed-signal designs, it can reduce the interference of digital noise on sensitive analog or RF circuits. The trap-rich layer 22 acts as a buffer layer and modulates stress. The trap-rich layer alters the electrical or optical behavior of the material by introducing deep or shallow level defects (such as vacancies, interstitial atoms, dislocations, etc.). For example, in semiconductors, traps can capture electrons or holes.

[0075] In some embodiments of this disclosure, a trap-rich layer 22 with controllable defect density can be formed by techniques such as oxygen ion implantation, electron beam bombardment, and femtosecond laser. However, for example in... Figure 1 In the structure of the semiconductor-on-insulator 100 shown, the grain size of the trap-rich layer 22 grown directly on the dielectric layer is difficult to control, and the surface roughness of the trap-rich layer 22 is high, resulting in a low bonding force between the trap-rich layer 22 and the buried oxide layer.

[0076] In the semiconductor-on-insulator 200 provided in this disclosure, the fusion layer 25 can be regarded as a seed layer guiding the growth of the trap-rich layer 22. Through this seed layer, the grain size of the trap-rich layer 22 can be better controlled, the surface roughness can be reduced, and the bonding force of the subsequent semiconductor-on-insulator can be increased. In addition, the seed layer is a seed layer that includes migration elements, so it can also act as a dielectric layer, that is, ensure that the resistivity of the substrate layer does not decrease.

[0077] In some embodiments of this disclosure, the trap-rich layer 22 is an amorphous or polycrystalline structure. Preferably, the trap-rich layer 22 is polycrystalline silicon, and therefore the trap-rich layer 22 is also referred to as a polycrystalline layer. Polycrystalline silicon is composed of a large number of tiny grains, and there are a large number of dangling bonds and defects at the grain boundaries, which naturally form the desired "traps".

[0078] In some embodiments of this disclosure, the trap-rich layer 22 and the fusion layer 25 are formed from the same material, such as polysilicon obtained from trichlorosilane, and the grain size of the trap-rich layer 22 and the fusion layer 25 is distinguished by controlling the temperature. For example, the grain size of the polysilicon in the fusion layer is smaller than the grain size of the polysilicon in the trap-rich layer.

[0079] In the embodiments of this disclosure, those skilled in the art can control the thickness of the fusion layer according to actual needs. For example, the thickness of the fusion layer can be controlled by controlling the flow rate of trichlorosilane and the implantation time of trichlorosilane at different temperatures. For example, the sum of the thicknesses of the semiconductor trap-rich layer 22 and the fusion layer 25 on the insulator, as observed by a microscope, is, for example, 1.7~1.9 μm.

[0080] In some embodiments of this disclosure, the thickness of the trap-rich layer 22 is 0.5 μm to 3 μm. Exemplarily, the thickness of the trap-rich layer 22 is any one of 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 2 μm, 2.5 μm, or 2.8 μm, or any value within a range consisting of any two values. If the thickness of the trap-rich layer 22 is too large (e.g., greater than 3 μm), it will increase parasitic capacitance, thereby degrading RF performance; it will also hinder heat dissipation, thereby affecting the reliability and power of the overall wafer structure; it will increase the internal stress of the wafer, thereby increasing the risk of warpage and cost; and it may also cause the carrier trapping effect of the trap-rich layer to reach saturation prematurely. If the thickness of the trap-rich layer 22 is too small (e.g., less than 0.5 μm), it will not be able to effectively isolate the substrate, leading to a sharp increase in RF loss, severe crosstalk, deterioration of linearity, significant substrate modulation effect, and complete loss of the functions that the high-resistivity polycrystalline layer or the trap-rich layer 22 should have. It will also bring problems such as difficulty in uniformity control and weakened mechanical support. Therefore, limiting the thickness of the trap-rich layer 22 to the range of 0.5~3μm can alleviate the above-mentioned problems.

[0081] In some embodiments of this disclosure, the grain size of the trap-rich layer 22 (i.e., the average size or size distribution of individual crystal particles (i.e., "grains"), also referred to as "grain size") is 100 nm to 1000 nm. Exemplarily, the grain size of the trap-rich layer 22 is any one of 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, or 900 nm, or any value within a range consisting of any two values. The grain size determines the grain boundary density, thereby controlling the number of traps, the carrier transport matrix, and the overall resistivity. If the grain size is too large (e.g., greater than 1000 nm), the purpose of trapping carriers in the trap-rich layer 22 will fail, leading to catastrophic linearity deterioration and substrate modulation problems, which need to be avoided in SOI applications for radio frequency. If the grain size is too small (e.g., less than 100 nm), although a larger trap density can be obtained, it will lead to a significant decrease in resistivity, resulting in a sharp increase in ohmic loss and deterioration in isolation.

[0082] In some embodiments of this disclosure, the trap density (i.e., the number of traps per cubic centimeter) of the trap-rich layer 22 is 10. 16 cm -3 ~10 18 cm -3 For example, the trap density of the trap-rich layer 22 is 3 × 10⁻⁶. 16 cm -3 5×10 16 cm -3 7×10 16 cm -3 1×10 17 cm -3 3×10 17 cm -3 5×10 17 cm -3 7×10 17 cm -3 Or 9×10 17 cm -3 Any value in the range or any value within a range consisting of any two values. If the trap density is too high (e.g., greater than 10). 18 cm -3 While it effectively "pins" surface potentials and suppresses parasitic surface channels and coupling noise, it introduces too many negative effects, such as a severe decrease in carrier mobility, significant frequency dispersion increasing performance instability, excessively high dielectric loss, and reduced reliability. If the trap density is too small (e.g., less than 10), further issues arise. 16 cm -3If the trap-rich layer fails to perform its intended function of capturing charge carriers, it will be unable to effectively suppress parasitic surface channels, resulting in a decrease in the effective resistivity of the substrate and an inability to "pin" the surface potential.

[0083] In some embodiments of this disclosure, the energy level distribution of the trap-rich layer 22 is Ec-0.2eV to 0.4eV. Exemplarily, the energy level distribution of the trap-rich layer 22 is any one of Ec-0.25eV, Ec-0.3eV, Ec-0.35eV, or Ec-0.38eV, or any value within a range consisting of any two values. If the trap energy levels are too deep, for example, greater than 0.38eV, greater than 0.5eV, or deeper, such traps are called "deep-level traps." These traps have extremely slow charging and discharging rates, resulting in a slower response speed and exacerbating temperature uncertainty. They may also fail to effectively suppress low-frequency parasitic effects. If the trap energy level is too shallow, such as less than 0.25 eV, less than 0.2 eV, or less than 0.1 eV, then such traps are called "shallow-level traps". They have excessively fast charging and discharging speeds, can fail due to thermal excitation, introduce additional scattering centers, and have the defect of excessively low mobility.

[0084] In some embodiments of this disclosure, the dielectric constant of the trap-rich layer 22 is 11.7 ± 0.5. Exemplarily, the dielectric constant of the trap-rich layer 22 is any one of 11.2, 11.3, 11.4, 11.5, 11.6, 11.7, 12, or 12.2, or any value within a range consisting of any two values.

[0085] In some embodiments of this disclosure, the interface state density of the trap-rich layer 22 is 10. 10 eV -1 cm -2 ~10 12 eV - 1 cm -2 For example, the interface state density of the trap-rich layer 22 is 3 × 10⁻⁶. 10 eV -1 cm -2 5×10 10 eV -1 cm -2 8×10 10 eV - 1 cm -2 1×10 11 eV -1 cm -2 3×1011 eV -1 cm -2 5×10 11 eV -1 cm -2 7×10 11 eV -1 cm -2 Or 9×10 11 eV -1 cm -2 Any value in the range or any value within the range of any two values. If the interface state density is too high, for example, greater than 10... 12 eV -1 cm -2 A high interface state density implies poor interface quality between the trap-rich layer 22 and the buried oxide layer 23, introducing a series of adverse problems related to carrier transport and stability, such as severe carrier mobility degradation, severe frequency dispersion, noise performance deterioration, threshold voltage instability, and hysteresis effects. Conversely, if the interface state density is too low, for example, less than 10... 10 eV -1 cm -2 It is difficult to form an effective depletion and shield.

[0086] In some embodiments of this disclosure, the thermal stability of the trap-rich layer 22 is ≤1200°C. Exemplarily, the thermal stability of the trap-rich layer 22 is any one of 1150°C, 1100°C, 1050°C, or 1000°C, or any value within a range of any two values. After undergoing a high-temperature annealing process exceeding 1200°C or even higher, the traps or defects in the trap-rich layer 22 may undergo annihilation, recombination, or other adverse changes, leading to uncontrollable trap properties and limitations in stress engineering.

[0087] In some embodiments of this disclosure, the stress intensity of the trap-rich layer 22 is 200 MPa to 600 MPa. Exemplarily, the stress intensity of the trap-rich layer 22 is any one of 250 MPa, 300 MPa, 350 MPa, 400 MPa, 450 MPa, 500 MPa, 550 MPa, or 580 MPa, or any value within a range consisting of any two values. If the stress intensity is too high (e.g., greater than 600 MPa), it can lead to reliability issues, lattice defects, and unstable electrical parameters, and may also cause wafer warping, difficult photolithography, poor process compatibility, and shortened carrier lifetime. If the stress intensity is too low (e.g., less than 200 MPa), it means that the trap-rich layer 22 is too "relaxed," which may stem from its overly disordered or porous structure. This can lead to a series of problems, such as insufficient mechanical strength and stability, poor thermal stability, and poor shielding effect. The aforementioned trap-rich layer 22 can exhibit ideal carrier mobility, good mechanical stability, and a stable structure within a stress window of 200~600MPa.

[0088] In some embodiments of this disclosure, the trap-rich layer 22 has a higher thermal conductivity than the buried oxide layer 23. The higher thermal conductivity of the trap-rich layer 22 (i.e., polycrystalline silicon) improves heat diffusion to the high-resistivity substrate, balancing electrical and thermal properties. For example, the buried oxide layer 23 may be silicon dioxide (SiO2), which typically has a low thermal conductivity of approximately 1.4 W / m·K, easily leading to localized heat accumulation. Therefore, the thermal conductivity of polycrystalline silicon, approximately 30 W / m·K, is higher than that of the buried oxide layer 23.

[0089] In some embodiments of this disclosure, the trap-rich layer 22 includes a dopant element. For example, the dopant element is boron.

[0090] In some embodiments of this disclosure, the doping amount of the dopant element (e.g., boron) is 1 × 10⁻⁶. 10 atmos / cm 3 ~5×10 10 atmos / cm 3 For example, the boron doping level is 2 × 10⁻⁶. 10 atmos / cm 3 3×10 10 atmos / cm 3 Or 4×10 10 atmos / cm 3The boron doping concentration can be any value within the range of values, or any value within the range of any two values. If the boron doping concentration is too high, the substrate cannot maintain a high resistivity, losing its advantages as a high-performance RF substrate. For example, problems may occur such as decreased substrate resistivity, loss of the shielding effect of the trap layer, and reduced effective trap density. Conversely, if the boron doping concentration is too low, problems arise such as difficulty in controlling resistivity uniformity, extreme sensitivity to contamination, the presence of de-trapping effects, and carrier dominance during thermal excitation. The boron doping concentration is 1 × 10⁻⁶. 10 atmos / cm 3 ~5×10 10 atmos / cm 3 This can at least partially avoid the above problems.

[0091] In some embodiments of this disclosure, the trap-rich layer 22 is obtained through a deposition process (e.g., low-pressure chemical vapor deposition (LPCVD)). For example, it can be obtained by epitaxial growth. Implementations for generating the trap-rich layer 22 are described below.

[0092] In some embodiments of this disclosure, the material of the buried oxide layer 23 is SiO2.

[0093] In some embodiments of this disclosure, the thickness of the buried oxide layer 23 is 0.1 μm to 4 μm. Exemplarily, the thickness of the buried oxide layer 23 is any one of 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 2.8 μm, or any value within a range consisting of any two values. If the thickness of the buried oxide layer 23 is too large, the difficulty and cost of wafer manufacturing will increase dramatically, and mechanical stress and wafer warping problems will also occur, and the benefits of reducing parasitic capacitance will diminish. If the thickness of the buried oxide layer is too thin, RF loss and isolation will deteriorate sharply, and the back-gate effect will be significant, and the effect of the trap-rich layer 22 will be limited, increasing the risk of breakdown and causing reliability problems. Setting the thickness of the buried oxide layer 23 within the above-mentioned range can at least partially avoid the occurrence of the above problems.

[0094] In some embodiments of this disclosure, the buried oxide layer 23 is formed by thermal oxidation or chemical vapor deposition. Implementation methods for generating the buried oxide layer 23 are described below.

[0095] In some embodiments of this disclosure, device layer 24 is made of single-crystal silicon. As the active region of the device, device layer 24 can be made of high-quality single-crystal material to ensure high mobility of charge carriers (electrons and holes). The thinness of device layer 24, for example, between tens and hundreds of nanometers, helps reduce parasitic capacitance and improve device speed.

[0096] In some embodiments of this disclosure, the semiconductor-on-insulator further includes an oxide layer located between the trap-rich layer and the buried oxide layer.

[0097] Figure 3 A schematic diagram of the structure of a semiconductor-on-insulator 300 provided in another embodiment of the present disclosure is shown.

[0098] like Figure 3 As shown, the semiconductor-on-insulator 300 is similar in structure to the semiconductor-on-insulator 200 except for the addition of an oxide layer 31. The oxide layer 31 is located between the trap-rich layer 22 and the buried oxide layer 23. The oxide layer 31 is, for example, obtained by oxidizing the surface of the trap-rich layer 22. In this embodiment, the addition of an oxide layer 31 between the trap-rich layer 22 and the buried oxide layer 23 reduces the requirements on the surfaces of the trap-rich layer 22 and the buried oxide layer 23 for bonding.

[0099] The above description uses silicon-on-insulator (SiI) as an example to illustrate embodiments of semiconductor-on-insulator (SOS) of this disclosure, where the substrate layer, fusion layer, trap-rich layer, buried oxide layer, and device layer are all based on silicon. However, the embodiments of this disclosure are not limited to this; SOS can also be based on other semiconductors, such as germanium (Ge) or other compounds.

[0100] Figure 4 A flowchart illustrating a method for fabricating a semiconductor on insulator according to at least one embodiment of the present disclosure is shown. Figure 5 A schematic diagram of a method for fabricating a semiconductor on insulator according to at least one embodiment of the present disclosure is shown.

[0101] like Figure 4 As shown, the preparation method includes steps S10 to S40.

[0102] Step S10: Provide a first donor, the first donor comprising a substrate layer and a compound generated based on the substrate layer.

[0103] Step S20: A fusion layer is generated based on the diffusion of migrating elements of the compound, and a trap-rich layer is obtained based on the fusion layer.

[0104] Step S30: Provide a second donor as a device layer and form a buried oxide layer on the surface of the second donor.

[0105] Step S40: Combine the trap-rich layer with the buried oxide layer to obtain a semiconductor on insulator.

[0106] The fusion layer obtained by this preparation method includes migrating elements, which can enhance the connection between the trap-rich layer and the substrate while ensuring that the resistivity of the substrate does not decrease, thereby improving the trap-rich layer's ability to capture impurities and reducing harmonic effects in radio frequency devices.

[0107] For step S10, the substrate can be any one of high-resistivity polycrystalline silicon, high-resistivity monocrystalline silicon, low-resistivity polycrystalline silicon, or low-resistivity monocrystalline silicon. Please refer to the description above for the compound generated based on the substrate.

[0108] like Figure 5 As shown in (a), the first donor 50 includes a substrate layer 501 and a compound 502 located on the surface of the substrate layer, the compound 502 being obtained based on the substrate layer. The substrate layer 501 is, for example, monocrystalline silicon, and the compound 502 is, for example, a silicon oxide thin film obtained by natural oxidation of the surface of monocrystalline silicon.

[0109] For example, the substrate 501 is monocrystalline silicon, and the compound 502 is, for example, a thin film of a compound (e.g., silicon nitride, silicon oxynitride, etc.) formed on the surface of monocrystalline silicon by a process.

[0110] In some embodiments of this disclosure, the substrate layer can be high-resistivity silicon. High-resistivity silicon can reduce the electrical interference of the substrate itself and, together with the trap-rich layer and buried oxide layer, improve the device performance. This is beneficial for achieving characteristics such as low parasitic effects, high insulation isolation, and anti-radiation interference, making it suitable for device scenarios with stringent electrical performance requirements.

[0111] Preferably, the substrate can be P-type monocrystalline silicon, that is, monocrystalline silicon doped with P-type impurities (e.g., boron). Please refer to the description of the substrate above for further details; it will not be repeated here.

[0112] For step S20, a seed layer is deposited on the first donor via a deposition process (e.g., low-pressure chemical vapor deposition, LPCVD). The seed layer is then bonded to a thin film (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) on the substrate surface to form a fusion layer. For example, the deposition process includes epitaxial growth, using a silicon source precursor as the initial material for the fusion layer. The seed layer is obtained on the first donor via epitaxial growth, and during the epitaxial growth process, the thin film on the substrate surface ablates and bonds to the seed layer to form the fusion layer. The silicon source precursor is, for example, a reactive gas containing epitaxial material, such as trichlorosilane (SiHCl3) or dichlorosilane (SiH2Cl2).

[0113] For example, a seed layer is a layer of polycrystalline silicon that grows slowly at 650-800℃. This layer has a slow growth rate and a small lattice, hence the name seed layer.

[0114] After obtaining the fusion layer, a trap-rich layer can be obtained, for example, through epitaxial growth. For instance, the silicon source precursor used for epitaxial growth of the fusion layer and the trap-rich layer may be the same, but the epitaxial growth environment (e.g., different temperatures) may differ, resulting in fusion layers and trap-rich layers with different grain sizes. Using the same silicon source precursor for both the fusion layer and the trap-rich layer not only simplifies the process but also makes it easier to guide the growth of the trap-rich layer from the fusion layer.

[0115] like Figure 5 As shown in (a) and (b), while a seed layer is epitaxially grown on the surface of the first donor, compound 502 is ablated (i.e., migrating elements diffuse into the seed layer), thereby fusing compound 502 with the seed layer to form a fusion layer 503. Subsequently, a trap-rich layer 504 is epitaxially grown on the fusion layer 503.

[0116] For step S30, the device layer is, for example, monocrystalline silicon. Please refer to the description above for information on the second donor and the buried oxide layer.

[0117] like Figure 5 As shown in (c), the second donor is device layer 60, on which buried oxide layer 601 is formed.

[0118] In some embodiments of this disclosure, step S30 includes forming an oxygen-buried layer on the surface of the second donor by a wet oxygen or dry oxygen process.

[0119] In some embodiments of this disclosure, for the wet oxidation method, the second donor silicon is pretreated at an environment of 700°C to 750°C to remove organic matter, metallic impurities, and native oxide layers from its surface, thus avoiding contamination of the oxide layer or defects. Then, the temperature is increased at a rate of 3 to 8°C / min. When the temperature reaches 800 to 1100°C, a mixture of hydrogen and oxygen is introduced to thermally oxidize the second donor silicon to form a buried oxide layer. The hydrogen flow rate is, for example, 5 L / min to 10 L / min, and the oxygen flow rate is 2.5 L / min to 8 L / min. The wet oxidation method has a faster growth rate and higher efficiency.

[0120] In some embodiments of this disclosure, for the dry oxidation method, after pretreating the second donor silicon at an environment of 700-750°C, the temperature is increased at a rate of 3-10°C / min. When the temperature reaches 800-1100°C, oxygen is introduced at a rate of 5-15 L / min to react with the second donor silicon to obtain a buried oxide layer. The dry oxidation method can yield oxide films with higher density, resulting in silicon dioxide films with higher electrical quality and reliability.

[0121] In some embodiments of this disclosure, the thickness of the buried oxide layer 601 is 0.1~3μm. For example, the thickness of the buried oxide layer 601 is any one of 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm or 2.8μm, or any one of any two values ​​within a range of values.

[0122] return Figure 4 Step S40 includes bonding the trap-rich layer to the buried oxide layer to obtain a semiconductor-on-insulator.

[0123] In this embodiment, the trap-rich layer and the buried oxide layer are directly bonded to obtain a semiconductor-on-insulator, with the trap-rich layer and the buried oxide layer in direct contact. In this embodiment, the bonding is achieved, for example, through the interaction between surface hydrogen atoms (-H) (i.e., HH bonding), utilizing van der Waals forces. This embodiment has low process complexity but requires high-quality surface treatment.

[0124] like Figure 5 As shown in (d), the trap-rich layer 504 is bonded to the buried oxide layer 601 to obtain the semiconductor-on-insulator 600.

[0125] In other embodiments of this disclosure, an oxide layer is formed on the surface of the trap-rich layer; and the oxide layer is bonded to the buried oxide layer to obtain a semiconductor-on-insulator. This embodiment has higher process complexity but less stringent surface requirements.

[0126] like Figure 5 As shown in (e), an oxide layer 602 is formed on the surface of the trap-rich layer 504; and the oxide layer 602 is bonded to the buried oxide layer 601 to obtain a semiconductor-on-insulator 700. In some embodiments of this disclosure, the oxide layer may be obtained using a wet oxide process or a dry oxide process. For details regarding wet oxide and dry oxide processes, please refer to the description above.

[0127] In some embodiments of this disclosure, bonding can be performed by room temperature bonding or vacuum bonding.

[0128] For example, for room temperature bonding, a 0.5-2 wt.% ammonia solution is used at 20-25°C to perform surface activation pretreatment on the trap-rich layer 504 and the buried oxide layer 601. A pressure of 1.5-3 N is applied to the pressure pad, with the pressure application point 9-30 mm away from the positioning groove. The pressure pad is a flexible or rigid component in the bonding equipment used to uniformly transmit the set pressure to the surface of the bonding components, preventing the pressure application mechanism from directly contacting the substrate and causing damage. The positioning groove is a recessed mechanical structure in the bonding equipment used to fix the position of the substrate (trap-rich layer, buried oxide layer). Another example is using a 0.8 wt.% ammonia solution at 22°C to perform surface activation pretreatment on the trap-rich layer 504 and the buried oxide layer 601. A pressure of 1.8 N is applied to the pressure pad, with the pressure application point 10 mm away from the positioning groove.

[0129] For example, in vacuum bonding, the trap-rich layer 504 and the buried oxide layer 601 are pretreated with ammonia solution at a concentration of 0.5-2 wt.% at 20-25°C for surface activation, and then subjected to a vacuum environment for 10... -3 ~10 -6 Apply a pressure of 1.5~3N to the pressure pad under the condition of Pa, and the pressure application position is 9~30mm away from the positioning groove.

[0130] For example, the trap-rich layer 504 and the buried oxygen layer 601 were pretreated with ammonia solution at a concentration of 0.6 wt.% at 22°C, and then subjected to surface activation in a vacuum environment for 10 minutes. -4 A pressure of 1.5 N is applied to the pressure pad under the condition of Pa, and the pressure application position is 10 mm away from the positioning groove.

[0131] Figure 6 A flowchart of a method for generating a fusion layer based on the diffusion of migrating elements of a compound, provided in at least one embodiment of this disclosure, is shown.

[0132] like Figure 6 As shown, step S20 includes steps S21 to S22.

[0133] Step S21: Place the first donor in a reaction chamber at a first temperature for a preset time length.

[0134] Step S22: Under the condition that the reaction chamber is at the second temperature, a silicon source precursor is injected into the reaction chamber, and the migrating elements in the compound in the reaction chamber diffuse and combine with the silicon source precursor to obtain a fusion layer.

[0135] For step S21, in some embodiments of this disclosure, the first donor is placed in the reaction chamber at the first temperature for a preset time period, and this preset time period is maintained. At this first temperature, the compound on the surface of the first donor is retained. During this preset time period, no other operation may be performed on the reaction chamber or the first donor; simply placing the first donor in the reaction chamber at the first temperature is sufficient. Placing the first donor in the reaction chamber at the first temperature for a preset time stabilizes the temperature within the reaction chamber, facilitating more precise subsequent temperature control. This preset time period is, for example, 60 seconds (s), 70 seconds, etc. The preset time period can be set by those skilled in the art based on experience or requirements. The first temperature is, for example, between 850°C and 1200°C.

[0136] In some other embodiments of this disclosure, after the first donor is placed in a reaction chamber at a first temperature, an inert gas that does not react with the compound is injected into the reaction chamber to pretreat the first donor in the reaction chamber for a predetermined time.

[0137] During a predetermined time period, the first donor is placed in a reaction chamber at a first temperature, and an inert gas is introduced into the reaction chamber for pretreatment while ensuring that the compound on the first donor is retained. In this embodiment, the predetermined time period is, for example, 120 seconds.

[0138] Inert gases can be, for example, helium, nitrogen, argon, etc. Inert gases can also be mixtures of multiple gases. For example, if the compound is silicon oxide, then the inert gas cannot be hydrogen, because hydrogen has reducing properties, which would prevent silicon oxide from being retained.

[0139] Inert gases can not only carry away reaction products and adsorbed impurities (such as organic matter and metal ions) through airflow, but also conduct heat, making the temperature in the reaction chamber uniform and stable.

[0140] The reaction chamber is, for example, an epitaxial reactor. An epitaxial reactor is a core piece of equipment in semiconductor manufacturing used for the epitaxial growth process. Epitaxial growth is a technique for precisely growing single-crystal thin films (epitaxy layers) on the surface of a substrate (such as a silicon wafer or compound semiconductor substrate). It allows for precise control of thickness, doping concentration, and crystal quality, and is a key process equipment for improving the performance of semiconductor devices.

[0141] For step S22, for example, the second temperature is lower than the first temperature. After the reaction chamber stabilizes at the first temperature, the reaction chamber is cooled to the second temperature. The second temperature is, for example, between 600°C and 800°C.

[0142] For example, at a second temperature of 750°C, trichlorosilane is introduced into the reaction chamber to grow a seed layer. The seed layer can be grown for 2 minutes, 3 minutes, etc., and those skilled in the art can control the growth time based on requirements such as seed layer thickness and experience. For example, at a second temperature of 650°C, trichlorosilane is introduced into the reaction chamber to grow a seed layer for 5 minutes.

[0143] A silicon source precursor is injected into the reaction chamber, and migrating elements in the compound in the reaction chamber diffuse and combine with the silicon source precursor to form a fusion layer.

[0144] At the second temperature, polycrystalline silicon is grown based on trichlorosilane as a seed layer. Simultaneously, the oxide film on the substrate surface melts, and oxygen atoms diffuse from the oxide film, thus fusing the oxide film and the seed layer into a fused layer. Please refer to the description above for information on silicon source precursors and migrating elements.

[0145] In some embodiments of this disclosure, obtaining a trap-rich layer based on the fusion layer includes: raising the temperature of the reaction chamber from a second temperature to a third temperature, and continuing to inject silicon source precursors into the reaction chamber to obtain a trap-rich layer based on the fusion layer.

[0146] For example, the third temperature is between 800℃ and 1000℃. The third temperature can be the same as the first temperature. For example, the second temperature can be raised to the third temperature using a heat lamp radiant heating method.

[0147] For example, after growing a seed layer of trichlorosilane at 650°C for 5 minutes to obtain a fusion layer, the temperature is increased to 900°C to grow a polycrystalline layer as a trap-rich layer.

[0148] For example, after growing a seed layer of trichlorosilane at 750°C for 2 minutes to obtain a fusion layer, the temperature is increased to 920°C to grow a polycrystalline layer as a trap-rich layer.

[0149] In some embodiments of this disclosure, when a silicon source precursor is injected into an epitaxial reactor to grow a trap-rich layer (i.e., under a third temperature condition), dopant elements such as boron and phosphorus (e.g., gases) can be injected simultaneously. By introducing specific impurities (such as boron) through dopant injection, a large number of "trap energy levels" are formed to trap charge carriers or defects, thereby optimizing device performance.

[0150] In some embodiments of this disclosure, the growth time of the silicon source precursor on the substrate and the flow rate of the silicon source precursor are controlled according to the thickness of the trap-rich layer. For example, the greater the thickness of the trap-rich layer, the longer the growth time of the silicon source precursor on the substrate and the greater the flow rate of the silicon source precursor. For example, the thickness of the trap-rich layer is 0.5 μm to 3 μm, the growth time is about 200 s, and the flow rate of the silicon source precursor is 2 slm to 3 slm.

[0151] The preparation method of this disclosure is further described below with reference to specific embodiments.

[0152] In the first embodiment provided in this disclosure, for example, the substrate is a high-resistivity monocrystalline silicon; the thickness of the high-resistivity monocrystalline silicon is 725 μm; the thickness of the silicon dioxide layer obtained by natural oxidation of the surface of the high-resistivity monocrystalline silicon is less than 0.1 μm; the second donor is a P-type monocrystalline silicon; the thickness of the second donor is 725 μm, and the thickness of the silicon dioxide layer (i.e., buried oxide layer) obtained by oxidation of the surface of the second donor is 0.4 μm.

[0153] For example, the first donor is preheated with nitrogen gas for 120 seconds at a temperature of 800°C at a flow rate of 2.5 L / min. Then, trichlorosilane is introduced and the mixture is heated at 650°C for 30 minutes to obtain a fusion layer. The reaction chamber temperature is then increased to 900°C, and trichlorosilane is continued to be introduced to obtain a trap-rich layer. For example, the total thickness of the fusion layer and the trap-rich layer is 1.9 μm. The total thickness of the fusion layer and the trap-rich layer can be measured using a microscope. Since both the fusion layer and the trap-rich layer are polycrystalline silicon with lattice matching, there is no obvious boundary between them under the microscope.

[0154] For example, a wet oxidation method is used to oxidize the second donor to obtain the buried oxygen layer. For example, the second donor is pretreated at 750°C, and then heated at a rate of 5°C / min. When the temperature reaches 950°C, a mixture of hydrogen and oxygen is introduced to thermally oxidize the buried oxygen layer, wherein the hydrogen flow rate is 6 L / min and the oxygen flow rate is 4 L / min.

[0155] Finally, the buried oxygen layer and the trap-rich layer are bonded at room temperature. For example, the surfaces of the trap-rich layer and the buried oxygen layer are activated and pretreated at 22°C using 0.3 wt.% ammonia solution. A pressure of 2 N is applied to the pressure pad, with the pressure point 10 mm away from the positioning groove.

[0156] In the second embodiment provided in this disclosure, for example, the substrate is a P-type monocrystalline silicon; the thickness of the P-type monocrystalline silicon is 650 μm; the thickness of the silicon dioxide layer obtained by natural oxidation of the P-type monocrystalline silicon surface is less than 0.1 μm; the second donor is a P-type monocrystalline silicon; the thickness of the second donor is 650 μm, and the thickness of the silicon dioxide layer (i.e., buried oxide layer) obtained by oxidation of the second donor surface is 0.4 μm.

[0157] For example, the first donor is preheated for 120 seconds at a temperature of, for example, 700°C. Then, trichlorosilane is introduced, and a seed layer is grown at 700°C for 4 minutes to obtain the fusion layer; for example, the vacuum degree is 10. -3The pressure (approximately 0.133 MPa) was then increased to 920°C using a heat lamp. This resulted in a combined fusion layer and a trap-rich layer with a thickness of, for example, 1.814 μm.

[0158] For example, a buried oxygen layer is obtained by oxidizing the second donor using dry oxidation. The second donor is pretreated at 750°C, and then heated at a rate of 10°C / min. When the temperature reaches 950°C, oxygen is introduced at a rate of 10 L / min.

[0159] Finally, the buried oxide layer and the trap-rich layer are bonded at room temperature. For example, vacuum bonding is used, and the surfaces of the polycrystalline silicon layer of the first donor silicon and the oxide layer of the second donor silicon are activated and pretreated at 22°C using 0.5 wt.% ammonia solution, under vacuum for 10 minutes. -3 A pressure of 2N is applied to the pressure pad under the condition of Pa, with the pressure position 10mm away from the positioning groove.

[0160] Figure 7 A schematic diagram of a substrate layer, fusion layer, and trap-rich layer under a microscope is shown, according to at least one embodiment of the present disclosure.

[0161] like Figure 7 As shown, a substrate layer 71, a fusion layer 72, and a trap-rich layer 73 are stacked sequentially. The fusion layer 72 and the trap-rich layer 73 are made of polycrystalline silicon, and the grain size of the fusion layer 72 is smaller than the grain size of the trap-rich layer 73.

[0162] The thickness of the fusion layer 72 and the trap-rich layer 73 is 1.814 μm.

[0163] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. Furthermore, specific examples have been used in the specification to illustrate the principles and implementation methods of the present invention. The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention, and the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A semiconductor-on-insulator, characterized in that, Including the following settings in sequence: Substrate layer; A fusion layer is located on one side of the substrate layer. The fusion layer is obtained by ablation of a compound generated on the substrate layer, and the fusion layer includes a migration element, wherein the migration element is obtained by diffusion of elements in the compound generated on the substrate layer, and the migration element is distributed at the grain boundaries of the fusion layer. A trap-rich layer is located on the side of the fusion layer away from the substrate layer; A buried oxide layer is located on the side of the trap-rich layer away from the substrate layer; and The device layer is located on the side of the buried oxide layer away from the trap-rich layer.

2. The semiconductor-on-insulator according to claim 1, characterized in that, The lattice structure or surface structure of the fusion layer is configured to guide the growth of the trap-rich layer.

3. The semiconductor-on-insulator according to claim 1, characterized in that, The fusion layer comprises polysilicon, and the trap-rich layer comprises polysilicon.

4. The semiconductor-on-insulator according to claim 3, characterized in that, The grain size of polysilicon in the fusion layer is smaller than that of polysilicon in the trap-rich layer.

5. The semiconductor-on-insulator according to claim 1, characterized in that, The concentration of the migrating element on the side of the fusion layer closer to the substrate layer is greater than the concentration of the migrating element on the side of the fusion layer closer to the rich trap layer.

6. The semiconductor-on-insulator according to claim 1, characterized in that, The substrate layer comprises monocrystalline silicon, the compound obtained based on the substrate layer is silicon oxide, and the migrating element is oxygen.

7. The semiconductor-on-insulator according to claim 1, characterized in that, The thermal conductivity of the trap-rich layer is higher than that of the buried oxygen layer.

8. The semiconductor-on-insulator according to claim 1, characterized in that, The trap-rich layer includes doped elements.

9. The semiconductor-on-insulator according to claim 1, characterized in that, The thickness of the buried oxide layer is 0.1 μm to 4 μm.

10. A method for preparing a semiconductor-on-insulator, characterized in that, The method includes: A first donor is provided, wherein the first donor comprises a substrate layer and a compound generated based on the substrate layer; The compound generated on the substrate layer is ablated, and a fusion layer is generated based on the diffusion of migrating elements in the compound. A trap-rich layer is obtained based on the fusion layer, wherein the migrating elements are distributed at the grain boundaries of the fusion layer. A second donor is provided as a device layer, and a buried oxide layer is formed on the surface of the second donor; and The trap-rich layer is combined with the buried oxide layer to obtain the semiconductor-on-insulator.

11. The preparation method according to claim 10, characterized in that, The fusion layer is generated based on the diffusion of the migrating element in the compound, comprising: The first donor is placed in a reaction chamber at a first temperature for a predetermined time; and With the reaction chamber at a second temperature, a silicon source precursor is injected into the reaction chamber, and the migrating element in the compound diffuses and combines with the silicon source precursor to obtain the fusion layer.

12. The preparation method according to claim 11, characterized in that, The rich trap layer is obtained based on the fusion layer, including: The temperature of the reaction chamber is increased from the second temperature to the third temperature, and the silicon source precursor is continued to be injected into the reaction chamber to obtain the trap-rich layer based on the fusion layer.

13. The preparation method according to claim 12, characterized in that, The first temperature is between 850℃ and 1200℃, the second temperature is between 600℃ and 800℃, and the third temperature is between 800℃ and 1000℃.

14. The preparation method according to claim 11, characterized in that, The preset time duration for placing the first donor in the reaction chamber at the first temperature includes: After placing the first donor in the reaction chamber at the first temperature, an inert gas that does not react with the compound is injected into the reaction chamber to pretreat the first donor in the reaction chamber for the preset time length.

15. The preparation method according to claim 11, characterized in that, The substrate layer comprises monocrystalline silicon, and the compound generated on the substrate layer is silicon oxide obtained by natural oxidation of the substrate layer, wherein the migrating element is oxygen.

16. The preparation method according to claim 11, characterized in that, The silicon source precursor includes trichlorosilane, and the fusion layer and the trap-rich layer are polycrystalline silicon. The grain size of polysilicon in the fusion layer is smaller than that of polysilicon in the trap-rich layer.

17. The preparation method according to claim 10, characterized in that, Providing the second donor as a device layer, and forming the buried oxide layer on the surface of the second donor, including: The buried oxygen layer is formed on the surface of the second donor by a wet oxygen or dry oxygen process.

18. The preparation method according to claim 10, characterized in that, Combining the trap-rich layer with the buried oxide layer to obtain the semiconductor-on-insulator comprises: The trap-rich layer is bonded to the buried oxide layer to obtain the semiconductor-on-insulator; or An oxide layer is formed on the surface of the trap-rich layer, and the oxide layer is bonded to the buried oxide layer to obtain the semiconductor-on-insulator.

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