Back contact solar cell preparation method, back contact solar cell and photovoltaic module

Abstract

The application provides a back contact solar cell preparation method, a back contact solar cell and a photovoltaic module. The preparation method comprises the following steps: preparing an initial structure of the back contact solar cell, forming a front passivation layer on a front surface texture structure, simultaneously forming a passivation protection sacrificial layer on an N-type doped polysilicon layer and a back surface texture structure, and forming an anti-reflection layer on the front passivation layer by using a high-temperature process; removing the passivation protection sacrificial layer, depositing and forming a second interface passivation layer and a P-type doped amorphous silicon layer on the N-type doped polysilicon layer and the back surface texture structure, removing part of the second interface passivation layer and the P-type doped amorphous silicon layer located in a first region, depositing a transparent conductive oxide layer, performing isolation groove processing, and performing metallization processing on the back surface of the back contact solar cell. The passivation performance of the N-type doped polysilicon layer is improved, and thus the performance of the HTBC solar cell is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of solar cells, in particular to a preparation method of a back contact solar cell, a back contact solar cell and a photovoltaic module. BACKGROUND

[0002] HTBC (Heterojunction Tunnel Oxide Back Contact) cell technology is a kind of high-efficiency crystalline silicon solar cell technology, which combines the technical features of TBC (Tunnel Oxide Back Contact) cell and heterojunction cell, and is a kind of high-performance crystalline silicon solar cell with great potential.

[0003] As a high-efficiency crystalline silicon-based single-junction solar cell, the HTBC cell has a broad market application prospect, but its industrialization process needs to be continuously improved and the photoelectric conversion efficiency needs to be improved to meet the market demand for high-efficiency and low-cost solar cells. SUMMARY

[0004] To solve the above technical problems, the present application discloses a preparation method of a back contact solar cell, a back contact solar cell and a photovoltaic module, so as to avoid the performance degradation of the polycrystalline silicon in the passivation contact structure of the first interface passivation layer due to the high-temperature preparation process, and improve the performance of the HTBC cell.

[0005] In a first aspect, the present application provides a preparation method of a back contact solar cell, comprising the following steps:

[0006] preparing a back contact solar cell initial structure;

[0007] The back contact solar cell initial structure comprises a silicon substrate, the front surface of the silicon substrate has a front surface textured structure, and the back surface of the silicon substrate is alternately provided with a first region and a second region. In the first region, the back surface of the silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer and an N-type doped polycrystalline silicon layer in the direction away from the silicon substrate. In the second region, the back surface of the silicon substrate has a back surface textured structure, and the N-type doped polycrystalline silicon layer is formed based on a high-temperature process;

[0008] forming a front surface passivation layer on the front surface textured structure, and simultaneously forming a passivation protection sacrificial layer on the N-type doped polycrystalline silicon layer and the back surface textured structure;

[0009] forming an anti-reflection layer on the front surface passivation layer by using a high-temperature process, wherein the high-temperature process simultaneously acts on the front surface passivation layer and the passivation protection sacrificial layer;

[0010] The high-temperature process has a temperature range of 400-1000℃;

[0011] The back contact solar cell is prepared by a low-temperature process;

[0012] The low-temperature process comprises:

[0013] The passivation protection sacrificial layer on the back surface is removed;

[0014] A second interface passivation layer and a P-type doped amorphous silicon layer are deposited on the N-type doped polysilicon layer and the back surface texturing structure;

[0015] A patterning process is performed to remove part of the second interface passivation layer and the P-type doped amorphous silicon layer in the first region;

[0016] A transparent conductive oxide layer is deposited;

[0017] An isolation groove process is performed, and the processing region of the isolation groove process is located in the first region, or the processing region of the isolation groove process is located in both the first region and the second region;

[0018] A metallization process is performed on the back surface of the back contact solar cell;

[0019] The low-temperature process has a temperature range of 20-400℃.

[0020] In some embodiments of the present application, in the high-temperature process:

[0021] The N-type doped polysilicon layer is prepared by a first high-temperature process having a temperature range of 500-1000℃;

[0022] The anti-reflection layer is formed by a second high-temperature process having a temperature range of 400-600℃, and the second high-temperature process simultaneously acts on the front surface passivation layer and the passivation protection sacrificial layer.

[0023] In some embodiments of the present application, in the low-temperature process:

[0024] The passivation protection sacrificial layer is removed by a first low-temperature process having a temperature range of 20-100℃;

[0025] The second interface passivation layer and the P-type doped amorphous silicon layer are formed by a second low-temperature process having a temperature range of 160-250℃;

[0026] The patterning process is performed by a third low-temperature process having a temperature range of 20-120℃;

[0027] depositing the transparent conductive oxide layer by a fourth low-temperature process with a temperature range of 25°C-240°C;

[0028] performing the isolation groove treatment by a fifth low-temperature process with a temperature range of 20°C-100°C;

[0029] performing the metallization treatment by a sixth low-temperature process with a temperature range of 120°C-300°C.

[0030] In some embodiments of the present application, the material of the front passivation layer and / or the passivation protection sacrificial layer comprises at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, titanium dioxide, hafnium dioxide, tantalum pentoxide, gallium oxide, zinc oxide, nickel oxide, molybdenum trioxide, tungsten oxide, vanadium pentoxide, and indium oxide.

[0031] In some embodiments of the present application, the front passivation layer and the passivation protection sacrificial layer have the same material;

[0032] The thickness of the front passivation layer is 0.1 nm-500 nm;

[0033] The thickness of the passivation protection sacrificial layer is 0.1 nm-500 nm.

[0034] In a second aspect, the present application provides a back contact solar cell prepared by the preparation method of the back contact solar cell according to the first aspect.

[0035] In some embodiments of the present application, the back contact solar cell comprises a silicon substrate, and the back surface of the silicon substrate is alternately provided with a first region and a second region;

[0036] In the first region, the back surface of the silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer, an N-type doped polysilicon layer, a second interface passivation layer, a P-type doped amorphous silicon layer, and a transparent conductive oxide layer;

[0037] In the second region, the back surface of the silicon substrate is sequentially provided with a second interface passivation layer and a P-type doped amorphous silicon layer, and the back surface of the silicon substrate has a back surface textured structure;

[0038] The front surface of the silicon substrate is sequentially provided with a front passivation layer and an anti-reflection layer, and the front surface of the silicon substrate has a front surface textured structure.

[0039] In some embodiments of the present application, the concentration of hydrogen atoms in the N-type doped polysilicon layer is 1×10 17 atoms / cm 3 ~1×10 19 atoms / cm 3 .

[0040] In some embodiments of the present application, the first region has at least one isolation groove.

[0041] In a third aspect, the present application provides a photovoltaic module, which comprises the solar cell according to the first aspect, or which comprises the solar cell prepared by the preparation method according to the second aspect.

[0042] Compared with the prior art, the present application has at least the following beneficial effects:

[0043] The preparation method of the back contact solar cell, the back contact solar cell and the photovoltaic module provided by the present application can form the front passivation layer and the passivation protection sacrificial layer on the front surface at the same time, so that the passivation protection sacrificial layer becomes denser after being subjected to high temperature in the subsequent process of forming the anti-reflection layer based on high temperature process, thereby blocking the overflow of hydrogen in the N-type doped polysilicon layer under high temperature conditions, and the hydrogen content in the N-type doped polysilicon layer can be retained to the greatest extent, so as to enhance the passivation effect of the N-type doped polysilicon layer, avoid the sharp decline of the passivation performance of the N-type doped polysilicon in the high temperature process, and maintain the passivation performance of the N-type doped polysilicon layer, thereby facilitating the acquisition of the HTBC solar cell with high performance; and the low-temperature process with a temperature range of 20-400℃ is used in the subsequent preparation of the second interface passivation layer and the P-type doped amorphous silicon layer, which can greatly reduce the diffusion and overflow of hydrogen in the N-type doped polysilicon layer, thereby retaining the hydrogen concentration in the N-type doped polysilicon layer to the greatest extent, so that the passivation performance of the formed N-type doped polysilicon layer will not be lost; and the front passivation layer and the passivation protection sacrificial layer are formed at the same time in one process, which reduces the process flow and improves the production efficiency of the HTBC solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] Figure 1 The structure diagram of the initial structure of the back contact solar cell in an embodiment of the present application;

[0046] Figure 2 The schematic diagram of forming the front passivation layer and the passivation protection sacrificial layer in an embodiment of the present application;

[0047] Figure 3 A schematic diagram for forming a passivation layer in an embodiment of the present application;

[0048] Figure 4 A schematic diagram for removing a passivation protection sacrificial layer in an embodiment of the present application;

[0049] Figure 5 A schematic diagram for forming a second interface passivation layer and a P-type doped amorphous silicon layer in an embodiment of the present application;

[0050] Figure 6 A schematic diagram for performing a patterning process in an embodiment of the present application;

[0051] Figure 7 A schematic diagram for forming a transparent conductive oxide layer in an embodiment of the present application;

[0052] Figure 8 A schematic diagram for performing an isolation groove process in an embodiment of the present application;

[0053] Figure 9 A schematic diagram for a structure of a back contact solar cell in an embodiment of the present application;

[0054] Figure 10 A schematic diagram for a silicon substrate in an embodiment of the present application;

[0055] Figure 11 A schematic diagram for forming a first interface passivation layer and an intrinsic amorphous silicon layer in an embodiment of the present application;

[0056] Figure 12 A schematic diagram for forming a doped inner extension layer and a PSG layer in an embodiment of the present application;

[0057] Figure 13 A schematic diagram for forming a texturing mask layer in an embodiment of the present application.

[0058] BRIEF DESCRIPTION OF DRAWINGS: silicon substrate - 1, intrinsic amorphous silicon layer - 2, front side texturing structure - 10, front side passivation layer - 11, anti-reflective layer - 12, back side texturing structure - 20, first region - 21, second region - 22, doped inner extension layer - 23, first interface passivation layer - 24, N-type doped polysilicon layer - 25, passivation protection sacrificial layer - 26, second interface passivation layer - 27, P-type doped amorphous silicon layer - 28, transparent conductive oxide layer - 29, back side electrode - 30, PSG layer - 31, texturing mask layer - 32, isolation groove - 291. DETAILED DESCRIPTION

[0059] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0060] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "vertical", "horizontal", "lateral", "longitudinal", and the like indicate the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not intended to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

[0061] In addition, in addition to indicating the orientation or positional relationship, the above-mentioned part of the terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain dependent relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the present application can be understood according to the specific situation.

[0062] In addition, the terms "mount", "set", "provided with", "connect", "connect" should be broadly understood. For example, it can be fixedly connected, detachably connected, or integrally constructed; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those skilled in the art, the specific meaning of the above-mentioned terms in the present application can be understood according to the specific situation.

[0063] In addition, the terms "first", "second", and the like are mainly used to distinguish different devices, elements or components (the specific type and structure may be the same or different), and are not intended to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise stated, the meaning of "multiple" is two or more.

[0064] The technical solutions of the present application will be further described below in combination with the embodiments and drawings.

[0065] In a first aspect, the present application provides a method for preparing a back contact solar cell, comprising the following steps:

[0066] Step A, preparing an initial structure of a back contact solar cell. Referring to Figure 1, the back contact solar cell initial structure comprises a silicon substrate 1, the front surface of the silicon substrate 1 has a front surface texturing structure 10, and the back surface of the silicon substrate 1 is provided with first regions 21 and second regions 22 alternately; in the first regions 21, the back surface of the silicon substrate 1 is sequentially provided with a doped inner expansion layer 23, a first interface passivation layer 24 and an N-type doped polysilicon layer 25 in a direction away from the silicon substrate 1, wherein the N-type doped polysilicon layer is formed based on a high-temperature process; and in the second regions 22, the back surface of the silicon substrate 1 has a back surface texturing structure 20;

[0067] Step B, referring to Figure 2 a front surface passivation layer 11 is formed on the front surface texturing structure 10, and a passivation protection sacrificial layer 26 is formed on the N-type doped polysilicon layer 25 and the back surface texturing structure 20 at the same time;

[0068] Step C, referring to Figure 3 a high-temperature process is used to form an anti-reflection layer 12 on the front surface passivation layer 11, wherein the high-temperature process acts on the front surface passivation layer 11 and the passivation protection sacrificial layer 26 at the same time;

[0069] In steps A and C, the temperature range of the high-temperature process is 400℃-1000℃.

[0070] In step A, the silicon substrate can be an N-type silicon substrate, and the thickness of the silicon substrate is 100μm-220μm.

[0071] In step B, an atomic layer deposition (ALD) device, a plasma enhanced atomic layer deposition (PE-ALD) device or a magnetron sputtering device can be used to deposit the front surface passivation layer 11 and the passivation protection sacrificial layer 26 at the same time, specifically, the front surface passivation layer 11 is deposited on the front surface of the silicon substrate 1, and the passivation protection sacrificial layer 26 is deposited on the back surface of the silicon substrate 1 at the same time, and the deposition temperature is 210℃-290℃. Of course, other deposition processes can also be used to form the above-mentioned front surface passivation layer 11 and passivation protection sacrificial layer 26. When the materials of the front surface passivation layer 11 and the passivation protection sacrificial layer 26 are aluminum oxide, trimethylaluminum (TMA), H2O, ozone (O3), dimethylaluminum amine (DMAA) or aluminum oxide (AlO x ) and the like can be used as raw materials for preparation; the flow rate range of TMA and H2O is 1%-50% of the maximum flow rate of the respective gas flow meters of the ALD device, and the deposition cycle number is 1-4200, which is not particularly limited in the present application.

[0072] In step C, the anti-reflection layer 12 can be formed based on a tubular plasma enhanced chemical vapor deposition (PECVD) device, and the thickness of the anti-reflection layer 12 is 40nm-120nm. It can be understood that the high temperature generated in the deposition process also acts on the front surface passivation layer 11 and the passivation protection sacrificial layer 26 at the same time.

[0073] Step D, a low-temperature process with a temperature range of 20°C to 400°C, the low-temperature process comprising the following sub-steps:

[0074] Step i: referring to Figure 4 , removing the passivation protection sacrificial layer 26 on the back surface;

[0075] Step ii: referring to Figure 5 , depositing and forming a second interface passivation layer 27 and a P-type doped amorphous silicon layer 28 on the N-type doped polysilicon layer 25 and the back surface texturing structure 20;

[0076] Step iii: referring to Figure 6 , performing a patterning process to remove part of the P-type doped amorphous silicon layer 28 and the second interface passivation layer 27 located in the first region 21;

[0077] Step iv: referring to Figure 7 , depositing a transparent conductive oxide layer 29;

[0078] Step v: referring to Figure 8 , performing an isolation groove process, the processing area of the isolation groove process being located in the first region 21, so as to form at least one isolation groove 291 in the first region 21; or, the processing area of the isolation groove process being located in both the first region 21 and the second region 22, so as to form at least one isolation groove 291 in the first region 21, and part of the isolation groove 291 extending to the second region.

[0079] Step vi: referring to Figure 9 , performing a metallization process on the back surface of the back contact solar cell, so as to form a back electrode 30.

[0080] In step i, the passivation protection sacrificial layer 26 in the first region 21 and the second region 22 can be removed by using a chain wet cleaning device, and the cleaning solution used can be a mixed solution of hydrochloric acid and hydrofluoric acid, the concentration of the mixed solution being 0.01 vol% to 50 vol%, the cleaning temperature being 5°C to 50°C, and the cleaning time being 10s to 1200s.

[0081] In step ii, the second interface passivation layer 27 and the P-type doped amorphous silicon layer 28 can be formed based on a plate PECVD device, wherein the thickness of the second interface passivation layer 27 is 0.1nm to 20nm, and the microstructure factor R is 0.01 to 0.99; the thickness of the P-type doped amorphous silicon layer 28 is 5nm to 100nm, and the effective doping concentration of boron element is 1×10 19 atoms / cm 3 ~9.9×10 20 atoms / cm 3 .

[0082] In step ii, the second interface passivation layer 27 and the P-type doped amorphous silicon layer 28 in the first region 21 can be subjected to a patterning process, so as to etch away part of the second interface passivation layer 27 and the P-type doped amorphous silicon layer 28, to expose the N-type doped polysilicon layer 25 under the second interface passivation layer 27. The patterning process can be performed by laser, and a green light picosecond laser with a wavelength of 532 nm and an energy density of 10 mJ / cm 2 1000 mJ / cm 2 After the patterning process, the solar cell semi-finished product can be cleaned by a chain type wet cleaning machine or a tank type wet cleaning machine.

[0083] In step iv, the transparent conductive oxide layer 29 can be formed based on a plate type physical vapor deposition (PVD) device. In an example, the transparent conductive oxide layer 29 can be an indium tin oxide film (In2O3: SnO2= 80-99: 1-20, mass ratio), with a thickness of 20 nm-150 nm, a square resistance of 10 Ω / sq-90 Ω / sq, and a carrier mobility of 10 cm² / V·s-120 cm² / V·s.

[0084] In step v, the isolation groove processing can be performed by a laser etching or a wet etching process. For example, an acid etching slurry can be used for screen printing, and then after drying and cleaning, part of the transparent conductive oxide layer 29 in the first region 21 is selectively etched to form a patterned isolation groove 291, and the width of the isolation groove 291 is 10 μm-200 μm. The acid etching slurry is not particularly limited in the present application, as long as it can etch the transparent conductive oxide layer.

[0085] In step v, during the metallization process, an electrode paste can be applied to the surface of the transparent conductive oxide layer 29 in the first region 21 and the second region 22, and after solidification treatment and light injection treatment, a back electrode 30 is formed. The electrode paste can be a silver-coated copper paste (silver content of 10 wt%-90 wt%, and the balance is copper). The solidification treatment and light injection treatment device can be a chain type furnace or a cassette type furnace.

[0086] The solar cell preparation method provided by the application forms a front passivation layer on the front surface and forms a passivation protection sacrificial layer on the N-type doped polysilicon layer and the back surface at the same time, so that in the subsequent process of forming the antireflection layer based on the high-temperature process, the high-temperature process acts on the front passivation layer and the passivation protection sacrificial layer at the same time, the high-temperature process accelerates the breaking of the chemical bond combined with hydrogen atoms and the diffusion of hydrogen, and the passivation protection sacrificial layer becomes more dense after high-temperature crystallization, thereby blocking the overflow of hydrogen in the N-type doped polysilicon layer, protecting the hydrogen in the N-type doped polysilicon layer, improving the passivation performance of the N-type doped polysilicon layer, and improving the electrical performance of the HTBC solar cell; and the low-temperature process with a temperature range of 20-400℃ is used in the subsequent preparation of the second interface passivation layer and the P-type doped amorphous silicon layer, so that the passivation performance of the N-type doped polysilicon layer is not adversely affected, thereby improving the passivation effect and electrical performance of the HTBC solar cell; and the front passivation layer and the passivation protection sacrificial layer are formed at the same time in one process, thereby reducing the process flow, improving the production efficiency and yield of the HTBC solar cell.

[0087] In some embodiments of the application, in the high-temperature process:

[0088] The first high-temperature process with a temperature range of 500-1000℃ is used to prepare the N-type doped polysilicon layer, wherein the raw materials used in the preparation of the N-type doped polysilicon layer 25 include SiH4, which can improve the hydrogen atom concentration, and the hydrogen atoms can migrate to the surface and inside of the crystalline silicon substrate 1 to passivate the dangling bonds on the back surface of the crystalline silicon substrate 1 during high-temperature diffusion, thereby improving the minority carrier lifetime of the silicon substrate in the first region and improving the electrical performance of the HTBC solar cell.

[0089] The second high-temperature process with a temperature range of 400-600℃ is used to form the antireflection layer, wherein the second high-temperature process acts on the front passivation layer and the passivation protection sacrificial layer at the same time, the passivation protection sacrificial layer becomes more dense after high-temperature crystallization, thereby blocking the diffusion and overflow of hydrogen in the N-type doped polysilicon layer, improving the passivation performance of the N-type doped polysilicon, and improving the electrical performance of the HTBC solar cell.

[0090] In some embodiments of the application, in the low-temperature process:

[0091] The first low-temperature process with a temperature range of 20-100℃ is used to remove the passivation protection sacrificial layer 26;

[0092] The second interface passivation layer 27 and the P-type doped amorphous silicon layer 28 are formed by a second low-temperature process with a temperature range of 160°C-250°C;

[0093] The patterning treatment is performed by a third low-temperature process with a temperature range of 20°C-120°C;

[0094] The transparent conductive oxide layer 29 is deposited by a fourth low-temperature process with a temperature range of 25°C-240°C;

[0095] The isolation groove treatment is performed by a fifth low-temperature process with a temperature range of 20°C-100°C;

[0096] The metallization treatment is performed by a sixth low-temperature process with a temperature range of 120°C-300°C, which includes a solidification treatment and a light injection treatment. The temperature of the solidification treatment is 120°C-300°C, and the time is 10 min-100 min. The temperature of the light injection treatment is 120°C-300°C, the light injection time is 100 s-200 s, and the light intensity is 10 KW / m 2 ~99 KW / m 2 .

[0097] The first low-temperature process to the sixth low-temperature process described above do not provide the hydrogen atoms in the N-type doped polysilicon layer 25 with the energy to break the bond because of the low process temperature, so the hydrogen passivation effect can be maintained to the greatest extent, thereby improving the passivation effect of the N-type doped polysilicon layer 25 on the silicon dangling bonds on the back surface of the silicon substrate, which is conducive to improving the electrical performance of the HTBC solar cell.

[0098] In some embodiments of the present application, the material of the front passivation layer and / or the passivation protection sacrificial layer includes at least one of aluminum oxide (AlO x ), silicon nitride (SiN X ), silicon oxynitride (SiNO X ), silicon oxide (SiO X ), titanium dioxide (TiO2), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), gallium oxide (Ga2O3), zinc oxide (ZnO), nickel oxide (NiO), molybdenum trioxide (MoO3), tungsten oxide (WO3), vanadium pentoxide (V2O5), and indium oxide (In2O3). The passivation protection sacrificial layer prepared based on the above-mentioned materials will form a more dense film layer structure after being subjected to high temperature in a high-temperature process, thereby blocking the overflow of hydrogen in the N-type doped polysilicon layer, so that the hydrogen concentration in the N-type doped polysilicon layer can be maintained to the greatest extent, the hydrogen passivation effect can be maintained, and the passivation effect of the N-type doped polysilicon layer 25 on the silicon dangling bonds on the back surface of the silicon substrate can be improved, which is conducive to improving the electrical performance of the HTBC solar cell.

[0099] In some embodiments of the present application, the material of the passivation protection sacrificial layer includes at least one of aluminum oxide, silicon nitride and silicon oxynitride. After the passivation protection sacrificial layer based on the above-mentioned material is subjected to high temperature in a high-temperature process, it not only becomes more dense, but also provides a hydrogen source for diffusion of a part of hydrogen atoms in the N-type doped polysilicon layer 25, thereby not only blocking the overflow of hydrogen in the N-type doped polysilicon layer, but also increasing the concentration of hydrogen atoms in the N-type doped polysilicon layer 25, thereby improving the passivation effect of the N-type doped polysilicon layer 25 on the silicon dangling bonds on the back surface of the silicon substrate, and being conducive to improving the electrical performance of the HTBC solar cell.

[0100] In some embodiments of the present application, the thickness of the front passivation layer is 2 nm to 20 nm, and the front passivation layer can be a single-layer structure, a stacked structure formed by the same material, or a stacked structure formed by different materials; and / or, the thickness of the passivation protection sacrificial layer is 0.1 nm to 500 nm, and the passivation protection sacrificial layer can be a single-layer structure, a stacked structure formed by the same material, or a stacked structure formed by different materials. For example, the thickness of the front passivation layer is 0.1 nm, 1 nm, 5 nm, 10 nm, 20 nm, 50 nm, 100 nm or 500 nm; and the thickness of the passivation protection sacrificial layer is 0.1 nm, 1 nm, 5 nm, 10 nm, 20 nm, 50 nm, 100 nm or 500 nm. The front passivation layer with the above-mentioned thickness range has good interface passivation performance; the passivation protection sacrificial layer has a dense film structure, and the passivation protection sacrificial layer with the above-mentioned thickness range can effectively block the overflow of hydrogen in the N-type doped polysilicon layer, and will not cause the blocking ability of hydrogen overflow to decrease due to being too thin, nor will it cause the production efficiency to be affected and the raw material cost to increase due to being too thick.

[0101] In some embodiments of the present application, the process of preparing the initial structure of the back contact solar cell by using a high-temperature process includes:

[0102] Step 1) referring to Figure 10 providing a silicon substrate 1;

[0103] Step 2) referring to Figure 11 depositing a first interface passivation layer 24 and an intrinsic amorphous silicon layer 2 on the back surface of the silicon substrate 1;

[0104] Step 3) referring to Figure 12 performing phosphorus doping and high-temperature annealing and crystallization treatment on the intrinsic amorphous silicon layer 2 to form an N-type doped polysilicon layer 25, and phosphorus atoms diffuse in the direction of the silicon substrate 1 in the high-temperature annealing process to form a doped inner diffusion layer 23 between the silicon substrate 1 and the first interface passivation layer 24, and a phosphosilicate glass (PSG) layer 31 is formed on the back surface of the N-type doped polysilicon layer 25;

[0105] Step 4) referring to Figure 13 , removing the PSG layer 31, and depositing a silicon nitride layer as a texturing mask layer 32 on the back surface of the N-type doped polysilicon layer 25;

[0106] Step 5) through laser etching and wet texturing, referring to Figure 1 , forming the first region 21 and the second region 22 on the back surface of the silicon substrate 1, and forming a front surface texturing structure on the front surface of the silicon substrate 1, and forming a back surface texturing structure on the back surface of the silicon substrate 1 in the second region 22.

[0107] In step 2), the first interface passivation layer can be prepared based on a high-temperature tube low-pressure chemical vapor deposition (LPCVD) device.

[0108] In step 3), the effective doping concentration of phosphorus atoms in the N-type doped polysilicon layer is 1×10 19 atoms / cm 3 ~9.9×10 20 atoms / cm 3 , and the thickness of the N-type doped polysilicon layer is 30 nm~500 nm.

[0109] In step 4), the texturing mask layer can be prepared based on a tube PECVD device, and the thickness of the texturing mask layer is 5 nm~200 nm, and the refractive index is 1.8~2.5.

[0110] In step 5), the silicon nitride of the texturing mask layer will undergo a wet texturing process, and after being treated by an alkali solution and a hydrofluoric acid solution, the mask layer is finally removed. As an optional patterning implementation, the laser uses a green light picosecond laser with a wavelength of 532 nanometers, and the energy density is 150 mJ / cm 2 ~1000 mJ / cm 2 ; the texturing process can use a conventional crystalline silicon solar cell wet texturing process, while matching appropriate texturing additives, which are not particularly limited in the present application; when removing the texturing mask layer, the concentration of the hydrofluoric acid solution is 1 vol%~50 vol%.

[0111] The material of the first interface passivation layer can include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the first interface passivation layer can be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent interface passivation performance, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a thin film with excellent reliability and durability to subsequent high-temperature processes. In order to better provide interface passivation for the substrate, the thickness of the first interface passivation layer can be 0.8 nm to 5 nm. For example, the thickness of the first interface passivation layer can be 0.8 nm, 1.0 nm, 1.2 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc., however, the present application is not limited thereto, and the thickness of the first interface passivation layer can have various values. The first interface passivation layer can also have a pinhole channel effect, allowing the free movement of carriers within the crystalline silicon solar cell, and selective passage of majority carriers through the heavily doped polysilicon, which is beneficial to reducing the recombination loss of minority carriers. In addition, the first interface passivation layer can act as a diffusion barrier layer to prevent the diffusion of dopants from the doped polysilicon layer into the semiconductor substrate.

[0112] In a second aspect, the present application provides a solar cell prepared by the solar cell preparation method of the first aspect.

[0113] In some embodiments of the present application, with reference to Figure 9 , the solar cell includes a silicon substrate 1, and a back surface of the silicon substrate 1 is alternately provided with a first region 21 and a second region 22; in the first region 21, the back surface of the silicon substrate 1 is sequentially provided with a doped inner expansion layer 23, a first interface passivation layer 24, an N-type doped polysilicon layer 25, a second interface passivation layer 27, a P-type doped amorphous silicon layer 28, and a transparent conductive oxide layer 29; in the second region 22, the back surface of the silicon substrate 1 is sequentially provided with the second interface passivation layer 27 and the P-type doped amorphous silicon layer 28, and the back surface of the silicon substrate 1 has a back surface texturing structure 20; and a front surface of the silicon substrate 1 is sequentially provided with a front surface passivation layer 11 and an anti-reflection layer 12, and the front surface of the silicon substrate 1 has a front surface texturing structure 10.

[0114] In some embodiments of the present application, the concentration of hydrogen atoms in the N-type doped polysilicon layer is 1 x 1019 atoms / cm3. 17 atoms / cm 3 ~1 x 1019 atoms / cm3. 19 atoms / cm 3 , indicating that the passivation protection sacrificial layer effectively inhibits the overflow of hydrogen in the N-type doped polysilicon layer.

[0115] In some embodiments of the present application, with reference to Figure 9In the first region 21, at least one isolation groove 291 is formed so as to electrically insulate the transparent conductive oxide layer 29 on both sides of the isolation groove 291. The number of the isolation grooves in the present application can be flexibly set according to the design requirements of the structure of the HTBC solar cell. For example, one corresponding isolation groove 291 can be provided between the first region 21 and the second region 22.

[0116] It should be noted that, in the preparation of the second interface passivation layer corresponding to the second region, since the intrinsic amorphous silicon film is usually used as the second interface passivation layer, it cannot withstand high-temperature processes above 400°C. Because the high-temperature environment provides crystallization energy for the amorphous material, causing the second interface passivation layer to be converted to a crystalline state, and even causing epitaxial growth of the intrinsic amorphous silicon film layer and weakening the interface passivation effect of the second interface passivation layer. Therefore, in order to more clearly illustrate the inventive concept of the present application, the process of preparing the second interface passivation layer is taken as a process node, and the process before preparing the second interface passivation layer is defined as a high-temperature process, mainly based on the fact that only the film layer structure corresponding to the first region can withstand a high-temperature environment without adversely affecting the conversion efficiency of the battery. The process after the second interface passivation layer is defined as a low-temperature process, because the second interface passivation layer can only withstand a low-temperature process environment less than 400°C.

[0117] In a third aspect, the present application provides a photovoltaic module, which comprises the solar cell prepared by the preparation method of the first aspect, or the photovoltaic module comprises the solar cell of the second aspect.

[0118] The present application also provides a photovoltaic module for converting received light energy into electrical energy and transmitting to an external load. The photovoltaic module comprises: at least one cell string connected by a plurality of solar cells described above; an encapsulating adhesive film for covering the surface of the cell string; and a cover plate for covering the surface of the encapsulating adhesive film away from the cell string.

[0119] Some experimental data of double-sided N-type doped polysilicon monitoring pieces when undergoing high-temperature processes. The experimental group is the N-type doped polysilicon monitoring piece with a passivation protection sacrificial layer (aluminum oxide), and the control group is the N-type doped polysilicon monitoring piece without a passivation protection layer. The experimental data is shown in Table 1:

[0120] Table 1: Performance data of the experimental group and the control group

[0121]

[0122] Note: In Table 1, the processing time at 530°C is 30 min.

[0123] From the data in Table 1, it can be found that the attenuation of iVoc and iFF of the N-type doped polysilicon monitoring piece with the passivation protection sacrificial layer after high temperature treatment is far less than that of the N-type doped polysilicon monitoring piece without the passivation protection sacrificial layer. It is confirmed that the preparation method of the back contact solar cell of the present application can effectively avoid the passivation performance degradation of the N-type doped polysilicon in the high temperature process.

[0124] The above has introduced in detail a preparation method of a back contact solar cell, a back contact solar cell and a photovoltaic module disclosed by the present application, specific examples have been applied in this paper to explain the principles and implementation manners of the present application, and the above example is only used to help understand the technical solutions and core invention points of the embodiments of the present application; at the same time, for the general technical personnel in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed, and on the basis of the above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: Preparing the initial structure of a back-contact solar cell; The initial structure of the back contact solar cell includes a silicon substrate. The front side of the silicon substrate has a textured surface structure, and the back side of the silicon substrate is alternately provided with a first region and a second region. In the first region, the back side of the silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer and an N-type doped polycrystalline silicon layer along the direction away from the silicon substrate. In the second region, the back side of the silicon substrate has a textured surface structure. The N-type doped polycrystalline silicon layer is formed based on a high-temperature process. A front passivation layer is formed on the front textured structure, and a passivation protection sacrificial layer is formed on the N-type doped polysilicon layer and the back textured structure. An antireflection layer is formed on the front passivation layer using a high-temperature process, wherein the high-temperature process acts on both the front passivation layer and the passivation protection sacrificial layer. The temperature range of the high-temperature process is 400℃~1000℃; Back-contact solar cells are fabricated using a low-temperature process; The low-temperature process includes: Remove the passivation protective sacrificial layer on the back side; A second interface passivation layer and a P-type doped amorphous silicon layer are deposited on the N-type doped polycrystalline silicon layer and the back textured structure. Perform graphical processing to remove a portion of the second interface passivation layer and P-type doped amorphous silicon layer located in the first region; Deposit a transparent conductive oxide layer; The isolation grooving process is performed, wherein the processing area of ​​the isolation grooving process is located in the first region, or the processing area of ​​the isolation grooving process is located in both the first region and the second region. Metallization is performed on the back side of the back contact solar cell; The temperature range of the low-temperature process is 20℃~400℃.

2. The preparation method according to claim 1, characterized in that, In the high-temperature process: The N-type doped polycrystalline silicon layer was prepared using a first high-temperature process with a temperature range of 500℃~1000℃. The antireflection layer is formed using a second high-temperature process with a temperature range of 400℃ to 600℃, wherein the second high-temperature process simultaneously acts on the front passivation layer and the passivation protection sacrificial layer.

3. The preparation method according to claim 1, characterized in that, In the aforementioned low-temperature process: The passivation protective sacrificial layer is removed using a first low-temperature process with a temperature range of 20℃ to 100℃. The second interface passivation layer and the P-type doped amorphous silicon layer are formed using a second low-temperature process with a temperature range of 160℃~250℃. The patterning process is performed using a third low-temperature process with a temperature range of 20℃ to 120℃. The transparent conductive oxide layer is deposited using a fourth low-temperature process with a temperature range of 25℃ to 240℃. The isolation grooving process is carried out using a fifth low-temperature process with a temperature range of 20℃ to 100℃. The metallization process is carried out using a sixth low-temperature process with a temperature range of 120℃ to 300℃.

4. The preparation method according to claim 1, characterized in that, The materials of the front passivation layer and / or the passivation protection sacrificial layer include at least one of aluminum oxide, silicon nitride, silicon oxynitride, silicon oxide, titanium dioxide, hafnium dioxide, tantalum pentoxide, gallium oxide, zinc oxide, nickel oxide, molybdenum trioxide, tungsten oxide, vanadium pentoxide, and indium oxide.

5. The preparation method according to claim 1, characterized in that, The front passivation layer and the passivation protection sacrificial layer have the same material; The thickness of the front passivation layer is 0.1 nm to 500 nm; The thickness of the passivation protective sacrificial layer is 0.1 nm to 500 nm.

6. A back-contact solar cell, characterized in that, The back-contact solar cell is prepared by the method described in any one of claims 1 to 5.

7. The back-contact solar cell according to claim 6, characterized in that, The back-contact solar cell includes a silicon substrate, and a first region and a second region are alternately disposed on the back side of the silicon substrate; In the first region, the back side of the silicon substrate is sequentially provided with a doped inner expansion layer, a first interface passivation layer, an N-type doped polycrystalline silicon layer, a second interface passivation layer, a P-type doped amorphous silicon layer, and a transparent conductive oxide layer. In the second region, a second interface passivation layer and a P-type doped amorphous silicon layer are sequentially disposed on the back side of the silicon substrate, and the back side of the silicon substrate has a back textured structure. The front side of the silicon substrate is provided with a front passivation layer and an anti-reflection layer in sequence, and the front side of the silicon substrate has a front textured structure.

8. The back-contact solar cell according to claim 6, characterized in that, The hydrogen atom concentration in the N-type doped polycrystalline silicon layer is 1×10⁻⁶. 17 atoms / cm 3 ~1×10 19 atoms / cm 3 .

9. The back-contact solar cell according to claim 6, characterized in that, The first region has at least one isolation groove.

10. A photovoltaic module, characterized in that, The photovoltaic module comprises a back-contact solar cell prepared by the preparation method according to any one of claims 1 to 5, or the photovoltaic module comprises a back-contact solar cell according to any one of claims 6 to 9.

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