Backside illumination image sensor fabrication method and backside illumination image sensor

Abstract

This disclosure relates to a method for fabricating a back-illuminated image sensor and the back-illuminated image sensor itself, relating to the field of integrated circuit technology. The method includes: providing a substrate including a first top surface; forming a first semiconductor layer on the first top surface of the substrate, the first semiconductor layer including a plurality of first photosensitive portions spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer; forming a second semiconductor layer covering the first semiconductor layer, the second semiconductor layer including a plurality of second photosensitive portions spaced apart along the first direction and extending through the second semiconductor layer along a second direction close to the substrate to the top surface of the plurality of first photosensitive portions; forming a third semiconductor layer covering the second semiconductor layer, the third semiconductor layer including a plurality of third photosensitive portions spaced apart along the first direction and extending through the second semiconductor layer along a second direction to the interior of the plurality of second photosensitive portions. This method can at least increase the electron concentration in the photosensitive area, improving the photosensitivity of the BSI image sensor.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a method for fabricating a back-illuminated image sensor and the back-illuminated image sensor itself. Background Technology

[0002] Back-side illumination (BSI) image sensors are a type of image sensor that offers better performance than front-side illumination image sensors in low-light conditions.

[0003] However, the photosensitivity of BSI image sensors manufactured using existing BSI image sensor fabrication methods cannot meet practical needs. Therefore, improving the photosensitivity of BSI image sensors has become one of the urgent technical problems to be solved. Summary of the Invention

[0004] Therefore, it is necessary to address the technical problem of insufficient light sensitivity of existing BSI image sensors by providing a back-illuminated image sensor fabrication method and a back-illuminated image sensor.

[0005] In a first aspect, this disclosure provides a method for fabricating a back-illuminated image sensor, comprising:

[0006] A substrate including a first top surface is provided; a first semiconductor layer is formed on the first top surface of the substrate, the first semiconductor layer including a plurality of first photosensitive portions spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer;

[0007] A second semiconductor layer is formed covering the first semiconductor layer. The second semiconductor layer includes a plurality of second photosensitive portions that are spaced apart along a first direction and extend through the second semiconductor layer along a second direction close to the substrate to the top surface of a plurality of first photosensitive portions.

[0008] A third semiconductor layer is formed to cover the second semiconductor layer. The third semiconductor layer includes a plurality of third photosensitive portions that are spaced apart along a first direction and penetrate the second semiconductor layer along a second direction and extend into the interior of a plurality of second photosensitive portions. The first photosensitive portions, the second photosensitive portions and the third photosensitive portions that are sequentially distributed along the second direction are used to form a photosensitive stack. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are used to form a PN junction with the photosensitive stack.

[0009] In the back-illuminated image sensor fabrication method described above, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are sequentially formed on the first top surface of a substrate. The first semiconductor layer includes a plurality of first photosensitive portions spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer. The second semiconductor layer includes a plurality of second photosensitive portions spaced apart along the first direction and extending through the second semiconductor layer and to the top surface of the plurality of first photosensitive portions along a second direction close to the substrate. The third semiconductor layer includes a plurality of third photosensitive portions spaced apart along the first direction and extending through the second semiconductor layer and into the interior of the plurality of second photosensitive portions along a second direction. The first, second, and third photosensitive portions spaced apart along the second direction are used to form a photosensitive stack. The first, second, and third semiconductor layers are used to form a PN junction with the photosensitive stack. The PN junction is used to achieve photoelectric isolation between the photosensitive stack and the first, second, or third semiconductor layers adjacent along the first direction, which can effectively avoid signal crosstalk between photosensitive stacks adjacent along the first direction. Photosensitive stacks can each comprise different Group 5 elements. When photosensitive stacks doped with different pentavalent elements are photoexcited, a concentration gradient is generated within them. This difference optimizes the transport path of photogenerated carriers, reducing the recombination rate during diffusion. Through the combined effect of these two factors, the quantum efficiency of photosensitive stacks based on this structure is effectively improved. Furthermore, since pentavalent elements have higher atomic masses than silicon, their mobility during epitaxial growth is lower, leading to uneven doping concentrations in a single doped layer. Growing different pentavalent elements in multiple stages can improve the uniformity of doping concentration in the pixel region.

[0010] In some embodiments, forming the first semiconductor layer includes: forming a first semiconductor material layer on a first top surface of a substrate, and then forming a first dielectric layer on the top surface of the first semiconductor material layer; etching the first dielectric layer and the first semiconductor material layer to form a plurality of first grooves spaced apart along a first direction in the first semiconductor material layer; forming a plurality of first photosensitive portions in the plurality of first grooves, wherein the top surface of the first photosensitive portion is higher than the top surface of the first dielectric layer; and the remaining first semiconductor material layer is used to constitute the first semiconductor layer.

[0011] In some embodiments, forming a second semiconductor layer includes: forming a second semiconductor material layer covering a plurality of first photosensitive portions and having a top surface higher than the top surface of the first photosensitive portions; forming a second dielectric layer on the top surface of the second semiconductor material layer; etching the second dielectric layer and the second semiconductor material layer to form a plurality of second grooves spaced apart along a first direction within the second semiconductor material layer; the size of the second grooves along the first direction being larger than the size of the first photosensitive portions along the first direction; forming a plurality of second photosensitive portions within the plurality of second grooves, the top surface of the second photosensitive portions being higher than the top surface of the second dielectric layer; and the remaining second semiconductor material layer is used to constitute the second semiconductor layer.

[0012] In some embodiments, forming a third semiconductor layer includes: forming a third semiconductor material layer covering a plurality of second photosensitive portions and having a top surface higher than the top surface of the second photosensitive portions; forming a third dielectric layer on the top surface of the third semiconductor material layer; etching the third dielectric layer and the third semiconductor material layer to form a plurality of third grooves spaced apart along a first direction within the third semiconductor material layer; the bottom surface of the third grooves being lower than the top surface of the second photosensitive portions; forming a plurality of third photosensitive portions within the plurality of third grooves, the top surface of the third photosensitive portions being higher than the top surface of the third dielectric layer; and the remaining third semiconductor material layer is used to constitute the third semiconductor layer.

[0013] In some embodiments, after forming a third photosensitive portion with its top surface higher than the top surface of the third dielectric layer, the method further includes: planarizing the top surface of the third photosensitive portion until the top surface of the remaining third photosensitive portion is flush with the top surface of the third dielectric layer; forming a plurality of grids spaced apart along a first direction on the top surface of the third dielectric layer, wherein the grids and photosensitive stacks are alternately arranged along the first direction.

[0014] In some embodiments, the substrate includes a plurality of trench isolation portions spaced apart along a first direction; a plurality of grids are located directly above the plurality of trench isolation portions.

[0015] In some embodiments, the first photosensitive portion and the second photosensitive portion contain different Group V elements; the second photosensitive portion and the third photosensitive portion contain different Group V elements; and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all contain Group III elements.

[0016] In some embodiments, the first photosensitive part includes a SiAs layer; the second photosensitive part includes a SiP layer; the third photosensitive part includes a SiAs layer; the SiAs layer is used to characterize As-doped silicon material; and the SiP layer is used to characterize P-doped silicon material.

[0017] Secondly, this disclosure provides a back-illuminated image sensor, fabricated using the back-illuminated image sensor fabrication method of any of the foregoing embodiments. The back-illuminated image sensor includes a substrate, a first semiconductor layer, a plurality of first photosensitive portions, a second semiconductor layer, a plurality of second photosensitive portions, a third semiconductor layer, and a plurality of third photosensitive portions. The substrate includes a first top surface. The first semiconductor layer is located on the first top surface of the substrate. The plurality of first photosensitive portions are located within the first semiconductor layer and are spaced apart along a first direction. The second semiconductor layer covers the first semiconductor layer. The plurality of second photosensitive portions are spaced apart along the first direction and penetrate the second semiconductor layer along a second direction close to the substrate, extending to the top surface of the plurality of first photosensitive portions. The third semiconductor layer covers the plurality of second photosensitive portions. The plurality of third photosensitive portions are spaced apart along the first direction and penetrate the third semiconductor layer along the second direction, extending into the interior of the plurality of second photosensitive portions. The first, second, and third photosensitive portions, sequentially distributed along the second direction, are used to form a photosensitive stack, and the first, second, and third semiconductor layers are used to form a PN junction with the photosensitive stack.

[0018] In some embodiments, the first photosensitive portion and the second photosensitive portion contain different Group V elements; the second photosensitive portion and the third photosensitive portion contain different Group V elements; and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all contain Group III elements.

[0019] The back-illuminated image sensor fabrication method and the back-illuminated image sensor disclosed in this embodiment have the following unexpected technical effects:

[0020] The first photosensitive layer and the first semiconductor layer are fabricated simultaneously in the same process steps; the second photosensitive layer and the second semiconductor layer are fabricated simultaneously in the same process steps; and the third photosensitive layer and the third semiconductor layer are fabricated simultaneously in the same process steps. The stacked first, second, and third photosensitive layers together constitute a photosensitive stack. The stacked first, second, and third semiconductor layers together constitute an isolation stack, which forms a PN junction with the photosensitive stack to achieve photoelectric isolation and avoid signal crosstalk. Because the photosensitive stack and the isolation stack are fabricated simultaneously in the same process steps, the complexity and cost of the fabrication process are effectively reduced. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1This is a schematic flowchart of a back-illuminated image sensor fabrication method provided in one embodiment;

[0023] Figure 2 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming a first dielectric layer on a substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0024] Figure 3 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first groove on the substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0025] Figure 4 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming a second dielectric layer on a substrate in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0026] Figure 5 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the second groove in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0027] Figure 6 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming the second photosensitive part in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0028] Figure 7 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the third groove in step S30 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0029] Figure 8 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming the third photosensitive part in step S30 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0030] Figure 9 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a grid in a back-illuminated image sensor fabrication method provided in one embodiment.

[0031] Figure 10 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a filter in a back-illuminated image sensor fabrication method provided in one embodiment.

[0032] Explanation of reference numerals in the attached figures:

[0033] 10. Substrate; 10a. First top surface; 101. Trench isolation portion; 102. Etch stop layer; 103. Interlayer dielectric layer; 21. First semiconductor layer; 211. First semiconductor material layer; 22. First dielectric layer; 30. First photosensitive portion; 31. First groove; 411. Second semiconductor material layer; 41. Second semiconductor layer; 42. Second dielectric layer; 50. Second photosensitive portion; 51. Second groove; 61. Third semiconductor layer; 62. Third dielectric layer; 70. Third photosensitive portion; 71. Third groove; 80. Grating; 81. First grating material layer; 82. Second grating material layer; 83. Third grating material layer; 90. Filter. Detailed Implementation

[0034] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0037] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0040] In this embodiment of the disclosure, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the direction away from the substrate surface (the thickness direction of the substrate) is, for example, a second direction. In this embodiment of the disclosure, the first direction can be the ox direction, and the second direction can be the oz direction.

[0041] Please refer to Figure 1 In some embodiments, a method for fabricating a back-illuminated image sensor is provided, comprising:

[0042] Step S10: Provide a substrate including a first top surface; form a first semiconductor layer on the first top surface of the substrate, wherein the first semiconductor layer includes a plurality of first photosensitive portions spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer;

[0043] Step S20: Form a second semiconductor layer covering the first semiconductor layer. The second semiconductor layer includes a plurality of second photosensitive portions that are spaced apart along a first direction and extend through the second semiconductor layer along a second direction close to the substrate to the top surface of a plurality of first photosensitive portions.

[0044] Step S30: Form a third semiconductor layer covering the second semiconductor layer. The third semiconductor layer includes a plurality of third photosensitive portions that are spaced apart along a first direction and penetrate the second semiconductor layer along a second direction and extend into the interior of a plurality of second photosensitive portions. The first photosensitive portions, the second photosensitive portions and the third photosensitive portions that are sequentially distributed along the second direction are used to form a photosensitive stack. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are used to form a PN junction with the photosensitive stack.

[0045] For example, please continue to refer to Figure 1 A first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are sequentially formed on the first top surface of a substrate. The first semiconductor layer includes a plurality of first photosensitive portions spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer. The second semiconductor layer includes a plurality of second photosensitive portions spaced apart along the first direction and extending through the second semiconductor layer along a second direction close to the substrate to the top surface of the plurality of first photosensitive portions. The third semiconductor layer includes a plurality of third photosensitive portions spaced apart along the first direction and extending through the second semiconductor layer along the second direction to the interior of the plurality of second photosensitive portions. The first, second, and third photosensitive portions spaced apart along the second direction are used to form a photosensitive stack. The first, second, and third semiconductor layers are used to form a PN junction with the photosensitive stack. The PN junction is used to achieve photoelectric isolation between the photosensitive stack and the first, second, or third semiconductor layers adjacent along the first direction, which can effectively avoid signal crosstalk between photosensitive stacks adjacent along the first direction. Photosensitive stacks can each comprise different Group 5 elements. When photosensitive stacks doped with different pentavalent elements are photoexcited, a concentration gradient is generated within them. This difference optimizes the transport path of photogenerated carriers, reducing the recombination rate during diffusion. Through the combined effect of these two factors, the quantum efficiency of photosensitive stacks based on this structure is effectively improved. Furthermore, since pentavalent elements have higher atomic masses than silicon, their mobility during epitaxial growth is lower, leading to uneven doping concentrations in a single doped layer. Growing different pentavalent elements in multiple stages can improve the uniformity of doping concentration in the pixel region.

[0046] Please refer to Figure 2 In some embodiments, the provided substrate 10 includes a plurality of trench isolation portions 101 spaced apart along a first direction, such as the ox direction. The material of the trench isolation portions 101 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or combinations thereof.

[0047] As an example, please continue to refer to Figure 2 The trench isolation portion 101 can be used to isolate electrons and light energy. The shape of the longitudinal section (the section parallel to the Zox plane) of the trench isolation portion 101 may include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or a combination of regular trapezoids, inverted trapezoids, rectangles, etc. This disclosure does not impose specific limitations on the shape, material, or size of the trench isolation portion 101, as long as it can isolate electrons, light energy, doped ions, etc. Furthermore, this embodiment does not impose specific limitations on the spacing between adjacent trench isolation portions 101, and it can be set according to actual needs.

[0048] As an example, please continue to refer to Figure 2 The substrate 10 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0049] As an example, please continue to refer to Figure 2 P-type ions, such as boron ions, can be implanted into the substrate 10 by ion implantation to form a P-type substrate, so that a PN junction of a photodiode can be formed between the P-type substrate and the N-type photosensitive stack.

[0050] Please continue to refer to this. Figure 2 In some embodiments, the front side of the trench isolation portion 101 is the surface facing away from the first top surface 10a of the substrate, and the front side of the trench isolation portion 101 is covered with an etch stop layer 102. The side of the etch stop layer 102 facing away from the trench isolation portion 101 includes an interlayer dielectric layer 103.

[0051] For example, please continue to refer to Figure 2After forming the etch stop layer 102, metal is deposited to form a partial interconnect structure, and an interlayer dielectric layer 103 is formed on this basis. When the etch stop layer 102 is multilayered, other process problems caused by cracks in a single layer and / or failure of the metal interconnect structure can be avoided. The interlayer dielectric layer 103 can be silicon oxide or other dielectric material layers. In addition, metal interconnect structures can be formed on the interlayer dielectric layer 103 as metal interconnect portions of the device.

[0052] Of course, this embodiment only illustrates one method. As long as the metal interconnect structure can be formed reasonably, the thickness of the etching stop layer 102 and the interlayer dielectric layer 103 is not limited and can be adjusted according to specific process requirements.

[0053] Please continue to refer to this. Figure 2 In some embodiments, after forming a shallow trench (STI) in the substrate 10 and filling the STI with dielectric material, a trench isolation portion 101 can be formed. Subsequently, the substrate 10 can be flipped over, and the back side of the substrate 10 can be thinned and planarized to expose the back side of the trench isolation portion 101, thereby obtaining a first top surface 10a of the substrate 10.

[0054] For example, please continue to refer to Figure 2 A first semiconductor material layer 211 is epitaxially grown on the first top surface 10a of a substrate 10 with a flush top surface. The thickness of the first semiconductor material layer 211 can be 50 nanometers to 60 nanometers. For example, the thickness of the first semiconductor material layer 211 can be 50 nanometers, 55 nanometers, or 60 nanometers, etc. The first semiconductor material layer 211 may include a SiB layer, which is used to characterize silicon material doped with boron (B).

[0055] For example, please continue to refer to Figure 2 After forming a first semiconductor material layer 211 on the first top surface 10a of the substrate 10 using a selective epitaxial growth process, a first dielectric layer 22 is formed on the top surface of the first semiconductor material layer 211. The first dielectric layer 22 is used to protect the first semiconductor material layer 211 from damage during subsequent etching or polishing processes.

[0056] For example, please continue to refer to Figure 2 The thickness of the first dielectric layer 22 can be 1 nm to 2 nm. For example, the thickness of the first dielectric layer 22 can be 1 nm, 1.5 nm, or 2 nm. The material of the first dielectric layer 22 can include silicon oxide.

[0057] Please refer to Figure 3In some embodiments, after a first patterned photoresist layer (not shown) is formed on the top surface of the first dielectric layer 22, the first patterned photoresist layer includes an opening pattern for defining the shape, position, and size of the first grooves 31. Based on the first patterned photoresist layer, the first dielectric layer 22 and the first semiconductor material layer 211 are etched to form a plurality of first grooves 31 spaced apart along a first direction within the first semiconductor material layer 211. The remaining first semiconductor material layer 211 is used to constitute the first semiconductor layer 21.

[0058] Please refer to Figure 4 In some embodiments, a selective epitaxial growth process can be used to form a first photosensitive portion 30 within the first groove 31. The first photosensitive portion 30 fills the first groove 31, and the top surface of the first photosensitive portion 30 is higher than the top surface of the first dielectric layer 22. The first photosensitive portion 30 may include a SiAs layer, which is used to characterize silicon material doped with arsenic (As).

[0059] Please continue to refer to this. Figure 4 In some embodiments, a selective epitaxial growth process can be used to form a second semiconductor material layer 411 covering the first photosensitive portion 30 and the second dielectric layer 42, wherein the top surface of the second semiconductor material layer 411 is higher than the top surface of the first photosensitive portion 30. The material of the second semiconductor material layer 411 can be the same as the material of the first semiconductor layer 21.

[0060] For example, please continue to refer to Figure 4 The second semiconductor material layer 411 may include a SiB layer, which is used to characterize silicon material doped with boron (B).

[0061] For example, please continue to refer to Figure 4 A second dielectric layer 42 is formed on the top surface of the second semiconductor material layer 411, and the thickness of the second dielectric layer 42 is less than the thickness of the second semiconductor material layer 411. The second dielectric layer 42 is used to protect the second semiconductor material layer 411 from damage during subsequent etching or polishing processes.

[0062] For example, please continue to refer to Figure 4 The material of the second dielectric layer 42 may include silicon oxide.

[0063] Please refer to Figures 4-5In some embodiments, after planarizing the top surface of the second dielectric layer 42, a second patterned photoresist layer (not shown) can be formed on the top surface of the second dielectric layer 42. The second patterned photoresist layer includes opening patterns for defining the shape, position, and size of the second grooves 51. The second dielectric layer 42 and the second semiconductor material layer 411 are etched based on the second patterned photoresist layer, forming a plurality of second grooves 51 spaced apart along a first direction within the second semiconductor material layer 411. The remaining second semiconductor material layer 411 is used to constitute the second semiconductor layer 41.

[0064] For example, please continue to refer to Figure 5 The second groove 51 is larger in size along the first direction than the first photosensitive part 30 is in size along the first direction; the second groove 51 can expose the entire top surface of the first photosensitive part 30.

[0065] Please refer to Figure 6 In some embodiments, a selective epitaxial growth process can be used to form a plurality of second photosensitive portions 50 within a plurality of second grooves 51. The second photosensitive portions 50 fill the second grooves 51, and the top surface of the second photosensitive portion 50 is higher than the top surface of the second dielectric layer 42. The second photosensitive portion 50 may include a SiP layer, which is used to characterize the phosphorus (P)-doped silicon material. The orthographic projection of the top surface of the first photosensitive portion 30 onto the bottom surface of the second photosensitive portion 50 is located within the bottom surface of the second photosensitive portion 50.

[0066] Please refer to Figure 7 In some embodiments, a selective epitaxial growth process can be used to form a third semiconductor material layer (not shown) covering the second photosensitive portion 50 and the second dielectric layer 42, with the top surface of the third semiconductor material layer being higher than the top surface of the second photosensitive portion 50. The material of the third semiconductor material layer can be the same as the material of the first semiconductor layer 21.

[0067] For example, please continue to refer to Figure 7 The third semiconductor material layer may include a SiB layer, which is used to characterize silicon material doped with boron (B).

[0068] For example, please continue to refer to Figure 7 A third dielectric layer 62 is formed on the top surface of the third semiconductor material layer, and the thickness of the third dielectric layer 62 is less than the thickness of the third semiconductor material layer. The third dielectric layer 62 is used to protect the third semiconductor material layer from damage during subsequent etching or polishing processes.

[0069] For example, please continue to refer to Figure 7After planarizing the top surface of the third dielectric layer 62, a third patterned photoresist layer (not shown) is formed on the top surface of the third dielectric layer 62. The third patterned photoresist layer includes opening patterns defining the shape, position, and size of the third grooves 71. Based on the third patterned photoresist layer, the third dielectric layer 62 and the third semiconductor material layer are etched, forming a plurality of third grooves 71 spaced apart along a first direction within the third semiconductor material layer. The remaining third semiconductor material layer is used to constitute the third semiconductor layer 61.

[0070] For example, please continue to refer to Figures 7-8 The dimension of the third groove 71 along the first direction is smaller than the dimension of the second photosensitive part 50 along the first direction; the bottom surface of the third groove 71 is lower than the top surface of the second photosensitive part 50.

[0071] Please refer to Figure 8 In some embodiments, a selective epitaxial growth process can be used to form a third photosensitive portion 70 within the third groove 71. The third photosensitive portion 70 fills the third groove 71, and the top surface of the third photosensitive portion 70 is higher than the top surface of the third dielectric layer 62. The third photosensitive portion 70 may include a SiAs layer, which is used to characterize silicon material doped with arsenic (As).

[0072] Please refer to Figure 9 In some embodiments, after forming the third photosensitive portion 70 whose top surface is higher than the top surface of the third dielectric layer 62, the method further includes:

[0073] Step S41: Planarize the top surface of the third photosensitive part 70 until the top surface of the remaining third photosensitive part 70 is flush with the top surface of the third dielectric layer 62.

[0074] Step S42: A plurality of grids 80 are formed on the top surface of the third dielectric layer 62 at intervals along the first direction, and the grids 80 and the photosensitive stack are arranged alternately along the first direction.

[0075] In some embodiments, the substrate 10 includes a plurality of trench isolation portions 101 spaced apart along a first direction; a plurality of grids 80 are located directly above the plurality of trench isolation portions 101.

[0076] Please continue to refer to this. Figure 9 In some embodiments, after step S41, a grid material stack (not shown) covering the top surface of the third photosensitive portion 70 and the top surface of the third dielectric layer 62 can be formed. The grid material stack includes a first grid material layer 81, a second grid material layer 82, and a third grid material layer 83 sequentially stacked along a second direction away from the substrate. The material of the first grid material layer 81 may include HfO2. The material of the second grid material layer 82 may include TiN. The material of the third grid material layer 83 may include Al.

[0077] Please continue to refer to this. Figures 9-10 In some embodiments, after forming the grid material stack, a fourth patterned photoresist layer (not shown) may be formed on the top surface of the grid material stack. The fourth patterned photoresist layer includes an opening pattern for defining the shape, position and size of the filter 90. The grid material stack is etched based on the fourth patterned photoresist layer to form a plurality of grids 80, wherein the plurality of grids 80 are located directly above the plurality of trench isolation portions 101.

[0078] Please continue to refer to this. Figures 9-10 In some embodiments, after forming the grid 80, the following steps are also included:

[0079] A filter 90 is formed between adjacent grids 80 along a first direction, such as the ox direction.

[0080] For example, please continue to refer to Figure 10 The filter 90 includes, but is not limited to, a red filter, a yellow filter, and a blue filter, and the three filters are arranged adjacent to each other as a pixel group. Among them, the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves.

[0081] Please refer to Figure 10 In some embodiments, a back-illuminated image sensor is provided, fabricated using the back-illuminated image sensor fabrication method described in any of the foregoing embodiments. The back-illuminated image sensor includes a substrate 10, a first semiconductor layer 21, a plurality of first photosensitive portions 30, a second semiconductor layer 41, a plurality of second photosensitive portions 50, a third semiconductor layer 61, and a plurality of third photosensitive portions 70. The substrate 10 includes a first top surface 10a; the first semiconductor layer 21 is located on the first top surface 10a of the substrate 10; the plurality of first photosensitive portions 30 are located within the first semiconductor layer 21 and are spaced apart along a first direction; the second semiconductor layer 41 covers the first semiconductor layer 21; the plurality of... The second photosensitive portions 50 are spaced apart along the first direction and extend through the second semiconductor layer 41 along the second direction close to the substrate 10 and to the top surface of the plurality of first photosensitive portions 30; the third semiconductor layer 61 covers the plurality of second photosensitive portions 50; the plurality of third photosensitive portions 70 are spaced apart along the first direction and extend through the third semiconductor layer 61 along the second direction and into the interior of the plurality of second photosensitive portions 50; the first photosensitive portions 30, the second photosensitive portions 50 and the third photosensitive portions 70 arranged sequentially along the second direction are used to form a photosensitive stack, and the first semiconductor layer 21, the second semiconductor layer 41 and the third semiconductor layer 61 are used to form a PN junction with the photosensitive stack.

[0082] Please continue to refer to this. Figure 10In some embodiments, the first photosensitive part 30 and the second photosensitive part 50 contain different Group V elements; the second photosensitive part 50 and the third photosensitive part 70 contain different Group V elements; and the first semiconductor layer 21, the second semiconductor layer 41 and the third semiconductor layer 61 all contain Group III elements.

[0083] For example, Group V elements include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0084] For example, Group 3 elements include boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).

[0085] Please continue to refer to this. Figure 10 In some embodiments, the first photosensitive unit 30 includes a SiAs layer; the second photosensitive unit 50 includes a SiP layer; and the third photosensitive unit 70 includes a SiAs layer. The SiAs layer is used to characterize the As-doped silicon material; and the SiP layer is used to characterize the P-doped silicon material. The N-type photosensitive stack can form a PN junction of a photodiode with the P-type substrate.

[0086] Please continue to refer to this. Figures 1-10 The back-illuminated image sensor fabrication method and back-illuminated image sensor in this disclosure embodiment have the following unexpected technical effects:

[0087] A first semiconductor layer 21, a second semiconductor layer 41, and a third semiconductor layer 61 are sequentially formed on the first top surface 10a of the substrate 10. The first semiconductor layer 21 includes a plurality of first photosensitive portions 30 spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer 21. The second semiconductor layer 41 includes a plurality of second photosensitive portions 50 spaced apart along the first direction and extending through the second semiconductor layer 41 and to the top surface of the plurality of first photosensitive portions 30 along a second direction close to the substrate 10. The third semiconductor layer 61 includes a plurality of second photosensitive portions 50 spaced apart along the first direction and extending through the second semiconductor layer 61 along the second direction. A conductor layer 41 extends into multiple third photosensitive portions 70 within multiple second photosensitive portions 50. First photosensitive portions 30, second photosensitive portions 50, and third photosensitive portions 70, sequentially distributed along a second direction, constitute a photosensitive stack. A first semiconductor layer 21, a second semiconductor layer 41, and a third semiconductor layer 61 form a PN junction with the photosensitive stack. This PN junction achieves photoelectric isolation between the photosensitive stack and adjacent first semiconductor layers 21, 41, or 61 along the first direction, effectively preventing signal crosstalk between adjacent photosensitive stacks along the first direction. The photosensitive stack can include different Group 5 elements. Photosensitive stacks doped with different pentavalent elements will generate a concentration gradient within them after photoexcitation. This difference optimizes the transport path of photogenerated carriers, reducing the recombination rate during diffusion. Under the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. In addition, since pentavalent elements have a higher atomic mass than silicon, their mobility is lower during epitaxial growth, resulting in uneven doping concentration in a single doped layer. Growing pentavalent elements with different dopants in multiple stages can improve the uniformity of doping concentration in the pixel area.

[0088] Furthermore, the first photosensitive portion 30 and the first semiconductor layer 21 are fabricated simultaneously in the same process steps, the second photosensitive portion 50 and the second semiconductor layer 41 are fabricated simultaneously in the same process steps, and the third photosensitive portion 70 and the third semiconductor layer 61 are fabricated simultaneously in the same process steps. The stacked first photosensitive portion 30, second photosensitive portion 50, and third photosensitive portion 70 together constitute a photosensitive stack; the stacked first semiconductor layer 21, second semiconductor layer 41, and third semiconductor layer 61 together constitute an isolation stack. This isolation stack can form a PN junction with the photosensitive stack to achieve photoelectric isolation and avoid signal crosstalk. Because the photosensitive stack and the isolation stack are fabricated simultaneously in the same process steps, the complexity and cost of the fabrication process are effectively reduced.

[0089] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0090] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, include: A substrate including a first top surface is provided; a first semiconductor layer is formed on the first top surface of the substrate, the first semiconductor layer including a plurality of first photosensitive portions spaced apart along a first direction and whose top surface is not lower than the top surface of the first semiconductor layer; the first semiconductor layer and the plurality of first photosensitive portions are prepared simultaneously in the same process steps; A second semiconductor layer is formed to cover the first semiconductor layer. The second semiconductor layer includes a plurality of second photosensitive portions that are spaced apart along the first direction and extend through the second semiconductor layer along a second direction close to the substrate to the top surface of the plurality of first photosensitive portions. The orthographic projection of the top surface of the first photosensitive portion onto the bottom surface of the second photosensitive portion is located inside the bottom surface of the second photosensitive portion. The second semiconductor layer and the plurality of second photosensitive portions are fabricated simultaneously in the same process steps. A third semiconductor layer is formed covering the second semiconductor layer. The third semiconductor layer includes a plurality of third photosensitive portions that are spaced apart along the first direction and penetrate the third semiconductor layer along the second direction and extend into the interior of the plurality of second photosensitive portions. The third photosensitive portions are circumferentially surrounded by the second photosensitive portions. The third semiconductor layer and the plurality of third photosensitive portions are fabricated simultaneously in the same process steps. The first photosensitive portions, the second photosensitive portions and the third photosensitive portions that are sequentially distributed along the second direction are used to form a photosensitive stack. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are used to form a PN junction with the photosensitive stack.

2. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, Forming the first semiconductor layer includes: After forming a first semiconductor material layer on the first top surface of the substrate, a first dielectric layer is formed on the top surface of the first semiconductor material layer; The first dielectric layer and the first semiconductor material layer are etched to form a plurality of first grooves spaced apart along the first direction in the first semiconductor material layer; A plurality of first photosensitive portions are formed within the plurality of first grooves, wherein the top surface of the first photosensitive portion is higher than the top surface of the first dielectric layer; the remaining first semiconductor material layer is used to form the first semiconductor layer.

3. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, Forming the second semiconductor layer includes: A second semiconductor material layer is formed that covers the plurality of first photosensitive portions and has a top surface higher than the top surface of the first photosensitive portions; A second dielectric layer is formed on the top surface of the second semiconductor material layer; The second dielectric layer and the second semiconductor material layer are etched to form a plurality of second grooves spaced apart along the first direction in the second semiconductor material layer; the size of the second grooves along the first direction is larger than the size of the first photosensitive portion along the first direction. A plurality of second photosensitive portions are formed within the plurality of second grooves, the top surface of the second photosensitive portion being higher than the top surface of the second dielectric layer; the remaining second semiconductor material layer is used to form the second semiconductor layer.

4. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, Forming the third semiconductor layer includes: A third semiconductor material layer is formed that covers the plurality of second photosensitive portions and has a top surface higher than the top surface of the second photosensitive portions; A third dielectric layer is formed on the top surface of the third semiconductor material layer; The third dielectric layer and the third semiconductor material layer are etched to form a plurality of third grooves spaced apart along the first direction in the third semiconductor material layer; the bottom surface of the third groove is lower than the top surface of the second photosensitive part; A plurality of third photosensitive portions are formed within the plurality of third grooves, the top surface of the third photosensitive portion being higher than the top surface of the third dielectric layer; the remaining third semiconductor material layer is used to form the third semiconductor layer.

5. The method for fabricating a back-illuminated image sensor according to claim 4, characterized in that, After forming the third photosensitive portion whose top surface is higher than the top surface of the third dielectric layer, the method further includes: The top surface of the third photosensitive part is planarized until the top surface of the remaining third photosensitive part is flush with the top surface of the third dielectric layer; A plurality of grids are formed on the top surface of the third dielectric layer at intervals along the first direction, and the grids and the photosensitive stack are arranged alternately along the first direction.

6. The method for fabricating a back-illuminated image sensor according to claim 5, characterized in that, The substrate includes a plurality of trench isolation portions spaced apart along the first direction; The plurality of grilles are located directly above the plurality of trench isolation sections.

7. The method for fabricating a back-illuminated image sensor according to any one of claims 1-6, characterized in that, The first photosensitive part and the second photosensitive part contain different Group V main elements; The second photosensitive part and the third photosensitive part contain different Group V main elements; The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all include elements from Group 3.

8. The method for fabricating a back-illuminated image sensor according to any one of claims 1-6, characterized in that, The first photosensitive part includes a SiAs layer; the second photosensitive part includes a SiP layer; the third photosensitive part includes a SiAs layer; the SiAs layer is used to characterize As-doped silicon material; the SiP layer is used to characterize P-doped silicon material.

9. A back-illuminated image sensor, characterized in that, The back-illuminated image sensor is fabricated using the method described in any one of claims 1-8, wherein the back-illuminated image sensor comprises: Substrate, including a first top surface; A first semiconductor layer is located on the first top surface of the substrate; Multiple first photosensitive elements are located within the first semiconductor layer and are spaced apart along the first direction; the first semiconductor layer and the multiple first photosensitive elements are fabricated simultaneously in the same process steps. A second semiconductor layer covers the first semiconductor layer; A plurality of second photosensitive portions are spaced apart along the first direction and extend through the second semiconductor layer along a second direction close to the substrate and to the top surface of the plurality of first photosensitive portions; A third semiconductor layer covers the plurality of second photosensitive portions; the orthographic projection of the top surface of the first photosensitive portion onto the bottom surface of the second photosensitive portion is located within the bottom surface of the second photosensitive portion; the second semiconductor layer and the plurality of second photosensitive portions are fabricated simultaneously in the same process steps; A plurality of third photosensitive portions are spaced apart along the first direction and penetrate the third semiconductor layer along the second direction, extending into the interior of the plurality of second photosensitive portions; the second photosensitive portions circumferentially surround the third photosensitive portions therein; the third semiconductor layer and the plurality of third photosensitive portions are fabricated simultaneously in the same process steps; the first photosensitive portions, the second photosensitive portions and the third photosensitive portions, which are sequentially distributed along the second direction, are used to form a photosensitive stack, and the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are used to form a PN junction with the photosensitive stack.

10. The back-illuminated image sensor according to claim 9, characterized in that, The first photosensitive part and the second photosensitive part contain different Group V main elements; The second photosensitive part and the third photosensitive part contain different Group V main elements; The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all include elements from Group 3.

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