Stress balance InP-InGaAs avalanche photodetector and preparation method thereof

Abstract

The invention discloses a stress balance InP-InGaAs avalanche photodetector and a preparation method thereof. An n-type InP buffer layer, an unintentionally doped In < 0.53 > Ga < 0.47 > As bottom absorption layer, a plurality of groups of unintentionally doped stress matching InGaAs absorption layers, an unintentionally doped In < 0.53 > Ga < 0.47 > As top absorption layer, an n-type InP charge layer and an unintentionally doped InP cover layer are sequentially grown on an n-type InP substrate; the optimal photosensitive wavelength of the avalanche photodetector is 2.0 microns, and the device can stably work at room temperature at low dark current.

Description

Technical Field

[0001] This invention relates to the field of photodetector technology, and more specifically to a stress-balanced InP-InGaAs avalanche photodetector and its fabrication method. Background Technology

[0002] Avalanche photodetectors (APDs) are optoelectronic devices that utilize the avalanche multiplication effect to achieve high-sensitivity detection, and are widely used in optical communication, lidar, infrared imaging, and spectral detection. In the near-infrared band (1-2 μm), InP-based InGaAs materials are ideal for APD devices due to their excellent carrier transport properties and tunable bandgap structure. Especially in the 2 μm band (e.g., 1.8-2.2 μm), they have attracted much attention in recent years due to their unique advantages in atmospheric transmission, medical diagnostics, and space communication. However, existing InP-InGaAs-based APDs still face the following key challenges in the 2 μm band:

[0003] 1. The problem of lattice mismatch and stress accumulation in materials

[0004] The lattice constant of a traditional InGaAs absorber layer differs from that of an InP substrate (e.g., the lattice constant of an InGaAs material with 53% In content matches that of an InP substrate, covering the 1.55 μm band). Extending to the 2 μm band requires increasing the In content (e.g., In...). 0.8 Ga 0.2 As), leading to severe lattice mismatch and dislocation defects, reducing device reliability. Existing stress balancing techniques (such as superlattice buffer layers or gradient buffer layers) can partially alleviate the mismatch, but they introduce complex epitaxial growth processes, increase costs, and may introduce interface defects that lead to increased dark current.

[0005] 2. Insufficient dark current and noise performance.

[0006] The narrow bandgap of InGaAs in the 2μm band leads to a significant increase in dark current at room temperature (especially tunneling current and thermally generated current), limiting the signal-to-noise ratio and detection sensitivity of APDs. Existing solutions (such as lowering the temperature or using a heterojunction charge layer) struggle to balance low dark current with high gain and have poor process compatibility.

[0007] 3. The contradiction between avalanche zone design and multiplication efficiency.

[0008] Traditional APDs (such as InP multiplication layers) require high electric fields to operate in their avalanche regions. However, the band shift between InP and InGaAs with high In content can lead to a decrease in carrier injection efficiency, affecting avalanche uniformity. Existing devices mostly employ a separated absorption-multiplication (SACM) structure, but insufficient optimization of the band matching between the absorption layer and the multiplication layer in the 2μm band results in reduced response speed or increased breakdown voltage.

[0009] 4. The trade-off between wavelength extension and quantum efficiency

[0010] To cover the 2μm band, it is necessary to increase the In composition of InGaAs or introduce a strain compensation layer (such as InAlAs). However, existing epitaxial techniques cannot simultaneously guarantee high quantum efficiency and low defect density, especially at the long wavelength edge (>2μm) where the responsivity drops sharply. Summary of the Invention

[0011] To address the shortcomings of the aforementioned technical solutions, the present invention aims to provide a stress-balanced InP-InGaAs avalanche photodetector and its fabrication method.

[0012] The objective of this invention is achieved through the following technical solution.

[0013] A method for fabricating a stress-balanced InP-InGaAs avalanche photodetector includes the following steps:

[0014] Step 1: Using MOCVD or MBE deposition methods, sequentially grow an n-type InP buffer layer and unintentionally doped In on an n-type InP substrate. 0.53 Ga 0.47 As bottom absorption layer, multiple sets of unintentionally doped stress-matched InGaAs absorption layers, and unintentionally doped In 0.53 Ga 0.47 As top absorption layer, n-type InP charge layer, and unintentionally doped InP capping layer;

[0015] Step 2: Deposit a first SiN-Zn diffusion mask on the upper surface of the unintentionally doped InP capping layer using PECVD deposition.

[0016] Step 3: Apply photoresist to the upper surface of the first SiN-Zn diffusion mask to form a circular diffusion pattern and at least one annular diffusion pattern around the circular diffusion pattern. Remove the first SiN-Zn diffusion mask on the circular diffusion pattern by etching. After etching, remove the photoresist to form a circular diffusion window. Remove the first SiN-Zn diffusion mask on the annular diffusion pattern by etching. After etching, remove the photoresist to form an annular diffusion window, so that the upper surface of the unintentionally doped InP capping layer is exposed.

[0017] Step 4: Using MOCVD or furnace tube method, the first Zn diffusion is performed on the upper surface of the unintentionally doped InP capping layer within the circular diffusion window and the annular diffusion window, diffusing to the upper part of the unintentionally doped InP capping layer to form a circular diffusion region and an annular diffusion region.

[0018] Step 5: Deposit a second SiN-Zn diffusion mask on all exposed upper surfaces using PECVD deposition.

[0019] Step 6: Apply photoresist to the upper surface of the second SiN Zn diffusion mask at the top of the circular diffusion region to form a circular central diffusion pattern. Remove the second SiN Zn diffusion mask on the circular central diffusion pattern by etching to expose the unintentionally doped InP capping layer below. After etching, remove the photoresist to form a central diffusion window.

[0020] Step 7: Perform a second Zn diffusion within the central diffusion window using MOCVD or furnace tube method to form a central diffusion region. The difference between the radius of the circular diffusion region and the radius of the central diffusion region is 5 μm, and the difference between the depth of the central diffusion region and the depth of the circular diffusion region is 100 nm - 2 μm.

[0021] Step 8: Deposit SiN antireflection film on all exposed upper surfaces using PECVD deposition.

[0022] Step 9: Apply photoresist to the SiN antireflection film to form a VIA hole pattern. Use etching to remove the SiN antireflection film under the VIA hole pattern, exposing part of the upper surface of the central diffusion region to form a VIA hole. The bottom outer edge of the VIA hole is tangent to the top outer edge of the central diffusion region. After etching, remove the photoresist.

[0023] Step 10: Electron beam evaporation or magnetron sputtering is used to deposit metal in the VIA aperture and the metal is stripped off. Annealing is then performed to form an ohmic contact and a P metal electrode is formed. The bottom of the P metal electrode is connected to the top of the central diffusion region.

[0024] Step 11: Thinning and polishing the back side of the n-type InP substrate;

[0025] Step 12: Using electron beam evaporation or magnetron sputtering, an N metal electrode is prepared on the back side of the polished n-type InP substrate, and then annealed to form an ohmic contact.

[0026] In the above technical solution, the thickness of the n-type InP buffer layer is 0.5–2 μm, and the doping concentration is 1 × 10⁻⁶. 17 / cm 3 ~2×10 18 / cm 3 .

[0027] In the above technical solution, the unintentionally doped In 0.53 Ga 0.47 The thickness of the bottom absorption layer of As is 0.1–2 μm, and its lattice constant matches that of the n-type InP substrate.

[0028] In the above technical solution, the number of groups of unintentionally doped stress-matching InGaAs absorber layers is 1 to 100, and each group of unintentionally doped stress-matching InGaAs absorber layers includes compressive stress InGaAs arranged from bottom to top. x1 GaAs absorber layer, compositionally graded In x1-.x2 GaAs layer, tensile stress In x2 GaAs absorber layer and compositional gradient In x2-.x1 GaAs layer; wherein the compressive stress In x1 The proportion of In in the GaAs absorber layer (x1) is 53%–80%, and the tensile stress In x2 The proportion of In in the GaAs absorber layer is 40% to 53% x2, and the In composition is gradually varied. x1-.x2 The proportion of In in the GaAs layer gradually changes from 53%–80% at bottom to 40%–53% at top; the compressive stress In x1 The thickness of the GaAs absorber layer is 1-20 nm, and the composition is gradually changed by In. x1-.x2 The thickness of the GaAs layer is 1-50 nm, and the tensile stress In x2 The thickness of the GaAs absorber layer is 1-50 nm, and the composition is gradually varied by In. x2-.x1 The thickness of the GaAs layer is 1-100 nm; the stress of each group of unintentionally doped stress-matched InGaAs absorber layers is 0 relative to the n-type InP substrate to achieve stress balance.

[0029] In the above technical solution, the unintentionally doped In 0.53 Ga 0.47 The thickness of the As top absorber layer is 0.1–2 μm, and its lattice constant matches that of the n-type InP substrate.

[0030] In the above technical solution, the thickness of the n-type InP charge layer is 0.1–2 μm, and its doping concentration is 1 × 10⁻⁶. 17 -5×10 17 / cm 3 .

[0031] In the above technical solution, the thickness of the unintentionally doped InP capping layer is greater than or equal to 2 μm.

[0032] In the above technical solution, the thickness of the annular diffusion region is from the thickness of the unintentionally doped InP capping layer minus 1000 nm to the thickness of the unintentionally doped InP capping layer minus 500 nm, and the thickness of the central diffusion region is from the thickness of the unintentionally doped InP capping layer minus 600 nm to the thickness of the unintentionally doped InP capping layer minus 100 nm.

[0033] In the above technical solution, the thickness of the circular diffusion region is 2000-3500 nm, the thickness of the central diffusion region is 3000-4000 nm, and the thickness of the annular diffusion region is 2000-3500 nm.

[0034] In the above technical solution, the SiN antireflection film has a transmittance of 70% or more for light with wavelengths of 1310nm to 2100nm.

[0035] In the above technical solution, the thickness of the n-type InP substrate is 50–200 μm.

[0036] Another aspect of the present invention includes a stress-balanced InP-InGaAs avalanche photodetector obtained by the preparation method.

[0037] The advantages and beneficial effects of this invention are as follows:

[0038] 1. The absorption region of the avalanche photodetector of the present invention employs 65 groups of unintentionally doped stress-matched InGaAs absorption layers. Each group of absorption layers comprises multiple layers with different In composition percentages, forming a high- and low-In composition strain-balanced heterostructure. The high-In composition layer exhibits compressive stress... x1 GaAs absorption layer (In) 0.71 Ga 0.29 The thickness of the As material reaches 520 nm, resulting in an internal quantum efficiency exceeding 20% ​​and a responsivity greater than 0.3 A / W. This is the P-type In material used in avalanche photodetectors. 0.52 Al 0.48 The As charge layer and avalanche amplification layer are made of InP material. The wide bandgap ensures that it can withstand high electric field strength and generate sufficient avalanche ionization to meet the high gain requirement. The PN structure of the device is realized by patterned Zn diffusion in an unintentionally doped InP capping layer. By controlling the depth of Zn diffusion, the thickness of the impact ionization layer can be adjusted. By performing Zn diffusion at different depths in different regions, an edge electric field protection ring can be formed to reduce the risk of edge breakdown, enabling the device to have an operating gain >10 and a maximum gain >100, thus resulting in an overall responsivity >3 A / W.

[0039] 2. The avalanche photodetector of the present invention. The advantage of using InP as the impact ionosphere in the detector of the present invention is that it can form a purely planar device structure, which can effectively reduce edge leakage current and improve device reliability.

[0040] 3. In this invention, in order to match the stress of unintentional doping with the high In content of the InGaAs absorber layer... 0.71 Ga 0.29To extend the room-temperature absorption cutoff wavelength of InGaAs materials to 2.1 μm, the In content needs to be further increased to over 71%. If epitaxial growth is performed directly on an n-type InP substrate, the In content needs to be increased beyond 71%. 0.71 Ga 0.29 After the relaxation critical thickness of As material is reached, it will be in In 0.71 Ga 0.29 The generation of numerous mismatch dislocations in As materials leads to a deterioration in crystal material quality. This invention addresses this issue by growing a strain-balanced InGaAs heterostructure (multiple sets of unintentionally doped stress-matched InGaAs absorber layers) on an n-type InP substrate. Specifically, high-In and low-In-content InGaAs materials are alternately grown on an n-type InP substrate to achieve stress balance, extending the room-temperature absorption cutoff wavelength to 2.1 μm without lattice relaxation. It is precisely because the influence of mismatch dislocations is eliminated that this structure possesses lattice-matched In... 0.53 Ga 0.47 As detectors have similar low dark current, they can operate at room temperature, improving device performance.

[0041] 4. The optimal light-sensing wavelength of the avalanche photodetector of the present invention is 2.0 μm, enabling the device to operate stably with low dark current at room temperature. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of steps 1 to 4 of the present invention.

[0043] Figure 2 This is a structural schematic diagram of steps 5 to 7 of the present invention.

[0044] Figure 3 This is a structural schematic diagram of steps 8 to 9 of the present invention.

[0045] Figure 4 This is a structural schematic diagram of steps 10 to 12 of the present invention.

[0046] Figure 5 This is the spectral response curve of the photodetector of the present invention.

[0047] Wherein, 1: n-type InP substrate, 2: n-type InP buffer layer, 3: unintentionally doped In 0.53 Ga 0.47 4: Unintentionally doped stress-matched InGaAs absorber layer; 5: Unintentionally doped In... 0.53 Ga 0.476: Top absorption layer; 7: n-type InP charge layer; 8: Unintentionally doped InP capping layer; 9-1: First SiN-Zn diffusion mask; 9-2: Annular diffusion window; 10-1: Circular diffusion region; 10-2: Annular diffusion region; 11: Second SiN-Zn diffusion mask; 12: Central diffusion window; 13: Central diffusion region; 14: SiN antireflection film; 15: VIA hole; 16: P metal electrode; 17: N metal electrode. Detailed Implementation

[0048] The technical solution of the present invention will be further described below with reference to specific embodiments.

[0049] like Figures 1-4 As shown, this embodiment provides a method for fabricating the stress-balanced InP-InGaAs avalanche photodetector described in Embodiment 1, including the following steps:

[0050] Step 1: Using MOCVD or MBE deposition methods, sequentially grow an n-type InP buffer layer 2 and an unintentionally doped In layer 3 on an n-type InP substrate 1. 0.53 Ga 0.47 3. Bottom absorption layer of As; 4. Multiple sets of unintentionally doped stress-matched InGaAs absorption layers; 5. Unintentionally doped In... 0.53 Ga 0.47 As top absorption layer 5, n-type InP charge layer 6, and unintentionally doped InP capping layer 7;

[0051] Step 2: Deposit a first SiN-Zn diffusion mask 8 on the upper surface of the unintentionally doped InP capping layer 7 using PECVD deposition.

[0052] Step 3: Apply photoresist to the upper surface of the first SiN Zn diffusion mask 8 to form a circular diffusion pattern and at least one annular diffusion pattern around the circular diffusion pattern. Remove the first SiN Zn diffusion mask 8 on the circular diffusion pattern by etching. After etching, remove the photoresist to form a circular diffusion window 9-1. Remove the first SiN Zn diffusion mask 8 on the annular diffusion pattern by etching. After etching, remove the photoresist to form an annular diffusion window 9-2, so that the upper surface of the unintentionally doped InP capping layer 7 is exposed.

[0053] Step 4: Using MOCVD or furnace tube method, the first Zn diffusion is performed on the upper surface of the unintentionally doped InP capping layer 7 within the circular diffusion window and the annular diffusion window, diffusing to the upper part of the unintentionally doped InP capping layer 7 to form a circular diffusion region 10-1 and an annular diffusion region 10-2.

[0054] Step 5: Deposit a second SiN-Zn diffusion mask 11 on all exposed upper surfaces using PECVD deposition.

[0055] Step 6: Photoresist is applied to the upper surface of the second SiN Zn diffusion mask 11 at the top of the circular diffusion region 10-1 to form a circular central diffusion pattern. The second SiN Zn diffusion mask 11 is removed by etching on the circular central diffusion pattern to expose the unintentionally doped InP capping layer 7 below. After etching, the photoresist is removed to form the central diffusion window 12.

[0056] Step 7: Perform a second Zn diffusion in the central diffusion window 12 using MOCVD or furnace tube method. The difference between the radius of the circular diffusion region 10-1 and the radius of the central diffusion region 13 is 5 μm, and the difference between the depth of the central diffusion region 13 and the circular diffusion region 10-1 is 100 nm - 2 μm.

[0057] Step 8: Deposit a SiN antireflection film 14 on all exposed upper surfaces using PECVD deposition method;

[0058] Step 9: Apply photoresist to the SiN antireflection film 14 to form a VIA hole 15 pattern. Remove the SiN antireflection film 14 under the VIA hole 15 pattern by etching, exposing part of the upper surface of the central diffusion region 13 to form a VIA hole 15. The bottom outer edge of the VIA hole 15 is tangent to the top outer edge of the central diffusion region 13-1. After etching, remove the photoresist.

[0059] Step 10: Electron beam evaporation or magnetron sputtering is used to deposit metal in the VIA hole 15 and the metal is stripped off. Annealing is then performed to form an ohmic contact, forming a P metal electrode 16. The bottom of the P metal electrode is connected to the top of the central diffusion region 13.

[0060] Step 11: Thinning and polishing the back side of the n-type InP substrate 1;

[0061] Step 12: Using electron beam evaporation or magnetron sputtering, an N metal electrode 17 is prepared on the back side of the polished n-type InP substrate 1, and then annealed to form an ohmic contact.

[0062] Furthermore, the n-type InP buffer layer 2 has a thickness of 0.5 μm and a doping concentration of 5 × 10⁻⁶. 17 / cm 3 Its function is to better match the difference in lattice constant between the epitaxial layer materials on the n-type InP substrate 1 and the n-type InP buffer layer 2 caused by different growth conditions, and to ensure the growth quality of the epitaxial layer.

[0063] Furthermore, the unintentionally doped In 0.53 Ga 0.47 The thickness of the bottom absorption layer 3 of As is 0.3 μm, and its lattice constant matches that of the n-type InP substrate 1.

[0064] Furthermore, the number of groups of the unintentionally doped stress-matching InGaAs absorber layers 4 is 65, and each group of unintentionally doped stress-matching InGaAs absorber layers 4 includes compressive stress InGaAs arranged from bottom to top. x1 GaAs absorber layer, compositionally graded In x1-.x2 GaAs layer, tensile stress In x2 GaAs absorber layer and compositional gradient In x2-.x1 GaAs layer; wherein the compressive stress In x1 The In component ratio (x1) in the GaAs absorber layer is 71%, and the tensile stress In... x2 The In component ratio in the GaAs absorber layer is 44% x2, and the component is gradually varied in In. x1-.x2 The proportion of In in the GaAs layer gradually changes from 71% to 44%; the composition of In gradually changes. x2-.x1 The proportion of In in the GaAs layer gradually changes from 44% to 71%; the compressive stress In x1 The GaAs absorber layer has a thickness of 80 nm, and the composition is graded In. x1-.x2 The GaAs layer is 10 nm thick, and the tensile stress In x2 The GaAs absorber layer has a thickness of 15 nm, and the composition is graded In. x2-.x1 The GaAs layer is 10 nm thick; the stress of each unintentionally doped stress-matched InGaAs absorber layer 4 is 0 relative to the n-type InP substrate 1 to achieve stress balance. Through stress balance, the structure can avoid the generation of mismatch dislocations and maintain the high crystal quality of the entire structure.

[0065] Furthermore, the unintentionally doped In 0.53 Ga 0.47 The thickness of the As top absorber layer 5 is 0.2 μm, and its lattice constant matches that of the n-type InP substrate 1.

[0066] Furthermore, the n-type InP charge layer 6 has a thickness of 0.2 μm and a doping concentration of 1.2 × 10⁻⁶. 17 / cm 3 .

[0067] Furthermore, the thickness of the unintentionally doped InP capping layer 7 is 4 μm.

[0068] Furthermore, the thickness of the first SiN Zn diffusion mask 8 is 100 nm, and the thickness of the second SiN Zn diffusion mask 11 is greater than or equal to 100 nm.

[0069] Furthermore, the thickness of the annular diffusion region 10-2 is 3000 nm, and the thickness of the central diffusion region 13-1 is 3400 nm.

[0070] Furthermore, the interval between two adjacent annular diffusion regions 10-2 is 4 μm, and the interval between the innermost annular diffusion region 10-2 and the central diffusion region 13 is 5 μm.

[0071] Furthermore, the SiN antireflection film 14 has a transmittance of greater than or equal to 70% for light with wavelengths of 1310nm to 2100nm.

[0072] Furthermore, the n-type InP substrate 1 has a thickness of 150 μm.

[0073] Depend on Figure 5 It is known that the optimal photosensitive wavelength of the stress-balanced InP-InGaAs avalanche photodetector of the present invention is 2.0 μm, enabling the device to operate stably with low dark current at room temperature.

[0074] The present invention has been described above by way of example. It should be noted that any simple modifications, alterations or other equivalent substitutions that can be made by those skilled in the art without creative effort without departing from the core of the present invention fall within the protection scope of the present invention.

Claims

1. A method for preparing a stress-balanced InP-InGaAs avalanche photodetector, characterized in that, The method comprises the following steps: Step 1: Using MOCVD or MBE deposition methods, sequentially grow an n-type InP buffer layer and unintentionally doped In on an n-type InP substrate. 0.53 Ga 0.47 As bottom absorption layer, multiple sets of unintentionally doped stress-matched InGaAs absorption layers, and unintentionally doped In 0.53 Ga 0.47 As top absorption layer, n-type InP charge layer, and unintentionally doped InP capping layer; Step 2: depositing a first SiN Zn diffusion mask on the upper surface of the unintentionally-doped InP cap layer by PECVD deposition; Step 3: applying photoresist on the upper surface of the first SiN Zn diffusion mask to form a circular diffusion pattern and at least one annular diffusion pattern surrounding the circular diffusion pattern, removing the first SiN Zn diffusion mask on the circular diffusion pattern by etching, removing the photoresist after etching to form a circular diffusion window, removing the first SiN Zn diffusion mask on the annular diffusion pattern by etching, and removing the photoresist after etching to form an annular diffusion window, so that the upper surface of the unintentionally-doped InP cap layer is exposed; Step 4: performing first Zn diffusion on the upper surface of the unintentionally-doped InP cap layer in the circular diffusion window and the annular diffusion window by MOCVD or furnace tube method, so that the upper part of the unintentionally-doped InP cap layer is diffused to form a circular diffusion region and an annular diffusion region; Step 5: depositing a second SiN Zn diffusion mask on all exposed upper surfaces by PECVD deposition; Step 6: applying photoresist on the upper surface of the second SiN Zn diffusion mask on the top of the circular diffusion region to form a circular central diffusion pattern, removing the second SiN Zn diffusion mask on the circular central diffusion pattern by etching to expose the underlying unintentionally-doped InP cap layer, removing the photoresist after etching to form a central diffusion window; Step 7: performing second Zn diffusion in the central diffusion window by MOCVD or furnace tube method to form a central diffusion region, wherein the difference between the radius of the circular diffusion region and the radius of the central diffusion region is 5 μm, and the difference between the depth of the central diffusion region and the circular diffusion region is 100 nm-2 μm; Step 8: depositing a SiN anti-reflection film on all exposed upper surfaces by PECVD deposition; Step 9: applying photoresist on the SiN anti-reflection film to form a VIA hole pattern, removing the SiN anti-reflection film under the VIA hole pattern by etching to expose the upper surface of part of the central diffusion region and form a VIA hole, wherein the bottom outer edge of the VIA hole is tangent to the top outer edge of the central diffusion region, and the photoresist is removed after etching; Step 10: depositing metal in the VIA hole by electron beam evaporation or magnetron sputtering and performing metal lift-off, and annealing to form an ohmic contact and form a P metal electrode, wherein the bottom of the P metal electrode is connected to the top of the central diffusion region; Step 11: thinning and polishing the back surface of the n-type InP substrate; Step 12: preparing an N metal electrode on the polished back surface of the n-type InP substrate by electron beam evaporation or magnetron sputtering, and annealing to form an ohmic contact.

2. The production method according to claim 1, characterized by, The thickness of the n-type InP buffer layer is 0.5-2 μm, and the doping concentration is 1×10 17 / cm 3 -2×10 18 / cm 3 .

3. The preparation method according to claim 1, characterized in that, In the step 1, the unintentionally doped In 0.53 Ga 0.47 The bottom absorption layer of As has a thickness of 0.1-2 μm and a lattice constant matching the n-type InP substrate.

4. The method of claim 1, wherein, The step 1, a plurality of groups of the unintentionally doped stress-matched InGaAs absorption layer, the number of groups is 1-100, each group of the unintentionally doped stress-matched InGaAs absorption layer includes, from bottom to top, compressive stress In x1 GaAs absorption layer, composition gradient In x1-.x2 GaAs layer, tensile stress In x2 GaAs absorption layer and composition gradient In x2-.x1 GaAs layer; wherein, the compressive stress In x1 The composition ratio x1 of In in the compressive stress In x2 GaAs absorption layer, the composition ratio x2 of In is 40%-53%, the composition gradient In x1-.x2 The composition ratio of In in the GaAs layer gradually changes from 53%-80% to 40%-53% from bottom to top; the compressive stress In x1 The thickness of the GaAs absorption layer is 1-20nm, the composition gradient In x1-.x2 The thickness of the GaAs layer is 1-50nm, the tensile stress In x2 The thickness of the GaAs absorption layer is 1-50nm, the composition gradient In x2-.x1 The thickness of the GaAs layer is 1-100nm; the stress of each group of the unintentionally doped stress-matched InGaAs absorption layer is 0 relative to the n-type InP substrate to achieve stress balance.

5. The preparation method according to claim 1, characterized in that, In the step 1, the unintentionally doped In 0.53 Ga 0.47 As top absorption layer has a thickness of 0.1-2 μm and its lattice constant is matched with the n-type InP substrate.

6. The method of claim 1, wherein, The thickness of the n-type InP charge layer is 0.1-2 μm, and the doping concentration is 1 x 10 17 -5 x 10 17 / cm 3 .

7. The preparation method according to claim 1, characterized in that, In step 1, the thickness of the unintentionally-doped InP cap layer is greater than or equal to 2 μm.

8. The method of claim 1, wherein, The thickness of the circular diffusion region is 2000-3500 nm, the thickness of the central diffusion region is 3000-4000 nm, and the thickness of the annular diffusion region is 2000-3500 nm.

9. The method of claim 1, wherein, The transmittance of the SiN anti-reflection film for light rays with a wavelength of 1310-2100 nm is greater than or equal to 70%, and the thickness of the n-type InP substrate after thinning and polishing is 50-200 μm.

10. The stress-balanced InP-InGaAs avalanche photodetector obtained by the preparation method according to any one of claims 1-9.

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