Transistor with bottom dielectric isolation and fully self-aligned direct back contact

Abstract

A microelectronic device includes a nanosheet transistor including a first source / drain (170) and a second source / drain (172), a front contact (182) connected to the first source / drain, and a back contact (210) connected to the second source / drain. A plurality of isolation layers are underlying the nanosheet transistors, and a second source / drain extends through the plurality of isolation layers to be in contact connection with the backside.

Description

Background Technology

[0001] This invention relates generally to the field of microelectronics, and more specifically to the formation of transistors having self-aligned back-side contacts.

[0002] Nanosheets are the dominant device structure in the continuous shrinking of CMOS. However, as shrinking makes devices smaller and closer together, nanosheet technology has shown problems, with them interfering with each other. As multiple devices are assembled in a smaller area, forming the necessary contacts and ensuring proper alignment of those contacts becomes more difficult. Summary of the Invention

[0003] Additional aspects and / or advantages will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the invention.

[0004] A microelectronic device includes a nanosheet transistor comprising a first source / drain and a second source / drain. A front contact is connected to the first source / drain, and a back contact is connected to the second source / drain. Multiple isolation layers are located beneath the nanosheet transistor, and the second source / drain extends through the multiple isolation layers to connect to the back contact.

[0005] The microelectronic device includes a first source / drain and a second source / drain. A front contact is connected to the first source / drain, and a back contact is connected to the second source / drain. Multiple isolation layers are located beneath the nanosheet transistor, and the second source / drain extends through the multiple isolation layers to connect to the back contact. The back contact extends into the multiple isolation layers to connect to the second source / drain.

[0006] A method includes the steps of forming a back-side interlayer dielectric layer on a first substrate. At least one back-side contact occupant is formed in the back-side interlayer dielectric layer, and a first dielectric layer is formed on top of the back-side interlayer dielectric layer and on top of the at least one back-side contact occupant. A plurality of alternating layers, including a channel layer and a sacrificial layer, are formed on a second substrate. A second dielectric layer is formed on top of the alternating layers. The second substrate is flipped, and the second dielectric layer is attached to the first dielectric layer, and a nanosheet transistor is formed from the alternating layers. Attached Figure Description

[0007] From the following description taken in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent, wherein:

[0008] Figure 1 The figure shows a top view of a plurality of nanodevices or transistors according to embodiments of the present invention.

[0009] Figure 2 The figure shows a cross-section X1 of substrate A after the formation of a plurality of occupiers and a first dielectric layer according to an embodiment of the present invention.

[0010] Figure 3 The figure shows a cross-section X2 of substrate A after the formation of multiple occupiers and a first dielectric layer according to an embodiment of the present invention.

[0011] Figure 4 The figure shows a cross-section X1 of substrate B after the formation of alternating layers according to an embodiment of the present invention.

[0012] Figure 5 The figure shows a cross-section X2 of substrate B after the formation of alternating layers according to an embodiment of the present invention.

[0013] Figure 6 The figure shows a cross-section Y of substrate A in the source / drain region after the formation of multiple occupiers and a first dielectric layer according to an embodiment of the present invention.

[0014] Figure 7 The figure shows a cross-section Y of substrate B in the source / drain region after the formation of alternating layers according to an embodiment of the present invention.

[0015] Figure 8 The figure shows a cross-section X1 of substrate A after substrate B has been flipped, according to an embodiment of the present invention.

[0016] Figure 9 The figure shows a cross-section X2 of substrate A after substrate B has been flipped, according to an embodiment of the present invention.

[0017] Figure 10 The figure shows a cross-section X1 of substrate B after it has been flipped according to an embodiment of the present invention.

[0018] Figure 11 The figure shows a cross-section X2 of substrate B after it has been flipped according to an embodiment of the present invention.

[0019] Figure 12 The figure shows a cross-section Y of substrate A in the source / drain region after substrate B has been flipped, according to an embodiment of the present invention.

[0020] Figure 13 The figure shows a cross-section Y of substrate B in the source / drain region after the substrate B has been flipped according to an embodiment of the present invention.

[0021] Figure 14 The figure shows a cross-section X1 of substrate A after substrate B has been attached to substrate A and multiple layers have been removed, according to an embodiment of the present invention.

[0022] Figure 15 The figure shows a cross-section X2 of substrate A after substrate B has been attached to substrate A and multiple layers have been removed, according to an embodiment of the present invention.

[0023] Figure 16 The figure shows a cross-section Y of substrate A in the source / drain region after substrate B is attached to substrate A and multiple layers are removed, according to an embodiment of the present invention.

[0024] Figure 17 The figure shows a cross-section X1 of a nanodevice after the formation of a dummy gate, a hard mask, and an upper spacer, according to an embodiment of the present invention.

[0025] Figure 18 The figure shows a cross-section X2 of the nanodevice after the formation of the dummy gate, hard mask, and upper spacer according to an embodiment of the present invention.

[0026] Figure 19 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after the alternating layers have been separated into multiple columns, according to an embodiment of the present invention.

[0027] Figure 20 The figure shows a cross-section X1 of a nanodevice after alternating layers have been separated into multiple columns and internal spacers have been formed, according to an embodiment of the present invention.

[0028] Figure 21 The figure shows a cross-section X2 of a nanodevice after alternating layers have been separated into multiple columns and internal spacers have been formed, according to an embodiment of the present invention.

[0029] Figure 22 The figure illustrates a cross-section Y of a nanodevice after the removal of alternating layers to form source / drain regions, according to an embodiment of the present invention.

[0030] Figure 23 The figure shows a cross-section X1 of the nanodevice after etching the first dielectric layer and the second dielectric layer to expose the back contact occupant according to an embodiment of the present invention.

[0031] Figure 24 The figure shows a cross-section X2 of the nanodevice after etching the first dielectric layer and the second dielectric layer to expose the back contact occupant according to an embodiment of the present invention.

[0032] Figure 25 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after etching a first dielectric layer and a second dielectric layer to expose a back contact occupant, according to an embodiment of the present invention.

[0033] Figure 26The figure shows a cross-section X1 of a nanodevice after the formation of the source / drain electrodes according to an embodiment of the present invention.

[0034] Figure 27 The figure shows a cross-section X2 of the nanodevice after the formation of the source / drain electrodes according to an embodiment of the present invention.

[0035] Figure 28 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after the formation of the source / drain, according to an embodiment of the present invention.

[0036] Figure 29 The figure shows an X1 cross-section of a nanodevice after the formation of the front interlayer dielectric layer according to an embodiment of the present invention.

[0037] Figure 30 The figure shows an X2 cross-section of a nanodevice after the formation of the front interlayer dielectric layer according to an embodiment of the present invention.

[0038] Figure 31 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after the formation of the front interlayer dielectric layer according to an embodiment of the present invention.

[0039] Figure 32 The figure shows an X1 cross-section of the nanodevice after the removal of the hard mask, dummy gate, and sacrificial layer, the formation of the gate, the increase of the height of the front interlayer dielectric layer, and the formation of the front contact, according to an embodiment of the present invention.

[0040] Figure 33 The figure shows a cross-section X2 of the nanodevice after the removal of the hard mask, dummy gate, and sacrificial layer, the formation of the gate, the increase of the height of the front interlayer dielectric layer, and the formation of the front contact, according to an embodiment of the present invention.

[0041] Figure 34 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after the removal of the hard mask, dummy gate, and sacrificial layer, the formation of the gate, the increase of the height of the front interlayer dielectric layer, and the formation of the front contact, according to an embodiment of the present invention.

[0042] Figure 35 The figure shows a cross-section X1 of the nanodevice after the formation of the back-end process (BEOL) layer and carrier wafer, the flipping of the nanodevice for back-end processing, and the removal of the first substrate, according to an embodiment of the present invention.

[0043] Figure 36 The figure shows a cross-section X2 of the nanodevice after the formation of the back-end process (BEOL) layer and carrier wafer, the flipping of the nanodevice for back-end processing, and the removal of the first substrate, according to an embodiment of the present invention.

[0044] Figure 37 The figure illustrates a cross-section Y of the nanodevice in the source / drain region after the formation of the back-end process (BEOL) layer and carrier wafer, the flipping of the nanodevice for back-end processing, and the removal of the first substrate, according to an embodiment of the present invention.

[0045] Figure 38 The figure shows a cross-section X1 of the nanodevice after the removal of the back contact occupant and the source / drain trenches according to an embodiment of the present invention.

[0046] Figure 39 The figure shows a cross-section X2 of the nanodevice after the removal of the back contact occupant and the source / drain trenches according to an embodiment of the present invention.

[0047] Figure 40 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after removing the back contact occupant and the source / drain trenches according to an embodiment of the present invention.

[0048] Figure 41 The figure shows a cross-section X1 of the nanodevice after the formation of the back contact and the back power distribution network according to an embodiment of the present invention.

[0049] Figure 42 The figure shows a cross-section X2 of the nanodevice after the formation of the back contact and the back power distribution network according to an embodiment of the present invention.

[0050] Figure 43 The figure illustrates a cross-section Y of a nanodevice in the source / drain region after the formation of the back contact and the back power distribution network, according to an embodiment of the present invention. Detailed Implementation

[0051] The following description, provided with reference to the accompanying drawings, is intended to aid in a full understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. It includes various specific details to aid understanding, but these details should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the invention. Furthermore, descriptions of well-known functions and structures may be omitted for clarity and brevity.

[0052] The terms and words used in the following description and claims are not limited to their literal meaning, but are merely intended to enable a clear and consistent understanding of the invention. Therefore, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the invention is for illustrative purposes only and is not intended to limit the invention as defined by the appended claims and their equivalents.

[0053] It should be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Thus, for example, unless the context clearly indicates otherwise, referring to “component surface” includes referring to one or more such surfaces.

[0054] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the embodiments disclosed herein are merely illustrative of the claimed structures and methods, which can be implemented in various forms. The invention can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Details of well-known features and techniques may be omitted in the specification to avoid unnecessarily obscuring the embodiments of the invention.

[0055] References to "an embodiment," "embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may exclude that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that, whether explicitly described or not, its influence on such feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0056] For the purposes described below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the disclosed structures and methods, as oriented as shown in the figures. The terms “cover,” “on top of,” “on top of,” “positioned on,” or “positioned on top” indicate that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intermediate elements, such as interface structures, may exist between the first and second elements. The term “direct contact” means that the first element (e.g., the first structure) and the second element (e.g., the second structure) are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0057] To avoid obscuring the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of various embodiments of the present invention.

[0058] Various embodiments of the invention are described herein with reference to the accompanying drawings. Alternative embodiments may be devised without departing from the scope of the invention. Note that various connections and positional relationships (e.g., above, below, adjacent, etc.) are illustrated between elements in the following description and drawings. Unless otherwise stated, these connections and / or positional relationships may be direct or indirect, and the invention is not intended to be limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, the description of forming layer "A" on layer "B" includes cases where one or more intermediate layers (e.g., layer "C") are located between layer "A" and layer "B," provided that the relevant characteristics and functions of layers "A" and "B" are substantially not altered by the intermediate layers.

[0059] The following definitions and abbreviations are used to interpret the claims and the specification. As used herein, the terms “comprising,” “including,” “containing,” “comprising,” “having,” “containing,” or any other variation thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0060] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" can be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" can be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0061] As used herein, the term "about" to modify the amount of an ingredient, component, or reactant of the present invention refers to a variation in numerical quantity that can occur, for example, through typical measurements used to prepare concentrations or solutions and liquid handling procedures. Furthermore, variations may occur due to unintentional errors in the measurement process, manufacturing differences, differences in origin, or the purity of the ingredients used to prepare the composition or carry out the method. The term "about" or "substantially" is intended to include the degree of error associated with a measurement of a specific amount based on equipment available at the time of filing of this application. For example, "about" may include a range of ±8%, or 5%, or 2% of a given value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0062] Various processes are used to form microchips that will be packaged into integrated circuits (ICs), and these fall into four main categories: film deposition, removal / etching, semiconductor doping, and patterning / photolithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP). Semiconductor doping alters electrical properties by doping (e.g., transistor sources and drains, typically by diffusion and / or ion implantation). These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing is used to activate the implanted dopant. Thin films of conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. Selective doping of different regions of a semiconductor substrate allows the conductivity of the substrate to be altered as a voltage is applied.

[0063] Reference will now be made in detail to embodiments of the invention, examples of which are shown in the accompanying drawings, wherein like reference numerals always denote like elements. The invention relates to forming nanosheet transistors on self-aligned back-side contacts. A plurality of first sacrificial components are formed in a first interlayer dielectric layer (back-side interlayer dielectric layer) located on a first substrate. A first dielectric layer is formed on top of the first interlayer dielectric layer and the plurality of first sacrificial components. A plurality of alternating layers (alternating sacrificial layers and channel layers, such as nanosheets) are formed on a second substrate, and a second dielectric layer is formed on top of the alternating layers. The invention utilizes two separate starting substrates to form initial components / layers individually on each respective starting substrate. The second substrate (e.g., a substrate with alternating layers) is flipped, and the second substrate is attached / bonded to the first dielectric layer located on the first substrate. The first dielectric layer and the second dielectric layer may comprise different dielectric materials or the same dielectric material. When the first dielectric layer and the second dielectric layer comprise the same dielectric material, a bonding seam is formed where the two dielectric layers connect to each other. The present invention has back contact occupants (i.e., a plurality of first sacrificial components) formed independently and separately from the alternating layers that will form nanosheet transistors.

[0064] Figure 1 The figure illustrates a top view of multiple devices, nanosheet transistors, or transistors according to embodiments of the present invention. Cross section X1 extends horizontally through the transistor of a nanodevice, nanostack, or one of the devices. Cross section X2 extends horizontally through the transistor of a nanodevice, nanostack, or one of the devices, wherein cross section X1 is parallel to cross section X2. Cross sections X1 and X2 extend perpendicular to the gate direction. Cross section Y is perpendicular to cross sections X1 and X2, wherein cross section Y passes through the source / drain regions spanning multiple nanostacks. Cross section Y is parallel to the gate direction.

[0065] Now for reference Figure 2 , Figure 3 ,as well as Figure 6 The figure illustrates the structure during an intermediate step of a method for fabricating a nanosheet transistor structure on a first substrate (substrate A) according to an embodiment of the present invention. Referring now to... Figure 4 , Figure 5 ,as well as Figure 6 The figure illustrates the structure during an intermediate step of a method for fabricating a nanosheet transistor structure on a first substrate (substrate B) according to an embodiment of the present invention. Figure 2 , Figure 3 ,as well as Figure 6 The figure illustrates the processing stages following the formation of multiple back-side contact berths in the back-side interlayer dielectric layer located on substrate A. Figure 2 , Figure 3 ,as well as Figure 6The figure illustrates a first substrate 105, a back interlayer dielectric layer 110, a first back contact occupant 112, a second back contact occupant 114, and a first dielectric layer 115. The first dielectric layer 115 includes a first dielectric material.

[0066] Figure 4 , Figure 5 ,as well as Figure 7 The diagram illustrates the processing stages following the formation of multiple alternating layers. Figure 4 , Figure 5 ,as well as Figure 7 The figure illustrates a second substrate 120, an etch stop layer 125, a third substrate 130, a plurality of alternating sacrificial layers 135, a channel layer 140, and a second dielectric layer 145. The second dielectric layer 145 comprises a second dielectric material, wherein the first dielectric material and the second dielectric material may be the same or different materials. For simplicity, the first dielectric layer 115 and the second dielectric layer 145 will be considered to comprise the same dielectric material. However, this is not intended to be limiting, and those skilled in the art will consider that these layers may comprise different dielectric materials.

[0067] The first substrate 105, the second substrate 120, and the third substrate 130 may be, for example, including but not limited to, materials such as silicon (Si), silicon-germanium (SiGe), carbon-doped silicon (Si:C), carbon-doped silicon-germanium (SiGe:C), III-V compound semiconductors, II-V compound semiconductors, or other similar semiconductors. In addition, multilayer semiconductor materials can be used as semiconductor materials for the first substrate 105, the second substrate 120, and the third substrate 130. In some embodiments, the first substrate 105, the second substrate 120, and the third substrate 130 include both semiconductor materials and dielectric materials. The semiconductor first substrate 105, the second substrate 120, and the third substrate 130 may also include organic semiconductors or layered semiconductors, such as silicon / silicon-germanium (Si / SiGe), silicon-on-insulator (Si-SiGe), or silicon-germanium-insulator (SiGe-on-insulator). Parts or all of the semiconductor first substrate 105, the second substrate 120, and the third substrate 130 may also include amorphous, polycrystalline, or single-crystal states. The first semiconductor substrate 105, the second substrate 120, and the third substrate 130 may be doped, undoped, or contain both doped and undoped regions.

[0068] The etch stop layer 125 may include, for example, epitaxial SiGe or SiO2, or another suitable material. Alternating layers include multiple channel layers 140 (e.g., Si nanosheets) and multiple sacrificial layers 135. The multiple sacrificial layers 135 may include SiGe, wherein Ge is in the range of approximately 15% to 35%. The multiple channel layers 140 may include, for example, Si.

[0069] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 ,as well as Figure 13 The figure illustrates the processing stage after flipping the substrate B to face / orient the second dielectric layer 145 toward the first dielectric layer 115. Figure 14 , Figure 15 Figures 1 and 16 illustrate the processing stages after substrate B is attached to substrate A and multiple layers are removed. After substrate B is flipped, it is then attached / bonded to substrate A. In the following text, substrate A and substrate B will not be referred to as separate substrates.

[0070] A second dielectric layer 145 located on substrate B is attached / bonded to a first dielectric layer 115 located on substrate A. When the dielectric layers comprise the same dielectric material, a bonding seam 150 is formed between the first dielectric layer 115 and the second dielectric layer 145. When the first dielectric layer 115 and the second dielectric layer 145 comprise different dielectric materials, two different dielectric layers are formed and / or a bonding seam 150 may be additionally formed. The second substrate 120, the etch stop layer 125, and the third substrate 130 are removed. A sacrificial layer 135 needs to be formed on the third substrate 130 to allow for the formation of alternating layers. The sacrificial layer 135 is removed to expose the top channel layer 140, which is closest to the channel layer 140 formed on the removed third substrate 130. During this processing stage, the first dielectric layer 115, the bonding seam 150, and the second dielectric layer 145 separate the alternating layer from the back interlayer dielectric layer 110 and the back contact occupants 112 and 114.

[0071] Figure 17 , Figure 18 ,as well as Figure 19 The figure illustrates the processing stages following the separation of the alternating layers into multiple columns and the formation of the dummy gate 155, hard mask 165, and upper spacer 160. Figure 19 The diagram illustrates how alternating layers are separated into multiple columns. Each column should be aligned / oriented on one of the back-contact occupies 112 and 114. Figure 19The figure illustrates a misalignment of alternating columns on back contact occupiers 112 and 114. Misalignment occurs when the alternating columns are not fully positioned above back contact occupiers 112 and 114. Figure 17 as well as Figure 18 A dummy gate 155 is formed on the top channel layer 140, and a hard mask 165 is formed on top of the dummy gate 155. The hard mask 165 and the dummy gate 155 are etched / patterned to form multiple columns. An upper spacer 160, or a gate spacer, is formed on the sidewall of each column of the dummy gate 155 and the hard mask 165.

[0072] Figure 20 , Figure 21 ,as well as Figure 22 The diagram illustrates the processing stages following the division of the alternating layers into multiple columns, the formation of internal spacers 167, and the removal of portions of the alternating layers to form the source / drain regions. The alternating layers are etched to form multiple columns or nano-stacks, and to form the source / drain regions. A sacrificial layer 135 is recessed rearward to form voids / empty spaces around the ends of the channel layer 140. These voids / empty spaces are filled with internal spacers 167. One region of the source / drain regions is aligned / located on a first back contact occupant 112, and another region of the source / drain regions is aligned / located on a second back contact occupant 114.

[0073] Figure 23 , Figure 24 ,as well as Figure 25 The diagram illustrates the processing stage following the etching of the first dielectric layer 115, the second dielectric layer 115, and the bonding seam 150 to expose the back contact berths 112 and 114. The second dielectric layer 145, the bonding seam 150, and the first dielectric layer 115 are etched in the source / drain regions to expose the top surfaces of the first back contact berths 112 and 114. If the etching process is not properly aligned, the top surface of the back interlayer dielectric layer 110 is exposed. The back interlayer dielectric layer 110 acts as an etch stop for the etching process to expose the first back contact berths 112 and 114.

[0074] Figure 26 , Figure 27 ,as well as Figure 28The diagram illustrates the processing stages following the formation of source / drain 170, source / drain 172, source / drain 177, and source / drain 179. The first source / drain 172 is epitaxially grown on the first back contact berth 112, and the second source / drain 170 is epitaxially grown in the source / drain region at the top of the second dielectric layer 145. The first source / drain 172 extends downward through the first dielectric layer 115, the second dielectric layer 145, and the bonding seam 150 to contact the front / top surface of the first back contact berth 112. The bottom surface of the first source / drain 172 is located lower than the bottom surface of the second source / drain 170. The third source / drain 179 is epitaxially grown on the second back contact berth 114, and the fourth source / drain 177 is epitaxially grown in the source / drain region at the top of the second dielectric layer 145. Figure 27 The figure shows a substrate spacer 175 located between the second back contact occupant 114 and the third source / drain 179. The bottom surface of the third source / drain 179 is located below the bottom surface of the fourth source / drain 177.

[0075] The first source / drain 172, the second source / drain 170, the third source / drain 179, and the fourth source / drain 177 can be, for example, n-type epitaxy or p-type epitaxy. For n-type epitaxy, an n-type dopant selected from a group of phosphorus (P), arsenic (As), and / or antimony (Sb) can be used. For p-type epitaxy, a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In), and / or thallium (Tl) can be used. Other doping techniques can be used, such as ion implantation, vapor phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, and / or any suitable combination of these techniques. In some embodiments, the dopant is activated by thermal annealing such as laser annealing, flash memory annealing, rapid thermal annealing (RTA), or any suitable combination of these techniques.

[0076] Figure 29 , Figure 30 ,as well as Figure 31 The diagram illustrates the processing stage following the formation of the front interlayer dielectric layer 180. The front interlayer dielectric layer 180 is formed on top of and around the source / drain 170, source / drain 172, source / drain 177, and source / drain 179. The front interlayer dielectric layer 180 is also formed on top of the second dielectric layer 145.

[0077] Figure 32 , Figure 33 ,as well as Figure 34The diagram illustrates the processing stages following the removal of the hard mask 165, dummy gate 155, and sacrificial layer 135, the formation of gate 185, increasing the height of the front interlayer dielectric layer 180, and the formation of front contacts 182 and 184. The hard mask 165 is removed, for example, by chemical mechanical planarization (CMP) to expose the dummy gate 155. The dummy gate 155 and sacrificial layer 135 are selectively removed to create empty spaces / voids for the formation of gate 185. Gate 185 is formed around channel layer 140 and extends over top channel layer 140 between segments of upper spacer 160. Gate 185 may include, for example, a gate dielectric liner (such as a high-k dielectric like HfO2, ZrO2, HfLaOx, etc.), a work function layer (such as TiN, TiAlC, TiC, etc.), and a conductive metal filler, such as tungsten (W).

[0078] An additional front-side interlayer dielectric 180 is deposited to extend the layer on top of the gate 185. Multiple trenches (not shown) are formed in the front-side interlayer dielectric layer 180. During the metallization process, the multiple trenches are filled with conductive metal to form front-side contacts 182 and 184. Front-side contacts 172 and 174 are located above and in contact with the second source / drain 170 and the fourth source / drain 177, respectively.

[0079] Figure 35 , Figure 36 ,as well as Figure 37 The figure illustrates the processing stages following the formation of the back-end process (BEOL) layer 190 and carrier wafer 195, the flipping of the nanodevices for back-side processing, and the removal of the first substrate 105. The BEOL layer 190 is formed on the front surface of the front interlayer dielectric layer 180 and on the front surfaces of front contacts 182 and 184. The carrier wafer 195 is attached to the BEOL layer 190, and the nanodevices are flipped for back-side processing. The first substrate 105 is removed to expose the back surface of the back interlayer dielectric layer 110, and the back surfaces of the first back contact occupant 112 and the second back contact occupant 114.

[0080] Figure 38 , Figure 39 as well as Figure 40The diagram illustrates the processing stage after trenching the back contact occupiers 112 and 114, and the source / drain electrodes 172 and 179. The first and second back contact occupiers 112 and 114 are removed. Removal of the first and second back contact occupiers 112 and 114 can expose the back surface of the first source / drain electrode 172 or the back surface of the substrate spacer 175. Trenching the back surface of the first source / drain electrode 172 creates indentations / pits in the source / drain, thereby increasing the exposed surface area of ​​the first source / drain electrode 172. The indentations / pits can extend below, equal to, or above the height of the bonding seam 150. Trenching the third source / drain electrode 179 removes the substrate spacer 179. The first dielectric layer 115, bonding seam 150, and second dielectric layer 145 prevent one of the adjacent gates 185 from being exposed by trenching. The removal of the first back contact occupier 112 and the trenching of the first source / drain 172 create a first back contact trench 200. The removal of the second back contact occupier 114 and the trenching of the third source / drain 179 create a second back contact trench 205. The first dielectric layer 115, the bonding seam 150, and the second dielectric layer 145 serve as separation layers between the first back contact trench 200 and the second back contact trench 205 and the adjacent gate 185, respectively.

[0081] Figure 41 , Figure 42 ,as well as Figure 43The illustration shows the processing stages after the formation of back contact 210, back contact 215, and back power distribution network 229. First back contact trench 200 and second back contact trench 205 are filled with conductive metal to form the first back contact 210 and second back contact 215. The first back contact trench 200 and second back contact trench 205 can contact the first dielectric layer 115. The first back contact trench 200 and second back contact trench 205 can also contact the bonding seam 150 and / or the second dielectric layer 145 depending on the trench depth of the first source / drain 172 and the third source / drain 179. Back power distribution network (BSPDN) 220 is formed on top of the back interlayer dielectric layer 110 and on top of the first back contact 210 and second back contact 215. The second dielectric layer 145, bonding seam 150, and first dielectric layer 115 form multiple isolation layers that separate the nanosheet transistor from the back contact 210, back contact 215, and BSPDN 220. The first source / drain 172 and the third source / drain 179 extend through the multiple isolation layers to connect to the back contact 210 and back contact 215, respectively. This ensures that the second dielectric layer 145, bonding seam 150, and first dielectric layer 115 are in contact with the sidewalls of the first source / drain 172 and the third source / drain 179.

[0082] Although the invention has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0083] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of one or more embodiments, their practical application in the market, or technical improvements, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A microelectronic device, comprising: a nanosheet transistor including a first source / drain and a second source / drain; a front side contact connected to the first source / drain and a back side contact connected to the second source / drain; and a plurality of isolation layers located beneath the nanosheet transistor, wherein the second source / drain extends through the plurality of isolation layers to connect with the back side contact.

2. The microelectronic device of claim 1, wherein one of the plurality of isolation layers is in direct contact with a back surface of the first source / drain.

3. The microelectronic device of any of the preceding claims, wherein a back surface of the first source / drain and a back surface of the second source / drain are located at different heights.

4. The microelectronic device of any of the preceding claims, wherein the plurality of isolation layers includes at least a first dielectric layer and a second dielectric layer.

5. The microelectronic device of claim 4, wherein the first dielectric layer and the second dielectric layer include the same dielectric material.

6. The microelectronic device of any of claims 4-5, further comprising a bond seam located between the first dielectric layer and the second dielectric layer.

7. The microelectronic device of any of claims 4-6, wherein the first dielectric layer is in contact with a back surface of the first source / drain, and wherein the first dielectric layer is in contact with a sidewall of the second source / drain.

8. The microelectronic device of any of claims 4-7, wherein the back side contact is in contact with the second dielectric layer.

9. The microelectronic device of any of claims 4 or 6-8, wherein the first dielectric layer and the second dielectric layer include different dielectric materials.

10. A microelectronic device, comprising: a nanosheet transistor including a first source / drain and a second source / drain; a front side contact connected to the first source / drain and a back side contact connected to the second source / drain; a plurality of isolation layers located beneath the nanosheet transistor, wherein the second source / drain extends through the plurality of isolation layers to connect with the back side contact, wherein the back side contact extends into the plurality of isolation layers to connect with the second source / drain.

11. The microelectronic device of claim 10, wherein one of the plurality of isolation layers is in direct contact with the back surface of the first source / drain.

12. The microelectronic device of any of claims 10-11, wherein a back surface of the first source / drain and a back surface of the second source / drain are located at different heights.

13. The microelectronic device of any of claims 10-12, wherein the plurality of isolation layers includes at least a first dielectric layer and a second dielectric layer. ​ 14. The microelectronic device of claim 13, wherein the first dielectric layer and the second dielectric layer comprise the same dielectric material.

15. The microelectronic device of any one of claims 13-14, further comprising a bond seam between the first dielectric layer and the second dielectric layer.

16. The microelectronic device of any one of claims 13-15, wherein the first dielectric layer is in contact with a backside surface of the first source / drain, and wherein the first dielectric layer is in contact with a sidewall of the second source / drain.

17. The microelectronic device of any one of claims 13-16, wherein the backside contact is in contact with the second dielectric layer.

18. The microelectronic device of any one of claims 13 or 15-17, wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials.

19. A method comprising: forming a backside ILD layer on a first substrate; forming at least one backside contact placeholder in the backside ILD layer; forming a first dielectric layer on top of the backside ILD layer and on top of the at least one backside contact placeholder; forming a plurality of alternating layers on a second substrate, the plurality of alternating layers comprising channel layers and sacrificial layers; forming a second dielectric layer on top of the alternating layers; flipping the second substrate and attaching the second dielectric layer to the first dielectric layer; and forming a nanosheet transistor from the alternating layers.

20. The method of claim 19, further comprising: forming a bond seam between the first dielectric layer and the second dielectric layer. ​

Images