Fork-shaped sheet device

Abstract

A semiconductor structure includes a dielectric strip disposed between a first source drain region and a second source drain region and physically separating the first source drain region from the second source drain region; a first silicide liner (160) located directly below the first source drain region; and a second silicide liner located directly below the second source drain region, where the first silicide liner is a different material than the second silicide liner.

Description

Background Technology

[0001] This invention generally relates to semiconductor structures, and more specifically to a fork-shaped wafer device structure having dual back-side silicides and a close N2P spacing.

[0002] Complementary metal-oxide-semiconductor (CMOS) technology is commonly used for field-effect transistors (FETs) that are part of advanced integrated circuits (hereinafter referred to as "ICs"), such as central processing units (hereinafter referred to as "CPUs"), memories, storage devices, etc. As the demand for miniaturizing transistor devices continues, nanosheet FETs help achieve reduced FET device footprints while maintaining FET device performance. A nanosheet FET comprises multiple stacked nanosheets extending between pairs of source and drain epitaxial regions. The device can be a gate ring device or a transistor in which the gate surrounds a portion of the nanosheet channel. The nanosheet device contains one or more layers of semiconductor channel material portions having a vertical thickness substantially smaller than its width. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include: a dielectric strip disposed between a first source-drain region and a second source-drain region, physically separating the first source-drain region and the second source-drain region; a first silicide liner located directly below the first source-drain region; and a second silicide liner located directly below the second source-drain region, wherein the first silicide liner is made of a different material than the second silicide liner.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include: a first nanosheet device including a first source-drain region; a second nanosheet device including a second source-drain region; a dielectric strip disposed between each source-drain region in the first source-drain region and each source-drain region in the second source-drain region, and physically separating each source-drain region in the first source-drain region from each source-drain region in the second source-drain region; a first silicide liner located directly below the first source-drain region; and a second silicide liner located directly below the second source-drain region, wherein the first silicide liner is a different material from the second silicide liner.

[0005] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include: an n-type nanosheet device including n-type source / drain regions; a p-type nanosheet device including p-type source / drain regions; a dielectric strip disposed between each n-type source / drain region in the n-type source / drain regions, and physically separating each n-type source / drain region in the n-type source / drain regions from each p-type source / drain region in the p-type source / drain regions; a first silicide liner located directly below the first source / drain regions; and a second silicide liner located directly below the second source / drain regions, wherein the first silicide liner is a different material from the second silicide liner. Attached Figure Description

[0006] The following detailed description will be best understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the invention thereto, wherein: Figure 1 , Figure 2 ,as well as Figure 3 This is a cross-sectional view of a semiconductor structure during an intermediate step of a method for manufacturing a fork-shaped thin-film device structure, according to an exemplary embodiment. Figure 4 , Figure 5 ,as well as Figure 6 This is a cross-sectional view of a semiconductor structure after the formation of the first hard mask, according to an exemplary embodiment; Figure 7 , Figure 8 ,as well as Figure 9 This is a cross-sectional view of a semiconductor structure after the formation of sidewall spacers and patterned nanosheet layers and a substrate, according to an exemplary embodiment. Figure 10 , Figure 11 ,as well as Figure 12 This is a cross-sectional view of a semiconductor structure after the dielectric strip has been formed, according to an exemplary embodiment. Figure 13 , Figure 14 ,as well as Figure 15 This is a cross-sectional view of a semiconductor structure after the shallow trench isolation region has been formed, according to an exemplary embodiment. Figure 16 , Figure 17 ,as well as Figure 18 This is a cross-sectional view of a semiconductor structure after forming and patterning the sacrificial gate dielectric and the sacrificial gate, forming the gate spacer, removing a portion of the nanosheet stack, and forming the inner spacer, according to an exemplary embodiment. Figure 19 , Figure 20 ,as well as Figure 21This is a cross-sectional view of a semiconductor structure after the formation of a sacrificial liner, the formation of a patterned mask, and the selective removal of portions of the sacrificial liner relative to the patterned mask, according to an exemplary embodiment. Figure 22 , Figure 23 ,as well as Figure 24 This is a cross-sectional view of a semiconductor structure after the formation of the sacrificial occupant, according to an exemplary embodiment; Figure 25 , Figure 26 ,as well as Figure 27 This is a cross-sectional view of a semiconductor structure after the sacrificial liner has been removed and a first source-drain region, a second source-drain region, and a dielectric layer have been formed, according to an exemplary embodiment. Figure 28 , Figure 29 ,as well as Figure 30 It is a cross-sectional view of a semiconductor structure after the formation of the gate structure, source and drain contacts, mid-process and back-process, and attachment carrier wafer, according to an exemplary embodiment. Figure 31 , Figure 32 ,as well as Figure 33 This is a cross-sectional view of a semiconductor structure after the component is flipped and the substrate is recessed, according to an exemplary embodiment. Figure 34 , Figure 35 ,as well as Figure 36 This is a cross-sectional view of the semiconductor structure after the remaining portion of the substrate has been removed, according to an exemplary embodiment. Figure 37 , Figure 38 ,as well as Figure 39 This is a cross-sectional view of a semiconductor structure after the formation of the back-side dielectric layer, according to an exemplary embodiment. Figure 40 , Figure 41 ,as well as Figure 42 This is a cross-sectional view of a semiconductor structure after the formation of the first back-side mask, according to an exemplary embodiment. Figure 43 , Figure 44 ,as well as Figure 45 This is a cross-sectional view of a semiconductor structure after the first portion of the sacrificial occupant has been removed to form a first back-side trench, according to an exemplary embodiment. Figure 46 , Figure 47 ,as well as Figure 48 This is a cross-sectional view of a semiconductor structure after the first back-side mask has been removed and shallow ion implantation has been performed, according to an exemplary embodiment. Figure 49 , Figure 50 ,as well as Figure 51 This is a cross-sectional view of a semiconductor structure after the formation of a first silicide liner, a first adhesive liner, and a first sacrificial filler, according to an exemplary embodiment. Figure 52 , Figure 53 ,as well as Figure 54 This is a cross-sectional view of a semiconductor structure after the removal of the second portion of the sacrificial occupant to form a second back-side trench and the performance of another shallow ion implantation, according to an exemplary embodiment. Figure 55 , Figure 56 ,as well as Figure 57 This is a cross-sectional view of a semiconductor structure after the formation of the second silicide liner, the second adhesive liner, and the second sacrificial filler, according to an exemplary embodiment; and Figure 58 , Figure 59 ,as well as Figure 60 This is a cross-sectional view of a semiconductor structure after the removal of the first and second sacrificial fillers, the formation of back-side source-drain contacts, and the formation of a back-side wiring layer, according to an exemplary embodiment.

[0007] The accompanying drawings are not necessarily to scale. They are merely schematic representations and not intended to depict specific parameters of the invention. For clarity and ease of explanation, the scale of elements may be exaggerated. The drawings are intended to depict only typical embodiments of the invention. In the drawings, the same reference numerals denote the same elements. Detailed Implementation

[0008] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which can be implemented in various forms. The invention can be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0009] References to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in the specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art, whether or not it is explicitly described.

[0010] For the purposes of the description below, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall apply to the disclosed structures and methods, as oriented as in the accompanying drawings. It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “above” another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly on” or “directly above” another element, there are no intermediate elements. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intermediate elements. Furthermore, the term “pre-lithography” may refer to a size or dimension smaller than the current size achievable through a photolithography process, and the term “photolithography” may refer to a size or dimension equal to or larger than the current size achievable through a photolithography process. Pre-lithography dimensions and photolithography dimensions can be determined by those skilled in the art at the time of filing the application.

[0011] The terms substantially, substantially similar, approximately, or any other terms indicating functional equivalence refer to situations where differences in length, height, or orientation do not convey the actual difference between a substantially similar variation and an explicit statement (e.g., a phrase without substantially similar terms). In one embodiment, substantial (and its derivative) refers to a generally accepted difference in engineering or manufacturing tolerances for similar devices, up to, for example, a deviation of 10% in value or 10° in angle.

[0012] To avoid obscuring the presentation of embodiments of the invention, some processing steps or operations known in the art may be combined for presentation and illustrative purposes in the following detailed description, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of various embodiments of the invention.

[0013] As semiconductor device dimensions continue to shrink, there is a growing desire to provide the closest possible distance (i.e., the “N2P spacing”) between the active regions of the nFET and pFET at approximately 8 nanometers (nm) to approximately 10 nm. Providing an N2P spacing at these dimensions can pose challenges for communication with the pFET and nFET portions. Specifically, the N2P spacing reduces the process window in such a sequence that the contact structures connecting the nFET and pFET portions may be electrically shorted to each other. While the process window can be widened by positioning the contact structures laterally offset from the N2P spacing, doing so increases the resistance between the contact structures and the corresponding pFET and nFET portions, thus negating any improvements in the process window and / or electrical characteristics of the multilayer IC device.

[0014] The continued trend towards reducing the footprint of FET devices has led to the development of bifurcated nanosheet semiconductor devices, also known as "fork-shaped wafer devices." Fork-shaped wafer devices realize nanosheets controlled by a tri-gate fork-shaped structure. This tri-gate fork-shaped structure is achieved by forming a dielectric strip or dielectric wall between the P-type and N-type devices. The dielectric strip physically isolates two adjacent devices from each other, allowing for a tighter N2P spacing, which facilitates better area and performance scalability compared to conventional nanosheet devices. However, the scalability achieved through fork-shaped wafer devices and the introduction of dielectric strips makes it difficult to maximize the source / drain contact area.

[0015] This invention generally relates to semiconductor structures, and more specifically, to a fork-shaped wafer device structure having dual back-side silicides and a tight N2P spacing. More specifically, the fork-shaped wafer device structure and associated methods disclosed herein enable a novel solution for providing dual back-side silicides at a very tight N2P spacing without patterning problems or contact short circuits. The following references... Figures 1 to 60 The accompanying drawings are provided to describe in detail exemplary embodiments of a fork-shaped wafer device structure having dual back-side silicides and close N2P spacing. It will be readily understood by those skilled in the art that the detailed description given herein with respect to these drawings is for illustrative purposes, as the invention extends beyond these limited embodiments.

[0016] Now for reference Figure 1 , Figure 2 ,as well as Figure 3 This illustrates a structure 100 during an intermediate step in a method for manufacturing a fork-shaped thin-film device structure according to an embodiment of the present invention. Figure 1 Depicting Figure 2 and Figure 3 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 2 Depicting Figure 1The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 3 Depicting Figure 1 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0017] Figures 1 to 3 The structure 100 shown includes a nanosheet layer 102 formed on a substrate 104. The nanosheet layer 102 includes an alternating series of silicon-germanium (SiGe) sacrificial nanosheets 106 (hereinafter referred to as "sacrificial nanosheets 106") and silicon (Si) channel nanosheets 108 (hereinafter referred to as "channel nanosheets 108"), as illustrated. Although only a limited number of nanosheet layers (102) are shown, one or more additional nanosheet layers and / or nanosheets may optionally be epitaxially grown in an alternating manner, and any additional nanosheets have the same properties as the corresponding nanosheets described herein.

[0018] In one or more embodiments, the nanosheet layer 102 is formed by epitaxially growing one layer at a time until the desired number and thickness of each layer are achieved. The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. The epitaxial silicon, silicon-germanium, and / or silicon-doped carbon (Si:C) can be undoped or can be doped during deposition by adding a dopant, an n-type dopant (e.g., phosphorus or arsenic), or a p-type dopant (e.g., boron or gallium) (in-situ doping), depending on the type of transistor. For example, the channel nanosheet 108 of the nanosheet layer 102 can be doped, undoped, or a combination thereof.

[0019] The terms "epitaxygrowth and / or deposition" and "epitaxygrowth formation and / or growth" refer to the growth of a semiconductor material (crystal material) on a deposition surface of another semiconductor material (crystal material), wherein the grown semiconductor material (crystal capping layer) has substantially the same crystal properties as the semiconductor material (seed material) deposited on the deposition surface. During epitaxial deposition, chemical reactants supplied by a source gas are controlled, and system parameters are set such that the deposited atoms have sufficient energy to reach the deposition surface to move back and forth on it, causing the deposited atoms to orient themselves toward a crystal arrangement of atoms on the deposition surface. Therefore, the epitaxially grown semiconductor material has substantially the same crystal properties as the deposition surface on which the epitaxial growth material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} oriented crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on semiconductor surfaces and typically does not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0020] In some embodiments, the gas source for depositing epitaxial semiconductor materials includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of: silane, diethylsilane, propane, tetrasilane, hexachlorodiethylsilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldiethylsilane, hexamethyldiethylsilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of: germanane, diethylgermanane, halogermanane, dichlorogermanane, trichlorogermanane, tetrachlorogermanane, and combinations thereof. Combinations of these gas sources can also be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0021] Substrate 104 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, wherein etch stop layer 110 separates the bottom substrate 112 from the top semiconductor layer 114. Unlike conventional layered semiconductor substrates, the etch stop layer 110 of substrate 104 may include any material that affects the desired etch selectivity during subsequent processing. For example, etch stop layer 110 may be a conventional buried oxide layer, or it may be a silicon-germanium layer with a specific germanium concentration. In practice, etch stop layer 110 will serve as an etch stop layer and may be composed of any material that supports this function.

[0022] In this embodiment, both the bottom substrate 112 and the top semiconductor layer 114 can be any bulk substrate made of any of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound semiconductor materials (e.g., III-V and II-VI). For example, both the bottom substrate 112 and the top semiconductor layer 114 can be made of silicon. Additionally, the etch stop layer 110 and the substrate 112 are sacrificial and will not be retained in the final structure.

[0023] Now for reference Figure 4 , Figure 5 ,as well as Figure 6 It shows the structure 100 after the formation of the first hard mask 116 according to an embodiment of the present invention. Figure 4 Depicting Figure 5 and Figure 6 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 5 Depicting Figure 4 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 6 Depicting Figure 4 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0024] The first hard mask 116 is formed according to known techniques. Specifically, for example, the first hard mask 116 can be formed by first depositing a hard mask material (e.g., silicon nitride) onto the uppermost layer of the nanosheet 102 using, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any suitable technique for dielectric deposition that does not cause physical or chemical changes to the uppermost layer of the nanosheet 102. The hard mask material is then patterned into multiple hard masks 116 or alternatively into individual masks. The patterned hard mask material is proportionate to the desired area and location occupied by the fork-shaped thin-film device structure.

[0025] Now for reference Figure 7 , Figure 8 ,as well as Figure 9 It shows a structure 100 after the formation of sidewall spacers 118 and patterned nanosheet layers 102 and substrate 104 according to an embodiment of the present invention. Figure 7 Depicting Figure 8 and Figure 9 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 8 Depicting Figure 7 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 9 Depicting Figure 7 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0026] First, a dielectric material layer can be conformally deposited on top of structure 100. Specifically, the dielectric material layer can be deposited directly on the exposed surfaces of hard mask 116 and nanosheet layer 102. In one embodiment, the dielectric material layer may include, for example, silicon nitride or silicon oxide, or SiOCN, SiC, TiOx, AlOx, etc. In some cases, preferably, the sidewall spacers 118 are fabricated from a material having an etch rate substantially different from that of the surrounding material to achieve good etch selectivity. In one embodiment, the dielectric material layer may preferably comprise an oxide, such as silicon oxide. The dielectric material layer can be deposited using conformal deposition techniques, such as any known atomic layer deposition technique, molecular layer deposition technique, or other known conformal deposition technique. In one embodiment, the dielectric material layer may have a substantially conformal and uniform thickness ranging from about 5 nm to about 20 nm and in between.

[0027] Next, a portion of the dielectric material layer can be removed from the horizontal surface of structure 100 using a directional anisotropic etching technique, leaving it on the sidewalls of the first hard mask 116. For example, reactive etching can be used to remove portions of the dielectric material layer directly above the nanosheet layer 102 and from the top surface of the first hard mask 116. The remaining portions of the dielectric material layer along the opposing sidewalls of the first hard mask 116 form sidewall spacers 118. Furthermore, both the first hard mask 116 and the sidewall spacers 118 should each include material that will allow the first hard mask 116 to be selectively removed subsequently relative to the sidewall spacers 118. It should also be noted here that the sidewall spacers 118 depicted in the figures are for illustrative purposes and may generally have a slightly different shape than those shown. For example, the sidewall spacers 118 may have rounded corners, which can be naturally formed during the directional etching process, as is known in the art.

[0028] The sidewall spacer 118 may have a lateral width that is substantially equal to the conformal thickness of the dielectric material layer described above. In embodiments, the lateral width of the sidewall spacer 118 may preferably be sub-lithographic, or smaller than the minimum lithographic size. The term "sub-lithographic" may refer to a size or size smaller than the current size achievable through a lithographic process, and the terms "lithography" or "minimum lithographic size" may refer to a size or size equal to or greater than the current size achievable through a lithographic process. Sub-lithographic size and lithographic size can be determined by those skilled in the art at the time of filing. While "minimum lithographic size" and "sub-lithographic size" are defined only relative to lithography tools and generally change with each generation of semiconductor technology, it is understood that minimum lithography size and sub-lithographic size are defined relative to the best performance of the lithography tools available in semiconductor manufacturing. By 2015, the minimum lithographic size was approximately 20 nm and is expected to shrink in the future. In embodiments, for example, the sidewall spacer 118 may have a lateral width ranging from about 5 nm to about 15 nm, and in between. It is possible to adjust the spacer width based on etching deviations or material loss during the process to meet the final technical target size. The sidewall spacer 118 defines a “fin pattern” or active region, which can then be transferred to the underlying layers, including the nanosheet layer 102 and the substrate 104. The first hard mask 116 and the sidewall spacer 118, along with the associated process, enable the formation of two nanosheet stacks 120 with small N2P spacing 122, instead of utilizing typical photolithography techniques. According to embodiments of the invention, the N2P spacing 122 is less than about 10 nm.

[0029] Now for reference Figure 10 , Figure 11 ,as well as Figure 12It shows the structure 100 after the formation of the dielectric strip 124 according to an embodiment of the present invention. Figure 10 Depicting Figure 11 and Figure 12 The cross-sectional view of structure 100 along line XX shown is as follows. Figure 11 Depicting Figure 10 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 12 Depicting Figure 10 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0030] According to known techniques and as shown, dielectric strips 124 are formed. Dielectric strips 124 are formed within N2P spacers 122 between adjacent nanosheet stacks 120. Specifically, dielectric material is first deposited to substantially fill the N2P spacers 122. Then, isotropic etch-back is used to selectively etch the dielectric material to cause it to recess below the top surfaces of the hard mask 116 and sidewall spacers 118, as shown.

[0031] Now for reference Figure 13 , Figure 14 ,as well as Figure 15 It shows the structure 100 after the shallow trench isolation region 126 is formed according to an embodiment of the present invention. Figure 13 Depicting Figure 14 and Figure 15 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 14 Depicting Figure 13 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 15 Depicting Figure 13 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0032] Shallow trench isolation region 126 (hereinafter referred to as "STI region 126") is formed according to known techniques. STI region 126 is formed at the bottom of a trench in substrate 104 formed during the patterning of nanosheet layer 102. Specifically, according to known techniques, a dielectric material is deposited at the bottom of the trench in substrate 104 to isolate adjacent devices from each other. STI region 126 can be formed of any suitable dielectric material, including, for example, silicon oxide (SiO2). x ) or silicon nitride (Si x N y ).

[0033] Now for reference Figure 16 , Figure 17 ,as well as Figure 18It shows a structure 100 after the formation and patterning of the sacrificial gate dielectric (not shown) and the sacrificial gate 128 according to an embodiment of the present invention. Figure 16 Depicting Figure 16 and Figure 18 The cross-sectional view taken along line XX of structure 100 shown. Figure 17 Depicting Figure 16 The cross-sectional view of structure 100 shown along line Y1-Y1, and Figure 18 Depicting Figure 16 The cross-sectional view of structure 100 along line Y2-Y2 shown.

[0034] According to known techniques, the sacrificial gate dielectric is deposited directly on the exposed surface of structure 100. Specifically, for example, a relatively thin silicon oxide layer (SiO2) is first conformally deposited on and around the nanosheet stack 120, as shown.

[0035] According to known techniques, the sacrificial gate 128 is blanket-deposited on and around the nanosheet stack 120. Specifically, for example, as shown, a relatively thick layer of amorphous silicon is blanket-deposited directly on the sacrificial gate dielectric. In this way, the sacrificial gate dielectric and the sacrificial gate 128 completely cover the nanosheet stack 120, as shown.

[0036] As used herein, “conformal” refers to a material layer having a continuous or substantially continuous thickness. For example, continuous thickness typically means that the first thickness measured from the bottom surface to the top surface is the same as the second thickness measured from the inner sidewall surface to the outer sidewall surface.

[0037] Next, a gate hard mask 130 (gate mask 130) is formed on structure 100. The gate mask 130 defines the gate region of each device. According to an exemplary embodiment, a selected mask material is deposited on the sacrificial gate 128 and then patterned into a plurality of corresponding gate masks 130. The pattern generated by the respective gate masks 130 is then transferred to the sacrificial gate dielectric and the sacrificial gate 128. Specifically, as shown, portions of the sacrificial gate dielectric and the sacrificial gate 128 are selectively etched or removed relative to the gate mask 130. A silicon RIE process can be used to remove portions of the sacrificial gate dielectric and the sacrificial gate 128.

[0038] Continue to refer to Figure 16 , Figure 17 ,as well as Figure 18The figure shows a structure 100 after the formation of gate spacer 132 according to an embodiment of the invention. Next, according to known techniques, spacer material is conformally deposited directly onto the exposed surface of structure 100. Specifically, for example, a relatively thin silicon nitride layer is conformally deposited, and then portions of the spacer material are selectively removed or etched from the horizontal surface according to known techniques. Doing so typically exposes portions of the nanosheet stack 120, substrate 104, and STI region 126, as shown. The remaining portion of the spacer material forms the gate spacer shown in the figures. In some embodiments, for example, gate spacer 132 may be composed of a combination of SiN, SiBCN, SiOCN, SiOC, or any other low-k material. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0.

[0039] Continue to refer to Figure 16 , Figure 17 ,as well as Figure 18 This illustrates a structure 100 after partial removal of the nanosheet stack 120 according to an embodiment of the invention. According to known techniques, partial removal of the nanosheet stack 120 is achieved by etching between the sacrificial gates 128. Specifically, the pattern created by the gate mask 130 and the gate spacers 132 is transferred into the nanosheet stack 120. In doing so, as shown, portions of the sacrificial nanosheets 106 and the channel nanosheets 108 are selectively removed relative to the gate mask 130 and the gate spacers 132.

[0040] In one embodiment, anisotropic etching (e.g., reactive ion etching) is used to remove portions of the nanosheet stack 120. Doing so may require a series of multiple etching steps using different etching chemicals, as is known in the art. The etching is designed to define source and drain regions and expose the ends of the individual nanosheet layers. In all cases, etching continues until the substrate 104 is exposed, as illustrated.

[0041] Continue to refer to Figure 16 , Figure 17 ,as well as Figure 18 This illustrates the structure 100 after the formation of the internal spacers 134 according to an embodiment of the invention. First, the sacrificial nanosheets 106 are laterally recessed to create spaces for the internal spacers 134. In one or more embodiments, the sacrificial nanosheets 106 are laterally recessed using an isotropic etching process with hydrogen chloride (HCl) gas, which etches silicon-germanium without etching silicon. In other embodiments, the sacrificial nanosheets 106 are laterally recessed using a ClF3 etching process. The cavities (not shown) are formed by the spacers occupied by portions removed from the sacrificial nanosheets 106.

[0042] Internal spacers 134 are formed by first conformally depositing spacer material on structure 100 to fill the cavities created by the laterally recessed sacrificial nanosheets 106. The conformal spacer material is then isotropically etched to remove all portions except those retained in the cavities, forming the internal spacers 134. In one or more embodiments, the internal spacers 134 are made of a nitride-containing material, such as silicon nitride (SiN). Although Figure 16 The internal spacers 134 shown are formed from a nitride-containing material, but they can be formed from any material that is not highly selective in subsequent device fabrication operations. Selectivity, as used herein, refers to the tendency of a process operation to affect a particular material. An example of low selectivity is a relatively slow etch rate. An example of higher or greater selectivity is a relatively faster etch rate. For the described embodiment, the material for the internal spacers 134 can be selected based on the selectivity of subsequent device fabrication operations for the selected material being below a predetermined threshold.

[0043] The internal spacer 134 is positioned such that the subsequent etching process used to remove the sacrificial nanosheet 106 during device fabrication does not erode the subsequently formed source and drain regions.

[0044] Now for reference Figure 19 , Figure 20 ,as well as Figure 21 It shows a structure 100 after forming a sacrificial liner 135, forming a patterned mask 136, and selectively removing portions of the sacrificial liner 135 relative to the patterned mask 136, according to an embodiment of the invention. Figure 19 Depicting Figure 20 and Figure 21 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 20 Depicting Figure 19 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 21 Depicting Figure 19 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0045] First, according to known techniques, the sacrificial liner 135 is conformally deposited directly on the exposed surface of the structure 100. Specifically, for example, a relatively thin silicon nitride (SiN) layer is conformally deposited on and around the nanosheet stack 120, the sacrificial gate 128, and the gate spacer 132, as shown.

[0046] Next, a patterned mask 136 is deposited and then patterned according to known techniques to expose certain portions of structure 100. Specifically, portions of the sacrificial liner 135 are exposed in areas designated for back-side source-drain contacts, such as... Figure 19 and 21 As shown in the figure.

[0047] The patterned mask 136 may be an organic planarization layer (OPL) or a material layer that can be planarized or etched using known techniques. In an embodiment, for example, the patterned mask 136 may be an amorphous carbon layer capable of withstanding the temperatures of subsequent processing. The patterned mask 136 may preferably have a thickness sufficient to cover an existing structure. After depositing the patterned mask 136, a dry etching technique is applied to pattern the mask 136 according to known techniques.

[0048] Next, portions of the sacrificial liner 135 in the region designated for back-side source-drain contacts are removed according to known techniques. Specifically, the exposed portions of the sacrificial liner 135 are removed using known etching techniques suitable for selectively removing silicon nitride relative to the surrounding material. In an embodiment, anisotropic etching (e.g., reactive ion etching) is used to remove portions of the sacrificial liner 135. In doing so, as... Figure 21 As shown, the exposed portion of the dielectric strip 124 can be etched, and ultimately recessed or lowered during the etching of the sacrificial liner 135.

[0049] Finally, etching continues into the substrate 104. Specifically, according to known techniques and as shown, the exposed portion of the top semiconductor layer 114 is removed. This forms the back-side contact trench 138.

[0050] Now for reference Figure 22 , Figure 23 ,as well as Figure 24 It shows the structure 100 after the formation of the sacrificial occupant 140 according to an embodiment of the present invention. Figure 22 Depicting Figure 23 and Figure 24 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 23 Depicting Figure 22 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 24 Depicting Figure 22 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0051] According to known techniques, a sacrificial occupant material is used to fill the back-side contact trench 138. Then, the sacrificial occupant material is recessed according to known techniques to form a sacrificial occupant 140. In embodiments, the sacrificial occupant material is SiC or SiOC, which is deposited using, for example, chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD) and subsequently recessed using, for example, reactive ion etching (RIE). Other suitable deposition and recessing techniques can be used, as long as they do not cause physical or chemical changes to the channel nanosheet 108. Finally, the sacrificial occupant 140 may also be referred to as a dielectric sacrificial occupant 140 or dielectric occupant 140. Finally, the remaining portion of the patterned mask 136 is removed according to known techniques (e.g., by ashing).

[0052] Now for reference Figure 25 , Figure 26 ,as well as Figure 27 It shows the structure 100 after the removal of the sacrificial liner 135 according to an embodiment of the present invention. Figure 25 Depicting Figure 26 and Figure 27 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 26 Depicting Figure 25 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 27 Depicting Figure 25 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0053] First, the remaining portion of the sacrificial liner 135 is removed according to known techniques. Specifically, the remaining portion of the second sacrificial liner 135 is removed using a known etching technique suitable for selectively removing silicon nitride relative to the surrounding material. In an embodiment, anisotropic etching (e.g., reactive ion etching) is used to remove the remaining portion of the sacrificial liner 135.

[0054] Continue to refer to Figure 25 , Figure 26 ,as well as Figure 27 It shows a structure 100 after the formation of the first source-drain region 142a and the second source-drain region 142b according to an embodiment of the present invention.

[0055] According to known techniques, source-drain regions 142a and 142b are formed on the exposed ends of the channel nanosheet 106 using an epitaxial layer growth process. Typically, in-situ doping is used to dope the source-drain regions 142a and 142b to create the necessary junctions for the semiconductor device. In fact, all semiconductor transistors are based on junction formation. Depending on the applied bias voltage, a junction can both block and allow current to flow. Junctions are typically formed by placing two semiconductor regions of opposite polarities in contact with each other. The most common junction is the pn junction, which consists of a contact between a hole-rich P-type silicon wafer and an electron-rich N-type silicon wafer. N-type and P-type devices are formed by selecting the regions of the device to form the necessary junctions using different types of dopants. For example, N-type devices can be formed by doping with arsenic (As) or phosphorus (P), and p-type devices can be formed by doping with boron (B).

[0056] According to an embodiment of the present invention, the first source-drain region 142a (on one side of the dielectric strip 124) is of a first type, such as P-type, and the second source-drain region 142b (on the opposite side of the dielectric strip 124) is of a second type, such as N-type. Figure 27 As shown in the figure.

[0057] Continue to refer to Figure 25 , Figure 26 ,as well as Figure 27 This illustrates a structure 100 after the formation of dielectric layer 144 according to an embodiment of the invention. According to known techniques, dielectric layer 144 is formed by blanket deposition of interlayer dielectric material on structure 100. Specifically, as shown, dielectric layer 144 is formed on source / drain regions 142a and 142b and substantially fills the remaining gaps between adjacent nanosheet stacks 120.

[0058] The dielectric layer 144 may be composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-coated low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. In another embodiment, a self-planarizing material such as spin-coated glass (SOG) or such as SiLK may be used. TM Spin-coated low-k dielectric material can be used as dielectric layer 144. Using a self-planarizing dielectric material as dielectric layer 144 avoids the need to perform a subsequent planarization step.

[0059] After the dielectric layer 144 is formed, the structure is polished according to known techniques (e.g., chemical mechanical polishing). Specifically, the dielectric layer 144, the gate spacer 132, and the gate mask 130 are polished until the top surface of the dielectric layer 144 is flush with or substantially flush with the top surfaces of the gate spacer 132 and the sacrificial gate 128.

[0060] Now for reference Figure 28 , Figure 29 ,as well as Figure 30 It shows the structure 100 after the formation of the gate structure 146 according to an embodiment of the present invention. Figure 28 Depicted Figure 29 and Figure 30 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 29 Depicting Figure 28 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 30 Depicting Figure 28 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0061] The sacrificial gate 128 and the sacrificial nanosheet 106 are selectively removed using known techniques.

[0062] First, according to known techniques, the sacrificial gate 128 is selectively etched and removed relative to the gate spacer 132 and the nanosheet stack 120. Next, according to known techniques, the sacrificial nanosheet 106 is selectively etched and removed to form the channel nanosheet 108 and the internal spacer 134. This can be achieved by varying germanium concentrations. In this case, the germanium-containing layer is selectively removed relative to the germanium-free layer.

[0063] Next, the gate structure 146 is formed according to known techniques. First, within the gate cavity or opening and spacers left by removing the sacrificial gate 128 and the sacrificial nanosheet 106 according to known techniques, a gate dielectric (not shown) is conformally deposited directly on the exposed surface of the structure 100. For example, the gate dielectric is conformally deposited on the exposed surfaces of the channel nanosheet 108 and the internal spacer 134.

[0064] The gate dielectric is made of any known gate dielectric material, such as oxides, nitrides, and / or oxide oxynitrides. In this example, the gate dielectric may be a high-k material having a dielectric constant greater than that of silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, and HfO. x N y ZrO x Ny La2O x N y Al2O x N y TiO x N y SrTiO x N y 、LaAlO x N y Y2O x N y SiON, SiN x The silicates and alloys thereof. Each value of x ranges from 0.5 to 3, and each value of y ranges from 0 to 2. In some embodiments, the multilayer gate dielectric structure comprises different gate dielectric materials. For example, a silicon dioxide layer and a high-k gate dielectric layer may be formed together and used as the gate dielectric. In at least one embodiment, the gate dielectric is made of hafnium oxide.

[0065] Next, according to known techniques, a work function metal (not shown) is conformally deposited on the first gate dielectric formed within the gate cavity. In at least one embodiment, the work function metal is made of the same conductive material that spans the entire structure. In at least another embodiment, in each device shown in the figures, the first functional metal is made of a different conductive material. In doing so, different conductive materials are deposited sequentially according to design parameters and desired operating characteristics.

[0066] The work function metal can include any known conductive gate material, including, for example, doped polycrystalline silicon, elemental metals (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), alloys of at least two elemental metals, elemental metal nitrides (e.g., tungsten nitride, aluminum nitride, and titanium nitride), elemental metal silicides (e.g., tungsten silicide, nickel silicide, and titanium silicide), or titanium carbide (TiC), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), or multilayer combinations thereof. In some embodiments, the work function metal can include an nFET gate metal. In other embodiments, the work function metal can include a pFET gate metal. When multiple gate cavities are formed, as illustrated herein, embodiments of the invention explicitly contemplate forming an nFET in at least one gate cavity and a pFET in at least another gate cavity.

[0067] In some embodiments, the gate metal or contact metal is deposited directly on the work function metal and fills the gate cavity. The first gate metal may comprise any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. Excess conductive material can then be polished using known techniques.

[0068] Finally, additional interlayer dielectric material is deposited according to known techniques. The dielectric layer 144 shown in the figures includes the additional interlayer dielectric material.

[0069] Continue to refer to Figure 28 , Figure 29 ,as well as Figure 30 It shows a structure 100 after forming source and drain contacts 148, forming mid-process and back-process 150, and attaching carrier wafer 152 according to an embodiment of the present invention.

[0070] Next, a portion of the dielectric layer 44 is removed to expose the source-drain regions 142a and 142b. Then, according to known techniques, a conductive material is used to fill the opening to form source-drain contacts 148. The source-drain contacts 148 may include any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, a metal silicide is formed at the bottom of the contact trench before the conductive material is used to fill the contact trench. In some embodiments, the source-drain contacts 148 do not contact the gate spacer 132. In other embodiments, the source-drain contacts 148 are self-aligned with the gate spacer 132, and therefore may be referred to as a self-aligned contact structure.

[0071] Finally, according to an embodiment of the invention, mid-process and back-process 150 (hereinafter MOL / BEOL 150) are formed, and carrier wafer 152 is attached to the top of structure 100. After the source-drain contacts 148 are formed, MOL / BEOL 150 is subsequently formed according to known techniques. The carrier wafer 150 is then attached or removably attached to MOL / BEOL 150. Typically, and not depicted, the carrier wafer 152 may be thicker than other layers. Temporarily attaching structure 100 to a thicker carrier provides improved processing and additional support for the back-side processing of thin wafers. After the back-side processing described below, structure 100 can be peeled off or removed from carrier wafer 152 according to known techniques.

[0072] Now for reference Figure 31 , Figure 32 ,as well as Figure 33 It shows the structure 100 after the component is flipped and the substrate 104 is recessed according to an embodiment of the present invention. Figure 31 Depicting Figure 32 and Figure 33 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 32 Depicting Figure 31 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 33 Depicting Figure 31The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0073] First, structure 100 is flipped 180 degrees to prepare for back-side processing. Typically, back-side processing involves fabricating or processing structure 100 opposite to the active devices and wiring layers. Next, substrate 104 is recessed according to known techniques. Specifically, as shown, substrate 112 is recessed or completely removed to expose etch stop layer 110.

[0074] Now for reference Figure 34 , Figure 35 ,as well as Figure 36 This illustrates the structure 100 after removing the remaining portion of the substrate 104 according to an embodiment of the present invention. Figure 34 Depicting Figure 37 and Figure 38 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 35 Depicting Figure 34 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 36 Depicting Figure 34 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0075] First, the etch stop layer 110 and the top semiconductor layer 114 are selectively removed according to known techniques. Specifically, the etch stop layer 110 is selectively removed relative to the top semiconductor layer 114, and then the top semiconductor layer 114 is selectively removed relative to the STI region 126, the sacrificial occupant 140, the source-drain region 142a, the source-drain region 142b, the dielectric strip 124, and the gate structure 146.

[0076] Now for reference Figure 37 , Figure 38 ,as well as Figure 39 This shows the structure 100 after the formation of the back-side dielectric layer 154 according to an embodiment of the present invention. Figure 37 Depicting Figure 38 and Figure 39 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 38 Depicting Figure 37 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 39 Depicting Figure 37 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0077] According to known techniques, a back-side dielectric layer 154 is formed by blanket deposition of interlayer dielectric material on structure 100. Specifically, as shown, the back-side dielectric layer 154 is formed on source-drain regions 142a and 142b, and between STI region 126 and dielectric strip 124.

[0078] The back-side dielectric layer 154 may be composed of silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate glass (BPSG), spin-coated low-k dielectric layer, chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. In another embodiment, a self-planarizing material such as spin-coated glass (SOG) or such as SiLK may be used. TM Spin-coated low-k dielectric material can be used as the back-side dielectric layer 154. Using a self-planarizing dielectric material as the back-side dielectric layer 154 avoids the need to perform a subsequent planarization step.

[0079] Now for reference Figure 40 , Figure 41 ,as well as Figure 42 It shows the structure 100 after the formation of the first back-side mask 156 according to an embodiment of the present invention. Figure 40 Depicting Figure 41 and Figure 42 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 41 Depicting Figure 41 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 42 Depicting Figure 41 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0080] According to known techniques, a first back-side mask 156 is deposited and subsequently patterned to expose certain portions of structure 100. The first back-side mask 156 may be an organic planarization layer (OPL) or a material layer capable of being planarized or etched using known techniques. In embodiments, for example, the first back-side mask 156 may be an amorphous carbon layer capable of withstanding the temperatures of subsequent processing. The first back-side mask 156 preferably has a thickness sufficient to cover the existing structure. After depositing the first back-side mask 156, a dry etching technique is applied according to known techniques to pattern the first back-side mask 156. Specifically, the first back-side mask 156 is patterned to expose portions of structure 100 that are substantially aligned with a first source / drain region 142a on one side of dielectric strip 124. Some patterning coverage or misalignment is acceptable, as illustrated, as long as portions of structure 100 that are substantially aligned with a second source / drain region 142b on the other side of dielectric strip 124 remain covered by the first back-side mask 156.

[0081] Now for reference Figure 43 , Figure 44 ,as well as Figure 45 It shows a structure 100 after the first portion of the sacrificial occupant 140 is removed to form a first dorsal groove 158 according to an embodiment of the present invention. Figure 43 Depicting Figure 44 and Figure 45 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 44 Depicting Figure 43 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 45 Depicting Figure 43 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0082] A first portion of the sacrificial berth 140 is selectively removed according to known techniques. Specifically, the first portion of the sacrificial berth 140 is selectively etched or removed relative to the STI region 126, the dielectric strip 124, and the first source / drain region 142a. For example, anisotropic etching techniques (e.g., reactive ion etching) can be used to remove the first portion of the sacrificial berth 140. The removal of the first portion of the sacrificial berth 140 creates a first back-side trench 158. Crucially, a portion of the first source / drain region 142a is exposed by the first back-side trench 158, as illustrated.

[0083] Now for reference Figure 46 , Figure 47 ,as well as Figure 48 It shows the structure 100 after the first back-side mask 156 has been removed and shallow ion implantation has been performed according to an embodiment of the present invention. Figure 46 Depicting Figure 47 and 48 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 47 Depicting Figure 46 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 48 Depicting Figure 46 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0084] First, the remaining portion of the first back-side mask 156 is removed using known techniques (e.g., by ashing). Next, shallow ion implantation is used to treat the exposed surfaces of the first source / drain regions 142a and improve contact resistance.

[0085] Now for reference Figure 49 , Figure 50 ,as well as Figure 51It shows a structure 100 after the formation of a first silicide liner 160, a first adhesive liner 162 and a first sacrificial filler 164 according to an embodiment of the present invention. Figure 49 Depicting Figure 50 and Figure 51 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 50 Depicting Figure 49 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 51 Depicting Figure 49 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0086] First, a first silicide liner 160 is deposited within the first backside trench 158 according to known techniques. For example, directional deposition techniques such as physical vapor deposition may preferably limit the deposition of the first silicide liner 160 on vertical or substantially vertical sidewalls. While the configuration thickness tolerance of the first silicide liner 160 is not critical, the first silicide liner 160 must have sufficient thickness in the Z direction to allow sufficient silicide formation during subsequent processes. As shown, the first silicide liner 160 may comprise any metal or combination of metals suitable for forming silicide at the bottom surface of the first source / drain region 142a. In an embodiment, the first silicide liner 160 is made of titanium, nickel, cobalt, and nickel-platinum. According to known techniques, additional processing may be used to remove excess material from the first silicide liner 160.

[0087] Next, a first adhesive liner 162 is deposited within the first backside trench 158 according to known techniques. Specifically, a relatively thin layer of titanium nitride or other suitable material is conformally deposited to improve the adhesion of subsequently deposited materials.

[0088] Next, a first sacrificial filler 164 is deposited within the first backside trench 158 according to known techniques. Specifically, the sacrificial material is deposited directly on top of the first adhesive liner 162 and fills the first backside trench 158, as shown. According to embodiments of the invention, the first sacrificial filler 164 may be amorphous silicon, or other suitable materials that can subsequently be selectively removed.

[0089] Finally, using known techniques, such as chemical mechanical polishing, excess material in the first adhesive liner 162 and the first sacrificial filler 164 is removed. Specifically, the first adhesive liner 162 and the first sacrificial filler 164 are polished until flush with or substantially flush with the STI region 126 and the dielectric strip 124, as illustrated.

[0090] Now for reference Figure 52 , Figure 53 ,as well as Figure 54It shows the structure 100 after removing the second portion of the sacrificial occupant 140 to create the second back trench 166 and performing another shallow ion implantation according to an embodiment of the invention. Figure 52 Depicting Figure 53 and Figure 54 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 53 Depicting Figure 52 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 54 Depicting Figure 52 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0091] The second portion of the sacrificial berth 140 is selectively removed according to known techniques. Specifically, the second portion of the sacrificial berth 140 is selectively etched or removed relative to the STI region 126, the dielectric strip 124, and the second source / drain region 142b. For example, anisotropic etching techniques (e.g., reactive ion etching) can be used to remove the second portion of the sacrificial berth 140. The removal of the second portion of the sacrificial berth 140 creates the second back-side trench 166. Crucially, a portion of the second source / drain region 142b is exposed by the second back-side trench 166, as shown.

[0092] Similar to the above, another shallow ion implantation technique is used to treat the exposed surface of the second source / drain region 142b and improve the contact resistance.

[0093] Now for reference Figure 55 , Figure 56 ,as well as Figure 57 It shows a structure 100 after the formation of a second silicide liner 168, a second adhesive liner 170 and a second sacrificial filler 172 according to an embodiment of the present invention. Figure 55 Depicting Figure 56 and Figure 57 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 56 Depicting Figure 55 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 57 Depicting Figure 55 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0094] First, a second silicide liner 168 is deposited within the second backside trench 166 according to known techniques. For example, directional deposition techniques such as physical vapor deposition may preferably limit the deposition of the second silicide liner 168 on vertical or substantially vertical sidewalls. While the configuration thickness tolerance of the second silicide liner 168 is not critical, the second silicide liner 168 must have sufficient thickness in the Z direction to allow for adequate silicide formation during subsequent processing. As shown, the second silicide liner 168 may comprise any metal or combination of metals suitable for forming silicide on the bottom surface of the second source / drain region 142b. In embodiments, the second silicide liner 168 is made of titanium, nickel, cobalt, and nickel-platinum. According to known techniques, additional processing may be used to remove excess material from the second silicide liner 168. In some embodiments, the first silicide liner 160 and the second silicide liner 168 are made of materials specifically tailored to match the source / drain regions on which they are formed. For example, titanium silicide liners are typically paired with N-type source and drain regions, while nickel-platinum silicide liners are typically paired with P-type source and drain regions.

[0095] Next, a second adhesive liner 170 is deposited within the second backside trench 166 according to known techniques. Specifically, a relatively thin layer of titanium nitride or other suitable material is conformally deposited to improve the adhesion of subsequently deposited materials.

[0096] Next, a second sacrificial filler 172 is deposited within the second backside trench 166 according to known techniques. Specifically, the sacrificial material is deposited directly on top of the second adhesive liner 170 and fills the second backside trench 166, as shown. According to embodiments of the invention, the second sacrificial filler 172 may be amorphous silicon, or other suitable materials that can be selectively removed subsequently.

[0097] Next, excess material in the second adhesive liner 170 and the second sacrificial filler 172 is removed using known techniques (e.g., chemical mechanical polishing). Specifically, the second adhesive liner 170 and the second sacrificial filler 172 are polished until flush with or substantially flush with the STI region 126 and the dielectric strip 124, as shown.

[0098] Finally, according to known techniques, a first silicide region (not shown) is formed at the interface between the first source / drain region 142a and the first silicide liner 160 using heat treatment (e.g., annealing), and a second silicide region (not shown) is formed at the interface between the second source / drain region 142b and the second silicide liner 168. Specifically, after the first silicide region is composed of elements from the first source / drain region 142a and the first silicide liner 160, the second silicide region is composed of elements from the second source / drain region 142b and the second silicide liner 168.

[0099] In one embodiment, for example, annealing may include subjecting structure 100 to temperatures ranging from about 800°C to about 1250°C for approximately 1 ns to about 500 ms. In yet another embodiment, a high-temperature rapid thermal annealing (RTA) technique, such as high-temperature peak annealing or laser peak annealing, may be used. Typically, high temperatures cannot be used at this stage of manufacturing due to the risk of damaging the gate metal or work function metal; however, in this case, the gate metal or work function metal has not yet been manufactured, thus allowing the use of high-temperature annealing.

[0100] Following annealing, and as is crucial to the embodiments disclosed herein, portions of the first silicide liner 160 and the second silicide liner 168 will remain in the final structure. It should also be noted that, as described immediately above, a specific annealing step is not always necessary. In such cases, silicides will form during subsequent heat treatment.

[0101] Now for reference Figure 58 , Figure 59 ,as well as Figure 60 It shows a structure 100 after removing the first sacrificial filler 164 and the second sacrificial filler 172, forming the back-side source-drain contact 174 and forming the back-side wiring layer 176 according to an embodiment of the present invention. Figure 58 Depicting Figure 59 and Figure 60 The cross-sectional view of structure 100 along line XX shown in the figure. Figure 59 Depicting Figure 58 The cross-sectional view of structure 100 along line Y1-Y1 shown in the figure, and Figure 60 Depicting Figure 58 The cross-sectional view of structure 100 along line Y2-Y2 shown in the figure.

[0102] First, according to known techniques, the first sacrificial filler 164 and the second sacrificial filler 172 are recessed and completely removed. Specifically, the first sacrificial filler 164 and the second sacrificial filler 172 are selectively etched relative to the first adhesive liner 162 and the second adhesive liner 170.

[0103] Next, according to known techniques, the openings created by removing the first sacrificial filler 164 and the second sacrificial filler 172 are then filled with conductive material to form back-side source-drain contacts 174. The back-side source-drain contacts 174 may comprise any suitable conductive material, such as copper, ruthenium, aluminum, tungsten, cobalt, or alloys thereof. In some embodiments, a metal silicide is formed at the bottom of the back-side trenches 166 before the conductive material is used to fill them. Afterward, excess conductive material can be polished using known techniques until the bottommost surface of the back-side source-drain contacts 174 is flush with or substantially flush with the bottommost surface of the STI region 126 and the back-side dielectric layer 154, as illustrated. After forming the back-side source-drain contacts 174, a back-side wiring layer 176 is subsequently formed according to known techniques.

[0104] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 According to an embodiment, structure 100 includes a dielectric strip 124 disposed between and physically separating a first source-drain region 142a and a second source-drain region 142b, a first silicide liner 160 located directly below the first source-drain region 142a, and a second silicide liner 168 located directly below the second source-drain region 142b, wherein the first silicide liner 160 is made of a different material than the second silicide liner 168.

[0105] Continue to refer to the embodiments Figure 58 , Figure 59 ,as well as Figure 60 Structure 100 includes: a first nanosheet device including a first source-drain region 142a; a second nanosheet device including a second source-drain region 142b; a dielectric strip 124 disposed between and physically separating each source-drain region in the first source-drain region 142a and each source-drain region in the second source-drain region 142b; a first silicide liner 160 located directly below the first source-drain region 142a; and a second silicide liner 168 located directly below the second source-drain region 142b, wherein the first silicide liner is a different material from the second silicide liner.

[0106] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60According to an embodiment, structure 100 includes: an n-type nanosheet device including an n-type source / drain region 142a; a p-type nanosheet device including a p-type source / drain region 142b; a dielectric strip 124 disposed between and physically separating each n-type source / drain region in the n-type source / drain region 142a and each p-type source / drain region in the p-type source / drain region 142b; a first silicide liner 160 located directly below the n-type source / drain region 142a; and a second silicide liner located directly below the p-type source / drain region 142b, wherein the first silicide liner 160 is a different material from the second silicide liner 168.

[0107] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 Furthermore, according to an embodiment, structure 100 further includes: a first silicide disposed between the first source / drain region and the first silicide liner and in direct contact with the first source / drain region and the first silicide liner; and a second silicide disposed between the second source / drain region and the second silicide liner and in direct contact with the second source / drain region and the second silicide liner.

[0108] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 Furthermore, according to an embodiment, structure 100 further includes: a first back-side source-drain contact, which is directly located below the first source-drain region and electrically connected to the first source-drain region; and a second back-side source-drain contact, which is directly located below the second source-drain region and electrically connected to the second source-drain region.

[0109] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 Furthermore, according to an embodiment, structure 100 further includes a first back-side source-drain contact, which is directly located below the first source-drain region and electrically connected to the first source-drain region, wherein the bottom surface of the first back-side source-drain contact is substantially flush with the bottom surface of the dielectric strip, and also includes a second back-side source-drain contact, which is directly located below the second source-drain region and electrically connected to the second source-drain region, wherein the bottom surface of the second back-side source-drain contact is substantially flush with the bottom surface of the dielectric strip.

[0110] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 Furthermore, according to an embodiment, the distance between the first source / drain region and the second source / drain region is less than 10 nm.

[0111] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 Furthermore, according to an embodiment, the lateral width of the dielectric strip is less than 10 nm.

[0112] Continue to refer to Figure 58 , Figure 59 ,as well as Figure 60 Furthermore, according to an embodiment, the first source / drain region and the sidewall of the first silicide liner directly contact the first sidewall of the dielectric strip, and the second source / drain region and the sidewall of the second silicide liner directly contact the second sidewall of the dielectric strip.

[0113] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: a dielectric strip arranged between and physically separating a first source-drain region and a second source-drain region; a first silicide liner located directly below the first source-drain region; and a second silicide liner located directly below the second source-drain region, wherein the first silicide liner is a different material than the second silicide liner.

2. The semiconductor structure of claim 1, further comprising: a first silicide arranged between and directly contacting the first source-drain region and the first silicide liner; and a second silicide arranged between and directly contacting the second source-drain region and the second silicide liner.

3. The semiconductor structure of claim 1, further comprising: a first backside source-drain contact located directly below and in electrical communication with the first source-drain region; and a second backside source-drain contact located directly below and in electrical communication with the second source-drain region.

4. The semiconductor structure of claim 1, further comprising: a first backside source-drain contact located directly below and in electrical communication with the first source-drain region, wherein a bottommost surface of the first backside source-drain contact is substantially flush with a bottommost surface of the dielectric strip; and a second backside source-drain contact located directly below and in electrical communication with the second source-drain region, wherein a bottommost surface of the second backside source-drain contact is substantially flush with the bottommost surface of the dielectric strip.

5. The semiconductor structure of claim 1, wherein a distance between the first source-drain region and the second source-drain region is less than 10 nm.

6. The semiconductor structure of claim 1, wherein a lateral width of the dielectric strip is less than 10 nm.

7. The semiconductor structure of claim 1, wherein a sidewall of the first source-drain region and a sidewall of the first silicide liner directly contact a first sidewall of the dielectric strip, wherein a sidewall of the second source-drain region and a sidewall of the second silicide liner directly contact a second sidewall of the dielectric strip.

8. A semiconductor structure, comprising: a first nanosheet device comprising a first source-drain region; a second nanosheet device comprising a second source-drain region; and a dielectric strip arranged between and physically separating the first source-drain region and the second source-drain region. ​ ​ ​ a dielectric strip arranged between and physically separating each of the first source-drain regions from each of the second source-drain regions; a first silicide liner located directly below the first source-drain regions; and a second silicide liner located directly below the second source-drain regions, wherein the first silicide liner is a different material than the second silicide liner.

9. The semiconductor structure of claim 8, further comprising: a first silicide arranged between each of the first source-drain regions and the first silicide liner, and directly contacting each of the first source-drain regions and the first silicide liner; and a second silicide arranged between each of the second source-drain regions and the second silicide liner, and directly contacting each of the second source-drain regions and the second silicide liner.

10. The semiconductor structure of claim 8, further comprising: a first backside source-drain contact located directly below and in electrical communication with each of the first source-drain regions; and a second backside source-drain contact located directly below and in electrical communication with each of the second source-drain regions.

11. The semiconductor structure of claim 8, further comprising: a first backside source-drain contact located directly below and in electrical communication with each of the first source-drain regions, wherein a bottommost surface of the first backside source-drain contact is substantially flush with a bottommost surface of the dielectric strip; and a second backside source-drain contact located directly below and in electrical communication with each of the second source-drain regions, wherein a bottommost surface of the second backside source-drain contact is substantially flush with a bottommost surface of the dielectric strip.

12. The semiconductor structure of claim 8, wherein a distance between each of the first source-drain regions and each of the second source-drain regions is less than 10 nm.

13. The semiconductor structure of claim 8, wherein a lateral width of the dielectric strip is less than 10 nm.

14. The semiconductor structure of claim 8, wherein a sidewall of each of the first source / drain regions and a sidewall of the first silicide liner directly contact a first sidewall of the dielectric strip, wherein a sidewall of each of the second source / drain regions and a sidewall of the second silicide liner directly contact a second sidewall of the dielectric strip.

15. A semiconductor structure, comprising: an n-type nanosheet device comprising n-type source / drain regions; a p-type nanosheet device comprising p-type source / drain regions; a dielectric strip disposed between and physically separating each of the n-type source / drain regions from each of the p-type source / drain regions; a first silicide liner located directly below the n-type source / drain regions; and a second silicide liner located directly below the p-type source / drain regions, wherein the first silicide liner is a different material than the second silicide liner.

16. The semiconductor structure of claim 15, further comprising: a first silicide disposed between and directly contacting the n-type source / drain regions and the first silicide liner; and a second silicide disposed between and directly contacting the p-type source / drain regions and the second silicide liner.

17. The semiconductor structure of claim 15, further comprising: a first backside source / drain contact located directly below and in electrical communication with the n-type source / drain regions; and a second backside source / drain contact located directly below and in electrical communication with the p-type source / drain regions.

18. The semiconductor structure of claim 15, wherein a distance between each of the n-type source / drain regions and each of the p-type source / drain regions is less than 10 nm.

19. The semiconductor structure of claim 15, wherein a lateral width of the dielectric strip is less than 10 nm.

20. The semiconductor structure of claim 15, wherein a sidewall of each of the n-type source / drain regions and a sidewall of the first silicide liner directly contact a first sidewall of the dielectric strip, wherein a sidewall of each of the p-type source / drain regions and a sidewall of the second silicide liner directly contact a second sidewall of the dielectric strip. ​ ​ ​

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