Main drive motor controller and gear shifting controller integration method

Abstract

The invention relates to the technical field of vehicle electric drive and transmission cooperative control, and discloses a main drive motor controller and gear shifting controller integration method. The method comprises the following steps: acquiring shell and water channel multiplexing constraint information and connector pin resource information, performing common-mode planning of a structure, heat dissipation and an interface, and establishing a unified constraint; executing multi-core chip bearing and low-voltage power supply collaborative partition, and configuring task interaction in the chip; performing whole-process combined control arrangement, constructing a cooperative control track according to a time sequence of each stage of gear shifting, and completing constraint matching; and finally, integrated integration is realized through joint calibration and topological configuration. Through deep cooperation from a physical layer to a control layer, the dynamic interference problem after the two controllers are integrated is solved, the gear shifting smoothness and the system reliability are remarkably improved, and the cost and the size are reduced.

Description

Technical Field

[0001] This invention relates to the field of vehicle electric drive and transmission coordinated control technology, and in particular to an integrated method for a main drive motor controller and a shift controller. Background Technology

[0002] Currently, the shift controller (TCU) and motor controller (MCU) of new energy electric vehicles are generally divided into two separate modules; The gear shifting operation requires two controller modules to drive the relevant actuators in coordination to complete the operation. The entire gear shifting process includes: TCU disengaging, MCU speed adjustment, and TCU engaging. With the industrial development trend of increasingly higher cost and performance requirements, the separate architecture of MCU and TCU has some problems that are difficult to improve: ① The separate controllers involve space constraints, requiring separate distribution and arrangement of the two controllers, which increases the difficulty of the arrangement; ② The two separate controllers require two complete structural envelopes and cannot share heat dissipation and housing; ③ During the gear shifting process, the MCU and TCU need to communicate and interact to complete the gear shifting operation. The two separate controllers inevitably involve communication harnesses and communication protocols, which limits the signal transmission rate. ④ Shifting performance is limited. To achieve a smoother and more refined shifting process, the TCU and MCU need to work together to calibrate dynamic response parameters and accelerate their communication rate to respond quickly to changes in parameters during shifting. Currently, with the MCU and TCU being separate control modules, the only way to enhance their collaboration is to increase the signal transmission rate. The current fast signal transmission cycle in the vehicle network is generally 10ms. Adjusting individual signals to a 2ms transmission cycle would significantly increase the bus load and cannot fundamentally solve the problem.

[0003] Furthermore, existing electric drive systems generally adopt a split architecture for the main drive motor controller and the shift controller, with the two controllers arranged independently, and their housings, heat sinks, connectors, and wiring harnesses configured separately. This type of architecture creates a large structural envelope in the overall vehicle layout, making it impossible to share cooling circuits, increasing the number of wiring harnesses and cross-device connection paths, and raising assembly complexity and maintenance difficulty. Split control also relies on the vehicle network to carry critical coordination signals. Network cycle, load, and priority constraints lead to uncertain delays in signal round-trip links, limiting the coordination coupling between shifting, speed adjustment, and gear engagement stages, and easily causing problems such as discontinuity of control parameters and inconsistency of task cycles at stage switching boundaries. In terms of thermal management, the main drive control unit often uses water cooling, while the shift control unit mostly uses air cooling or separate heat sink components. The lack of unified modeling for the thermal design boundaries, cooling channels, and sealing benchmarks of both makes it difficult to achieve common-mode planning of structural-thermal boundary conditions at the controller level.

[0004] At the hardware resource level, the main control processing unit, peripherals, and low-voltage power supply modules are distributed in a dispersed manner. The ownership relationship between processing units and peripherals, the division of power supply domains, and the redundancy of power integrity lack a unified partitioning standard. Power budget and power supply redundancy cannot be matched with the control task load, resulting in an imbalance in the utilization of processing and power supply resources. At the communication and scheduling level, there is a lack of a unified orchestration mechanism for the interaction signal table and task cycle table oriented towards the chip. The shortest processing link and shortest transmission link of the critical interaction path are not established with entry-level references under the same naming convention and coordinate system. The time components, spatial connectivity components, and power supply domain components of the timing boundary are difficult to summarize within the same constraint system. The target delay allocation cannot support the phased coordination of the entire shift process.

[0005] Existing integration solutions mostly focus on structural parallel connections or wiring harness bundles, and have not yet formed a full-link method that starts from the structural-thermal-interface common mode planning constraint set data, links multi-core load and low-voltage power supply collaborative partitioning result data, then constructs the chip interaction and task cycle table, completes the stage timing construction and torque and speed difference target trajectory generation, and then transmits it step by step to the joint control configuration result data, joint calibration and consistency tuning, unified topology and interface compact configuration. Existing technologies lack a common mode modeling and verification process for information such as shell and water channel reuse, connector pin mapping, sealing boundary conditions and cooling channel parameters within a single shell, and lack a set of rules for consistency verification and resource adjustment of the common mode planning results with multi-core partitioning diagrams, processing unit allocation information and peripheral binding information.

[0006] In terms of intra-chip communication and task scheduling, existing methods lack an entry-level process for extracting key interaction paths and timing boundaries from interaction signal table data and task cycle table data. They also lack a standardized process for generating target delay budget data through constraint calculations under multi-dimensional fields such as stage affiliation, cross-stage references, path length indexes, path stacking constraints, power domain references, and installation and sealing references. Therefore, it is difficult to support subsequent scheduling orchestration to generate intra-chip interaction and task cycle table configuration result data. Regarding joint control and calibration, there is a lack of a unified entry point for mapping stage timing orchestration data and torque and speed difference target trajectory data into full-process joint control configuration result data. Furthermore, there is a lack of a seamless process for training a joint calibration model based on this configuration result data, outputting joint calibration parameter data, and then performing consistency calculations and parameter tuning to generate consistency index data.

[0007] There is still a lack of methodology for unified topology and interface compact configuration at the vehicle level: there is a lack of a systematic approach to combine consistency index data with connector pin mapping data to complete interface reuse mapping, connection path and node grouping extraction, harness reduction list generation, and then perform topology verification and structural mapping on the harness reduction list data and consistency index data to generate topology connection diagram data. Summary of the Invention

[0008] To address the aforementioned technical problems, this invention provides a method for integrating a main drive motor controller and a shift controller, comprising: Obtain the reuse constraint information of the shell and water channel, and the pin resource information of the connector. Perform common mode planning processing of structure-thermal-interface with unified reference coordinates and the same naming standard. Perform the extraction of sealing boundary conditions and cooling channel parameters, common mode planning modeling of structure-thermal-interface, and interface grouping and boundary consistency verification to generate common mode planning constraint set data of structure-thermal-interface. Perform multi-core load and low-voltage power supply collaborative partitioning processing including installation benchmark, sealing benchmark and channel benchmark, and perform pre-configuration of multi-core partitioning map data, calculation and consistency verification and resource adjustment of low-voltage power budget data and power integrity margin data, and generate multi-core load and low-voltage power supply collaborative partitioning result data; Perform on-chip interaction and task cycle table configuration operations that include final processing unit allocation information and final peripheral binding information. Perform preprocessing of interaction signal table data and task cycle table data, extraction and constraint calculation of key interaction paths and timing boundaries, and scheduling and orchestration to generate on-chip interaction and task cycle table configuration result data. The process involves joint control and orchestration of the entire process, including phased task schedules and interaction path schedules. This includes constructing phased time sequence orchestration data, extracting phase boundaries and velocity difference targets, generating trajectories, and matching constraints, thereby generating joint control configuration result data for the entire process. Perform joint calibration model training and parameter tuning operations to generate consistency index data; Perform unified topology and interface concise configuration processing to generate topology connection diagram data.

[0009] Furthermore, the shell and waterway reuse constraint information and connector pin resource information include: The specific constraint information for the reuse of the shell and waterway includes the shell geometry, mounting plane, fastening hole positions, rib distribution, sealing groove cross-section and orientation, and the range of the gap between the external mounting perimeter and the shell edge; The connector pin resource information includes the interface socket model, number and size of cavities, type of terminals that can be assembled in each cavity, rated current range of terminals, temperature resistance rating of terminals, shielding and grounding requirements, terminal position code, allowable bending radius of terminals and wire harnesses, insertion and removal direction of the interface socket, and physical interface parameters of the operating space.

[0010] Furthermore, the process of generating the joint control configuration result data for the entire process also includes: The chip-interactive and task cycle table configuration result data is obtained, and the joint control orchestration timing construction of the entire process, including the phased task time table and interaction path time table, is executed to obtain the phased timing orchestration data. The phased timing orchestration data includes the joint time axis, phase switching mark, segmented power supply domain occupancy, tightly coupled partition list and its reference relationship with the installation reference, sealing reference and channel reference. Extract the stage boundary and speed difference target, and perform full-process joint control and orchestration trajectory generation including speed difference observation sequence and torque reference sequence to obtain torque and speed difference target trajectory data. The torque and speed difference target trajectory data includes the target trajectory set within the stage, continuous segment markers, tightly coupled partition priority labels and power supply domain references. Constraint matching is performed, including power supply domain consistency verification and path connectivity verification, to generate full-process joint control configuration result data. The full-process joint control configuration result data includes a joint time axis, a trajectory-to-task mapping list, a list of connection segments and preparation and release segments, stage switching markers and continuous segment markers, segmented power supply domain occupancy verification results, and reference paths to installation benchmarks, sealing benchmarks, and channel benchmarks.

[0011] Furthermore, the construction of the joint control and orchestration timing for the entire process includes: Using the in-chip interaction and task cycle table configuration results as input, which includes a phased task timetable, a phased interaction path timetable, and a power domain occupancy summary table, the phased task timetable is interpreted according to three stages: pick-up, speed adjustment, and gear advance. Under the same coordinates and naming conventions, the task entries of each processing unit are arranged into continuous segments according to their start and end times, forming a set of task segments within each stage. The phased interaction path timetable is interpreted synchronously, reading the allocation start and end points of each interaction path, and recording the signal name, source processing unit, destination processing unit, and step sequence associated with the interaction path. A mapping is established for continuous time windows to form a set of interactive path segments. While reading the power supply domain occupancy summary table, the segmented occupancy results of control logic power supply, execution drive power supply, and sensing and communication power supply in each stage are marked on the corresponding task segments and interactive path segments, so that each time segment has a clear power supply domain reference. Based on the indexes of the installation reference, sealing reference, and channel reference, the interface partitions and path indexes related to the execution drive are retrieved to confirm that the physical connectivity conditions required for deploying synchronous mechanism control, clutch execution, and main drive speed regulation in the stage have not been destroyed. Interface partitions with physical adjacency constraints are marked as tightly coupled partitions as boundary items when constructing the timing sequence.

[0012] Furthermore, the construction of the entire process joint control orchestration timing also includes: Using stages as the main framework, a two-layer alignment is applied to the task segment set and interaction path segment set for each stage: The first layer is intra-stage alignment, where the start and end positions of task segments directly associated with an interaction path segment are adjusted using the allocation start and end points as anchor points. This ensures that the latest processing position on the signal generation side is no later than the start point of the interaction path segment, and the earliest processing position on the signal consumption side is no earlier than the end point of the interaction path segment, thus forming non-overlapping execution windows within the same stage. The second layer is boundary alignment, where consecutive time windows across stages are used as anchor points between adjacent stages. The interaction path segments of the two stages are spliced ​​together, and the end point of the cross-stage entry is matched with the start point of the corresponding entry in the next stage. A stage switching mark is recorded at the matching position. For the interface partition identified as a tightly coupled partition, while aligning the two layers, the indexes of the sealing reference and the channel reference are called to check whether there is temporary occupation superposition of the path index corresponding to the interface partition. If there is superposition, the low priority entries in the task segment set are slightly moved without changing the relative order of the interaction path segments, the temporary occupation of the interface partition is released and the corresponding start time and end time are updated.

[0013] Furthermore, the construction of the entire process joint control orchestration timing also includes: Threshold checks are performed on the segmented occupancy of each power supply domain within each stage. If the occupancy entries of a power supply domain in any time slice exceed the available upper limit given in the power supply domain occupancy summary table, segment compression and segment migration are implemented in the local time slice: the duration of non-critical task segments is compressed first; if the limit is still exceeded after compression, the non-critical task segment is migrated to the idle time slice of the same stage, and the associated interaction path segment reference is added at the migration position; through intra-segment alignment, boundary alignment and power supply domain checks, the task segments and interaction path segments at the processing unit level are integrated into a stage-level joint time axis, forming a stage timing draft that includes stage switching markers, segment start and end positions, interaction path references and power supply domain references.

[0014] Furthermore, the generation of the entire process joint control and orchestration trajectory includes: The joint time axis and stage switching markers are read from the stage timing arrangement data, and the start and end positions of each stage segment are linearly expanded according to time sequence to obtain the stage boundary set. At the same time, the tightly coupled partition list is retrieved to mark the positions of segments involving synchronization mechanism control, clutch execution, and main drive speed regulation, thereby establishing two subsets in the stage boundary set: synchronization-related boundaries and execution-related boundaries. The established signal reference relationship is invoked to extract signal entries related to speed difference estimation, synchronization target calculation, and torque adjustment commands from the joint time axis. Their distribution positions within the stage and their continuity relationships between stages are concatenated to generate time indices for the speed difference observation sequence and torque reference sequence. The power supply domain reference and the path index of the tightly coupled partition are superimposed on the time index to confirm that there are no cases where the power supply domain is unavailable or the path is unreachable at the key nodes of the trajectory segment. If there are, a usable alternative node is inserted into the time index, and the signal references of adjacent segments are re-associated.

[0015] Furthermore, the generation of the entire process joint control and orchestration trajectory also includes: The speed difference observation sequence and torque reference sequence are segmented in stages: In the disengagement stage, the segmented sequences related to clutch engagement, disengagement synchronization, and main drive deceleration are extracted and implemented as clutch control segments, synchronization control segments, and main drive deceleration segments; in the speed regulation stage, the segmented sequences related to speed difference tracking, speed transition, and synchronization propulsion are extracted and implemented as speed difference tracking segments, speed transition segments, and synchronization propulsion segments; in the gear engagement stage, the segmented sequences related to gear engagement promotion, clutch engagement, and main drive recovery are extracted and implemented as gear engagement promotion segments, clutch engagement segments, and main drive recovery segments; for each segment, a clear start and end point are assigned according to the start and end positions of the joint time axis segment, and a signal drive sequence is established within the segment according to the order of interactive path references, so that the segment has an itemized structure that can be called step by step by the execution unit.

[0016] Furthermore, the generation of the entire process joint control and orchestration trajectory also includes: Connecting adjacent segments: When there is a gap between upstream and downstream segments on the time axis, a transition segment is inserted at the gap position, and the transition segment is checked for consistency with the power supply domain reference; when upstream and downstream segments overlap on the time axis, the segment associated with the tightly coupled partition is retained first, and the other segment is shortened or shifted without changing the stage boundary until the overlap is eliminated; the fragmented sequence within each stage is spliced ​​in the segment order to generate the torque target segment sequence and speed difference target segment sequence within the stage, and the continuity across stages is checked: for signal references with continuous time windows across stages, continuous segment markers are established at the splicing boundary between two stages, and the end position of the previous stage and the start position of the next stage are recorded on the continuous segment markers to ensure that there are no undefined segment gaps at the stage switching markers.

[0017] Furthermore, constraint matching includes: At the stage level, the torque and speed difference target trajectory data are aligned with the stage timing orchestration data: the joint time axis and stage switching markers in the stage timing orchestration data are read, and the target trajectory set within the stage in the torque and speed difference target trajectory data is projected onto the joint time axis to form a target trajectory alignment view; in the target trajectory alignment view, continuous segment markers and tightly coupled partition priority labels are located one by one, indicating the set of segments that need to be prioritized; the segmented power supply domain occupancy and tightly coupled partition list in the stage timing orchestration data are called to perform power supply domain consistency verification and path matching on the target trajectory alignment view. Path connectivity verification: When the power supply domain occupancy of a time slice containing a trajectory segment exceeds the available limit, the positions of adjacent non-tightly coupled segments within the same stage are adjusted first to bring the occupancy of that time slice into the available range; if the adjustment is still insufficient, the dwell time of that segment in that time slice is shortened without changing the stage switching mark, and the shortened part is moved to an idle time slice in the same stage; when the path index of a trajectory segment is inconsistent with that of a tightly coupled partition, a preparation segment is inserted before that segment and a release segment is inserted after that segment to ensure that the paths to and from the tightly coupled partition are reachable.

[0018] The key innovations of this invention include: (1) The common-mode object connects the shell, waterway, seal, cooling and connector pin mapping, so that structural constraints and interface constraints are landed in the same data body, and bidirectional references are established with partitioning, scheduling and topology steps to form a single source that is consistent across domains.

[0019] (2) Multi-core co-loading and low-voltage power supply collaborative partitioning integrates processing unit allocation information, peripheral binding information, low-voltage power budget data, and power integrity margin data, providing a partition map with power supply domain annotation, and providing auditable energy support references for the construction of critical interaction paths and timing boundary calculation.

[0020] (3) The chip-interactive and task cycle table completes the shortest link splicing, time window synthesis and priority order compression under the staged organization to generate target delay budget data, so that the stage timing arrangement data and torque and speed difference target trajectory data have traceable constraint sources.

[0021] The following are its main beneficial effects: (1) This invention focuses on the deep integration of the main drive motor controller and the shift controller under a single housing, constructing a continuous data chain from structure, heat, interface to chip internal scheduling and vehicle topology. Based on the structure-heat-interface common mode planning constraint set data and the multi-core load and low-voltage power supply collaborative partitioning result data, an interaction signal table and task cycle table with the same naming standard and the same coordinate system are formed. On this basis, the entry-level extraction and constraint solution of key interaction paths and timing boundaries are carried out to generate target delay budget data. Thus, the stage timing arrangement data and torque and speed difference target trajectory data can generate the whole process joint control configuration result data under unified constraints. Subsequently, the joint calibration parameter data of the drive is generated and the consistency index data is output. Finally, it is merged with the connector pin mapping data to complete the integrated generation of interface reuse mapping, harness reduction list and topology connection diagram data, forming a three-dimensional design to implementation closed loop.

[0022] (2) In terms of structure and thermal aspects, this invention incorporates the shell and water channel reuse constraint information, sealing boundary conditions and cooling channel parameters into the common-mode object. The connector pin mapping data is grouped and boundary checked within the same object, thereby making the reference source of subsequent power distribution partitions and chip internal links clear and avoiding constraint conflicts caused by inconsistent cross-domain information. The common-mode object directly provides input for multi-core co-loading and low-voltage power supply collaborative partitioning. A bidirectional reference is established between processing unit allocation information and peripheral binding information and low-voltage power budget data and power integrity margin data, so that subsequent scheduling stages can be uniformly audited according to power supply domain, processing domain and peripheral domain.

[0023] (3) At the chip's internal communication and scheduling level, this invention manages interactive signals in a unified manner across the three stages of gear picking, speed adjustment, and gear shifting, within the same naming convention and coordinate system. Based on the correspondence between the source and destination processing units and the path index, it constructs the shortest processing link and the shortest transmission link, and incorporates task priority, processing time limit fields, power supply domain references, and path stacking constraints into the same constraint set. Then, it generates target delay budget data through operations such as time window synthesis, path stacking, and priority compression. This budget data serves as the primary input for the chip's internal interaction and task cycle table configuration results, ensuring that the construction of stage timing arrangement data and the generation of torque and speed difference target trajectory data have traceable timing and power supply boundaries. Attached Figure Description

[0024] Figure 1 A schematic diagram of the hardware topology for integrated control of a main drive motor controller and a shift controller provided in this application embodiment; Figure 2 A schematic diagram of the software architecture and task interaction of an integrated control system for a main drive motor controller and a shift controller provided in this application embodiment; Figure 3 This is a flowchart illustrating a method for integrating a main drive motor controller and a shift controller, as provided in an embodiment of this application. Detailed Implementation

[0025] As the electronic and electrical architecture of new energy electric vehicles develops towards integration and domain control, the integration of power domain controllers has become a key path to improve system performance and reduce manufacturing costs. The main drive motor controller (MCU) and shift controller (TCU), as tightly coupled core control units in the powertrain system, are responsible for power output and power transmission control, respectively. In existing technologies, the MCU and TCU typically exist as independent components, leading to problems such as structural separation, hardware resource redundancy, high signal interaction delay, and high complexity in collaborative calibration. This invention aims to overcome these technical bottlenecks by deeply integrating the MCU and TCU. Specifically, the integration scheme of this invention is reflected in the following aspects: At the structural level, it achieves reuse of the shell and water channels, sharing water cooling and mechanical support, significantly improving space utilization and cost-effectiveness; at the hardware level, it achieves collaborative partitioning of multi-core chips and power supply resources, sharing the main control chip and board-level resources, reducing the number of electronic components and interconnection losses; at the software level, through unified configuration of in-chip interaction and task cycle tables, it converts signals originally transmitted via external buses into in-chip communication, greatly improving the interaction rate and determinism of control commands and status feedback, achieving microsecond-level response; at the calibration level, based on the joint control orchestration of the entire process, it provides a unified calibration service interface, realizing collaborative tuning and consistency optimization of MCU and TCU parameters, thereby improving the smoothness of power output, the speed of gear shifting, and the energy efficiency of the entire vehicle at the system level. Therefore, the deep integration method provided by this invention has significant technical advantages for promoting the integrated design of power domain controllers and enhancing product competitiveness.

[0026] To achieve the above objectives, this application provides a hardware integration scheme for a main drive motor controller (MCU) and a shift controller (TCU). Figure 1 This is a schematic diagram of a hardware topology for an integrated control system combining a main drive motor controller and a shift controller, as provided in an embodiment of this application. The architecture of the integrated solution is as follows: Figure 1As shown, it mainly includes: a vehicle CAN network module, a vehicle low-voltage battery module, a vehicle high-voltage battery module, a low-voltage power supply module, a main drive motor drive module, a main drive motor module, a shift motor drive module, a shift motor module, a control module, a communication module, and a cooling module. Among these, the control module, as the core of the integration, internally implements the hardware resource collaborative partitioning and software task collaborative scheduling of the MCU and TCU functions on a multi-core chip through the aforementioned methods (S100-S600). The specific connection relationships are as follows: the communication module is connected to the vehicle CAN network module and the control module respectively, for realizing information interaction between the integrated controller and the vehicle level; the vehicle low-voltage battery module provides power to the low-voltage power supply module and the shift motor drive module, and the low-voltage power supply module converts the power to power the control module; the vehicle high-voltage battery module is connected to the main drive motor drive module, providing it with high-voltage power; the control module, as a unified computing and control center, sends control commands to the main drive motor drive module and the shift motor drive module respectively, and receives their feedback information; the main drive motor drive module and the shift motor drive module respectively drive the main drive motor module and the shift motor drive module to perform power output and shifting actions; the cooling module is connected to the main drive motor drive module, the shift motor drive module and the main drive motor module, and performs unified thermal management of the key heat sources of the system based on the structure-thermal common-mode planning (S100) and the reuse of water channels and shell. This architecture achieves substantial integration of the MCU and TCU in terms of physical structure, hardware circuitry, control logic, and thermal management through deep integration of control modules and resource reuse.

[0027] To further illustrate the implementation effects of this integration method, this application provides the implementation methods of the integration scheme at the structural, hardware, and software levels. At the structural integration level, the MCU and TCU integrated controller, based on structure-thermal-interface common-mode planning (S100), achieves the reuse of the housing and cooling channels. Compared with the separate solution, the integrated solution shares a single housing, saving material and mold costs; the TCU no longer requires a separate air-cooling structure, but shares a water-cooling channel with the MCU, achieving efficient reuse of heat dissipation resources. Regarding interfaces, through unified interface consolidation configuration (S600), the large number of pin resources required by the TCU and the small number of pin resources required by the MCU under the separate solution are integrated and optimized, reducing two external connectors to one, significantly reducing connector costs and wiring complexity. At the hardware integration level, based on multi-core co-loading and low-voltage power supply collaborative partitioning (S200), the integrated controller maximizes the utilization of the main control chip and power supply resources. Specifically, the MCU and TCU functions, which originally ran on two separate controller chips, are now collaboratively deployed on different cores of the same multi-core chip through in-chip interaction and task cycle table configuration (S300), thus saving a main control chip. At the same time, only one low-voltage power supply module is needed to meet the logic power supply requirements of the entire system, achieving deep integration of hardware resources and cost reduction. Figure 2 This application provides a schematic diagram of the software architecture and task interaction for integrated control of a main drive motor controller and a shift controller, as shown in the embodiments of this application. At the software integration level, for example... Figure 2 As shown, the integrated controller runs a unified underlying software stack (such as OS, Services, COM, etc.), and the application layer functions of the MCU and TCU are independent software modules that interact through the runtime environment (RTE). Based on the task cycle table generated by the full-process joint control orchestration (S400), the interaction signals between the MCU and TCU (such as torque commands and gear status) no longer rely on an external bus, but are instead transmitted through the chip via the RTE at high speed and with deterministic communication. The interaction task cycle can be flexibly configured to milliseconds (such as 1ms) or even sub-milliseconds (such as 0.1ms) according to the control accuracy requirements, greatly improving the response speed and coordination efficiency of the control system.

[0028] In one embodiment, reference is made to Figure 3 This is a flowchart illustrating a method for integrating a main drive motor controller and a shift controller according to an embodiment of the present invention. The process may include at least steps S100-S600: S100: Obtain the shell and water channel reuse constraint information and connector pin resource information, perform structure-thermal-interface common mode planning processing with unified reference coordinates and the same naming standard, including the extraction of sealing boundary conditions and cooling channel parameters, structure-thermal-interface common mode planning modeling and interface grouping and boundary consistency verification, and generate structure-thermal-interface common mode planning constraint set data; S200: Perform multi-core load and low-voltage power supply collaborative partitioning processing including installation reference, sealing reference and channel reference, and perform pre-configuration of multi-core partitioning map data, calculation and consistency verification and resource adjustment of low-voltage power budget data and power integrity margin data, and generate multi-core load and low-voltage power supply collaborative partitioning result data; S300: Perform the chip-in-chip interaction and task cycle table configuration operation, which includes the final processing unit allocation information and the final peripheral binding information. Perform preprocessing of interaction signal table data and task cycle table data, extraction and constraint calculation of key interaction paths and timing boundaries, and scheduling and orchestration to generate chip-in-chip interaction and task cycle table configuration result data. S400 executes the full-process joint control orchestration processing, which includes a phased task schedule and an interaction path schedule. This process includes constructing phased time sequence orchestration data, extracting phase boundaries and speed difference targets, generating trajectories, and matching constraints, and generating full-process joint control configuration result data. S500 performs joint calibration model training and parameter tuning operations to generate consistency index data; S600 performs unified topology and interface intensive configuration processing to generate topology connection diagram data.

[0029] Step S100 includes at least steps S110-S130: S110. Obtain the shell and waterway reuse constraint information and connector pin resource information, perform structure-thermal-interface common mode planning preprocessing, and obtain shell and waterway reuse constraint data; The shared constraint information for the housing and water channels specifically includes geometric parameters such as housing geometry, mounting plane, fastening hole positions, rib distribution, sealing groove cross-section and orientation, and the gap range between the external mounting perimeter and the housing edge, obtained from the three-dimensional structural data of the main drive motor controller and the shift controller. It also includes thermal management parameters such as the inlet and outlet positions, cooling channel cross-sectional specifications, minimum allowable turning radius of the channel, minimum spacing between channel branches, allowable pressure drop range, and safe distance from surrounding components, obtained from the cooling module data. The connector pin resource information specifically includes physical interface parameters such as interface socket model, number and size of cavities, type of terminals that can be assembled in each cavity, terminal rated current range, terminal temperature resistance rating, shielding and grounding requirements, terminal position code, allowable bending radius of terminals and wiring harnesses, insertion and removal direction of the interface socket, and operating space. It also includes the correspondence between functions and pins defined in the existing schemes for the main drive motor controller and the shift controller. The above information together constitutes the pre-input of the structure-thermal-interface common mode planning. By unifying and itemizing these multi-source heterogeneous information, a structured data reference foundation is provided for subsequent collaborative design.

[0030] Specifically, in an integration method for a main drive motor controller and a shift controller, S110 uses structure-thermal-interface common-mode planning as a prerequisite. First, it obtains the housing geometry, mounting plane, fastening hole positions, rib distribution, sealing groove cross-section and orientation, and the range of gaps between the external mounting perimeter and the housing edge from the three-dimensional structural data of the main drive motor controller and the shift controller. Then, it obtains the specific locations of the inlet and outlet, the cross-sectional specifications of the cooling channels, the minimum allowable turning radius of the channels, the minimum spacing of channel branches, the allowable pressure drop range, and the safety distance from surrounding components from the cooling module data. To ensure that data from different sources can be directly accessed within the same reference system, S110 unifies the aforementioned geometric and cooling parameters to the same reference coordinates and naming conventions, and marks the reference lines of the mounting surface, the center references of the holes, the outlines of the sealing grooves, and the center lines of the channels, so that any subsequent step can reference these markings. Subsequently, S110 organizes connector information around the interface physical layer. Connector pin resource information includes interface socket model, number and size of interface socket cavities, types of terminals that can be fitted into each cavity, rated current range of terminals, temperature rating of terminals, shielding and grounding requirements, terminal position codes, allowable bending radii of terminals and wire harnesses, insertion and removal directions of the interface socket, and the operating space required for insertion and removal. It also includes corresponding entries for the functions of the main drive motor controller and shift controller in existing schemes. To achieve direct alignment for subsequent modeling, S110 categorizes the functions of all pins into five functional domains using unified terminology: power supply, signal acquisition, execution and drive, communication interaction, and diagnostics and maintenance. Pins within each functional domain are described using entries such as number, terminal type, current carrying capacity, shielding requirements, grounding method, temperature rating, and recommended wire harness diameter. Subsequently, S110 performs preliminary conflict screening on the housing geometry, sealing groove orientation, and cooling channel path: using the mounting plane, fastening hole positions, rib distribution, and spatial position of the sealing groove as constraints, it identifies areas that cannot be traversed, areas that can be traversed but must be sealed, and areas that can be directly passed through; using the channel centerline and turning radius as constraints, it identifies the minimum turning space for channel bends and the minimum safe distance for channel branches; using the insertion / removal direction of the interface socket and the operating space as constraints, it identifies the boundary areas where the outer surface window of the interface socket can be installed and where the wire harness outlet can be installed. S110 superimposes the above constraints onto a unified coordinate system and naming convention to form callable structural entries, sealing entries, and through-strip entries, and records the source, boundary shape, and availability status of each entry. Next, S110 maps the connector pin resource information to available outer surface windows, available wire harness outlets, and available mounting planes, marking connection paths that conflict with channel turning space, contradict sealed restricted areas, or overlap with fastener operating space as unavailable, and marking connection paths that meet the operating space and minimum spacing requirements as available.For connection paths marked as available, S110 calculates the set of reachable paths from the interface housing cavity to the harness outlet based on the harness's allowable bending radius and minimum laying spacing, and records the path length segments as reference data for subsequent power budgeting and harness planning. Through the above preprocessing, S110 outputs housing and water channel reuse constraint data. This data consists of four sets: structural entries, sealing entries, flow strip entries, and interface reachable path entries. Each set is assigned a unified index and availability status identifier for direct reference in subsequent modeling. Understandably, the housing and water channel reuse constraint data is not only used in S120 for extracting and modeling sealing boundary conditions and cooling channel parameters, but also serves as the boundary input for initial board-level layout in S200's multi-core load and low-voltage power supply collaborative partitioning, as the constraint background for external interface routing and installation windows in S300's chip-level interaction and task cycle table configuration, and as the initial boundary for interface reuse and harness planning in S600's unified topology and interface compact configuration.

[0031] S120. Extract sealing boundary conditions and cooling channel parameters from the shell and water channel reuse constraint data, perform structure-thermal-interface common mode planning modeling, and obtain connector pin mapping data. S120 takes the shared constraint data of the shell and water channels as input, uses the same coordinate system and naming convention to extract sealing boundary conditions and cooling channel parameters, and completes the structure-thermal-interface common model planning modeling in the same model. It outputs connector pin mapping data that can be directly used for interface and wiring harness design. Specifically, S120 first parses the sealing entries, unifying the cross-sectional specifications of the sealing groove, the press-fit depth and width, the compression section of the sealing material, the bridging length of the sealing ring, and the boundary lines of the sealing isolation area and the sealing passage area into a searchable boundary set. It further determines the boundary segments where interface seat openings can be set and the boundary segments where wiring harness passage holes can be set, and marks the sealing forbidden areas where openings are prohibited in the set with an index. Subsequently, S120 parses the channel entries, reading the inlet and outlet positions, channel cross-sectional specifications, channel centerline, channel turning points, channel branch points, and minimum safe distances from surrounding components. It cross-compares the turning radius and branch spacing with the internal ribs, bearing plates, and studs of the housing to determine the turning space for channel turns and the minimum clearance for channel branches, and marks the minimum safe distance between the channel and the interface seat in the set. In parallel, S120 searches for structural entries and interface reachable path entries, solidifying the available external surface windows, available harness exits, and reachable path sets into the model as interface candidate windows, harness candidate exits, and path candidate sets, ensuring that subsequent function-to-pin mapping can be filtered within the same space and boundary.

[0032] After the boundary sets are defined, S120 models the pin functional domains using unified terminology. First, following the order of power supply, signal acquisition, execution drive, communication interaction, and diagnostics and maintenance, pin entries within each functional domain are initially bound to interface candidate windows. During binding, both the sealed boundary set and the channel boundary set are searched, eliminating candidate windows that would fall into the sealed restricted area, have insufficient bridging length, insufficient channel turning space, or conflict with the minimum safe distance of the channel. Next, S120 checks the continuity between the filtered candidate windows and the candidate path set for the harness exit. Based on the harness bending radius, minimum laying spacing, and path stacking constraints, combinations that are too short leading to insufficient bending radius, paths that cross causing excessive stacking, or paths that are too long causing unnecessary detours are eliminated, retaining combinations that meet the continuity requirements. For the retained combination relationships, S120 performs consistency verification between the interface socket cavity, terminal type, terminal rating, shielding and grounding requirements and the pin entries. If the terminal rating is lower than the current carrying capacity recorded in the pin entry or the shielding and grounding requirements do not match, the combination is removed from the set. If the consistency is satisfied, the combination is fixed as a function-to-pin-to-cavity triplet entry, and the corresponding interface candidate window, harness candidate outlet, and path candidate set index are recorded. To ensure that the terminology is consistent with the subsequent control and calibration process, S120 identifies the type of terminals involved in communication and diagnostics in the triplet entry, so that they can be directly referenced as external interface lists in the subsequent generation of interaction signal tables and task cycle tables; and identifies the power supply domain of terminals involved in power supply and actuation drive, so that they can be directly checked as power supply domain terminal sets in subsequent power calculations and power integrity margin assessments. Based on the aforementioned screening, binding, and verification, S120 outputs connector pin mapping data. This data primarily consists of a triplet list from functional domain to pin number to interface socket cavity, supplemented by corresponding interface candidate window indices, harness candidate exit indices, and path candidate set indices, along with sealing constraint identifiers and channel constraint identifiers. This allows subsequent steps to directly retrieve the data without altering the coordinates and naming conventions. Understandably, this connector pin mapping data is not only directly used for interface grouping and boundary consistency verification in S130, but also indexed as an external interface constraint list in the full-process joint control orchestration of S400, used as the basis for interface reuse and harness planning in the unified topology and intensive interface configuration of S600, and used as a boundary reference for peripheral binding and board-level layout in the multi-core co-loading and low-voltage power supply collaborative partitioning of S200.

[0033] S130, perform interface grouping and boundary consistency verification on the pin mapping data of the docking plug, and generate structure-thermal-interface common mode planning constraint set data; S130 takes connector pin mapping data as input and forms the final structure-thermal-interface common mode planning constraint set data that can be directly called by subsequent processes, based on interface grouping and boundary consistency verification. Specifically, S130 first groups interfaces of power supply, signal acquisition, execution drive, communication interaction, and diagnosis and maintenance according to the triple list. Triples belonging to the same functional domain and having the same interface candidate window index are aggregated into interface grouping units. Based on the interface socket cavity geometry and insertion / removal direction, the relative arrangement of each cavity is determined within the same outer surface window to ensure that the terminal release space, insertion / removal operation space, and terminal polarity marking can be expressed within the same window. Subsequently, S130 performs three types of boundary consistency checks on each interface group unit: The first type is the sealing consistency check, which retrieves the sealing isolation line, sealing crossing line, and sealing restricted area within the sealing boundary set, and checks whether the interface opening position and the wire harness crossing hole position fall on the allowable line segment, whether the pressing section of the sealing material meets the pressing depth and width requirements, and whether the bridging length of the sealing ring meets the bridging range; The second type is the channel consistency check, which retrieves the channel center line, channel turning point, and channel branch position, and checks whether the interface seat shape and terminal release space intrude into the channel rotation space, whether the minimum safe distance is maintained between the wire harness candidate outlet and the channel branch, and whether the path in the path candidate set crosses the channel restricted area; The third type is the structural consistency check, which retrieves the installation plane, fastening hole position, and rib position distribution, and checks whether the geometric relationship between the interface seat fixing point and the fastening hole position meets the installation strength and assembly operation space, and whether there is direct interference between the terminal and the rib position. If any check item is not satisfied, S130 makes fine adjustments within the interface grouping unit according to the relative arrangement of cavities and the path candidate set, prioritizing the preservation of functional domain grouping, adjusting the cavity order or changing the path candidate set within the window's allowable range; if it still cannot be satisfied, it backtracks to S120 to select a new interface candidate window or harness candidate outlet, rebinds and generates a new triplet entry until consistency is satisfied.

[0034] After passing three types of consistency checks, S130 confirms the connectivity of each interface group based on the path candidate set index, checking each path length, bending radius, minimum laying spacing, and stacking limit one by one, and recording the confirmed paths in the form of a path list under the interface group unit. Subsequently, S130 archives the interface group unit, path list, and boundary check results to form three types of structured entries: interface group entries, path entries, and boundary check entries. It then establishes an index association between these three types of entries and the structural entries, sealing entries, and flow strip entries formed in S110, as well as the triplet list formed in S120, forming a complete callable entry system. Based on the above entry system, S130 generates structural-thermal-interface common mode planning constraint set data. This data is presented in the form of an indexed entry list, including at least shell and waterway reuse constraint entries, connector pin mapping entries, interface group entries, path entries, and boundary check entries. Each entry is given a unified index, unified naming, and reference relationship to ensure direct retrieval and consistent representation in subsequent steps. To achieve process-level closed loop, S130 specifies the following reference paths in the set data: In S210, peripheral binding and initial board-level allocation positions are determined according to interface grouping entries and mounting plane indexes; in S220, the power domain terminal set and path current carrying capacity are checked and power budgeted according to connector pin mapping entries and path entries; in S310, an external interface list of interaction signal table and task cycle table is generated according to communication interaction type and diagnostic and maintenance type interface grouping entries; in S610, interface multiplexing mapping and harness reduction list are constructed according to connector pin mapping entries and interface grouping entries; in S630, the topology connection diagram is checked and structural mapping is performed according to mounting plane, sealing boundary and channel boundary. Through the above indexed references, S130 ensures that the structure-thermal-interface common mode planning constraint set data runs through the implementation paths of S200, S300 and S600, and is continuously retrieved as an external interface and boundary list in S400 and S500.

[0035] This step, from S110 to S130, forms a continuous link from basic constraints to modeling mapping and then to group verification. This allows structural constraints, sealing constraints, and channel constraints to be extracted, bound, and verified under the same model, ultimately converging into a set of data that can be directly called by subsequent steps. This ensures that itemized connections and process-level closed loops are achieved between structure-thermal-interface common-mode planning, multi-core co-loading and low-voltage power supply collaborative partitioning, chip-internal interaction and task cycle table configuration, and unified topology and interface intensive configuration.

[0036] Step S200 includes at least steps S210-S230: S210. Obtain the structure-thermal-interface common mode planning constraint set data, perform multi-core load and low-voltage power supply collaborative partitioning pre-configuration, and obtain multi-core partitioning map data; In a method for integrating a main drive motor controller and a shift controller, S210 takes structural-thermal-interface common-mode planning constraint set data as input. This data includes housing and waterway reuse constraint entries, connector pin mapping entries, interface grouping entries, path entries, and boundary verification entries, all of which are invoked under the same coordinates and naming conventions. Specifically, S210 first reads the housing and waterway reuse constraint entries, mapping the reference plane, fixing holes, partition areas, and channel rotation spaces of the board-level layout one-to-one based on the installation reference, sealing reference, and channel reference. This solidifies the effective areas capable of supporting the processing unit and housing the power conversion module into a searchable set of regions. Simultaneously, it reads the interface grouping entries and path entries, spatially labeling the interface socket partitions, insertion / removal directions, wiring harness exits, and reachable paths required for peripheral binding, forming a peripheral interface boundary consistent with the region set. Furthermore, S210 retrieves the correspondence between functional domains, pin numbers, and interface socket cavities from the connector pin mapping entries, and assigns power supply, signal acquisition, execution drive, communication interaction, and diagnosis and maintenance categories as candidate sets for peripheral binding according to functional domains without changing the mapping relationship, so that subsequent processing units can bind and allocate at the functional domain level.

[0037] After the region set and candidate set are established, S210 performs pre-configuration around multi-core co-loading. Understandably, multi-core co-loading here does not change the physical form of the processor core, but rather divides the responsibility boundaries and task loads of processing units at the logical layer. S210 first, based on the timing characteristics of the entire shifting process during the disengagement, speed adjustment, and engagement phases, categorizes control tasks related to rapid closed-loop control into timing-sensitive domains, service tasks related to status monitoring, diagnosis, and calibration into service assurance domains, and tasks related to communication management and data gateways into communication hub domains. Then, referring to boundary check entries and path entries, it verifies the connectivity between each domain and interface grouping entry, confirming that the execution drive class and signal acquisition class terminals required by the timing-sensitive domain have coherent reachable paths within the corresponding interface partitions, confirming that the service assurance domain can directly access the diagnosis and maintenance class terminals and has connectivity with the calibration interface, and confirming that the communication hub domain can establish a stable physical link with the external network via the communication interaction class terminals. Based on the above verification results, S210 initially binds the three types of task domains to the processing units to form processing unit allocation information. Using the interface partitions, harness exits and path indexes required for peripheral binding as constraints, it establishes a one-to-one reference relationship between the peripheral entries of each functional domain and the corresponding processing units to form peripheral binding information.

[0038] To ensure the successful implementation of multi-core co-loading and low-voltage power supply zoning at the board level, S210, while generating processing unit allocation information and peripheral binding information, calls the channel reference in the housing and water channel reuse constraint entries to confirm the relative position and minimum safe distance between high heat flux density components and water channel passages. Based on this, it delineates the permissible hot zone range for each processing unit, avoiding the risk of conflicts with channel rotation space in subsequent power supply domain division. Subsequently, S210 outputs multi-core partitioning map data using unified coordinates and naming conventions. The multi-core partitioning map data has processing unit allocation information and peripheral binding information as its core content, and embeds reference indexes with installation references, sealing references, and channel references for direct retrieval in subsequent steps. Among them, the processing unit allocation information specifies the binding relationship between task domains and processing units, and the peripheral binding information specifies the binding relationship between functional domains and interface partitions, and between harness exits and path indexes. The multi-core partition map data serves as input to S220, used to extract processing unit allocation information and peripheral binding information and perform power calculations. It is also marked as the pre-boundary of the chip interaction and task cycle table configuration in S300 to ensure that the generation of subsequent interaction signal table data and task cycle table data follows the same physical and functional mapping.

[0039] S220. Extract processing unit allocation information and peripheral binding information from multi-core partition map data, perform multi-core load and low-voltage power supply collaborative partition power calculation, and obtain low-voltage power budget data and power integrity margin data. S220 takes multi-core partition map data as its sole input. This data includes processing unit allocation information, peripheral binding information, and reference indices to installation, sealing, and channel references. Specifically, S220 first parses the processing unit allocation information, expanding the processing unit lists corresponding to the timing-sensitive domain, service assurance domain, and communication hub domain, and loading the task set bound to each processing unit. Next, it parses the peripheral binding information, expanding the interface partitions, harness exits, and path indices corresponding to power supply, signal acquisition, execution drive, communication interaction, and diagnostic and maintenance classes, and loading the bound pin entries and terminal rating requirements for each functional domain. To ensure that power calculation and path constraints are performed under the same semantics, S220 calls the reference indices transferred by S210 to extract connector pin mapping entries and path entries from the structure-thermal-interface common-mode planning constraint set data. This allows each terminal to be associated with specific path lengths, allowable bending radii, and minimum laying spacing in power calculations, as well as specific shielding and grounding methods and harness diameter recommendations.

[0040] After data expansion and index association are completed, S220 performs low-voltage power budget-related aggregation. Specifically, S220 divides the power budget into three power supply domains: control logic power supply, execution drive power supply, and sensing and communication power supply. It then aggregates these domains by itemizing them according to the binding relationship between processing units and functional domains: For control logic power supply, S220 reads the list of processing units and their load entries within the timing-sensitive domain and service guarantee domain, combining terminal rating requirements and wire harness diameter recommendations in the path entries to form a load list for control logic power supply; for execution drive power supply, S220 reads the list of peripherals bound to the execution drive class, combining their terminal rating requirements and path length segments to form a load list for execution drive power supply; for sensing and communication power supply, S220 reads the list of peripherals bound to the signal acquisition class and communication interaction class, combining their shielding and grounding methods and path stacking limitations to form a load list for sensing and communication power supply. S220 checks the temperature rating of the terminals and the allowable bending radius of the wiring harness item by item on the three types of load list. If the path index of a certain peripheral device shows that the bending radius is insufficient or the stacking limit is triggered, the peripheral device is marked as a candidate object that needs to be adjusted in S230, and is temporarily stored as a conservative load entry in this calculation.

[0041] After the load list is established, S220 segments and summarizes the entries within each power supply domain to generate low-voltage power budget data. Simultaneously, it performs a continuity check on the path entries to confirm that there are no abnormalities such as limited heat dissipation due to excessively short paths or accumulated voltage drops due to excessively long paths between the designated interface partitions and harness exits. Furthermore, S220 conducts a margin assessment around power integrity, specifically checking the voltage stability and transient support capabilities at key nodes in each power supply domain. This involves verifying the path length and stacking limit information provided by the path entries, and relying on the terminal rating requirements, shielding, and grounding methods provided by the connector pin mapping entries, thereby locating potential fluctuations and couplings within the same entry system. When signs of insufficient margin are found at key nodes, S220 marks the corresponding processing unit and peripheral entries as candidates for resource adjustment, and records the power supply domain name, interface partition index, and path index that triggered the marking, for S230 to perform consistency verification and resource adjustment. At this point, S220 outputs low-voltage power budget data and power integrity margin data. Both data carry bidirectional references to processing units, peripherals, power supply domains, interface partitions, and path indexes, ensuring that subsequent steps can directly retrieve these data without altering coordinates and naming conventions. Understandably, the low-voltage power budget data will be used as one of the inputs to the task cycle boundary in S300's intra-chip interaction and task cycle table configuration. The power integrity margin data will be referenced as an external constraint for stage timing orchestration in S400's end-to-end joint control orchestration, and will be read as the power supply condition background for parameter tuning in S500's integrated joint calibration and consistency tuning.

[0042] S230. Perform consistency verification and resource adjustment on low-voltage power budget data and power integrity margin data to generate multi-core load and low-voltage power supply collaborative partitioning result data. The S230 takes low-voltage power budget data and power integrity margin data as inputs. Both low-voltage power budget data and power integrity margin data establish bidirectional references with processing units, peripherals, power supply domains, interface partitions, and path indexes. Specifically, S230 first performs a consistency check. Under a unified coordinate and naming convention, it checks the power supply for control logic, execution drive, and sensing and communication one by one, following the power supply domain as the main line: For control logic power supply, S230 calls the processing unit allocation information to check whether the load list of timing-sensitive domains and service guarantee domains is consistent with the corresponding power supply domains, and calls the boundary check items to check whether the hot zone range marked in the housing and waterway reuse constraint items is complied with; For execution drive power supply, S230 calls the interface grouping items and path items to check whether the peripherals and interface partitions and their paths conform to the sealed boundaries and channel boundaries, and checks whether the path stacking restrictions are met; For sensing and communication power supply, S230 calls the connector pin mapping items to check whether the shielding and grounding methods are consistent with the terminal rating requirements, and checks whether the path length segment and allowable bending radius are within the range of the extracted records. If an inconsistency occurs in any check step, S230 does not directly modify the aforementioned items themselves, but instead adjusts resources based on the processing unit allocation information and peripheral binding information in the multi-core partition map data.

[0043] Resource adjustments are made based on the differences in the consistency check. Specifically, for candidate objects triggered by path stacking restrictions, S230 prioritizes adjusting the cavity sequence and path index within the same interface partition, keeping the functional domain unchanged and minimizing changes to the interface partition and harness exit. If this is not possible within the same interface partition, candidate windows with the same shielding and grounding methods and compatibility with the sealed boundary and channel boundary are searched in adjacent interface partitions, and replaced according to the reachability index provided by the path entry. For candidate objects triggered by insufficient power integrity margin, S230 prioritizes load balancing at the processing unit level, migrating non-critical service tasks in the timing-sensitive domain and service guarantee domain between processing units to relieve load pressure on critical nodes. When load migration is still insufficient to meet margin requirements, S230 adjusts peripheral affiliation at the power supply domain level, transferring some high-occupancy peripherals in the execution drive power supply to the interface partition with shorter paths and more relaxed stacking restrictions, and synchronously updates the corresponding path index. After the power supply domain adjustment is completed, S230 calls the boundary check entry again to verify the sealed boundary and channel boundary to prevent new conflicts.

[0044] After all discrepancies have been adjusted and approved, S230 rewrites and solidifies the processing unit allocation information and peripheral binding information, forming multi-core load and low-voltage power supply collaborative partitioning result data. The multi-core load and low-voltage power supply collaborative partitioning result data records three aspects in an itemized structure: first, the final processing unit allocation information, indicating the task domain carried by each processing unit and the corresponding peripheral references; second, the final peripheral binding information, indicating the binding relationship between each functional domain and interface partition, harness exit and path index, and recording the shielding and grounding methods used; third, the power supply domain to processing unit and peripheral attribution list, indicating the load entries at the node level for control logic power supply, execution drive power supply and sensing and communication power supply and their association with path entries. To ensure seamless workflow, S230 synchronously embeds reference paths in the result data for direct retrieval by subsequent steps: Result data is acquired by S300 to generate interaction signal table data and task cycle table data, and provides a unified view of processing units and peripherals for boundary settings of target delay budget data; result data is acquired by S400 to construct external power supply constraints for phase timing orchestration data and torque and speed difference target trajectory data; result data is acquired by S500 as the power supply conditions and processing unit carrying conditions background for joint calibration parameter data and consistency index data; result data is acquired by S600 to call the final interface partition and path index in the generation of interface reuse mapping data and harness reduction list data. At this point, S230 completes consistency verification and resource adjustment and outputs multi-core co-loading and low-voltage power supply collaborative partitioning result data. Understandably, through the continuous implementation of S210 to S230, under the same coordinates and naming conventions, a closed-loop transfer is completed from constraint set to pre-configuration, from pre-configuration to power calculation, and from power calculation to consistency verification and resource adjustment. This enables processing unit allocation information, peripheral binding information, low-voltage power budget data, and power integrity margin data to be traceable and reused at the item level. In turn, it provides a directly callable boundary and reference basis for subsequent in-chip interaction and task cycle table configuration, full-process joint control orchestration, integrated joint calibration and consistency tuning, and unified topology and interface intensive configuration.

[0045] Step S300 includes at least steps S310-S330: S310: Obtain multi-core load and low-voltage power supply collaborative partitioning result data, perform chip-interactive and task cycle table configuration preprocessing, and obtain interactive signal table data and task cycle table data. In a method for integrating a main drive motor controller and a shift controller, S310 uses multi-core load and low-voltage power supply collaborative partitioning result data as the sole input. This result data includes final processing unit allocation information, final peripheral binding information, and a list of power supply domain affiliations to processing units and peripherals, embedded with reference indexes for installation references, sealing references, and channel references. Specifically, S310 first parses the final processing unit allocation information under a unified coordinate and naming convention, identifying the set of processing units responsible for fast closed-loop tasks related to shifting, speed regulation, and gear shifting; the set of processing units responsible for status monitoring, fault diagnosis, and calibration services; and the set of processing units responsible for communication aggregation and data forwarding. Simultaneously, it retrieves the final peripheral binding information, expanding the terminals within the five functional domains—power supply, signal acquisition, execution drive, communication interaction, and diagnosis and maintenance—along with interface partitions, harness exits, and path indexes, to form a searchable set of peripheral entries. To ensure that interaction construction and power supply constraints are carried out under the same semantics, S310 synchronously calls the power supply domain to the attribution list of processing units and peripherals, and marks the load entries of the three power supply domains—control logic power supply, execution drive power supply, and sensing and communication power supply—at the node level, so that the signal pairs extracted from the interaction perspective can be mapped to a clear power supply background.

[0046] After the aforementioned data expansion, S310 establishes a correspondence between signal sources and signal destinations based on the in-chip interactive preprocessing. Specifically, S310, according to the final processing unit allocation information, decomposes the task set of each processing unit into signal generation side entries and signal consumption side entries, and establishes bidirectional references between the two types of entries and the final peripheral binding information, so that any signal can obtain a unified identifier at the task level and the peripheral level. Subsequently, S310 uses the three stages of shifting, speed adjustment, and shifting as the timeline, and assigns stage affixes to signals related to stage switching, torque adjustment, speed difference management, synchronization mechanism control, clutch execution, and safety diagnosis, and marks signals used across stages as cross-stage entries to ensure that the timing continuity is maintained during subsequent interactive path extraction. To support the pre-configuration of subsequent task cycles, S310 adds a processing time limit field to each of the above signal entries to record the latest processing time available for scheduling on the generation side and the earliest time that the signal must be processed on the consumption side. The processing time limit field is determined by the task priority order in the final processing unit allocation information and the path length index recorded in the peripheral entry set, so that the order of processing and transmission can be uniformly expressed within the same entry system.

[0047] After the signal entries and processing time limits are fixed, S310 generates interactive signal table data and task cycle table data. The interactive signal table data requires fields such as signal name, source processing unit, destination processing unit, source peripheral entry, destination peripheral entry, stage affiliation, cross-stage marker, processing time limit, and power supply domain reference. It also records indexes of installation reference, sealing reference, and channel reference, enabling subsequent scheduling to understand physical boundaries without accessing the geometric model. The task cycle table data aggregates signal consumption-side entries and signal generation-side entries from the interactive signal table data, indexed by processing unit. It arranges the task sets within each processing unit according to stage affiliation and priority, and records the interactive signal list, peripheral entry list, and power supply domain reference list that the task set depends on in each entry. To ensure consistency between the two types of data, S310 cross-checks the interaction signal table data and the task cycle table data. If a task is found to be arranged in high priority order in the task cycle table data, but its dependent signal is marked as a cross-stage entry in the interaction signal table data, and the processing time limit field contradicts the earliest processing time of the task, then the entry is marked as a constraint pending entry in the current step, and will be calculated uniformly in subsequent steps before a decision is made. The output of S310 is the interaction signal table data and the task cycle table data, which are stored in a unified naming and unified index format, and respectively carry bidirectional reference relationships to the final processing unit allocation information, the final peripheral binding information, and the power supply domain to the processing unit and peripheral attribution list, serving as the sole input of S320.

[0048] S320: Extract key interaction paths and timing boundaries from interaction signal table data and task cycle table data, perform in-chip interaction and task cycle table configuration constraint calculations, and obtain target latency budget data. The S320 takes the interaction signal table data and task cycle table data output by the S310 as its sole inputs, and performs critical interaction path extraction and timing boundary calculation under the same coordinates and naming conventions. Specifically, the S320 first organizes the interaction signal table data into three sets: the picking stage set, the speed adjustment stage set, and the advancing stage set, based on stage affiliation. It then establishes horizontal references for cross-stage entries to ensure parameter continuity in subsequent constraint calculations at stage switching boundaries. Subsequently, the S320 traverses the signal entries in each stage set, and based on the correspondence between the source processing unit and the destination processing unit, as well as the path indexes recorded in the source peripheral entries and the destination peripheral entries, it concatenates them to form the shortest processing link and the shortest transmission link within the chip. It then performs entry-level aggregation on the task cycle, task priority, processing time limit fields, power domain references, and path length indexes involved in the link to form a candidate set of critical interaction paths. To avoid candidate sets containing links that conflict with power supply constraints or physical boundaries, S320 calls the power supply domain to the attribution list of processing units and peripherals during candidate set generation, verifying the support conditions at the node level for the three types of power supply domains: control logic power supply, execution drive power supply, and sensing and communication power supply. Simultaneously, it calls the installation reference, sealing reference, and channel reference indexes carried in the interaction signal table data and task cycle table data to check the physical connectivity corresponding to the path index. If a candidate link is found to have insufficient support for critical nodes in its power supply domain references, or if its path index is incompatible with the channel loop space, the candidate link is marked as unavailable, and a backtracking flag is issued in the current step for S330 to refer to during scheduling and orchestration.

[0049] After the candidate set is selected, S320 performs time boundary calculations on the key interaction paths. Specifically, S320 uses the task set of each processing unit in the task cycle table data as the time basis, reads the list of interaction signals that the task set depends on, compares the latest processing time of the signal generation entry with the earliest processing time of the signal consumption entry through entry reference, and defines the allocatable time window between the two as the first component of the time boundary; then, using the path length index and path stacking constraint recorded in the interaction signal table data as the spatial basis, and combining the reachable path sets of the source peripheral entry and the destination peripheral entry, it determines the shortest reachable channel of the signal in spatial connectivity, obtaining the second component of the time boundary; at the same time, using the power domain reference as the constraint basis, it transforms the steady-state support capability and transient support capability at the key node into the available processing gap, thereby limiting the allocatable processing share within the time window, obtaining the third component of the time boundary. S320 superimposes the above three components at the entry level to form an allocatable time window set for each critical interaction path, and retains unavailable links indicated by backtracking markers in the set so as to avoid them from being selected in subsequent scheduling.

[0050] After the timing boundaries are defined, S320 performs constraint calculations to generate target delay budget data. Constraint calculations are performed at the granularity of critical interaction paths, determining the tightest constraint in the allocable time window set for each of the three stages: pick-up, speed adjustment, and gear advancement. This tightest constraint serves as the upper bound of the processing share that can be allocated to that interaction path within that stage. For signals with cross-stage markers, S320 establishes a connection between the tightest constraints of adjacent stages, forming continuous time windows across stages to avoid gaps at stage transitions. For items with undetermined constraint markers, S320, without changing the task priority, compresses idle segments of lower-priority tasks within the same processing unit to free up necessary processing shares for that item, and records the compression results as notes under the task set of that processing unit. Finally, the S320 outputs the target delay budget data. The target delay budget data has the following required fields: interaction path identifier, stage affiliation, set of allocable time windows, index of the tightest constraint, continuous time window segment across stages, and notes on constraint pending processing. It also establishes a bidirectional reference relationship with the interaction signal table data and the task cycle table data, serving as the sole input to the S330.

[0051] S330: Schedule and orchestrate the target latency budget data and task lifecycle table data to generate in-chip interaction and task lifecycle table configuration result data; S330 takes the target delay budget data output by S320 and the task cycle table data output by S310 as its only inputs, and performs scheduling and orchestration under the same coordinates and naming conventions. Specifically, S330 first reads the task set in the task cycle table data on a processing unit basis, and splits the task set into the picking stage task segment, the speed adjustment stage task segment, and the advancing stage task segment according to the stage affiliation. It then establishes a one-to-one reference between the task entries in each task segment and the set of allocable time windows in the target delay budget data that they depend on. Subsequently, S330 performs two levels of orchestration within each stage: The first level is interaction path-level orchestration, which allocates non-overlapping processing segments to each interaction path according to the tightest constraint index recorded in the target latency budget data and the continuous time window across stages, and removes unusable links with backtracking markers from the candidate set; The second level is task-level orchestration, which refines the task entries that depend on the interaction path within the processing segment allocated to the interaction path according to the task priority and processing time limit fields, so that the earliest processing time of the task consumption side entries is consistent with the allocation start point of the interaction path, and the latest processing time of the task generation side entries is consistent with the allocation end point of the interaction path, so that the tasks and interaction paths are closely aligned on the time coordinate by a one-to-one matching method.

[0052] After the two-level orchestration is completed, S330 performs a global check on the interaction alignment relationship between processing units. Specifically, for interaction paths across processing units, S330 compares whether there is insufficient overlap or alignment offset in the processing segments allocated to the source and destination processing units. If an alignment offset occurs, the arrangement of low-priority tasks is adjusted first within the task segment of the destination processing unit to leave continuous segments for the arrival of the interaction path. If the adjustment is still insufficient, the time position of the signal generation side is adjusted within the task segment of the source processing unit until the two segments form an alignable interaction window. To ensure that power domain constraints are respected in scheduling, S330 performs power domain reference statistics on the processing segments of each processing unit in each stage. If the occupancy of a power domain in a certain stage exceeds the allowed segmented occupancy limit for that stage, the duration of non-critical task items in that stage is reduced or they are moved to other idle segments in the same stage without changing the interaction path allocation.

[0053] Finally, the S330 generates the on-chip interaction and task cycle table configuration result data. This data, organized by processing unit, records three aspects: first, a phased task timetable, listing the start and end times of each task item within the three phases of pick-up, speed adjustment, and gear advance, along with task priority and processing time limits; second, a phased interaction path timetable, listing the allocation start and end points of each interaction path within the corresponding phase, along with the tightest constraint index and cross-phase continuous time windows; and third, a power supply domain occupancy summary table, listing the segmented occupancy of each power supply domain within each phase, along with an index referencing the power supply domain's affiliation to the processing unit and peripherals. To form a closed-loop connection with subsequent steps, the S330 embeds a unified index with the installation reference, sealing reference, and channel reference in the data header, so that the entire process joint control and orchestration can directly read the stage timing orchestration data and torque and speed difference target trajectory data; and embeds the reference path of the final peripheral binding information and connector pin mapping entries in the data tail, so that the unified topology and interface compact configuration can be called when the interface multiplexing mapping and harness reduction list are generated.

[0054] S310 solidifies the interaction signal table data and task cycle table data into a consistent mapping between the processing unit and peripherals through a unified entry system. S320 calculates key interaction paths and timing boundaries on this entry system and generates target delay budget data. S330 completes scheduling and orchestration under the joint constraints of target delay budget data and task cycle table data and outputs the in-chip interaction and task cycle table configuration result data. The three form a continuous closed loop from partitioning results to interaction configuration under the same coordinates and naming conventions, and provide a directly callable and traceable timetable and interaction table basis for subsequent full-process joint control orchestration, integrated joint calibration and consistency tuning, and unified topology and interface intensive configuration. The continuous implementation of S310 to S330, while maintaining consistency with the installation reference, sealing reference, and channel reference, achieves unified integration and connection of stage affiliation, cross-stage marking, processing time limit field, power domain reference, path length index, and path stacking restriction from the binding view of the processing unit and peripherals. This enables the logical links of interaction within the chip and the time links of the task cycle to be synchronized and aligned at the item level, thereby providing configuration result data with a consistent index system for subsequent steps at the process level.

[0055] Step S400 includes at least steps S410-S430: S410: Obtain the configuration result data of the chip interaction and task cycle table, perform full-process joint control orchestration timing construction, and obtain stage timing orchestration data; In a method for integrating a main drive motor controller and a shift controller, S410 takes the configuration result data of the chip-interactive and task cycle table as input. This data includes a phased task timetable, a phased interaction path timetable, and a power supply domain occupancy summary table. A unified index for the installation reference, sealing reference, and channel reference is embedded in the data header. Specifically, S410 first interprets the phased task timetable according to three stages: shifting, speed adjustment, and shifting. Under the same coordinates and naming convention, the task entries of each processing unit are arranged into continuous segments according to their start and end times, forming a set of task segments within each stage. Simultaneously, the phased interaction path timetable is interpreted, reading the allocation start and end points of each interaction path. A mapping is established between the signal name associated with the interaction path, the source processing unit, the destination processing unit, and its cross-stage continuous time window segments, forming a set of interaction path segments. To ensure the availability of subsequent joint orchestration timing, S410, while reading the power domain occupancy summary table, marks the segmented occupancy results of control logic power supply, execution drive power supply, and sensing and communication power supply in each stage onto the corresponding task segments and interaction path segments, ensuring that each time segment has a clear power domain reference. Subsequently, based on the indexes of the installation reference, sealing reference, and channel reference, S410 retrieves the interface partitions and path indexes related to the execution drive, confirming that the physical connectivity conditions required for deploying synchronization mechanism control, clutch execution, and main drive speed regulation within the stage have not been disrupted, and identifies interface partitions with physical adjacency constraints as tightly coupled partitions, serving as boundary items during timing construction.

[0056] After the segment set and boundary items are determined, S410 constructs the timing sequence for the entire process joint control orchestration. Specifically, S410 uses the stage as the main line and performs two-layer alignment on the task segment set and interaction path segment set for each stage: The first layer is intra-segment alignment, that is, within the same stage, using the allocation start and end points of the interaction path segment as anchor points, the start and end positions of the task segments directly associated with the interaction path are adjusted so that the latest processing position on the signal generation side is no later than the start point of the interaction path segment, and the earliest processing position on the signal consumption side is no earlier than the end point of the interaction path segment, thereby forming non-overlapping execution windows within the same stage; The second layer is boundary alignment, that is, between adjacent stages, using the cross-stage continuous time window segment as anchor points, the interaction path segments of the two stages are spliced ​​together, the end point of the cross-stage item is matched with the start point of the corresponding item in the next stage, and a stage switching mark is recorded at the matching position. For an interface partition identified as a tightly coupled partition, S410, while aligning the two layers mentioned above, calls the indices of the sealing reference and the channel reference to check whether there is any temporary occupation overlap in the path index corresponding to the interface partition. If there is overlap, without changing the relative order of the interaction path segments, it performs a micro-shift on the low priority entries in the task segment set, releases the temporary occupation of the interface partition, and updates the corresponding start and end times.

[0057] To ensure that the boundaries of power supply domains are reflected in the timing structure, S410 performs threshold checks on the segmented occupancy of each power supply domain within each stage. If the number of occupancy entries for a power supply domain in any time slice exceeds the available upper limit given in the power supply domain occupancy summary table, segment compression and migration are implemented in the local time slice: the duration of non-critical task segments is compressed first; if the limit is still exceeded after compression, the non-critical task segment is migrated to the idle time slice of the same stage, and the associated interaction path segment reference is added at the migration location. Through intra-segment alignment, boundary alignment, and power supply domain checks, S410 integrates the task segments and interaction path segments at the processing unit level into a stage-level joint timeline, forming a stage timing draft that includes stage switching markers, segment start and end positions, interaction path references, and power supply domain references. Subsequently, S410 performs a consistency review of the draft phase timing, comparing the phased task timetable with the phased interaction path timetable to ensure that every task segment can find a corresponding signal in the interaction path segment, and every interaction path segment can find corresponding generation and consumption entries in the task segment set. If an isolated segment is found, a minimum compensation segment is inserted in the current phase according to the original priority order, and a signal reference is established. Finally, S410 outputs phase timing orchestration data. The phase timing orchestration data is indexed by phase and records the joint timeline, phase switching markers, segmented power supply domain occupancy, tightly coupled partition list, and their reference relationships with installation reference, sealing reference, and channel reference, serving as the sole input to S420.

[0058] S420. Extract the stage boundary and speed difference target from the stage timing arrangement data, perform full-process joint control arrangement trajectory generation, and obtain torque and speed difference target trajectory data. S420 takes stage timing data as input and processes it around the extraction and trajectory generation of stage boundaries and speed difference targets to form torque and speed difference target trajectory data that can be directly referenced in subsequent parameter tuning. Specifically, S420 first reads the joint time axis and stage switching markers from the stage timing data, and linearly expands the start and end positions of each stage segment according to time sequence to obtain the stage boundary set; at the same time, it retrieves the tightly coupled partition list and marks the positions of segments involving synchronization mechanism control, clutch execution, and main drive speed regulation, thereby establishing two subsets in the stage boundary set: synchronization-related boundaries and execution-related boundaries. Subsequently, S420 calls the signal reference relationships established in S310 and S320, extracts signal entries related to speed difference estimation, synchronization target calculation, and torque adjustment commands from the joint time axis, and concatenates their distribution positions within the stage with their continuity relationships between stages to generate time indices for the speed difference observation sequence and torque reference sequence. To ensure that the generated trajectory is consistent with the physical boundary, S420 overlays the power supply domain reference and the path index of the tightly coupled partition on the aforementioned time index to confirm that there are no cases where the power supply domain is unavailable or the path is unreachable at the key nodes of the trajectory segment; if there are, an available alternative node is inserted into the time index, and the signal references of adjacent segments are re-associated.

[0059] After establishing the stage boundaries and time indexes, S420 initiates the generation of the entire process joint control orchestration trajectory. Specifically, S420 segments the speed difference observation sequence and torque reference sequence on a stage-by-stage basis: In the disengagement stage, based on the interactive path references in the joint time axis, it extracts segmented sequences related to clutch engagement, disengagement synchronization, and main drive deceleration, and implements these segmented sequences as clutch control segments, synchronization control segments, and main drive deceleration segments within the corresponding stage boundaries; in the speed regulation stage, it extracts segmented sequences related to speed difference tracking, speed transition, and synchronization propulsion, and implements them as speed difference tracking segments, speed transition segments, and synchronization propulsion segments; in the gear engagement stage, it extracts segmented sequences related to gear engagement promotion, clutch engagement, and main drive recovery, and implements them as gear engagement promotion segments, clutch engagement segments, and main drive recovery segments. For each segment, S420 assigns a clear start and end point based on the segment's start and end positions in the joint time axis, and establishes a signal drive sequence within the segment according to the order of interactive path references, giving the segment an itemized structure that can be progressively invoked by the execution unit. Subsequently, S420 performs connection processing on adjacent segments: when there is a gap between upstream and downstream segments on the time axis, S420 inserts a transition segment at the gap position and performs consistency verification between the transition segment and the power supply domain reference; when upstream and downstream segments overlap on the time axis, S420 prioritizes retaining the segment associated with the tightly coupled partition and shortens or shifts the other segment without changing the stage boundary until the overlap is eliminated.

[0060] To form a target trajectory that can be directly indexed by subsequent tuning, S420 splices the fragmented sequences within each stage in segment order to generate a torque target segment sequence and a speed difference target segment sequence within the stage, and verifies the continuity across stages: for signal references with continuous time windows across stages, S420 establishes continuous segment markers at the splicing boundaries between two stages, and records the end position of the previous stage and the start position of the next stage on the continuous segment markers to ensure that there are no undefined segment gaps at the stage switching markers. Subsequently, S420 merges the two types of segment sequences within a stage into a target trajectory set within the stage, and merges the target trajectory sets of the three stages into a full target trajectory set; during the merging process, S420 retains the priority of trajectory segments related to tightly coupled partitions, and compresses non-tightly coupled segments in time slices with locally high occupancy, using the power supply domain occupancy summary table as a reference. Through segment generation, segment connection and trajectory merging, S420 outputs torque and speed difference target trajectory data. The torque and speed difference target trajectory data are indexed by stage, including the target trajectory set within the stage, continuous segment markers, tightly coupled partition priority labels and power supply domain references, and establishes a bidirectional reference relationship with the stage timing arrangement data, serving as the sole input of S430.

[0061] S430, Constrain matching is performed on the torque and speed difference target trajectory data and the stage timing arrangement data to generate the joint control configuration result data for the entire process; The S430 takes torque and speed difference target trajectory data and stage timing arrangement data as input, performs constraint matching under the same coordinates and naming conventions, and produces the joint control configuration result data for the entire process. Specifically, the S430 first aligns the two types of inputs at the stage level: it reads the joint time axis and stage switching markers in the stage timing arrangement data, and projects the target trajectory set within the stage in the torque and speed difference target trajectory data onto the joint time axis to form a target trajectory alignment view; in the target trajectory alignment view, the S430 locates the continuous segment markers and tightly coupled partition priority labels one by one, indicating the set of segments that need to be satisfied first. Subsequently, S430 calls the segmented power domain occupancy and tightly coupled partition list in the stage timing orchestration data to perform power domain consistency and path connectivity checks on the target trajectory alignment view: when the power domain occupancy of a time slice containing a trajectory segment exceeds the available limit, S430 prioritizes adjusting the position of adjacent non-tightly coupled segments within the same stage to bring the occupancy of that time slice into the available range; if the adjustment is still insufficient, the duration of the segment in that time slice is shortened without changing the stage switching marker, and the shortened portion is moved to an idle time slice in the same stage; when the path index of a trajectory segment is inconsistent with that of a tightly coupled partition, S430 inserts a preparation segment before the segment and a release segment after the segment to ensure that the paths to and from the tightly coupled partition are reachable, and synchronizes the two inserted segments with the joint time axis.

[0062] After verifying the power supply domain and path, S430 performs item-level matching between the target trajectory and the task segment. Specifically, S430 uses the target trajectory set within the stage as the main line, searches for task segments in the stage's timing arrangement data that coincide with the time and have the same signal reference, forming candidate mappings from trajectory to task. If multiple task segments can map the same trajectory segment, S430 sorts them according to the priority of tightly coupled partitions, prioritizing the task segments associated with tightly coupled partitions. If no mappable task segments exist, S430 calls the staged interaction path time table, finds the interaction path segment related to the signal within that time slice, and inserts the smallest task segment on both sides to establish a mapping relationship. After all candidate mappings are determined, S430 resolves conflicts in the mapping set: when two trajectory segments are mapped to the same task segment and overlap, S430 adjusts the local start and end positions of the two segments according to the allocation start and end points of the interaction path segment to make the overlap disappear; when a trajectory segment is mapped to two task segments and there is a gap, S430 inserts a connecting segment in the gap and records the correspondence between the connecting segment and the joint time axis.

[0063] After item-level matching and conflict resolution are completed, S430 performs a final check on the consistency of the entire process. Specifically, S430 compares the trajectory segments at the end of the previous stage with the trajectory segments at the beginning of the next stage, using the stage switching marker as the boundary, to confirm that the two ends indicated by the continuous segment markers have been aligned through the task segments; it also checks the high-occupancy time slices on the entire time axis with reference to the power supply domain occupancy summary table to confirm that there are no new occupancy peaks; and it performs a geometric reachability check on the mapping pairs executed within the tightly coupled partition, using the installation reference, sealing reference, and channel reference as constraints, to confirm that there are no arrangements that cross prohibited boundaries or weaken the sealing pressure fit. Finally, the S430 generates the overall joint control configuration result data. The overall joint control configuration result data is indexed by stage and records the joint time axis, the mapping list from trajectory to task, the list of connection sections and preparation and release segments, the stage switching mark and continuous segment mark, the segmented power supply domain occupancy verification result, and the reference path with the installation reference, sealing reference, and channel reference. In addition, the data end provides bidirectional references to the interaction signal table data, task cycle table data, and torque and speed difference target trajectory data, so that subsequent integrated joint calibration and consistency tuning can directly read the solidified time and trajectory relationship in this result data, and the unified topology and interface compact configuration can be based on this to improve the interface reuse mapping and harness reduction list.

[0064] S410 obtains stage timing arrangement data through staged alignment and boundary verification. Based on this data, S420 generates torque and speed difference target trajectory data consistent with power supply domain and path constraints. S430 completes constraint matching with the two types of data as input and outputs the joint control configuration result data of the whole process. Thus, a closed-loop configuration link from timing to trajectory and from trajectory to task is formed under the same coordinates and the same naming standard, ensuring that subsequent steps can be directly called and reused without rebuilding the boundary and repeating the alignment.

[0065] Step 500 includes at least steps S510-S530: S510. Based on the configuration result data of the whole process joint control and the target trajectory data of torque and speed difference, the joint calibration model is trained to obtain the pre-trained joint calibration model. In a method for integrating a main drive motor controller and a shift controller, S510 uses the full-process joint control configuration result data and torque and speed difference target trajectory data as paired inputs to conduct a training process. The full-process joint control configuration result data includes a joint time axis, a mapping list from trajectory to task, a list of connection sections and preparation and release segments, stage switching markers and continuous segment markers, segmented power supply domain occupancy verification results, and reference paths to installation reference, sealing reference, and channel reference. The torque and speed difference target trajectory data includes the target trajectory set within the stage, continuous segment markers, tightly coupled partition priority labels, and power supply domain references. Specifically, S510 first aligns the two types of inputs under a unified coordinate and naming convention: using the joint time axis as the time skeleton, the target trajectory set is divided into three segments: pick-up segment, speed adjustment segment, and gear advance segment, and each trajectory segment is mapped to a specific task segment according to the trajectory-to-task mapping list; adjacent segments with continuous segment markers are spliced ​​according to the stage switching markers to form a continuous training spline across stages; for segments with tightly coupled partition priority markers, path indexes corresponding to the installation reference, sealing reference, and channel reference are added to make the spline traceable in terms of spatial constraints. Subsequently, S510 extracts the occupancy entries of control logic power supply, execution drive power supply, and sensing and communication power supply in each time slice from the segmented power supply domain occupancy verification results, as the constraint-side attributes of the training spline, which together with the torque target and speed difference target entries on the spline constitute the sample entry set.

[0066] After the sample entry set is determined, S510 performs sample grouping and window alignment: Stage sample clusters are established on a stage-by-stage basis, merging time-adjacent entries within the same stage that map to the same task segment into a single training window; for training splines that span consecutive stages, cross-stage sample clusters are established to ensure that the window boundary at the stage switching marker is consistent with the start and end positions of adjacent stages; for splines containing connection segments or preparation and release segments, auxiliary entries are added to both ends of the window to ensure that the training window fully covers the start and end of the task segment. Subsequently, S510 sets sample weight indexes based on the tight-coupling partition priority label, prioritizing windows involving synchronization mechanism control, clutch execution, and main drive speed regulation during training; simultaneously, the executability of samples is verified by power supply domain references. When the power supply domain occupancy of any time slice within a window reaches its available limit, the window is marked as a restricted window, and restricted updates are performed in subsequent parameter estimation stages. To improve the stability of training data, the S510 performs consistency cleaning on the sample entry set: for isolated entries lacking mapping pairs, the minimum necessary entries are added based on the list of connection segments and preparation and release segments; for entries with duplicate mappings, the first item is retained according to the original order from trajectory to task, and the remaining entries are grouped together to maintain the monotonicity of the entry sequence. Through alignment, grouping, and cleaning, the S510 forms a structured training sample library.

[0067] Subsequently, the S510 constructs the training input and output of the joint calibration model on the training sample library. Specifically, the training input consists of three parts: first, the time part, including the start and end positions of the window, stage switching markers, and continuous segment markers; second, the spatial and physical constraint part, including tightly coupled partition priority labels, path indexes, and reference paths to installation references, sealing references, and channel references; and third, the resource constraint part, including the occupancy entries for control logic power supply, execution drive power supply, and sensing and communication power supply for each time slice, as well as window restriction markers. The training output consists of two types of targets: one is torque target entries, which record the itemized description of the torque change amount and torque change sequence to be achieved within the window; the other is speed difference target entries, which record the itemized description of the speed difference change amount and speed difference change sequence to be achieved within the window. Without changing any original field semantics, the S510 binds the above inputs and outputs one by one into sample pairs, and establishes clustered training sequences according to the grouping relationship between stage sample clusters and cross-stage sample clusters.

[0068] After the sample pairs are established, S510 performs cluster-by-cluster iterative training. For stage sample clusters, S510 updates the model according to the sequence order of the joint time axis, using sample pairs within the stage as sequence units, so that the model learns the correspondence between trajectory segments and task segments within a single stage. For cross-stage sample clusters, S510 maintains window overlap at stage switching markers and uses continuous segment markers as glue terms for sequence boundaries, prompting the model to learn continuity constraints between adjacent stages. For restricted windows, S510 only allows entries within the window that do not conflict with power domain occupancy to participate during updates, and postpones the impact of other entries to the window corresponding to the next available time slice. During training, S510 continuously calls the trajectory-to-task mapping list to verify whether each update is still consistent with the mapping relationship; calls the connection segment and preparation and release segment lists to ensure that the updated entries have path connections when entering and leaving tightly coupled partitions; and calls the segmented power domain occupancy verification results to ensure that any update does not introduce new occupancy peaks in the same time slice. After iterative convergence, S510 obtains the pre-trained joint calibration model and writes the joint time axis index, stage switching marker, continuous segment marker, tightly coupled partition priority label, and power supply domain reference resolution rules into the model metadata, so that the model can directly receive data structures consistent with the above fields in subsequent inferences. The output of S510 is the pre-trained joint calibration model, and it maintains bidirectional references to the joint control configuration result data and torque and speed difference target trajectory data of the entire process, serving as the sole model source for S520.

[0069] S520. Input the configuration result data of the whole process joint control into the pre-trained joint calibration model to generate joint calibration parameter data; The S520 takes the joint control configuration result data of the entire process as input and feeds it into the pre-trained joint calibration model to carry out the estimation process. Specifically, the S520 first checks the consistency of the joint time axis, the mapping list of trajectory to task, and the list of connection segments and preparation and release segments to confirm that it is consistent with the parsing rules during the training of the S510. Then, the stage switching marker and continuous segment marker are loaded as sequence control terms, so that the model generates parameter entries segment by segment along the sequence of stages and the continuous relationship across stages during estimation. For task segments with tight coupling partition priority labels, the S520 attaches the priority label and path index to the model input, so that the entry updates in the model achieve higher generation density in segments close to the synchronization mechanism control and clutch execution. For time slices with limited window markers, the S520 attaches the relevant occupancy entries from the segmented power domain occupancy verification results to the model input, so that the model only generates parameter entries that meet the available occupancy in that time slice.

[0070] During parameter entry generation, the S520 establishes parameter clusters in stages: In the disengagement stage, it generates clutch release-related parameter entries, main drive torque unloading-related parameter entries, and synchronization leader-related parameter entries, aligning them with the start and end positions of the task segment and the start and end points of the interaction path allocation; in the speed regulation stage, it generates speed difference tracking-related parameter entries, speed transition-related parameter entries, and synchronization propulsion-related parameter entries, splicing entries with continuous segment markers with adjacent stages; in the gear engagement stage, it generates engagement promotion-related parameter entries, clutch engagement-related parameter entries, and main drive recovery-related parameter entries, appending the necessary closing entries for the release segment at the end of the task segment. To facilitate subsequent consistency calculations, the S520 binds a source mapping pair, the stage it belongs to, the power supply domain reference of the time slice it belongs to, and a tightly coupled partition priority label next to each parameter entry to form a traceable list of parameter entries.

[0071] Subsequently, S520 performs union-based integration of intra-stage and inter-stage parameter clusters to generate joint calibration parameter data. This joint calibration parameter data is indexed by stage and includes a list of parameter entries, mappings from entries to task segments, references from entries to interaction path segments, references from entries to power domain occupancy entries, and path indices from entries to installation references, sealing references, and channel references. It also retains an alignment table at the end of the data, showing alignment with the joint timeline, stage switching markers, and continuous segment markers. To ensure seamless integration with subsequent steps, S520 adds reference entries for connector pin mapping entries and placeholders related to interface multiplexing mappings to the header of the joint calibration parameter data. This allows for direct resolution of interface-side constraints based on the unified topology and interface compact configuration. The output of S520 is the joint calibration parameter data, which serves as the sole input for S530's consistency calculations and parameter tuning.

[0072] S530. Perform consistency calculation and parameter tuning on the joint calibration parameter data to generate consistency index data; S530 takes joint calibration parameter data as input and performs consistency calculations and parameter tuning around three types of constraints: time consistency, spatial consistency, and resource consistency, generating consistency index data. Specifically, S530 first reads the alignment table in the joint calibration parameter data and reconstructs the parameter entries into intra-stage parameter sequences and cross-stage parameter sequences on the joint time axis according to stage switching markers and continuous segment markers. For intra-stage parameter sequences, S530 checks the mapping relationship from entries to task segments and the reference relationship from entries to interaction path segments, confirming that each entry is within the intersection of its mapped segment and referenced segment. If an entry is found to be out of bounds, it is locally shifted within the sequence without changing the order of adjacent entries, so that the entry re-enters the intersection range. For cross-stage parameter sequences, S530 checks the connection between the beginning and end of continuous segment markers at the stage switching marker. If there is a gap, it adds a minimum connection entry without changing the continuous segment marker and binds it to the adjacent task segment.

[0073] Regarding spatial consistency, S530 calls the path index recorded in the parameter entry and the reference path of the installation reference, sealing reference, and channel reference. For entries with tight-coupled partition priority markings, geometric reachability verification is performed: when an entry is located in a tight-coupled partition and the channel pointed to by the path index is inconsistent with the channel of the current segment, S530 inserts a preparation entry before the entry and a release entry after the entry, so that the parameter sequence has a clear path switching process when entering and leaving the partition; when there is a pressure fitting conflict between the entry and the sealing reference, S530 performs a minimum time translation on the dwell position of the entry and adds a sealing alignment mark at the translation position, recording the latest relationship between the entry and the sealing boundary.

[0074] Regarding resource consistency, the S530 establishes a time-slice-level occupancy overlay view based on the reference relationship between entries and power domain occupancy entries, calculating the total occupancy of control logic power supply, execution drive power supply, and sensing and communication power supply for each slice. When an occupancy exceeds the limit in a certain time slice, the S530 adopts a two-step tuning process: First, within that time slice, the duration of non-tightly coupled partition entries is preferentially compressed, and the compressed amount is carried over to the idle time slice of the same stage; Second, if the occupancy still exceeds the limit, the positions of adjacent non-critical entries in the cross-stage parameter sequence are slightly shifted to bring the occupancy of the time slice that exceeds the limit back to the available range. After the above tuning is completed, the S530 performs a final check on all parameter sequences to confirm that there are no new out-of-limit or conflicting events.

[0075] Finally, the S530 summarizes the results of consistency calculation and parameter tuning into consistency index data. This consistency index data is indexed by stage and includes sets of time consistency entries, spatial consistency entries, and resource consistency entries. It records the location and magnitude of out-of-bounds corrections, geometric reachability verification results and path switching records, time-slice-level power domain occupancy and tuning trajectories, respectively. The data header provides a reverse reference to the joint calibration parameter data, and the data tail provides reference entries to connector pin mapping entries and placeholders for interface reuse mappings, enabling direct access for unified topology and interface aggregation configuration. In essence, the consistency index data generated by the S530 provides a parameter-side constraint baseline for subsequent unified topology and interface aggregation configuration, while maintaining consistent indexing with the overall joint control configuration results data, torque and speed difference target trajectory data, and joint time axis, thus closing the chain from structural constraints, task timing, target trajectory to parameter configuration at the data level.

[0076] In summary, S510 obtains a pre-trained joint calibration model through sample alignment, window grouping, and constrained updates. S520 generates joint calibration parameter data carrying mapping, reference, and constraint information under model-driven conditions. Based on this, S530 completes consistency calculation and parameter tuning for time, space, and resources, and forms consistency index data. Thus, within a semantic framework consistent with the joint time axis, phase switching markers, continuous segment markers, tightly coupled partition priority annotations, and power supply domain references, a continuous link from configuration to parameters to consistency is realized, providing a directly usable constraint and reference foundation for subsequent unified topology and interface intensive configuration.

[0077] Step S600 includes at least steps S610-S630: S610: Obtain consistency index data and connector pin mapping data, perform unified topology and interface compact configuration constraint parsing, and obtain interface reuse mapping data; In an integration method for a main drive motor controller and a shift controller, S610 uses consistency index data and connector pin mapping data as input to perform unified topology and interface intensive configuration constraint parsing. Specifically, firstly, the consistency index data is loaded at the item level, and three types of indexes are established according to the existing grouping of time consistency item sets, spatial consistency item sets, and resource consistency item sets. During the loading process, the stage switching markers and continuous segment markers from the time consistency item sets are reconstructed into joint time axis references, so that subsequent path parsing can be performed under the same time skeleton. The path switching records, seal alignment markers, and reference paths with installation references, seal references, and channel references from the spatial consistency item sets are deduplicated and ordered, forming a path constraint table that can be searched item by item. The time-slice-level power supply domain occupancy and setting trajectory from the resource consistency item sets are used as the input database to form a power supply domain occupancy view. Subsequently, the pin mapping data of the docking plug is loaded on the interface side. An initial mapping from pins to functional domains is established based on pin naming conventions and functional domain classifications (control logic, execution drive, sensing, and communication). For pins with physical location markings, the relative position descriptions with the housing surface, sealing boundaries, and cooling channels are read and recorded in the interface geometry table. For interface groups already completed in the structure-thermal-interface common-mode planning phase, the order within the group and boundary consistency markers remain unchanged, serving as the basic unit for subsequent reuse judgment. At this point, the input loading of the S610 is complete, and its output target is set to the interface multiplexing mapping data.

[0078] Based on the three types of indexes, path constraint table, power domain occupancy view, and interface geometry table that have been completed, S610 performs constraint resolution. Specifically, it traverses the task segments of each stage according to the joint timeline. For parameter entries within each task segment, it retrieves the corresponding path switching records and reference paths to the installation reference, sealing reference, and channel reference in the path constraint table to determine the connection paths that the entries depend on. Then, using the time slice occupancy of the entry in the resource consistency entry set as the key, it retrieves the occupancy entries for control logic power supply, execution drive power supply, and sensing and communication power supply from the power domain occupancy view and marks them as entry resource-side attributes. Subsequently, using the functional domain pointed to by the entry as a clue, it searches for a set of candidate pins in the connector pin mapping data that meet the requirements of functional domain consistency, geometric reachability, and boundary consistency identifier matching. For each candidate set, it combines the description of the relative positions of the shell surface, sealing boundary, and cooling channel in the interface geometry table to filter out candidates that cross the sealing boundary or intrude into the cooling channel, and retains candidates that are consistent with the path switching record, forming a candidate relationship between the entry and the pin. For candidate relationships that are referenced by multiple entries, S610 calls the group order and boundary consistency flag for secondary pruning. When there are pin pairs in the group that are naturally continuous and share a joint time axis segment with adjacent entries, they are marked as reusable pairs.

[0079] After obtaining the candidate relationships and reusable pairs from entries to pins, S610 enters the multiplexing and merging stage. Specifically, firstly, candidate relationships are aggregated into candidate groups according to task segments and functional domains, and reusable pairs in the candidate groups are merged to form pin multiplexing entries for the same connection path. Subsequently, the power supply domain occupancy view is called at the time slice level, and the occupancy overlap of each pin multiplexing entry within the same time slice is calculated. When the overlap reaches the occupancy limit on the control logic power supply or sensing and communication power supply side, the pin multiplexing entry is marked as a restricted multiplexing entry, and its alternative segment on the joint time axis is recorded for path detour in the subsequent harness planning stage. Pin multiplexing entries that do not reach the occupancy limit and whose boundary consistency identifier remains stable are marked as regular multiplexing entries. To ensure the physical feasibility of reuse entries, S610 calls the interface geometry table again to search for the geometric adjacency relationship between regular reuse entries and restricted reuse entries. If an interface interference risk is found on the same housing surface, records of interface position reservation and interface position clearance are inserted before and after the reuse entry, respectively, so as to facilitate the subsequent planning of wire harness vias and adapters.

[0080] Finally, S610 binds the aforementioned candidate groups, pin multiplexing entries, restricted multiplexing entries, regular multiplexing entries, and records of interface position reservations and interface position yielding into interface multiplexing mapping data according to the hierarchical structure of task segment → connection path → functional domain → pin pair. A reverse reference to the consistency index data is retained in the data header, and a reverse reference to the connector pin mapping data is retained in the data tail to ensure data link continuity with the preceding steps. S610 uses the interface multiplexing mapping data as the sole output, providing S620 with directly extractable connection paths and node grouping criteria.

[0081] S620. Extract connection paths and node groups from the interface reuse mapping data, perform unified topology and interface compact configuration harness planning, and obtain harness reduction list data. The S620 takes interface reuse mapping data as input and performs unified topology and interface compact configuration harness planning around connection paths and node grouping. Specifically, firstly, in the interface reuse mapping data, connection paths are enumerated by task segment. For each connection path, its functional domains and pin pairs are collected, and pin pairs are merged into node candidates using the functional domain as the key. For pin pairs marked as regular reuse entries, their functional domains are directly confirmed as nodes. For pin pairs marked as restricted reuse entries, they are temporarily confirmed as nodes and detour flags are set, waiting to be replaced and merged during subsequent path deployment. After completing the extraction of node candidates, the S620 splices adjacent connection paths according to the sequence of task segments to form a connection path chain within a stage. For continuous connection path chains across stages, cross-stage splicing is performed based on continuous segment markings to ensure that the node candidate set is continuously referenced on the joint time axis.

[0082] After obtaining the connection path chain and node candidate set, S620 performs harness layering and segment division. Specifically, S620 uses the assembly mounting reference outside the housing as a starting point and clusters the connection path chains according to spatial projection into a main harness layer and a branch harness layer; the main harness layer carries collinear pin pairs across functional domains, and the branch harness layer carries the terminal leads leading into specific nodes. For collinear segments of adjacent connection path chains within the main harness layer, S620 establishes a main harness segment and marks the reserved interface positions and interface position clearance records; for paths branching from the main harness segment to a single node within the branch harness layer, S620 establishes a branch harness segment and records the access method leading out from the main harness segment at the beginning of the segment. Subsequently, S620 retrieves the pin pairs contained in each trunk harness segment and branch harness segment, calls the multiplexing entry information in the interface multiplexing mapping data, performs intra-bundle merging and strip merging on pin pairs with the same functional domain and physically adjacent within the same segment, and converges multiple parallel entries into a single or a small number of entries; for restricted multiplexing entries with detour markers, temporary detour bundle segments are established on adjacent trunk harness segments or branch harness segments according to their replacement segments, and connection records with the original segment are established at the start and end positions of the detour bundle segments.

[0083] After completing the segment division, S620 performs harness counting, length estimation, and merging planning. Specifically, S620 counts the change in the number of pin pairs before and after merging for each main harness segment, recording this as main harness merging statistics; it also counts the change in the number of pin pairs before and after merging for each branch harness segment, recording this as branch merging statistics; based on the spatial distribution of the connection path chain, it provides a length estimate for each harness segment, and adds the length increment introduced by the interface position reservation and interface position yielding records; for paths with temporary bypass harness segments, it records the alternative length on the bypass harness segment and the alternative empty space on the original harness segment. Subsequently, S620 summarizes the main harness merging statistics, branch merging statistics, length estimation and alternative length, and alternative empty space to form a harness reduction entry; for each harness reduction entry, it binds its source connection path chain, node candidate set, and corresponding reuse entry or restricted reuse entry to make it traceable.

[0084] Finally, S620 compiles all harness reduction entries into a harness reduction list. The harness reduction list is indexed by trunk harness segments and branch harness segments, and includes parallel position statistics, length estimation, detour records, access methods, and the correspondence between these and interface location reservations and relocations. A reverse reference to the interface reuse mapping data is recorded at the head of the list. The harness reduction list is the sole output of S620, used by S630 for topology verification and structure mapping. Simultaneously, S620 retains a reference entry for consistency indicator data at the end of the list, enabling resource-side and time-side verification during the S630 phase.

[0085] S630. Perform topology verification and structural mapping on the wire harness reduction list data and consistency index data to generate topology connection diagram data; S630 takes harness reduction list data and consistency index data as input and performs topology verification and structure mapping. Specifically, firstly, it reconstructs the global connectivity graph based on the indexes of trunk harness segments and branch harness segments in the harness reduction list data. Each trunk harness segment is regarded as a trunk edge of the connectivity graph, and each branch harness segment is regarded as a branch edge of the connectivity graph. Functional domain carrying points identified as nodes in stage S620 are regarded as nodes of the connectivity graph. For temporary bypass harness segments with bypass records, they are connected to the connectivity graph as temporary edges and a mapping edge is established with the original harness segment. Subsequently, stage switching markers and continuous segment markers are extracted from the time consistency entry set of the consistency index data and attached to the edges of the connectivity graph to form a time label layer, so as to ensure that connectivity can be inspected along the time dimension during the topology verification process.

[0086] After constructing the time-marking layer, S630 calls the resource consistency entry set of the consistency index data to perform superimposed calculations on the power supply domain occupancy for each time slice. Specifically, along the time-marking layer, the edges and nodes of the global connected graph are traversed with time slices as the step size. The parallel position statistics and detour records of the corresponding time slices in the trunk and branch bundle segments are mapped to the interface carrying entries for that time slice. The interface carrying entries are matched one by one with the occupancy entries of control logic power supply, execution drive power supply, and sensing and communication power supply in the resource consistency entry set. If an out-of-bounds error occurs after superposition in any time slice, a resource conflict point is marked on the edge corresponding to that time slice, and a transferable alternative empty space is searched on the edge of the adjacent time slice. If an alternative empty space exists, a resource transfer edge is established in the connected graph, recording the transfer relationship from the original edge to the alternative edge. If no alternative empty space exists, a temporary detour bundle segment is searched, a resource transfer edge is established on the detour bundle segment, and the transfer relationship from the original edge to the detour edge is recorded. Through the above mapping, the resource marking layer is formed.

[0087] Subsequently, S630 performs structural mapping on the space side. Specifically, S630 refers to the reference paths loaded and regularized in stage S610 with the installation reference, sealing reference, and channel reference, and performs geometric position matching on each side of the connectivity diagram: when the main harness segment or branch harness segment corresponding to the side crosses the sealing boundary, the interface position clearance record in the harness reduction list data is retrieved. If a match exists, a clearance node is marked on the side; if no match exists, the interface position reservation record is retrieved. If a match exists, a reservation node is marked on the side, and the estimated length of the harness segment at that location is increased by the length increment corresponding to the reservation record; when the main harness segment or branch harness segment corresponding to the side is adjacent to the channel reference of the cooling channel, the channel adjacent node is marked, and the path at that location is corrected with the limiting direction of the channel reference; when the harness segment corresponding to the side is located at the corner or through-hole position of the housing surface, a through-hole node is inserted according to the guidance of the installation reference, and short sides are established on both sides of the through-hole node to represent the path polyline at that location. After the above annotations are completed, S630 obtains a composite connected graph containing a time annotation layer, a resource annotation layer, and a structure annotation layer.

[0088] To ensure the correctness of the composite connectivity graph, the S630 performs topology verification. Specifically, firstly, a connectivity check is performed on the time-marked subgraph of each stage to confirm the existence of complete paths from the main edge to each branch edge; then, a bridging check is performed at the splicing points of continuous segments across stages to confirm that the edges covered by the continuous segment markers are referenced by the same node group on both sides of the stage switching marker; subsequently, a capacity check is performed on the resource annotation layer to confirm that each time slice after resource transfer edge processing does not generate out-of-bounds errors in the three power supply domains; finally, a geometric reachability check is performed on the structural annotation layer to confirm that the yielding nodes, reserved nodes, channel adjacent nodes, and via nodes are spatially consistent with the shell surface, sealing boundary, and cooling channel location descriptions in the interface geometry table. For any isolated nodes or broken edges found, the S630, without changing the harness reduction list data, traces back to the interface reuse mapping data based on the mapped edges, and accordingly supplements the missing branch harness segments or restores the over-parallelized main harness segments until connectivity and reachability are simultaneously satisfied.

[0089] After passing connectivity, capacity, and accessibility checks, the S630 solidifies the composite connectivity graph into a topology connection diagram. The topology connection diagram data primarily consists of a node list and a connection list. The node list records node identifiers, functional domain references, path indexes to installation references, sealing references, and channel references, as well as markings for clearance nodes, reserved nodes, channel adjacent nodes, and via nodes. The connection list records the identity of main harness segments, branch harness segments, and temporary bypass harness segments, their associated connection path chains, merging statistics, length estimates, alternative lengths and alternative empty spaces, and indexes of resource transfer edges and mapping edges. A reverse reference to the harness reduction list data is written at the beginning of the data, and a reverse reference to the consistency index data and connector pin mapping data is written at the end. Thus, the S630 uses the topology connection diagram data as its sole output, providing a direct data carrier for vehicle layout and subsequent manufacturing drawings.

Claims

1. A method for integrating a main drive motor controller and a shift controller, characterized in that, include: Obtain the reuse constraint information of the shell and water channel, and the pin resource information of the connector. Perform common mode planning processing of structure-thermal-interface with unified reference coordinates and the same naming standard. Perform the extraction of sealing boundary conditions and cooling channel parameters, common mode planning modeling of structure-thermal-interface, and interface grouping and boundary consistency verification to generate common mode planning constraint set data of structure-thermal-interface. Perform multi-core load and low-voltage power supply collaborative partitioning processing including installation benchmark, sealing benchmark and channel benchmark, and perform pre-configuration of multi-core partitioning map data, calculation and consistency verification and resource adjustment of low-voltage power budget data and power integrity margin data, and generate multi-core load and low-voltage power supply collaborative partitioning result data; Perform on-chip interaction and task cycle table configuration operations that include final processing unit allocation information and final peripheral binding information. Perform preprocessing of interaction signal table data and task cycle table data, extraction and constraint calculation of key interaction paths and timing boundaries, and scheduling and orchestration to generate on-chip interaction and task cycle table configuration result data. The process involves joint control and orchestration of the entire process, including phased task schedules and interaction path schedules. This includes constructing phased time sequence orchestration data, extracting phase boundaries and velocity difference targets, generating trajectories, and matching constraints, thereby generating joint control configuration result data for the entire process. Perform joint calibration model training and parameter tuning operations to generate consistency index data; Perform unified topology and interface concise configuration processing to generate topology connection diagram data.

2. The method according to claim 1, characterized in that, The information on the reuse constraints of the housing and waterway, and the connector pin resource information include: The specific constraint information for the reuse of the shell and waterway includes the shell geometry, mounting plane, fastening hole positions, rib distribution, sealing groove cross-section and orientation, and the range of the gap between the external mounting perimeter and the shell edge; The connector pin resource information includes the interface socket model, number and size of cavities, type of terminals that can be assembled in each cavity, rated current range of terminals, temperature resistance rating of terminals, shielding and grounding requirements, terminal position code, allowable bending radius of terminals and wire harnesses, insertion and removal direction of the interface socket, and physical interface parameters of the operating space.

3. The method according to claim 1, characterized in that, The process of generating the joint control configuration result data for the entire process also includes: The chip-interactive and task cycle table configuration result data is obtained, and the joint control orchestration timing construction of the entire process, including the phased task time table and interaction path time table, is executed to obtain the phased timing orchestration data. The phased timing orchestration data includes the joint time axis, phase switching mark, segmented power supply domain occupancy, tightly coupled partition list and its reference relationship with the installation reference, sealing reference and channel reference. Extract the stage boundary and speed difference target, and perform full-process joint control and orchestration trajectory generation including speed difference observation sequence and torque reference sequence to obtain torque and speed difference target trajectory data. The torque and speed difference target trajectory data includes the target trajectory set within the stage, continuous segment markers, tightly coupled partition priority labels and power supply domain references. Constraint matching is performed, including power supply domain consistency verification and path connectivity verification, to generate full-process joint control configuration result data. The full-process joint control configuration result data includes a joint time axis, a trajectory-to-task mapping list, a list of connection segments and preparation and release segments, stage switching markers and continuous segment markers, segmented power supply domain occupancy verification results, and reference paths to installation benchmarks, sealing benchmarks, and channel benchmarks.

4. The method according to claim 3, characterized in that, The construction of the entire process joint control orchestration timing includes: Using the in-chip interaction and task cycle table configuration results as input, which includes a phased task timetable, a phased interaction path timetable, and a power domain occupancy summary table, the phased task timetable is interpreted according to three stages: pick-up, speed adjustment, and gear advance. Under the same coordinates and naming conventions, the task entries of each processing unit are arranged into continuous segments according to their start and end times, forming a set of task segments within each stage. The phased interaction path timetable is interpreted synchronously, reading the allocation start and end points of each interaction path, and recording the signal name, source processing unit, destination processing unit, and step sequence associated with the interaction path. A mapping is established for continuous time windows to form a set of interactive path segments. While reading the power supply domain occupancy summary table, the segmented occupancy results of control logic power supply, execution drive power supply, and sensing and communication power supply in each stage are marked on the corresponding task segments and interactive path segments, so that each time segment has a clear power supply domain reference. Based on the indexes of the installation reference, sealing reference, and channel reference, the interface partitions and path indexes related to the execution drive are retrieved to confirm that the physical connectivity conditions required for deploying synchronous mechanism control, clutch execution, and main drive speed regulation in the stage have not been destroyed. Interface partitions with physical adjacency constraints are marked as tightly coupled partitions as boundary items when constructing the timing sequence.

5. The method according to claim 4, characterized in that, The construction of the entire process joint control orchestration timing also includes: Using stages as the main framework, a two-layer alignment is applied to the task segment set and interaction path segment set for each stage: The first layer is intra-stage alignment, where the start and end positions of task segments directly associated with an interaction path segment are adjusted using the allocation start and end points as anchor points. This ensures that the latest processing position on the signal generation side is no later than the start point of the interaction path segment, and the earliest processing position on the signal consumption side is no earlier than the end point of the interaction path segment, thus forming non-overlapping execution windows within the same stage. The second layer is boundary alignment, where consecutive time windows across stages are used as anchor points between adjacent stages. The interaction path segments of the two stages are spliced ​​together, and the end point of the cross-stage entry is matched with the start point of the corresponding entry in the next stage. A stage switching mark is recorded at the matching position. For the interface partition identified as a tightly coupled partition, while aligning the two layers, the indexes of the sealing reference and the channel reference are called to check whether there is temporary occupation superposition of the path index corresponding to the interface partition. If there is superposition, the low priority entries in the task segment set are slightly moved without changing the relative order of the interaction path segments, the temporary occupation of the interface partition is released and the corresponding start time and end time are updated.

6. The method according to claim 5, characterized in that, The construction of the entire process joint control orchestration timing also includes: Threshold checks are performed on the segmented occupancy of each power supply domain within each stage. If the occupancy entries of a power supply domain in any time slice exceed the available upper limit given in the power supply domain occupancy summary table, segment compression and segment migration are implemented in the local time slice: the duration of non-critical task segments is compressed first; if the limit is still exceeded after compression, the non-critical task segment is migrated to the idle time slice of the same stage, and the associated interaction path segment reference is added at the migration position; through intra-segment alignment, boundary alignment and power supply domain checks, the task segments and interaction path segments at the processing unit level are integrated into a stage-level joint time axis, forming a stage timing draft that includes stage switching markers, segment start and end positions, interaction path references and power supply domain references.

7. The method according to claim 3, characterized in that, The entire process of joint control and orchestration trajectory generation includes: The joint time axis and stage switching markers are read from the stage timing arrangement data, and the start and end positions of each stage segment are linearly expanded according to time sequence to obtain the stage boundary set. At the same time, the tightly coupled partition list is retrieved to mark the positions of segments involving synchronization mechanism control, clutch execution, and main drive speed regulation, thereby establishing two subsets in the stage boundary set: synchronization-related boundaries and execution-related boundaries. The established signal reference relationship is invoked to extract signal entries related to speed difference estimation, synchronization target calculation, and torque adjustment commands from the joint time axis. Their distribution positions within the stage and their continuity relationships between stages are concatenated to generate time indices for the speed difference observation sequence and torque reference sequence. The power supply domain reference and the path index of the tightly coupled partition are superimposed on the time index to confirm that there are no cases where the power supply domain is unavailable or the path is unreachable at the key nodes of the trajectory segment. If there are, a usable alternative node is inserted into the time index, and the signal references of adjacent segments are re-associated.

8. The method according to claim 7, characterized in that, The entire process of joint control and orchestration trajectory generation also includes: The speed difference observation sequence and torque reference sequence are segmented in stages: In the disengagement stage, the segmented sequences related to clutch engagement, disengagement synchronization, and main drive deceleration are extracted and implemented as clutch control segments, synchronization control segments, and main drive deceleration segments; in the speed regulation stage, the segmented sequences related to speed difference tracking, speed transition, and synchronization propulsion are extracted and implemented as speed difference tracking segments, speed transition segments, and synchronization propulsion segments; in the gear engagement stage, the segmented sequences related to gear engagement promotion, clutch engagement, and main drive recovery are extracted and implemented as gear engagement promotion segments, clutch engagement segments, and main drive recovery segments; for each segment, a clear start and end point are assigned according to the start and end positions of the joint time axis segment, and a signal drive sequence is established within the segment according to the order of interactive path references, so that the segment has an itemized structure that can be called step by step by the execution unit.

9. The method according to claim 8, characterized in that, The entire process of joint control and orchestration trajectory generation also includes: Connecting adjacent segments: When there is a gap between upstream and downstream segments on the time axis, a transition segment is inserted at the gap position, and the transition segment is checked for consistency with the power supply domain reference; when upstream and downstream segments overlap on the time axis, the segment associated with the tightly coupled partition is retained first, and the other segment is shortened or shifted without changing the stage boundary until the overlap is eliminated; the fragmented sequence within each stage is spliced ​​in the segment order to generate the torque target segment sequence and speed difference target segment sequence within the stage, and the continuity across stages is checked: for signal references with continuous time windows across stages, continuous segment markers are established at the splicing boundary between two stages, and the end position of the previous stage and the start position of the next stage are recorded on the continuous segment markers to ensure that there are no undefined segment gaps at the stage switching markers.

10. The method according to claim 3, characterized in that, Constraint matching includes: At the stage level, the torque and speed difference target trajectory data are aligned with the stage timing orchestration data: the joint time axis and stage switching markers in the stage timing orchestration data are read, and the target trajectory set within the stage in the torque and speed difference target trajectory data is projected onto the joint time axis to form a target trajectory alignment view; in the target trajectory alignment view, continuous segment markers and tightly coupled partition priority labels are located one by one, indicating the set of segments that need to be prioritized; the segmented power supply domain occupancy and tightly coupled partition list in the stage timing orchestration data are called to perform power supply domain consistency verification and path matching on the target trajectory alignment view. Path connectivity verification: When the power supply domain occupancy of a time slice containing a trajectory segment exceeds the available limit, the positions of adjacent non-tightly coupled segments within the same stage are adjusted first to bring the occupancy of that time slice into the available range; if the adjustment is still insufficient, the dwell time of that segment in that time slice is shortened without changing the stage switching mark, and the shortened part is moved to an idle time slice in the same stage; when the path index of a trajectory segment is inconsistent with that of a tightly coupled partition, a preparation segment is inserted before that segment and a release segment is inserted after that segment to ensure that the paths to and from the tightly coupled partition are reachable.

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