Chip efficient detection system and method

Abstract

The application relates to the chip detection field and discloses a chip high-efficiency detection system and method, which are used for realizing long-term performance degradation detection of a chip. The system comprises the following steps: under the working state of a to-be-detected chip, electric-thermal coupling characteristic data sets are generated by synchronously collecting power pin electric signals and chip surface thermal imaging data; impedance and heat conduction characteristic parameters are extracted through impedance spectrum analysis and thermal time constant calculation; internal signal transmission path characteristic parameters are acquired based on impedance characteristic parameter analysis; a mathematical model of chip dynamic current and working voltage is established by combining the above two models; system identification results are generated; and finally, chip detection results and fault positioning information are generated by comprehensively combining various parameters. The application carries out system benchmark testing, environment interference monitoring and compensation, and realizes high-precision and high-robustness of the detection results.

Description

Technical Field

[0001] This invention relates to the field of chip testing, and in particular to a high-efficiency chip testing system and method. Background Technology

[0002] With the rapid development of integrated circuit technology, chips, as core components of electronic devices, directly determine the operational quality of the entire system through their performance and reliability. In fields with high reliability requirements, such as aerospace, automotive electronics, and industrial control, chip failures can not only lead to system malfunctions but may even trigger catastrophic consequences. Therefore, efficient and accurate chip testing has become a crucial step in ensuring stable system operation.

[0003] Traditional chip testing methods mainly rely on the monitoring and analysis of a single physical quantity (electrical signal or thermal signal).

[0004] Detection methods based on electrical signals evaluate the chip's operating status by analyzing parameters such as voltage and current. However, these methods cannot fully reflect the complex physical processes inside the chip, especially the impact of thermal effects on chip performance.

[0005] While thermal imaging-based detection methods can capture the temperature distribution on the chip surface, they lack in-depth analysis of the coupling relationship between electrical and thermal signals, which limits the accuracy of fault location.

[0006] Therefore, we propose a high-efficiency chip detection system and method to solve the above problems. Summary of the Invention

[0007] This invention provides a high-efficiency chip testing system and method for detecting long-term performance degradation of chips.

[0008] The first aspect of this invention provides a high-efficiency chip testing method, comprising: simultaneously acquiring electrical signals from the power supply pins and thermal imaging data of the chip surface while the chip is in operation, generating an electrothermal coupling feature dataset; performing impedance spectral analysis and thermal time constant calculation on the electrothermal coupling feature dataset to extract impedance characteristic parameters and thermal conduction characteristic parameters of the chip at multiple frequency points; analyzing the signal transmission path inside the chip based on the impedance characteristic parameters to obtain path characteristic parameters; combining the electrothermal coupling feature dataset and the path characteristic parameters to establish a mathematical model of the chip's dynamic current and operating voltage, generating a system identification result; and integrating the impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification result to generate chip detection results and fault location information.

[0009] Optionally, in a first implementation of the first aspect of the present invention, the method includes: performing frequency sweep excitation on voltage and current data in the electrothermal coupling feature dataset to obtain the voltage and current responses of the chip at different frequencies, generating frequency domain impedance spectrum data; analyzing the temperature response curve of the chip under power step change based on the temperature distribution data in the electrothermal coupling feature dataset, and extracting the thermal time constant sequence; fitting an equivalent circuit model to the frequency domain impedance spectrum data to identify internal parasitic parameters and material property parameters of the chip, generating an impedance characteristic parameter set; establishing a three-dimensional thermal conduction model of the chip by combining the thermal time constant sequence and temperature distribution data, calculating the thermal resistance and thermal capacity distribution, and generating a thermal conduction characteristic parameter set; performing correlation analysis on the impedance characteristic parameter set and the thermal conduction characteristic parameter set to identify electrothermal coupling characteristics, and generating complete impedance characteristic parameters and thermal conduction characteristic parameters.

[0010] Optionally, in a second implementation of the first aspect of the present invention, the method includes: injecting a high-speed step signal into the key signal transmission path of the chip, acquiring the reflected waveforms of each node in the transmission path, and generating time-domain reflected waveform data; identifying impedance discontinuities in the time-domain reflected waveform data based on the impedance characteristic parameters, and locating the impedance mismatch position of the transmission path inside the chip; analyzing the time delay characteristics of the reflected waveform, and reconstructing the topology of the signal transmission path inside the chip by combining the impedance mismatch position information; calculating the propagation speed and attenuation coefficient of the signal in each transmission segment inside the chip based on the reconstructed transmission path topology, and generating signal transmission characteristic parameters; and quantitatively evaluating signal integrity and transmission delay characteristics based on the impedance mismatch position, the transmission path topology, and the signal transmission characteristic parameters, and generating path characteristic parameters.

[0011] Optionally, in the third implementation of the first aspect of the present invention, the method includes: constructing a multivariate time series of chip operating states based on voltage and current time series data in the electrothermal coupling feature dataset, and generating a dynamic response feature set; combining the signal transmission delay characteristics in the path feature parameters, performing time delay embedding reconstruction on the dynamic response feature set to generate an extended phase space dataset; processing the extended phase space dataset to extract the nonlinear kernel function features of the chip system, and generating a nonlinear feature set; constructing a nonlinear autoregressive model of chip dynamic current and operating voltage based on the nonlinear feature set, and obtaining the model coefficient matrix through parameter identification; using the model coefficient matrix to detect and verify the dynamic response of the chip under different operating modes, and generating a system identification result.

[0012] Optionally, in a fourth implementation of the first aspect of the present invention, the nonlinear kernel function features of the chip system are extracted by processing the extended phase space dataset:

[0013] ,

[0014] in, To detect current; This is the DC component; (τ) is a first-order kernel function; It is a second-order kernel function; The error term represents noise or unmodeled dynamics that the model did not capture; the truncation length T = 10.

[0015] Optionally, in the fifth implementation of the first aspect of the present invention, a test excitation signal covering the entire operating range of the chip is designed based on the model coefficient matrix to generate a multi-mode verification test sequence; the multi-mode verification test sequence is applied to the chip under test, and voltage response and current response data are collected simultaneously to generate a measured dynamic response dataset; the multi-mode verification test sequence is input into a nonlinear autoregressive model to calculate the theoretical detection response and generate a detection response dataset; the measured dynamic response dataset and the detection response dataset are compared to calculate the model detection error distribution and generate a model accuracy verification report; the model accuracy verification report and the nonlinear feature parameters in the model coefficient matrix are combined to generate a system identification result.

[0016] Optionally, in the sixth implementation of the first aspect of the present invention, the method includes: establishing an electrothermal correlation feature matrix based on parasitic parameters and material characteristic parameters in impedance characteristic parameters, combined with thermal resistance distribution in thermal conduction characteristic parameters, to generate a chip structure integrity index; analyzing the degree of chip functional performance degradation using signal integrity assessment results in path characteristic parameters and nonlinear characteristics in system identification results, to generate a functional performance degradation index; evaluating chip timing characteristic stability based on model accuracy index in system identification results and transmission delay characteristics in path characteristic parameters, to generate a timing stability index; identifying potential chip fault modes through multi-dimensional correlation analysis based on the electrothermal correlation feature matrix and functional performance degradation index, to generate a fault type judgment result; and determining the fault location and impact range by combining the timing stability index and fault type judgment result, to generate a chip detection result.

[0017] Optionally, in the seventh implementation of the first aspect of the present invention, the method further includes: before the detection begins, performing a system benchmark test to obtain the calibration coefficients and system error distribution of each measurement channel, and generating a system calibration parameter set; performing error compensation and accuracy correction on the real-time acquired electrothermal coupling feature dataset based on the system calibration parameter set, and generating corrected measurement data; monitoring the impact of ambient temperature changes and power fluctuations on the measurement results under different chip operating modes, establishing an environmental interference feature model, and generating dynamic compensation parameters; using the dynamic compensation parameters to correct the corrected measurement data in real time, eliminating the impact of environmental factors on the detection results, and generating environmental robustness detection data; comparing and analyzing the environmental robustness detection data with a historical qualified chip database, establishing a long-term trend analysis report of the detection results, and generating a chip reliability detection assessment.

[0018] A second aspect of the present invention provides a high-efficiency chip testing system, comprising: a data acquisition module for simultaneously acquiring electrical signals from the power pins of the chip under test and thermal imaging data of the chip surface while the chip is in operation, generating an electrothermal coupling feature dataset; a parameter extraction module for performing impedance spectral analysis and thermal time constant calculation on the electrothermal coupling feature dataset to extract impedance characteristic parameters and thermal conduction characteristic parameters of the chip at multiple frequency points; a path analysis module for analyzing the internal signal transmission path of the chip based on the impedance characteristic parameters to obtain path characteristic parameters; a detection optimization module for combining the electrothermal coupling feature dataset and path characteristic parameters to establish a mathematical model of the chip's dynamic current and operating voltage, generating a system identification result; and an evaluation detection module for comprehensively considering the impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification result to generate chip detection results and fault location information.

[0019] The mechanism of this invention is as follows: by extracting multi-dimensional parameters such as impedance characteristics, thermal conduction characteristics, and signal transmission characteristics, a nonlinear autoregressive model is used to accurately describe the dynamic characteristics of the chip, thereby achieving a comprehensive evaluation from structural integrity and functional performance to timing stability. This breaks through the limitations of traditional single-parameter detection and enables precise location of chip faults.

[0020] Beneficial effects: Simultaneous acquisition and fusion analysis of electrical signals and thermal imaging data can more comprehensively reflect the actual state of the chip during operation;

[0021] By acquiring frequency domain impedance spectrum data through frequency sweep signal excitation and analyzing the temperature response curve under power step change to extract the thermal time constant sequence, the impedance mismatch location of a specific component or transmission path inside the chip can be accurately determined, which greatly improves the accuracy of fault location and reduces false positives and false negatives.

[0022] Injecting high-speed step signals into the critical signal transmission path of a chip can help identify bottlenecks or interference sources in the signal transmission path in advance, providing important reference for the optimized design of the chip.

[0023] It fully considers the highly nonlinear and time-varying characteristics of the dynamic response of the chip under different working modes. By using nonlinear modeling, the dynamic behavior of the chip can be described more accurately, enabling the detection of the chip's future state, the early detection of potential fault risks, and providing strong support for the real-time monitoring of the chip. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of one embodiment of the chip high-efficiency detection method in this invention;

[0025] Figure 2This is a schematic diagram of another embodiment of the chip high-efficiency detection method in this invention;

[0026] Figure 3 This is a schematic diagram illustrating the data acquisition process of the high-efficiency chip detection method in this embodiment of the invention.

[0027] Figure 4 This is a schematic diagram illustrating the principle analysis and evaluation of the time-domain reflectometer for the high-efficiency chip detection method in this embodiment of the invention;

[0028] Figure 5 This is a schematic diagram of one embodiment of the high-efficiency chip detection system of the present invention;

[0029] Figure 6 This is a schematic diagram of one embodiment of the high-efficiency chip testing device in this invention. Detailed Implementation

[0030] This invention provides a high-efficiency chip testing system and method for detecting long-term performance degradation of chips. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 One embodiment of the chip high-efficiency detection method in this invention includes:

[0032] 101. While the chip under test is in operation, simultaneously acquire electrical signals from its power supply pins and thermal imaging data from the chip surface to generate an electrothermal coupling feature dataset containing voltage, current, and temperature distribution.

[0033] It is understood that the executing entity of this invention can be a high-efficiency chip detection system, a terminal, or a server; no specific limitation is made here. This embodiment of the invention will be described using a server as an example.

[0034] It should be noted that for automotive-grade microcontroller units (MCUs), the core equipment includes: Electrical signal acquisition: a high-precision digital multimeter and power analyzer are used, with a sampling rate set to 1MS / s (millions of times per second), measuring the voltage (range 0.9V-1.1V, accuracy ±1mV) and current (range 0-500mA, accuracy ±0.1mA) of the power supply pins. Thermal imaging acquisition: an infrared thermal imager (supporting a 20μm macro lens) is used, with a thermal sensitivity of 30mK and a frame rate of 30fps, ensuring the capture of minute temperature changes on the chip surface (5mm×5mm). Synchronization mechanism: a unified timestamp pulse (accuracy ±1μs) is sent to all devices through a synchronization signal generator on the server, ensuring strict alignment of the electrical signals and the time axis of the thermal image data. Workload simulation: the automotive-grade MCU under test is subjected to a dynamic load cycle (0%-50%-100% CPU utilization step change), and test vectors are applied through the JTAG interface to simulate actual operating conditions.

[0035] Startup and Synchronous Acquisition: The server sends a start command, and the MCU enters the test state. The electrical signal acquisition device records the instantaneous values ​​of the power supply pin voltage V and current I in real time (at time t=1.500s, V=1.032V and I=85.6mA are measured). The thermal imager simultaneously records thermal image video of the chip surface (resolution 320×240 pixels) and aligns it with the electrical signal data in time via a synchronization signal.

[0036] Electrothermal data association: Thermal images at a specific time (t=1.500s) are extracted. Temperature distribution is analyzed using software, revealing a maximum temperature of 63.5℃ in the chip's center and 58.2℃ in the corner areas, generating a temperature distribution matrix. The voltage (1.032V) and current (85.6mA) at that moment are then bound to the temperature distribution matrix (containing the temperature value of each pixel) to form a data unit, which is then marked with a precise timestamp.

[0037] Dataset construction: Repeat the above process in multiple load cycles (lasting 3 minutes) to collect tens of thousands of synchronous data units.

[0038] The integrated electrothermal coupling feature dataset has the following core structure:

[0039]

[0040] 102. Perform impedance spectrum analysis and thermal time constant calculation on the electrothermal coupling characteristic dataset to extract the impedance characteristic parameters and thermal conduction characteristic parameters of the chip at multiple frequency points;

[0041] It should be noted that, for automotive-grade microcontroller units (MCUs) (taking MC9S08QL8 as an example), after completing the synchronous electrothermal data acquisition in step 101, impedance spectrum analysis and thermal time constant calculation are performed on the electrothermal coupling characteristic dataset:

[0042] Based on the voltage and current timing data of the power supply pins (sampling rate 1MS / s), impedance characteristics are analyzed through frequency domain transformation. Fourier transforms are performed on the voltage and current signals to obtain the amplitude and phase at different frequencies, and the complex impedance Z=V / I is calculated, where the real part is the resistance component and the imaginary part is the reactance component. The analysis scans the frequency band from 10Hz to 1MHz (covering the typical operating frequency of the MCU), focusing on the three characteristic frequency points of 1kHz, 10kHz, and 100kHz.

[0043] Example data: 1kHz frequency: Real part of impedance is 50.2Ω, imaginary part is -12.5Ω (capacitive characteristic), phase angle -14°. 10kHz frequency: Real part drops to 48.1Ω, imaginary part becomes -5.8Ω, phase angle -7° (capacitive weakening). 100kHz frequency: Real part is 45.0Ω, imaginary part is close to 0Ω (resistive dominance), phase angle -1°. Analysis output: Generates Nyquist plot and Bode plot, showing the impedance versus frequency curve. Characteristic frequency parameters are used for subsequent fault diagnosis (abnormal imaginary part indicates internal capacitance degradation).

[0044] Extract the transient response of chip surface temperature from thermal imaging data (the temperature rise process after the MCU switches from idle state to full load). Differentiate the temperature-time curve to identify the thermal time constant corresponding to the inflection point of the curve. Each time constant corresponds to the thermal conduction delay of different structural layers inside the chip (silicon chip, solder, package).

[0045] Example Data: Fast time constant τ1: 120ms (corresponding to thermal conduction in the chip silicon layer), determined by the first peak of the differential curve, contributing 60% to the temperature rise. Slow time constant τ2: 350ms (corresponding to thermal conduction in the package layer), determined by the second plateau region of the curve, contributing 40% to the temperature rise. Calculation Principle: The thermal time constant satisfies τ = Rth × Cth with respect to thermal resistance (Rth) and thermal capacity (Cth). If the chip layer thermal resistance is 5℃ / W and the thermal capacity is 24mJ / ℃, then τ1 ≈ 5 × 0.024 = 120ms. Output Parameters: After extracting τ1 and τ2, combined with the steady-state temperature rise (from 25℃ to 63℃), the thermal resistance of each layer is calculated (chip layer Rth1 = 6.5℃ / W, package layer Rth2 = 4.2℃ / W) to evaluate the integrity of the heat dissipation path.

[0046] Impedance characteristic parameters: real / imaginary part of impedance at characteristic frequencies, phase angle, resonant frequency (no obvious resonance was observed in this example), and outliers (a sudden increase in the imaginary part at 10kHz) indicate a failure of the power supply pin bypass capacitor. Thermal conduction characteristic parameters: thermal time constants (τ1, τ2), layer thermal resistance, and estimated thermal capacity (chip layer thermal capacity is approximately 25mJ / ℃). If τ2 is significantly greater than the standard value (>400ms), it indicates a poor solder joint or void at the package interface.

[0047] 103. Using the principle of time-domain reflectometer, analyze the signal transmission path inside the chip based on impedance characteristic parameters to obtain path characteristic parameters including signal integrity and transmission delay characteristics;

[0048] It should be noted that, for automotive-grade microcontroller units (MCUs) (taking AMEC's ​​automotive-grade MCUs as an example), after extracting the impedance characteristic parameters in step 102, the internal signal transmission path of the chip is analyzed using the time-domain reflectometer principle to obtain the path characteristic parameters:

[0049] Time-domain reflectometers (TDDRs) inject high-speed pulse signals into the internal signal path of a chip (clock distribution network or power management bus) and capture the reflected signals from impedance discontinuities. Based on the polarity of the reflected pulses (positive pulses indicate open circuits, negative pulses indicate short circuits) and the time difference, fault points are located and signal integrity is analyzed. System configuration: A terahertz time-domain reflectometer system (Advantest TS9001TDR) is used. Its core parameters include: pulse width: an ultra-short terahertz pulse of 50 femtoseconds (fs), rise time of approximately 20 picoseconds (ps), and time jitter of less than 30 fs. Detection accuracy: fault location resolution up to 5 μm (compared to millimeter-level for traditional TDRs). Connection method: A high-frequency probe is used to contact a specific pin of the MCU (clock input pin or SPI communication pin), injecting a pulse signal and simultaneously acquiring the reflected signal. Test conditions: The MCU is in dynamic operating mode (running a communication task with a 10MHz clock cycle), and the signal path load includes the internal bus, transistor gate capacitors (typically 1-5pF), etc.

[0050] A pulse signal was injected into the SPI master control pin of the MCU, and the transmission time (t0) and the arrival time of the first reflected pulse (t1) were measured. In the experimental data, t0=0ns and t1=86.5ps.

[0051] Through formula (where c is the speed of light and εe is the equivalent dielectric constant, taken as 4.1 for chip internal dielectric estimation), calculate the distance to the fault point. In a real-world case, the measured path length was 3.52 mm, with an error of only 0.02 mm (0.6%) from the design value of 3.50 mm.

[0052] Reflected Pulse Analysis: Open Circuit Fault Identification: When the pulse encounters an open circuit (bonded wire breakage) at the end of its path, the peak value of the reflected positive pulse is +0.8V (reflection coefficient ρ=1 for reference impedance matching). A positive pulse is detected at the pin pad, indicating an open circuit in the interface. Short Circuit Fault Identification: If the power supply and ground are short-circuited, the peak value of the reflected negative pulse is -0.7V (ρ=-1). In actual testing, a negative pulse is captured at a distance of 1.2mm from the pin, locating the metal layer leakage point. Slight Impedance Mismatch: For gradual impedance changes (changes in conductor width), the reflected pulse amplitude is ±0.1V~0.3V, indicating impaired signal integrity (return loss increases by 3dB).

[0053] Transmission delay characteristic calculation: Signal group delay is analyzed using multipath reflection time difference. The main path delay is 85ps, but due to secondary reflections on the branch lines (delay of 172ps), clock jitter increases by 2ps. The standard deviation of delay is extracted as a stability parameter (0.5ps in this example). If it exceeds the threshold (2ps), it indicates a synchronization abnormality.

[0054] Path characteristic parameter list: Signal integrity parameters: return loss (-25dB), characteristic impedance deviation (±5%), reflection coefficient (-0.3 to +0.8). Transmission delay parameters: main path delay (85ps), jitter (0.5ps), branch path additional delay (87ps).

[0055] Fault location example: A certain automotive-grade MCU failed to communicate during high-temperature testing. TDR found a -0.4V reflected pulse at 2.1mm on the SPI pin path, diagnosed as a quasi-short circuit (impedance dropped to 20Ω). Dissection verification confirmed that metal migration caused leakage in the power / signal lines.

[0056] 104. Based on the theory of nonlinear system identification, and combined with the electrothermal coupling feature dataset and path feature parameters, a mathematical model of chip dynamic current and operating voltage is established to generate system identification results containing nonlinear features.

[0057] It should be noted that after obtaining the electrothermal coupling feature dataset and path feature parameters in the previous steps, this step constructs a mathematical model of dynamic current and operating voltage based on nonlinear system identification theory:

[0058] Input variable selection: Dynamic current excitation signal: Extracted current timing data (sampling rate 1MS / s) from the electrothermal coupling dataset, covering the current fluctuation range (85mA to 320mA) of the MCU under different load modes (0%-50%-100% CPU utilization). Operating voltage: Synchronously acquired power pin voltage data (fluctuation range 0.98V-1.05V). Auxiliary variables: Integrating signal transmission delay (85ps±0.5ps jitter) from the path characteristic parameters and real-time chip surface temperature (63℃±5℃) from the electrothermal dataset. Output variable: The model output is the dynamic response of the voltage, focusing on its nonlinear distortion characteristics (harmonic components).

[0059] Nonlinear model structure selection and parameter identification: Model type: Hammerstein-Wiener model is adopted. This structure can separate static nonlinearity and dynamic linearity, and is suitable for describing current-voltage hysteresis and saturation effects in MCUs. Static nonlinearity: The steady-state relationship between current and voltage is fitted using a polynomial, and the coefficients of the second-order polynomial are identified through experimental data.

[0060] (Where I is the current unit mA and V is the voltage unit V), capturing voltage saturation in the high-voltage region (voltage drops below 1.02V when current > 300mA). Dynamic linear element: The transient response of voltage to current change is described using a transfer function, identifying a first-order inertial element with a time constant of 2.5ms, indicating that voltage stabilization requires 6ms after a current step. Parameter identification method: Recursive least squares method is used, with a root mean square error of less than 2mV as the convergence criterion. Voltage response data is collected to train the model by injecting a current step signal with gradually changing amplitude (50mA→200mA→350mA).

[0061] Nonlinear Feature Extraction: Harmonic Distortion: Under 100Hz sinusoidal current excitation, the total harmonic distortion (THD) of the model output voltage reaches 3.5%, significantly higher than the 0.8% of the linear model, reflecting the nonlinear conduction characteristics of the PN junction inside the chip. Temperature Drift Coefficient: The model reveals that for every 10℃ increase in temperature, the voltage reference drifts by 0.3mV (1.032V at 25℃, decreasing to 1.029V at 85℃). Fault Sensitivity Parameter: When the path delay jitter exceeds 1.5ps, the model detection error increases to 5mV, indicating signal integrity degradation.

[0062] When the MCU runs the standard test program (AES encryption algorithm), the measured data is compared with the model's detected values. As shown in the table below, the voltage detection error is controlled within ±0.5%, verifying the model's accuracy.

[0063]

[0064] In this example, the system identification results revealed that the nonlinear mapping between dynamic current and operating voltage is affected by both temperature and signal transmission quality. When the temperature exceeds 100°C, the harmonic distortion rate of the model output increases sharply to 8%, which can be directly related to the aging of the MCU power management module.

[0065] 105. By combining impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification results, chip detection results and fault location information are generated through multi-parameter fusion analysis.

[0066] It should be noted that after obtaining impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification results in the preceding steps, this step uses multi-parameter fusion analysis to comprehensively assess the chip's health status and locate faults.

[0067] All parameters are standardized and converted into a health index of 0-100 (100 being optimal). For every 1Ω deviation of the real part of impedance from the standard value, 5 points are deducted; for every 10ms of thermal time constant exceeding the range, 3 points are deducted. Weighting: Based on the functional safety requirements of automotive-grade standards AEC-Q100 and ISO26262, different parameters are assigned weights. Electrical parameters (impedance, path characteristics) have a weight of 40%, thermal parameters 30%, and system nonlinear characteristics 30%, reflecting the sensitivity of the automotive-grade MCU to electrical stability and thermal management. Fault Logic Tree: A fault diagnosis tree is constructed based on the parameter logic relationships. If the thermal time constant is abnormal and the imaginary part of the impedance abruptly changes, the "packaging defect" branch is triggered; if both path delay jitter and harmonic distortion exceed the standard, it points to "signal integrity degradation."

[0068] The table below uses measured data as an example to illustrate the parameter fusion analysis process (normal range refers to automotive-grade MCU benchmark values):

[0069]

[0070] Health score calculation: (out of 100)

[0071] According to automotive standards: ≥90 points is "Excellent", 80-89 points is "Good but requires monitoring", and <80 points is "High risk of failure". This example scored 85.2 points, and its status is "Good".

[0072] Key abnormal parameters: τ2 is abnormal (450ms > 400ms) and transmission delay jitter exceeds the standard (2.5ps): This indicates thermal conduction delay in the packaging layer. Combined with path characteristic analysis, a void was located at the interface between the chip package and the substrate (increased thermal resistance leads to signal path timing distortion). Although the imaginary part of the impedance (-12.5Ω) is within the normal range, it is close to the lower limit. The superimposed temperature drift coefficient is normal, indicating slight aging of the bypass capacitor on the power supply pin, but it does not affect voltage stability.

[0073] Fault tree analysis: Using a fault logic tree to verify that the τ2 anomaly and delay jitter occur simultaneously (probability weight 70%), triggering the "package thermal defect" branch; the harmonic distortion is normal, ruling out the possibility of core transistor degradation (confidence level 90%).

[0074] The health status assessment report output, with a summary example as follows: Overall health: 85.2 points (Good). Main risk: Degraded package thermal management capabilities, potentially leading to timing errors at high temperatures. Maintenance recommendations: Enhance heat dissipation design; it is recommended to retest the τ2 parameter during a temperature cycle of -40℃ to 125℃. Fault location: Solder interface void (located in the lower layer of the chip package, coordinates X=2.1mm, Y=3.5mm); the integrity of the solder joint needs to be thoroughly inspected.

[0075] In this embodiment of the invention, a mathematical model of dynamic current and operating voltage is constructed based on nonlinear system identification theory. By adopting a specific model structure and parameter identification method, the electrical, thermal and signal transmission characteristics inside the chip can be deeply explored, and key parameters reflecting the health status of the chip can be accurately obtained. This provides detailed and accurate basis for fault diagnosis, thereby improving the accuracy and reliability of fault diagnosis.

[0076] Impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification results are uniformly converted and weighted according to automotive-grade standards. A fault logic tree is constructed for multi-parameter fusion analysis, which comprehensively considers the electrical, thermal, and signal transmission factors of the chip. This avoids the one-sidedness of single-parameter evaluation, and can more comprehensively and accurately assess the health status of the chip, accurately locate the cause of the fault, provide scientific and reasonable suggestions for chip maintenance and optimization, improve the reliability and stability of the chip, and ensure the safety of automotive-grade applications.

[0077] It can meet the stringent requirements of automotive-grade chips for high reliability and high safety, ensuring stable operation of the chip in the complex automotive working environment, reducing safety risks caused by chip failure, and ensuring the normal operation of automotive electronic systems and passenger safety.

[0078] Please see Figure 2-4 Another embodiment of the chip high-efficiency detection method in this invention includes:

[0079] 201. While the chip under test is in operation, simultaneously acquire electrical signals from its power supply pins and thermal imaging data from the chip surface to generate an electrothermal coupling feature dataset containing voltage, current, and temperature distribution.

[0080] Specifically, voltage probes and current sensors are deployed in parallel at multiple power pins of the chip under test, while an infrared thermal imager is placed on the chip surface to acquire raw voltage waveform data, raw current time-series data, and raw thermal images. Ripple analysis and transient response extraction are performed on the raw current time-series data to generate current characteristic parameters containing current ripple characteristics and transient response characteristics. Temperature gradient calculation and hot spot region identification are performed on the raw thermal images to generate thermal time-series data containing temperature distribution gradient and hot spot location information. The raw voltage waveform data, current characteristic parameters, and thermal time-series data are synchronized based on timestamps to establish an electrothermal correlation matrix. The above acquisition process is repeated under different load conditions of the chip, and multiple sets of electrothermal correlation matrices are integrated to generate an electrothermal coupling feature dataset.

[0081] It should be noted that a 5W power amplifier chip (3mm×3mm, BGA package) was used as the test object, and its electrothermal coupling characteristics under different loads were monitored.

[0082] Electrical signal acquisition: High-precision voltage probes (1GHz bandwidth) and surface-mount current sensors (0.5% accuracy) are connected in parallel on the three core power supply pins of the chip. Raw voltage waveforms (sampling rate 1GS / s) and current timing data (sampling rate 100kS / s) are acquired during switching transients, steady-state conditions, and light / full load transitions. Thermal imaging acquisition: An infrared thermal imager (equipped with a 50μm macro lens, thermal sensitivity 30mK) is used to record the temperature distribution video of the chip during operation at a frame rate of 100Hz, generating a raw thermal image sequence.

[0083] Current and thermal imaging data processing, current feature extraction: The raw current data is first subjected to Fourier transform to analyze the frequency domain ripple component (identifying a ripple amplitude of 15mA corresponding to a 120kHz switching frequency); then, through step response analysis, transient features such as current rise time (typical value 2μs) and overshoot (maximum value 5%) are extracted. Thermal data analysis: Pixel-level temperature gradient calculations are performed on the thermal imaging image, identifying two hotspot regions (with maximum temperatures reaching 85℃ and 78℃ respectively), and generating temperature distribution curves (spatial resolution 10μm) and hotspot coordinate information.

[0084] All acquisition devices are triggered by a synchronization signal generator to ensure that the timestamps of voltage, current, and thermal data are aligned (deviation <10μs). Using a 1ms time window, the synchronized voltage RMS value, current ripple characteristics, and hot spot temperature time series data are integrated to form an electrothermal correlation matrix (matrix dimension: time point × (voltage + current characteristics + temperature data)).

[0085] The above steps were repeated under three power states: standby (0.5W), medium load (2W), and full load (5W), with data collection lasting for 2 minutes under each state. Three sets of electrothermal correlation matrices were obtained, forming an electrothermal coupling feature dataset containing multi-dimensional parameters such as voltage, current ripple, transient response, temperature gradient, and hotspot location, providing a foundation for subsequent analysis.

[0086] 202. Perform impedance spectrum analysis and thermal time constant calculation on the electrothermal coupling characteristic dataset to extract the impedance characteristic parameters and thermal conduction characteristic parameters of the chip at multiple frequency points;

[0087] Specifically, the voltage and current data in the electrothermal coupling feature dataset are subjected to frequency sweep signal excitation to obtain the voltage and current responses of the chip at different frequencies, generating frequency domain impedance spectrum data. Based on the temperature distribution data in the electrothermal coupling feature dataset, the temperature response curve of the chip under power step change is analyzed, and the thermal time constant sequence is extracted. The frequency domain impedance spectrum data is fitted with an equivalent circuit model to identify internal parasitic parameters and material property parameters of the chip, generating an impedance characteristic parameter set. Combining the thermal time constant sequence and temperature distribution data, a three-dimensional thermal conduction model of the chip is established to calculate the thermal resistance and thermal capacity distribution, generating a thermal conduction characteristic parameter set. The impedance characteristic parameter set and the thermal conduction characteristic parameter set are subjected to correlation analysis to identify electrothermal coupling characteristics and generate complete impedance characteristic parameters and thermal conduction characteristic parameters.

[0088] Furthermore, the equivalent circuit model is fitted to the frequency domain impedance spectrum data to identify internal parasitic parameters and material property parameters of the chip, generating an impedance characteristic parameter set. This also includes: performing Cole-Cole plot analysis on the frequency domain impedance spectrum data to identify multiple relaxation processes in the impedance spectrum and generate complex impedance distribution characteristics; based on the complex impedance distribution characteristics, constructing a distributed equivalent circuit model including parasitic inductance, distributed capacitance, and contact resistance to generate the circuit topology; optimizing the parameters of the distributed equivalent circuit model using a nonlinear least squares fitting algorithm to extract the electrical characteristic parameters of each functional unit inside the chip; combining the material thermal properties in the thermal conductivity parameters to analyze the temperature dependence of the electrical characteristic parameters and generate a temperature-compensated accurate parameter set; and calculating the impedance matching characteristics of the chip under high-frequency operating conditions based on the accurate parameter set to generate an impedance characteristic parameter set including frequency-varying and temperature-dependent characteristics.

[0089] It should be noted that this step is based on the electrothermal coupling feature dataset obtained in the previous step, and further extracts the impedance characteristics and thermal conduction characteristics of the chip.

[0090] Frequency Sweep Measurement and Spectrum Analysis: A network analyzer was used to apply a frequency sweep signal from 100Hz to 100MHz to the chip. The voltage and current responses at each frequency point were measured to obtain the complex impedance value. At 1MHz, the real part of the impedance was measured to be 85mΩ, and the imaginary part was -120mΩ (capacitive). Equivalent Circuit Fitting: Based on the obtained frequency domain impedance spectrum data (usually presented as a Nyquist plot or Bode plot), a distributed equivalent circuit model was constructed. This model includes parameters such as package parasitic inductance (approximately 0.8nH), bond wire resistance (approximately 25mΩ), and chip internal capacitance (approximately 150pF). The model parameters were optimized using a nonlinear least squares method to ensure that the root mean square error between the model and the measured spectrum was less than 3%. Temperature Compensation and High-Frequency Characteristic Generation: Combining thermal data (the chip junction temperature rises to 85℃ under full load), the temperature coefficient (0.4% / ℃) of key impedance parameters (such as metal interconnect resistance) was analyzed. After temperature compensation, a precise set of impedance parameters containing both frequency-varying and temperature-dependent characteristics is generated, which is used to evaluate impedance matching characteristics under high-frequency operating conditions.

[0091] Thermal time constant sequence extraction: The temperature response curves during the power step transition from 0.5W (standby) to 5W (full load) were analyzed. Using the structure function method or equivalent circuit model fitting, multiple thermal time constants representing different material layers were identified: silicon chip layer (τ1=12ms), encapsulation epoxy resin layer (τ2=280ms), and solder ball array (τ3=850ms).

[0092] 3D Thermal Model Construction: Combining the temperature distribution (spatial gradient) provided by thermal imaging data and the extracted thermal time constant, a 3D thermal conduction model of the chip was established. This model calculated the steady-state thermal resistance RθJC distribution from junction to shell, identifying a hotspot region with a thermal resistance of 18.5 K / W and a non-hotspot region with a thermal resistance of 9.2 K / W. Simultaneously, the heat capacity of each layer was estimated, with the active region of the chip showing a heat capacity of approximately 0.08 J / K.

[0093] Correlation analysis is performed between the impedance characteristic parameter set and the thermal conduction characteristic parameter set to generate comprehensive electrothermal coupling characteristic parameters, as shown in the following example:

[0094]

[0095] 203. Using the principle of time-domain reflectometer, analyze the signal transmission path inside the chip based on impedance characteristic parameters to obtain path characteristic parameters including signal integrity and transmission delay characteristics;

[0096] Specifically, a high-speed step signal is injected into the critical signal transmission path of the chip, and the reflected waveforms of each node in the transmission path are collected to generate time-domain reflected waveform data. Based on impedance characteristic parameters, impedance discontinuities are identified in the time-domain reflected waveform data to locate the impedance mismatch position in the internal transmission path of the chip. The time delay characteristics of the reflected waveform are analyzed, and combined with the impedance mismatch position information, the topology of the signal transmission path inside the chip is reconstructed. Based on the reconstructed transmission path topology, the propagation speed and attenuation coefficient of the signal in each transmission segment inside the chip are calculated to generate signal transmission characteristic parameters. By combining the impedance mismatch position, transmission path topology, and signal transmission characteristic parameters, the signal integrity and transmission delay characteristics are quantitatively evaluated to generate path characteristic parameters.

[0097] Furthermore, by comprehensively considering impedance mismatch locations, transmission path topology, and signal transmission characteristic parameters, the signal integrity and transmission delay characteristics are quantitatively evaluated, and path characteristic parameters are generated. This includes: constructing a signal reflection and crosstalk coupling model based on the distribution of impedance mismatch locations in the transmission path topology to generate signal integrity degradation characteristic data; calculating signal quality indices for key transmission paths using propagation speed and attenuation coefficients from signal transmission characteristic parameters, combined with signal integrity degradation characteristic data; establishing a multi-path transmission delay model based on the length differences of each transmission segment in the transmission path topology and signal transmission characteristic parameters to generate timing deviation characteristics; constructing a comprehensive evaluation matrix for signal integrity and transmission delay based on signal quality indices and timing deviation characteristics to generate quantitative evaluation results; and comparing the quantitative evaluation results with chip design specifications to identify parameter anomalies exceeding tolerance limits and generate path characteristic parameters including fault warning levels.

[0098] It should be noted that, based on the impedance characteristic parameters obtained in the previous step (parasitic inductance 0.8nH, distributed capacitance 150pF), the integrity and delay characteristics of the internal transmission path of the chip are analyzed by a high-precision TDR system.

[0099] A terahertz TDR system (Advantest TS9001, pulse width 50 fs) was used to inject a high-speed step signal with a rising edge of 20 ps into the critical signal path of the chip (the transmission line from the clock input pin to the core amplifier unit). The reflected waveforms at each node of the path were collected by contacting the BGA solder balls with a high-frequency probe. Measured data showed that the first reflection peak (amplitude +12%) appeared at timestamp t1=25.6 ps, and the second reflection peak (amplitude -8%) appeared at t2=48.3 ps, generating a time-domain reflection waveform sequence.

[0100] Based on impedance characteristic parameters (characteristic impedance reference 50Ω), the reflected waveform is analyzed: the positive peak at t1 indicates an increase in impedance, corresponding to an open circuit point in the microstrip line (bonded wire breakage), located 1.92mm from the test point; the negative peak at t2 indicates a decrease in impedance, corresponding to a distributed capacitive coupling point (short circuit between adjacent lines), located 3.62mm from the test point. Combining the time delay difference (Δt=22.7ps) with the chip layout, the signal path topology is reconstructed: input pin → bonded wire (length 1.5mm) → internal microstrip line (length 2.1mm) → output buffer, with a total path delay of approximately 85ps.

[0101] Based on the reconstructed topology, the signal transmission parameters of each transmission segment are calculated, and the signal integrity and transmission delay characteristics are comprehensively evaluated, as shown in the table below:

[0102]

[0103] By constructing a signal reflection model, the timing deviation of the critical path was calculated to be ±15ps, and the eye diagram quality index was 0.82 (pass threshold >0.75). Comprehensive evaluation showed that the path transmission delay was 85ps, within the chip specification tolerance (<100ps), but an open circuit in the bonding wire caused signal integrity degradation, generating a path characteristic parameter set with a medium fault warning level.

[0104] 204. Based on the theory of nonlinear system identification, and combined with the electrothermal coupling feature dataset and path feature parameters, a mathematical model of chip dynamic current and operating voltage is established to generate system identification results containing nonlinear features.

[0105] Specifically, based on the voltage and current time-series data in the electrothermal coupling feature dataset, a multivariate time series of the chip's operating state is constructed to generate a dynamic response feature set. Combining the signal transmission delay characteristics in the path feature parameters, the dynamic response feature set is reconstructed through time-delay embedding to generate an extended phase space dataset. The Volterra series expansion method is applied to process the extended phase space dataset, extracting the nonlinear kernel function features of the chip system to generate a nonlinear feature set. Based on the nonlinear feature set, a nonlinear autoregressive model of the chip's dynamic current and operating voltage is constructed, and the model coefficient matrix is ​​obtained through parameter identification. The model coefficient matrix is ​​then used to detect and verify the chip's dynamic response under different operating modes, generating system identification results that include model accuracy indicators and nonlinear features.

[0106] Furthermore, the dynamic response of the chip under different operating modes is detected and verified using the model coefficient matrix, generating system identification results that include model accuracy indicators and nonlinear characteristics. This also includes: designing test excitation signals covering the entire operating range of the chip based on the model coefficient matrix, generating a multi-mode verification test sequence; applying the multi-mode verification test sequence to the chip under test, simultaneously acquiring voltage and current response data, generating a measured dynamic response dataset; inputting the multi-mode verification test sequence into a nonlinear autoregressive model, calculating the theoretical detection response, generating a detection response dataset; comparing the measured dynamic response dataset with the detection response dataset, calculating the model detection error distribution, generating a model accuracy verification report; and combining the model accuracy verification report and the nonlinear characteristic parameters in the model coefficient matrix to generate system identification results that include model confidence level and system nonlinear characteristics.

[0107] It should be noted that, based on the electrothermal coupling feature dataset (containing voltage, current time-series data, and temperature distribution) and path feature parameters (typical signal transmission delay of 10 ps) generated in the previous steps, a mathematical model of dynamic current and operating voltage is established using nonlinear system identification theory. The specific implementation process is as follows:

[0108] Voltage-current timing data (sampling rate 100kS / s, duration 100ms) was extracted from the electrothermal coupling dataset, covering three states: standby (0.5W), medium load (2W), and full load (5W). Under full load, the voltage fluctuation range was 3.2–3.4V, and the transient peak current was 1.5A.

[0109] By incorporating the average transmission delay (10 ps) from the path feature parameters, a time-delay embedding reconstruction is performed on the dynamic response feature set: the univariate sequence is expanded into a multidimensional phase space, the embedding dimension is set to 3, and the delay time step is set to 5 sampling points (corresponding to 50 μs). The reconstructed extended phase space dataset contains 10,000 sample points, each containing the variables: [V(t), I(t), I(t-5), I(t-10)].

[0110] The extended dataset is processed using discrete second-order Volterra series, and the model expression is:

[0111] ,

[0112] The kernel function truncation length T=10, and the first-order kernel function is identified using correlation analysis. (τ) and second-order kernel function Nonlinear characteristics were extracted: the first-order kernel peak appeared at τ=2 (amplitude 0.45A / V), characterizing the linear gain of voltage on current; the second-order kernel diagonal peak (τ1=τ2=2) had an amplitude of -0.08A / V. 2This reflects the system's saturation characteristics. The generated nonlinear feature set includes the kernel function amplitude, memory depth, and nonlinear gain coefficient.

[0113] Based on the nonlinear feature set, a NARX model is established:

[0114]

[0115] The parameters were optimized through nonlinear least squares fitting, resulting in the coefficient matrix: a1=0.72, a2=0.38, b1=−0.05, b2=−0.12, c=0.02. The model fitting error variance is 0.003A. 2 .

[0116] Design test stimulus sequences covering the entire operating range, including voltage step (3.0V→3.6V), sinusoidal sweep (10Hz–100kHz), and pseudo-random binary sequence (PRBS).

[0117] Comparison of measured and detected responses (taking full-load step response as an example): Measured current rise time: 2.0 μs, overshoot 8%; Detected current rise time: 2.1 μs, overshoot 7.5%. Root mean square error (RMSE) is 0.05 A, relative error <3%.

[0118] Generate a model accuracy verification report and fault warning indicators (as shown in the table below).

[0119]

[0120] The final system identification results include: NARX model coefficient matrix, nonlinear kernel function feature set, accuracy verification report (average RMSE=0.03A), and fault warning level based on confidence level (>85%) and degree of nonlinear distortion. This model can accurately detect the current response of the chip under dynamic load.

[0121] 205. By combining impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification results, chip detection results and fault location information are generated through multi-parameter fusion analysis.

[0122] Specifically, based on parasitic parameters and material properties in impedance characteristics, and combined with thermal resistance distribution in thermal conductivity characteristics, an electrothermal correlation feature matrix is ​​established to generate a chip structure integrity index. Using signal integrity assessment results in path characteristic parameters and nonlinear characteristics in system identification results, the degree of chip functional performance degradation is analyzed, generating a functional performance degradation index. Based on model accuracy indices in system identification results and transmission delay characteristics in path characteristic parameters, the chip timing stability is evaluated, generating a timing stability index. Based on the electrothermal correlation feature matrix and functional performance degradation index, potential chip fault modes are identified through multi-dimensional correlation analysis, generating fault type judgment results. Combining the timing stability index and fault type judgment results, a spatial positioning algorithm is used to determine the fault location and impact range, generating a chip detection result containing health status level and precise location information.

[0123] It should be noted that, based on the impedance characteristic parameters (parasitic inductance 0.8nH), thermal conduction characteristic parameters (junction-to-case thermal resistance 18.5K / W), path characteristic parameters (signal transmission delay 85ps), and system identification results (nonlinear autoregressive model accuracy RMSE = 0.05A) extracted in the previous steps, a health status assessment report is generated through multi-parameter fusion analysis. The specific implementation process is as follows:

[0124] An electrothermal correlation matrix was constructed by combining the parasitic resistance (25mΩ) in the impedance parameters and the thermal resistance distribution (18.5K / W in the hot spot region) in the thermal parameters. When the chip temperature rises from 25℃ to 85℃, the parasitic resistance increases by 15% due to the self-heating effect, causing the electrothermal coupling coefficient to exceed the limit (>10%), which is marked as a structural degradation warning.

[0125] Functional performance degradation metrics: These are achieved using signal quality metrics from path characteristic parameters (eye diagram height ratio 0.82, threshold > 0.75) and the nonlinear gain coefficient (-0.08 A / V) from system identification results. 2 The analysis focused on functional degradation. The measured signal integrity degradation (8% overshoot) was correlated with the nonlinear saturation characteristics, resulting in a medium level of functional degradation. Timing stability metrics: Based on the detection error (RMSE=0.05A) and path transmission delay deviation (±15ps) of the system identification model, the calculated timing jitter rate was 4.2% (tolerance <5%), classifying timing stability as slightly risky.

[0126] Multi-dimensional correlation analysis revealed that the exceeding of the electrothermal coupling coefficient and signal integrity degradation were synchronous in time (correlation coefficient 0.92), pointing to impedance mismatch and heat accumulation caused by bond wire aging. Simultaneously, the nonlinear saturation characteristics were correlated with timing jitter, suggesting degradation of the output stage transistors.

[0127] Spatial localization algorithm: Combining the coordinates of the thermal imaging hotspot (1.2mm and 0.8mm from the top left corner of the chip) and the TDR impedance mismatch point (1.5mm from the input pin), the fault was located at the connection between the end of the bonding wire and the output buffer using triangulation, with an impact range of approximately 0.3mm. 2 .

[0128] Based on the above analysis, a quantitative health status report was generated (as shown in the table below). The final assessment of the chip's health level is moderate degradation, and it is recommended to replace the bonding wires first and monitor the output stage current.

[0129]

[0130] 206. Before testing begins, a system benchmark test is performed using a standard calibration chip to obtain the calibration coefficients and system error distribution for each measurement channel, generating a system calibration parameter set. Based on the system calibration parameter set, error compensation and accuracy correction are performed on the real-time acquired electrothermal coupling characteristic dataset to generate corrected measurement data. Under different chip operating modes, the impact of ambient temperature changes and power fluctuations on the measurement results is monitored, an environmental interference characteristic model is established, and dynamic compensation parameters are generated. The corrected measurement data is then corrected in real time using the dynamic compensation parameters to eliminate the influence of environmental factors on the test results, generating environmental robustness test data. The environmental robustness test data is compared and analyzed with a historical database of qualified chips to establish a long-term trend analysis report of the test results, generating a chip reliability test assessment.

[0131] It should be noted that the testing system for a 5W power amplifier chip (3.3V operating voltage, BGA package) explains how to ensure the accuracy and environmental robustness of the measurement results through system calibration, environmental compensation, and data analysis before and during testing, and ultimately generate a reliability test assessment.

[0132] Standard calibration chip usage: Select a standard chip with known parameters (precision resistor with a resistance of 1.000Ω±0.01% and a reference source with a thermistor coefficient of 50ppm / ℃) for system benchmark testing.

[0133] Calibration coefficient acquisition: Voltage channel: Apply standard voltage 2.5V, measure value 2.503V, calculate calibration coefficient. Current channel: Apply standard current 1A, measure value 1.012A, calibration factor. Thermal imager temperature: 29.7℃ at a standard blackbody source of 30℃, calibration factor. System error distribution: Statistical error distribution from multiple measurements (Gaussian distribution of voltage error: mean +0.12%, standard deviation 0.05%), generating a system calibration parameter set containing calibration coefficients and error distributions for each channel.

[0134] Application of error compensation formula:

[0135] in The voltage was taken from the mean of the error distribution. The original voltage measurement was 3.302V, and the corrected value was... Accuracy correction results: After correction, the voltage measurement accuracy improved from ±0.5% to ±0.1%, the current accuracy improved from ±1% to ±0.2%, and the temperature accuracy improved from ±1℃ to ±0.3℃.

[0136] Environmental Interference Characteristic Model: Temperature Effect: When the ambient temperature rises from 25℃ to 40℃, the chip's static current drifts by +0.5mA / ℃. Compensation parameters are established.

[0137] mA. Power supply fluctuation: Monitors power supply ripple (100mVpp) causing voltage measurement jitter of ±0.8%, and generates dynamic compensation parameters. Real-time correction: The measured data is corrected by applying dynamic compensation parameters. The measured current at full load is 1.48A, which is corrected to 1.465A after temperature and ripple compensation. This eliminates the influence of environmental factors and generates environmentally robust test data.

[0138] Historical database comparison: The environmental robustness test data is compared with the historical qualified chip database (including data of 1,000 qualified chips) to analyze the long-term drift of key parameters (thermal resistance, impedance).

[0139] Reliability testing and assessment: It was found that the thermal resistance R of this chip... θJC =19.2K / W, a 3.8% deviation from the historical average (18.5K / W), but still within the tolerance (±5%). Combined with the historical trend of power supply current drift rate with temperature (0.5mA / ℃), the chip's lifetime under high-temperature operating conditions is estimated to be 8.5 × 10⁻⁶. 4 Hours (less than 10 on average) 5 (Hours), generate a reliability test report. The data summary is shown in the table below:

[0140]

[0141] In this embodiment of the invention, impedance spectrum analysis and thermal time constant calculation are performed on the electrothermal coupling feature dataset. This not only extracts conventional impedance characteristic parameters but also deeply analyzes the relaxation process in the impedance spectrum, constructs a distributed equivalent circuit model, and analyzes the temperature dependence of electrical characteristic parameters in conjunction with thermal conduction characteristics, generating a precise parameter set after temperature compensation. Regarding thermal conduction characteristics, a series of thermal time constants are extracted using various methods, and a three-dimensional thermal conduction model is established to calculate thermal resistance and heat capacity distribution. Utilizing the principle of a time-domain reflectometer, the signal transmission path inside the chip is analyzed based on impedance characteristic parameters. This not only locates the impedance mismatch position but also reconstructs the transmission path topology, calculates signal transmission characteristic parameters, and further quantifies and evaluates signal integrity and transmission delay characteristics, constructing a comprehensive evaluation matrix. This system can precisely characterize the performance features of a chip in various aspects, providing detailed and accurate parameter data for chip design optimization, performance evaluation, and fault diagnosis. This helps improve chip performance and reliability, and reduce product failure rates. It can comprehensively and accurately assess the health status of the chip, achieving precise fault location, providing clear guidance for chip maintenance and repair, reducing maintenance time and costs, and improving chip lifespan and operating efficiency. It effectively eliminates the influence of system errors and environmental factors on the test results, ensuring the accuracy and environmental robustness of the measurement results. It can promptly detect potential trends in chip performance changes, providing strong support for long-term chip reliability assessment, helping to take preventative measures to ensure stable system operation.

[0142] The above describes the high-efficiency chip detection method in the embodiments of the present invention. The following describes the high-efficiency chip detection system in the embodiments of the present invention. Please refer to [link / reference]. Figure 5 One embodiment of the high-efficiency chip testing system of the present invention includes: a data acquisition module 301, used to simultaneously acquire electrical signals from the power supply pins and thermal imaging data from the chip surface while the chip under test is in operation, generating an electrothermal coupling feature dataset; a parameter extraction module 302, used to perform impedance spectrum analysis and thermal time constant calculation on the electrothermal coupling feature dataset, extracting impedance characteristic parameters and thermal conduction characteristic parameters of the chip at multiple frequency points; a path analysis module 303, used to analyze the internal signal transmission path of the chip based on the impedance characteristic parameters, and obtain path characteristic parameters; a detection optimization module 304, used to combine the electrothermal coupling feature dataset and path characteristic parameters to establish a mathematical model of the chip's dynamic current and operating voltage, and generate system identification results; and an evaluation detection module 305, used to integrate the impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification results to generate chip detection results and fault location information.

[0143] In this embodiment of the invention, impedance spectrum analysis and thermal time constant calculation are performed on the electrothermal coupling feature dataset. Simultaneously, impedance and thermal conductivity parameters of the chip at multiple frequency points are extracted. This allows for in-depth analysis of chip characteristics from both electrical and thermal perspectives. Compared to single parameter extraction, this provides a more detailed characterization of chip performance, offering a more comprehensive basis for accurately assessing chip health and locating faults. Analyzing the internal signal transmission path based on impedance parameters and obtaining path characteristic parameters creates a novel method for analyzing the internal signal transmission path from an impedance perspective, facilitating a deeper understanding of the chip's internal working mechanism and identifying potential signal transmission problems. A mathematical model of the chip's dynamic current and operating voltage is established by combining the electrothermal coupling feature dataset and path characteristic parameters, generating system identification results. This comprehensively considers multiple factors such as electricity, heat, and signal transmission paths, providing a more accurate simulation of the chip's actual operating conditions compared to traditional models, improving the accuracy of system identification and providing strong support for chip performance evaluation and fault detection. Finally, by integrating impedance parameters, thermal conductivity parameters, path characteristic parameters, and system identification results, chip detection results and fault location information are generated, enabling assessment of chip health from multiple angles and accurate identification of fault locations.

[0144] above Figure 5 The chip high-efficiency testing system in this embodiment of the invention is described in detail from the perspective of modular functional entities. The chip high-efficiency testing device in this embodiment of the invention is described in detail from the perspective of hardware processing.

[0145] Figure 6 This is a schematic diagram of a high-efficiency chip testing device provided in an embodiment of the present invention. The device 400 may include a processor 401, a receiver 402, a transmitter 403, and a memory 404. The receiver 402, transmitter 403, and memory 404 are respectively connected to the processor 401 via a bus. It should be noted that in some possible implementations, the processor 401 and the memory 404 may be integrated together.

[0146] The processor 401 includes one or more processing cores. The processor 401 executes the methods performed by the base station in the random access method provided in this application embodiment by running software programs and modules. The memory 404 can be used to store software programs and modules. Specifically, the memory 404 can store an operating system 4041 and at least one application module 4042 required for a function. The receiver 402 is used to receive communication data sent by other devices, and the transmitter 403 is used to send communication data to other devices.

[0147] The present invention also provides a high-efficiency chip testing device, which includes a memory and a processor. The memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor performs the steps of the high-efficiency chip testing method in the above embodiments.

[0148] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the steps of the chip efficient detection method.

[0149] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0150] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0151] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-efficiency chip detection method, characterized in that, The high-efficiency chip detection method includes: While the chip under test is in operation, the electrical signals of its power pins and thermal imaging data of the chip surface are collected simultaneously to generate an electrothermal coupling feature dataset. Impedance spectral analysis and thermal time constant calculation were performed on the electrothermal coupling feature dataset to extract the chip's impedance and thermal conductivity parameters at multiple frequency points, including: The voltage and current data in the electrothermal coupling feature dataset are excited by a frequency sweep signal to obtain the voltage and current response of the chip at different frequencies and generate frequency domain impedance spectrum data. Based on the temperature distribution data in the electrothermal coupling feature dataset, the temperature response curve of the chip under power step change is analyzed, and the thermal time constant sequence is extracted. Equivalent circuit model fitting is performed on frequency domain impedance spectrum data to identify internal parasitic parameters and material property parameters of the chip, and to generate a set of impedance characteristic parameters; By combining the thermal time constant sequence and temperature distribution data, a three-dimensional thermal conduction model of the chip is established, the thermal resistance and thermal capacity distribution are calculated, and a set of thermal conduction characteristic parameters is generated. Correlation analysis is performed on the impedance characteristic parameter set and the thermal conduction characteristic parameter set to identify electrothermal coupling characteristics and generate complete impedance characteristic parameters and thermal conduction characteristic parameters. Based on the impedance characteristic parameters, the internal signal transmission path of the chip is analyzed to obtain path characteristic parameters, including: Inject high-speed step signals into the key signal transmission path of the chip, collect the reflection waveforms of each node in the transmission path, and generate time-domain reflection waveform data; Based on the impedance characteristic parameters, impedance discontinuities are identified in the time-domain reflection waveform data to locate the impedance mismatch position of the transmission path inside the chip. By analyzing the time delay characteristics of the reflected waveform and combining the impedance mismatch location information, the topology of the signal transmission path inside the chip is reconstructed. Based on the reconstructed transmission path topology, the propagation speed and attenuation coefficient of the signal in each transmission segment inside the chip are calculated, and signal transmission characteristic parameters are generated. Based on the impedance mismatch location, transmission path topology, and signal transmission characteristic parameters, the signal integrity and transmission delay characteristics are quantitatively evaluated, and path characteristic parameters are generated. By combining the electrothermal coupling feature dataset and path feature parameters, a mathematical model of chip dynamic current and operating voltage is established to generate system identification results; By combining the impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters, and system identification results, chip detection results and fault location information are generated.

2. The high-efficiency chip detection method according to claim 1, characterized in that, include: Based on the voltage and current time series data in the electrothermal coupling feature dataset, a multivariate time series of chip operating state is constructed to generate a dynamic response feature set. By combining the signal transmission delay characteristics in the path feature parameters, the dynamic response feature set is reconstructed by time delay embedding to generate an extended phase space dataset; Process the extended phase space dataset to extract the nonlinear kernel function features of the chip system and generate a nonlinear feature set; A nonlinear autoregressive model of chip dynamic current and operating voltage is constructed based on a nonlinear feature set, and the model coefficient matrix is ​​obtained through parameter identification. The dynamic response of the chip under different operating modes is detected and verified using the model coefficient matrix, and system identification results are generated.

3. The high-efficiency chip detection method according to claim 2, characterized in that, Extracting nonlinear kernel function features from extended phase space datasets for chip systems: in, To detect current; This is the DC component; ( ) is a first-order kernel function; It is a second-order kernel function; This is the error term, representing noise or unmodeled dynamics not captured by the model; the truncation length T=10. t represents the current time sampling point; The thermal time constant; It is a fast time constant; The time constant is slow. ； ； 。 4. The high-efficiency chip detection method according to claim 1, characterized in that, Based on the model coefficient matrix, test excitation signals covering the entire operating range of the chip are designed, and multi-mode verification test sequences are generated. A multi-mode verification test sequence is applied to the chip under test, and voltage and current response data are collected simultaneously to generate a measured dynamic response dataset. Input the multi-mode validation test sequence into the nonlinear autoregressive model to calculate the theoretical detection response and generate a detection response dataset. By comparing the measured dynamic response dataset with the detection response dataset, the model detection error distribution is calculated, and a model accuracy verification report is generated. The system identification results are generated by combining the model accuracy verification report and the nonlinear feature parameters in the model coefficient matrix.

5. The high-efficiency chip detection method according to claim 1, characterized in that, include: Based on the parasitic parameters and material properties in the impedance characteristics, and combined with the thermal resistance distribution in the thermal conductivity characteristics, an electrothermal correlation feature matrix is ​​established to generate a chip structure integrity index. By utilizing the signal integrity assessment results in the path characteristic parameters and the nonlinear characteristics in the system identification results, the degree of chip functional performance degradation is analyzed, and a functional performance degradation index is generated. Based on the model accuracy index in the system identification results and the transmission delay characteristics in the path feature parameters, the stability of the chip timing characteristics is evaluated, and a timing stability index is generated. Based on the electrothermal correlation feature matrix and functional performance degradation index, potential fault modes of the chip are identified through multi-dimensional correlation analysis, and fault type judgment results are generated. By combining timing stability indicators and fault type judgment results, the location and scope of the fault are determined, and chip detection results are generated.

6. The high-efficiency chip detection method according to claim 1, characterized in that, Also includes: Before the test begins, a system benchmark test is performed to obtain the calibration coefficients and system error distribution of each measurement channel, and a system calibration parameter set is generated. Error compensation and accuracy correction are performed on the real-time acquired electrothermal coupling feature dataset based on the system calibration parameter set to generate corrected measurement data; Under different chip operating modes, monitor the impact of ambient temperature changes and power fluctuations on measurement results, establish an environmental interference characteristic model, and generate dynamic compensation parameters. The dynamic compensation parameters are used to correct the calibrated measurement data in real time, eliminating the influence of environmental factors on the test results and generating environmentally robust test data. By comparing and analyzing environmental robustness test data with a historical database of qualified chips, a long-term trend analysis report of the test results is established, generating a chip reliability test assessment.

7. A high-efficiency chip detection system, characterized in that, The high-efficiency chip detection system includes: The data acquisition module is used to simultaneously acquire electrical signals from the power pins and thermal imaging data from the surface of the chip while it is in operation, and generate an electrothermal coupling feature dataset. The parameter extraction module is used to perform impedance spectral analysis and thermal time constant calculation on the electrothermal coupling feature dataset, and to extract the impedance characteristic parameters and thermal conduction characteristic parameters of the chip at multiple frequency points, including: The voltage and current data in the electrothermal coupling feature dataset are excited by a frequency sweep signal to obtain the voltage and current response of the chip at different frequencies and generate frequency domain impedance spectrum data. Based on the temperature distribution data in the electrothermal coupling feature dataset, the temperature response curve of the chip under power step change is analyzed, and the thermal time constant sequence is extracted. Equivalent circuit model fitting is performed on frequency domain impedance spectrum data to identify internal parasitic parameters and material property parameters of the chip, and to generate a set of impedance characteristic parameters; By combining the thermal time constant sequence and temperature distribution data, a three-dimensional thermal conduction model of the chip is established, the thermal resistance and thermal capacity distribution are calculated, and a set of thermal conduction characteristic parameters is generated. Correlation analysis is performed on the impedance characteristic parameter set and the thermal conduction characteristic parameter set to identify electrothermal coupling characteristics and generate complete impedance characteristic parameters and thermal conduction characteristic parameters. The path analysis module is used to analyze the signal transmission path inside the chip based on the impedance characteristic parameters and obtain path characteristic parameters, including: Inject high-speed step signals into the key signal transmission path of the chip, collect the reflection waveforms of each node in the transmission path, and generate time-domain reflection waveform data; Based on the impedance characteristic parameters, impedance discontinuities are identified in the time-domain reflection waveform data to locate the impedance mismatch position of the transmission path inside the chip. By analyzing the time delay characteristics of the reflected waveform and combining the impedance mismatch location information, the topology of the signal transmission path inside the chip is reconstructed. Based on the reconstructed transmission path topology, the propagation speed and attenuation coefficient of the signal in each transmission segment inside the chip are calculated, and signal transmission characteristic parameters are generated. Based on the impedance mismatch location, transmission path topology, and signal transmission characteristic parameters, the signal integrity and transmission delay characteristics are quantitatively evaluated, and path characteristic parameters are generated. The detection optimization module is used to combine the electrothermal coupling feature dataset and path feature parameters to establish a mathematical model of the chip's dynamic current and operating voltage, and generate system identification results. The evaluation and detection module is used to integrate the impedance characteristic parameters, thermal conduction characteristic parameters, path characteristic parameters and system identification results to generate chip detection results and fault location information.

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