Electroencephalogram acquisition and information processing system and information processing method

Abstract

According to the electroencephalogram collecting and information processing system and method, the service analysis process processing line of the whole system is clear, a plurality of function modules correspond to different threads, and the different threads run in parallel to improve the data processing efficiency; different function modules are provided with corresponding independent buffer areas, the buffer areas are used for storing data needing to be processed by the corresponding function modules, and a single function module can send a processing result to the buffer area of a target function module after completing data processing in a corresponding thread of the single function module. Therefore, control decoupling and data decoupling among a plurality of functional modules are realized. Therefore, the system has high stability and maintainability, and meanwhile, each functional module can be independently tested, so that a new module can be conveniently inserted into the upper computer or the module can be conveniently upgraded, and the expandability of the electroencephalogram acquisition and information processing system is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of information processing, in particular to an electroencephalogram acquisition and information processing system and an information processing method. BACKGROUND

[0002] Electroencephalogram information acquisition is an important means of neuroscience research, which is used for monitoring and analyzing brain activity. With the deepening of neuroscience research, electroencephalogram acquisition systems are developing towards high precision, high efficiency and high real-time.

[0003] However, although the existing electroencephalogram acquisition system has realized basic signal acquisition, filtering, storage and waveform drawing functions, due to the close coupling between different modules and the high dependence between modules, the electroencephalogram acquisition system has problems of poor stability and poor scalability. SUMMARY

[0004] The present application provides an electroencephalogram acquisition and information processing system and an information processing method to solve the problems in the related prior art. The technical scheme provided by the present application is as follows:

[0005] The present application provides an electroencephalogram acquisition and information processing system, which comprises:

[0006] A plurality of electroencephalogram electrodes connected to the brain of a living body to detect electroencephalogram signals;

[0007] A plurality of acquisition front ends connected to the electroencephalogram electrodes to acquire electroencephalogram signals and pre-process the acquired electroencephalogram signals;

[0008] A control module connected to the plurality of acquisition front ends to perform secondary processing on the pre-processed electroencephalogram signals;

[0009] An upper computer in communication with the control module to receive the secondary-processed electroencephalogram signals and perform data processing, wherein

[0010] The upper computer comprises a system control module and a plurality of function modules in communication with the system control module;

[0011] The system control module sends operation instructions to each function module to trigger the function modules to start running and process data;

[0012] The plurality of function modules correspond to different threads, the different threads run in parallel, and each function module is configured with a corresponding independent buffer area, the buffer area is used to store data required to be processed by the function module, and after a single function module completes data processing in its corresponding thread, it can send the processing result to the buffer area of the target function module.

[0013] Further, after the plurality of function modules start running, data storage association information of a corresponding buffer is detected first, and when the data storage association information meets a predetermined condition, data stored in the buffer is processed, wherein the data in the buffer of the function module is sent by a hardware device or other function modules, and the data sent by the other function modules is data obtained after data processing of the other function modules.

[0014] Further, the data storage association information is a data amount, and the predetermined condition includes that the data amount in the buffer is not less than a data amount threshold.

[0015] Further, a target function module corresponding to each of the function modules is determined based on a data flow relationship between the function modules, and the data flow relationship is unidirectional flow.

[0016] Further, the function modules include one or more of a device control module, a lead calculation module, a filtering module, a saving module, a noise reduction module, a data visualization module, and a waveform drawing module.

[0017] The data flow relationship includes at least one of:

[0018] A data flow relationship from the device control module to the lead calculation module, wherein the target function module is the lead calculation module.

[0019] A data flow relationship from the lead calculation module to the filtering module, wherein the target function module is the filtering module.

[0020] A data flow relationship from the lead calculation module to the saving module, wherein the target function module is the saving module.

[0021] A data flow relationship from the filtering module to the noise reduction module, wherein the target function module is the noise reduction module.

[0022] A data flow relationship from the filtering module to the data visualization module, wherein the target function module is the data visualization module.

[0023] A data flow relationship from the noise reduction module to the waveform drawing module, wherein the target function module is the waveform drawing module.

[0024] Further, the control module comprises an ARM part and an FPGA part, the control module is configured with a control flow thread and a data flow thread which are independent of each other, wherein in the control flow thread, the ARM part receives the operation instruction sent by the host computer and configures the FPGA part with corresponding parameters according to the operation instruction; in the data flow thread, the ARM part receives the running result of the operation instruction and sends the running result to the host computer after conversion.

[0025] Further, the ARM part comprises an FPGA control module and a data control module, and the FPGA part comprises an instruction sending state machine and a data reading state machine, wherein the FPGA control module communicates with the instruction sending state machine through an AXI bus to realize the control flow thread; the data reading state machine communicates with the data control module through DMA data transmission to realize the data flow thread.

[0026] Further, the control module further comprises a storage submodule and a data buffer submodule to ensure that there is sufficient buffer space to temporarily store data in high-speed real-time signal acquisition, wherein the storage submodule is connected with the ARM part, and the data buffer submodule is connected with the FPGA part.

[0027] Further, the preprocessing of the electroencephalogram signal comprises amplification, filtering, analog-to-digital conversion and digital processing of weak electroencephalogram signals; and the secondary processing of the electroencephalogram signal comprises data serial-to-parallel conversion, data preliminary screening, data frame construction, data caching and data transmission conversion.

[0028] In addition, the present application further provides an information processing method, which is applied to the electroencephalogram acquisition and information processing system, and the method comprises the following steps:

[0029] The operation instruction is sent to the control module by the system control module of the host computer to control a plurality of electroencephalogram electrodes to start collecting electroencephalogram signals.

[0030] The collected electroencephalogram signals are transmitted to the host computer after preprocessing by the acquisition front end and secondary processing by the control module, the host computer stores the received electroencephalogram signals in the buffer area, and the functional module performs data processing based on the data in the corresponding buffer area.

[0031] In addition, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps in the above information processing method.

[0032] In addition, the application further provides a computer program product, which stores a computer program, and the computer program, when executed by a processor, implements the steps in the information processing method.

[0033] For the prior art, the application has the following beneficial effects:

[0034] The application provides an electroencephalogram acquisition and information processing system and an information processing method. By arranging a control module, direct interaction between an upper computer and massive electroencephalogram acquisition data is avoided, and a data processing relay station and a temporary control core are provided. At the same time, the business analysis process of the entire system is clear, different functional modules are arranged to correspond to different threads, and different threads are run in parallel to improve the data processing efficiency; different functional modules are configured with corresponding independent buffer areas, and the running state of each functional module is only controlled by the system control module and is irrelevant to upstream and downstream modules, so that the control between the multiple functional modules of the electroencephalogram acquisition and information processing system provided by the application is completely decoupled. At the same time, the related data of a single functional module are processed in the thread of the functional module, and only the processing result is output to the target functional module; and the data flow between the functional modules is unidirectional, and there is no back-and-forth interaction between the data of the functional modules, so that the data between the multiple functional modules of the electroencephalogram acquisition and information processing system provided by the application are also completely decoupled.

[0035] In summary, the electroencephalogram acquisition and information processing system provided by the application has high stability and maintainability. In addition, the control and data between the functional modules are decoupled, and each functional module can also be independently tested, so that new modules or module upgrades can be inserted in the upper computer. At the same time, the newly inserted modules or upgraded modules can also be managed by the system control module, so as to enhance the scalability of the electroencephalogram acquisition and information processing system. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0037] Figure 1 is a schematic diagram of the overall structure of the electroencephalogram acquisition and information processing system in some embodiments of the application;

[0038] Figure 2 is a schematic diagram of the detailed structure of the electroencephalogram acquisition and information processing system in some embodiments of the application;

[0039] Figure 3is a control module structure schematic diagram in the electroencephalogram acquisition and information processing system in some embodiments of the present application;

[0040] Figure 4 is a structure schematic diagram of the host computer in the electroencephalogram acquisition and information processing system in some embodiments of the present application;

[0041] Figure 5 is a flow schematic diagram of the information processing method in the electroencephalogram acquisition and information processing system in some embodiments of the present application.

[0042] The figure mark explanation:

[0043] 1. Electroencephalogram acquisition and information processing system;

[0044] 100. Electroencephalogram electrode;

[0045] 200. Acquisition front end;

[0046] 300. Control module; 310. FPGA part; 320. ARM part; 311. Running control state machine; 312. Instruction sending state machine; 313. Data reading state machine; 314. Data buffer sub-module; 321. Target system control module, 322. FPGA control module; 323. Data control module; 324. Communication module; 325. Storage sub-module;

[0047] 400. Host computer; 410. System control module; 420. Function module; 421. Device control module; 422. Lead calculation module; 423. Filtering module; 424. Saving module; 425. Noise reduction module; 426. Data visualization module; 427. Waveform drawing module. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0049] It should be understood that although the terms "first", "second" and the like are used herein to describe various elements or other objects, these elements or objects should not be limited by these terms. These terms are only used to distinguish one element / object from another element / object.

[0050] The application provides an electroencephalogram acquisition and information processing system, an information processing method and a computer readable storage medium. The information processing method is executed by the electroencephalogram acquisition and information processing system, which can be integrated in a computer device, which can be a server or a terminal device.

[0051] The server can be a stand-alone physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services. The terminal device can be a medical robot, a monitoring device, a treatment device, an examination device, an in-vitro diagnostic device, etc., but is not limited thereto.

[0052] Before the scheme in the embodiments of the application is described in detail, the existing problems are analyzed.

[0053] Electroencephalogram information acquisition and processing play an important role in the fields of neuroscience research, clinical diagnosis and brain-computer interface technology. With the rapid development of electronic technology and computer science, electroencephalogram information acquisition and processing systems are developing towards high precision, high efficiency and high real-time.

[0054] However, the existing electroencephalogram information acquisition system has realized basic signal acquisition, filtering, storage and waveform drawing functions, but still has obvious deficiencies in data processing efficiency, system stability, coupling degree between modules and scalability. Specifically, the data processing efficiency is low, and a single-thread processing mode is often used, which limits the processing speed in high-throughput data scenarios; the system stability is poor, and the modules are tightly coupled, so that a fault in one module can easily cause the entire system to crash; the maintenance cost is high, and the modules are highly dependent, making system maintenance and upgrading complex and time-consuming; the scalability is poor, and the existing system architecture is closed, making it difficult to flexibly add new functions or modules.

[0055] Therefore, there is an urgent need for an electroencephalogram acquisition and information processing system that can solve the above technical problems.

[0056] The technical scheme of the application is described in detail through the following embodiments. It should be noted that the order of the following embodiments is not limited to the preferred order of the embodiments.

[0057] It should be noted that the electroencephalogram acquisition and information processing system can be a system for electroencephalogram information acquisition and processing, or other systems with multiple functional modules, such as electrocardiogram and electroencephalogram acquisition and information processing systems, electrocardiogram, electromyogram and electroencephalogram acquisition and information processing systems, etc., which are not limited by the embodiments of the application.

[0058] In some embodiments, the electroencephalogram acquisition and information processing system comprises a data acquisition module, a data preprocessing module, a data processing module, a data storage module and a data transmission module. Figure 1 and Figure 2As shown, the present application provides an electroencephalogram acquisition and information processing system 1, which comprises:

[0059] a plurality of electroencephalogram electrodes 100 connected to the brain of a living body to detect electroencephalogram signals;

[0060] a plurality of acquisition front ends 200 connected to the electroencephalogram electrodes 100 in correspondence to acquire electroencephalogram signals and pre-process the acquired electroencephalogram signals;

[0061] a control module 300 connected to the plurality of acquisition front ends 200 to perform secondary processing on the pre-processed electroencephalogram signals;

[0062] a host computer 400 in communication with the control module 300 to receive the secondary-processed electroencephalogram signals for data processing, wherein

[0063] the host computer 400 comprises a system control module 410 and a plurality of function modules 420 in communication with the system control module 410;

[0064] the system control module 410 sends operation instructions to each function module 420 to trigger the function modules 420 to start running and process data;

[0065] the plurality of function modules 420 correspond to different threads, the different threads run in parallel, and each function module 420 is configured with a corresponding independent buffer area, the buffer area is used to store data required to be processed by the corresponding function module 420, and after a single function module 420 completes data processing in its corresponding thread, it can send the processing result to the buffer area of the target function module.

[0066] Optionally, in some embodiments, the plurality of electroencephalogram electrodes 100 can be scalp electrodes and / or electrocorticography (ECoG) electrodes and / or stereoelectroencephalography (SEEG) electrodes, wherein the scalp electrodes perform non-invasive electroencephalogram activity recording; the ECoG electrodes are placed on the surface of the cerebral cortex to record cortical electrical activity; and the SEEG electrodes are inserted into specific brain regions to capture deep structure electrical activity.

[0067] Optionally, in some embodiments, the plurality of acquisition front ends 200 are connected to the electroencephalogram electrodes 100 in correspondence through lead wires to ensure that the electroencephalogram signals can be transmitted from the electroencephalogram electrodes 100 to the acquisition front ends 200. It should be noted that the acquisition front ends 200 can be provided with compatible interfaces of the electroencephalogram electrodes 100 to facilitate connection with different types of electroencephalogram electrodes 100.

[0068] Optionally, in some embodiments, the preprocessing of the collected electroencephalogram signals by the acquisition front end 200 includes amplification, filtering, analog-to-digital conversion, and other digital processing of weak electroencephalogram signals.

[0069] Optionally, in some embodiments, the control module 300 is connected with the acquisition front end 200 and the host computer 400, and the secondary processing of the preprocessed electroencephalogram signals by the control module 300 includes data serial-to-parallel conversion, data preliminary screening, data frame construction, data caching, data transmission conversion, and other processing.

[0070] Optionally, in some embodiments, the host computer 400 refers to a computer or device that is in a high-level control in a multi-computer system or a multi-layer network system. The host computer 400 is usually responsible for managing and controlling the entire system, receiving data from lower-level devices (i.e., the control module 300 and the acquisition front end 200, etc.), processing and decision-making, and sending instructions to the control module 300. The host computer 400 is in communication connection with the control module 300.

[0071] Optionally, a serial-to-USB-TypeC interface is provided between the host computer 400 and the control module 300 to establish a wired connection. For example, the host computer 400 and the control module 300 are connected based on a bus protocol. The host computer 400 can also be connected with the control module 300 through a wireless manner. The wireless connection mode includes short-range wireless technology, medium- and long-range wireless technology, etc.

[0072] Optionally, in some embodiments, the operation instructions of the system control module 410 include a running start signal, which is a signal for starting the running of each functional module 420 of the electroencephalogram acquisition and information processing system 1. Specifically, the system control module 410 sends the running start signal to each functional module 420 through the connection between the system control module 410 and each functional module 420, so that each functional module 420 works based on the respective running logic of each functional module 420 and processes the received data after receiving the running start signal.

[0073] Optionally, in some embodiments, the plurality of functional modules 420 correspond to different threads, and the threads of each functional module 420 run in parallel. That is, different functional modules 420 correspond to running in different threads, and different threads can run in parallel. For better understanding, for example, the plurality of functional modules 420 include a device control module 421, a lead calculation module 422, a filtering module 423, a noise reduction module 425, a waveform drawing module 427, a data visualization module 426, and a saving module 424, etc., the device control module 421 runs in a first thread, the lead module runs in a second thread, the filtering module 423 runs in a third thread, the noise reduction module 425 runs in a fourth thread, the waveform drawing module 427 runs in a fifth thread, the data visualization module 426 runs in a sixth thread, and the saving module 424 runs in a seventh thread, wherein the first thread, the second thread, the third thread, the fourth thread, the fifth thread, the sixth thread, and the seventh thread run in parallel. By running different functional modules 420 in different threads, it ensures efficient operation like a pipeline to achieve high-throughput data processing.

[0074] Optionally, in some embodiments, the specific content of the data processed by each functional module 420 is related to the functional module, for example, when the functional module 420 is the filtering module 423, the buffer corresponding to the functional module 420 stores data that needs to be filtered. For another example, when the functional module 420 is the noise reduction module 425, the buffer corresponding to the functional module 420 stores data that needs to be noise reduced. After receiving the running start signal from the system control module 410, each functional module 420 processes and transmits data according to the data stored in the buffer corresponding to the functional module 420 and the running logic.

[0075] Optionally, in some embodiments, the target functional module refers to the functional module 420 that needs to be processed, and the other functional module to which the data processed by the functional module 420 needs to flow. The data processed by the functional module 420 should be stored in the buffer corresponding to the target functional module.

[0076] It should be noted that the functional module 420 can be specifically determined according to the actual needs of the electroencephalogram acquisition and information processing system 1, and the embodiments of the present application are not limited.

[0077] It is particularly emphasized that the electroencephalogram acquisition and information processing system 1 provided by the application avoids the direct interaction of the host computer 400 with the massive electroencephalogram acquisition data by setting the control module 300, and provides a data processing transfer station and a temporary control core. At the same time, the business analysis process of the whole system is clear, different functional modules 420 are correspondingly set with different threads, and different threads run in parallel to improve the data processing efficiency. Different functional modules 420 are configured with corresponding independent buffer areas, and the running state of each functional module 420 is only controlled by the system control module 410 and is irrelevant to the upstream and downstream modules, so the control between the multiple functional modules 420 of the electroencephalogram acquisition and information processing system 1 provided by the application is completely decoupled. At the same time, the related data of a single functional module 420 is processed in the thread of the functional module 420, and only the processing result is output to the target functional module; and the data flow between the functional modules 420 is unidirectional, and there is no back-and-forth interaction between the data of the functional modules 420, so the data between the multiple functional modules 420 of the electroencephalogram acquisition and information processing system 1 provided by the application is also completely decoupled.

[0078] In summary, the electroencephalogram acquisition and information processing system 1 provided by the application has high stability and maintainability. In addition, the control and data between the functional modules 420 are decoupled, and each functional module 420 can be independently tested, facilitating the insertion of new modules or the upgrading of modules in the host computer 400. At the same time, the newly inserted modules or the upgraded modules can also be managed by the system control module 410, thereby enhancing the scalability of the electroencephalogram acquisition and information processing system 1.

[0079] Optionally, in some embodiments, after the start of the operation of the several functional modules 420, the data storage association information of the corresponding buffer area needs to be detected first, and when the data storage association information meets the predetermined condition, the data stored in the buffer area is subjected to data processing. The data in the buffer area of the functional module 420 can be sent by a hardware device or other functional modules, and the data sent by other functional modules is the data obtained after data processing by other functional modules.

[0080] Optionally, in some embodiments, the data storage association information refers to the information related to the data stored in the buffer area of the functional module 420. The data storage association information can include but is not limited to data volume, data type, data granularity, data source, etc.

[0081] Optionally, the aforementioned predetermined condition refers to the condition for triggering the data processing of the data stored in the buffer area of the functional module 420. The specific content of the predetermined condition can be adjusted according to the data storage association information and the actual situation, and the embodiments of the application are not limited.

[0082] In some embodiments, in a case where the data storage association information is a data source, the predetermined condition can include that the data source of the data in the buffer of the functional module 420 is a target data source.

[0083] Specifically, in a case where the data source of the data in the buffer of the functional module 420 is the target data source, the functional module 420 is triggered to perform data processing based on the data in its buffer.

[0084] Optionally, in some embodiments, the data storage association information is a data amount, and the predetermined condition includes that the data amount in the buffer is not less than a data amount threshold.

[0085] Specifically, in a case where the data amount in the buffer of the functional module 420 is not less than the data amount threshold, the functional module 420 is triggered to perform data processing based on the data in its buffer.

[0086] The data amount threshold can be set according to actual conditions. The data amount threshold can be a data amount for single processing, or the data amount threshold can be a data amount for single storage.

[0087] It should be noted that the data amount thresholds corresponding to different functional modules 420 can be the same or different.

[0088] Optionally, in some embodiments, in combination with Figure 2 As shown in FIG. 4, the target functional module of each functional module 420 is determined based on a data flow relationship between the functional modules 420, and the data flow relationship is unidirectional flow.

[0089] The data flow relationship is used to indicate the flow direction of data between the functional modules 420.

[0090] Optionally, in combination with Figure 1 and Figure 2 In some embodiments, the plurality of functional modules 420 can include one or more of a device control module 421, a lead calculation module 422, a filtering module 423, a saving module 424, a noise reduction module 425, a data visualization module 426, and a waveform drawing module 427.

[0091] The device control module 421 is used to abstract hardware devices, extract key factors, design corresponding control classes, implement instruction generation and analysis logic, and implement data flow analysis logic to achieve communication purposes.

[0092] In some embodiments, the device control module 421 is connected with the hardware device. The device control module 421 is used to send a running instruction to the hardware device after starting running, trigger the hardware device to collect data, and send the collected data to the device control module 421. Specifically, the system control module 410 sends a start running signal to each functional module 420, and after the device control module 421 receives the start running signal and starts running, the device control module 421 sends a running instruction to the hardware device, triggers the hardware device to collect data, and the hardware device sends the collected data to the device control module 421 after preprocessing and secondary processing, that is, the device control module 421 starts to continuously receive data from the hardware device. The hardware device refers to a device for collecting raw data of the electroencephalogram acquisition and information processing system 1. For example, the hardware corresponding to the electroencephalogram electrode 100, the acquisition front end 200, and the control module 300.

[0093] The lead calculation module 422 can support multiple reference methods of electroencephalogram signals such as multiple reference, single reference, and average reference, and can be flexibly configured according to actual needs.

[0094] The filter module 423 realizes software high-pass, low-pass, and notch filtering functions, and constructs a Butterworth filter to make all data flow through the filter to realize filtering functions.

[0095] The saving module 424 stores data as a file in EDF format.

[0096] It is particularly emphasized that in the entire system, the saving module 424 can be adaptively adjusted and set according to actual needs, and flexibly set after any functional module to store the data of the corresponding functional module as a file in EDF format.

[0097] The noise reduction module 425 uses various noise reduction methods to eliminate noise based on the characteristics of noise and artifacts in specific needs.

[0098] The data visualization module 426 can help users more intuitively understand the characteristics of electroencephalogram signals based on methods such as spectrograms and heat maps, and improve data analysis efficiency.

[0099] The waveform drawing module 427 provides rich settings, including channel spacing, horizontal and vertical coordinate scales, channel names, and waveform colors. According to the reference position of each channel, the horizontal and vertical coordinate scales, the data is calculated to obtain the corresponding drawing point position, and the waveform drawing is realized by repeating this process.

[0100] In particular, in some embodiments, in actual arrangement among various functional modules, some functional modules with less processing performance pressure can be combined, for example, the lead computing module 422 and the filtering module 423 are combined. In some embodiments, according to different functions required to be implemented by the host computer, only a part of the various functional modules 420 is selected, and the various functional modules can be flexibly pruned, combined and merged according to actual needs.

[0101] Optionally, in some embodiments, in combination with Figure 1 and Figure 2 It is shown that the data flow relationship of the electroencephalogram acquisition and information processing system 1 provided by the present application includes at least one of the following, which can be specifically seen from Figure 4 It is shown.

[0102] The data flow relationship can include a data flow relationship between the device control module 421 and the lead computing module 422, wherein the target functional module is the lead computing module 422.

[0103] Specifically, the device control module 421 parses the received data frame according to the data protocol, and based on the data flow relationship between the device control module 421 and the lead computing module 422, sends the data in the form of data stream into the buffer area of the lead computing module 422.

[0104] The data flow relationship can include a data flow relationship between the lead computing module 422 and the filtering module 423, wherein the target functional module is the filtering module 423.

[0105] Specifically, the lead computing module 422 polls the amount of data in the buffer area of the lead computing module 422 to reach a single processing threshold, reads the data from the buffer area of the lead module, and after completing the lead computation, based on the data flow relationship between the lead computing module 422 and the filtering module 423, sends the data into the buffer area of the filtering module 423.

[0106] The data flow relationship can include a data flow relationship between the lead module and the saving module 424, wherein the target functional module is the saving module 424.

[0107] Specifically, the lead computing module 422 polls that the amount of data in the buffer of the lead computing module 422 reaches the single processing threshold, reads the data from the buffer of the lead computing module 422, completes the lead computing, and based on the data flow relationship between the lead computing module 422 and the saving module 424, sends the data into the buffer of the saving module 424. In addition, the saving module 424 polls that the amount of data in the buffer of the saving module 424 reaches the single storage length, reads the data from the buffer of the saving module 424, and based on the lead computing data, stores the data as a file in EDF or the like format.

[0108] The data flow relationship can include a data flow relationship between the filtering module 423 and the noise reduction module 425, and the target function module is the noise reduction module 425.

[0109] Specifically, the filtering module 423 polls that the amount of data in the buffer of the filtering module 423 reaches the single processing threshold, reads the data from the buffer of the filtering module 423, completes the filtering processing, and based on the data flow relationship between the filtering module 423 and the noise reduction module 425, sends the data into the buffer of the noise reduction module 425.

[0110] The data flow relationship can include a data flow relationship between the filtering module 423 and the data visualization module 426, and the target function module is the data visualization module 426.

[0111] Specifically, the filtering module 423 polls that the amount of data in the buffer of the filtering module 423 reaches the single processing threshold, reads the data from the buffer of the filtering module 423, completes the filtering processing, and based on the data flow relationship between the filtering module 423 and the data visualization module 426, sends the data into the buffer of the data visualization module 426. In addition, the data visualization module 426 polls that the amount of data in the buffer of the data visualization module 426 reaches the single processing threshold, reads the data from the buffer of the data visualization module 426, and draws the corresponding data analysis chart.

[0112] The data flow relationship can include a data flow relationship between the noise reduction module 425 and the waveform drawing module 427, and the target function module is the waveform drawing module 427.

[0113] Specifically, the noise reduction module 425 polls to the situation that the amount of data in the buffer of the noise reduction module 425 reaches the single processing threshold, reads the data from the buffer of the noise reduction module 425, completes the noise reduction processing, and based on the data flow relationship between the noise reduction module 425 and the waveform drawing module 427, sends the data into the buffer of the waveform drawing module 427. In addition, the waveform drawing module 427 polls to the situation that the amount of data in the buffer of the waveform drawing module 427 reaches the single processing threshold, reads the data from the buffer of the waveform drawing module 427, and draws the corresponding waveform.

[0114] Optionally, in some embodiments, in combination with Figure 2 and Figure 3 As shown, the control module 300 itself executes the corresponding behavior according to the instructions sent by the host computer 400, and then sends the data results collected after the preprocessing and secondary processing to the host computer 400.

[0115] Specifically, the control module 300 includes an FPGA part 310 and an ARM part 320, and the control module 300 is configured with a respective independent control flow thread and a data flow thread.

[0116] In the control flow thread, the ARM part 320 receives the operation instruction sent by the host computer 400, and configures the FPGA part 310 with corresponding parameters according to the operation instruction. Further, after the FPGA part 310 completes the parameter configuration, it can control the running state of a plurality of acquisition front ends 200 and electroencephalogram electrodes 100 in turn, and finally control the electroencephalogram electrodes 100 to complete the electroencephalogram signal acquisition.

[0117] In the data flow thread, the ARM part 320 receives the running result of the operation instruction, and sends the running result to the host computer 400 after conversion. That is, the electroencephalogram signal collected after the control flow thread is run is transmitted to the FPGA part 310 after being preprocessed by a plurality of acquisition front ends 200, and the FPGA part 310 and the ARM part 320 complete the secondary processing of the preprocessed electroencephalogram signal data through AXI bus communication interaction, and then send it to the host computer 400.

[0118] Optionally, in some embodiments, the ARM part 320 includes an embedded subsystem, which plays a bridging role in the whole EEG acquisition and information processing system 1, can help the host computer 400 to control and manage the FPGA part 310, and at the same time share part of the functions that do not need continuous data transmission. For example, when the whole control module 300 is disconnected from the host computer 400, the ARM part 320 can temporarily act as the control core of the whole EEG acquisition and information processing system 1, maintain the normal work of the EEG electrode 100, the acquisition front end 200 and the control module 300, so as to ensure that the whole system function deployment is more reasonable, greatly improve the use freedom of the whole EEG acquisition and information processing system 1, and also support the off-bed flexible use of the whole EEG acquisition and information processing system 1.

[0119] Optionally, in some embodiments, the embedded subsystem is configured with virtual modules corresponding to system control function, FPGA control function and data control function, corresponding to target system control module 321, FPGA control module 322 and data control module 323 respectively.

[0120] Among them, the target system control module 321 is responsible for the overall operation of the ARM part 320 and the FPGA part 310, and the target system control module 321 can control the state of the FPGA control module 322 and the data control module 323.

[0121] The FPGA control module 322 is used to shield the configuration details of the FPGA part 310 for the target system control module 321, and provide an abstract control interface.

[0122] The data control module 323 is used to shield the data transmission details for the target system control module 321, and provide an abstract data reading interface.

[0123] Optionally, the ARM part 320 further includes a communication module 324, which shields the network connection and TCP protocol details for the target system control module 321, and provides an abstract communication interface to realize the communication interaction between the ARM part 320 and the host computer 400.

[0124] Optionally, in some embodiments, in combination with Figure 1 and Figure 2 As shown, the FPGA part 310 can simultaneously control multiple acquisition front ends 200 in parallel to realize high sampling rate and high passband signal acquisition. Specifically, the FPGA is connected and interacted with the acquisition front end 200 through a bidirectional SPI interface, can send acquisition instructions to the acquisition front end 200 at the same time, and collect preprocessed acquisition result data.

[0125] Optionally, in some embodiments, to achieve the required functions of the FPGA part 310, a running control state machine 311, an instruction sending state machine 312 and a data reading state machine 313 are arranged in the FPGA part 310.

[0126] The running control state machine 311 is configured as the master state machine of the whole FPGA part 310, and is connected and interacted with the FPGA control module 322 of the ARM part 320 through the AXI bus, and is responsible for not only the control of the instruction sending state machine 312 and the data reading state machine 313, but also the configuration of each item of the FPGA part 310, and manages the running state and running performance of the whole FPGA part 310.

[0127] The instruction sending state machine 312 sends instructions to the acquisition front end 200 according to different task configurations of the running control state machine, such as acquisition chip calibration, chip signal verification, impedance test, data acquisition, etc., and different task configurations will configure different instruction sequences.

[0128] The data reading state machine 313 receives the instruction running results returned by the acquisition front end 200, and also completes the serial-parallel conversion and preliminary screening of data.

[0129] It is particularly pointed out that the FPGA control module 322 communicates with the instruction sending state machine 312 through the AXI bus to realize the control flow thread, and further, the FPGA control module 322 realizes it by directly reading and writing the registers in the FPGA part 310, and the instruction sending state machine 312 can perform corresponding register configuration; the data reading state machine 313 communicates with the data control module 323 through the direct memory (Direct Memory Access, DMA) data transmission to realize the data flow thread.

[0130] Optionally, in some embodiments, in combination with Figure 2 and Figure 3 As shown, high-frequency multi-channel continuous sampling will continuously generate a large amount of data, and the embedded subsystem in the ARM part 320 is a non-real-time system, in order to ensure smooth transmission of data, the data needs to be buffered to avoid data loss due to insufficient transmission to the host computer 400, so the control module 300 further includes a storage submodule 325 connected with the ARM part 320, and the storage submodule 325 ensures that there is sufficient buffer space to temporarily store data in high-speed real-time signal sampling.

[0131] Optionally, the storage medium of the storage submodule 325 can adopt a TF card (Micro SD Card) or the like, and the use of the TF card is more conducive to the miniaturization of the whole device and has lower power consumption.

[0132] Optionally, in some embodiments, in combination withFigure 2 and Figure 3 As shown in FIG. 3, to ensure that there is sufficient buffer space to temporarily store data in high-speed real-time signal acquisition, the control module 300 further comprises a data buffering sub-module 314 connected to the FPGA part 310. Optionally, the data buffering sub-module 314 can use chips, hard disks, TF cards, etc. to construct a hardware buffer, such as DDR3, DDR4 chips, etc., which can effectively alleviate the pressure caused by the time difference between data processing and transmission in the management terminal.

[0133] Optionally, at the same time, since high-throughput real-time acquisition of electroencephalogram signals will generate a large amount of data, which will have a great test on the real-time data throughput and processing capacity of the electroencephalogram acquisition and signal processing system, in order to ensure smooth transmission of data, the control module 300 comprises a data buffer, and a plurality of micro buffers for adjusting data bit width and smooth timing can be arranged before and after the data buffer to jointly form a multi-level buffer structure. Data is stored in the multi-level buffer structure to assist in data buffering.

[0134] Optionally, in some embodiments, the electroencephalogram acquisition and information processing system 1 can further comprise a user interaction interface.

[0135] The user interaction interface refers to an interface that can be displayed on the electroencephalogram acquisition and information processing system 1 for user interaction.

[0136] Therefore, in response to a running event initiated by the user interaction interface, a running start signal is sent to each function module 420 through the system control module 410 to trigger the function module 420 to start running.

[0137] The content of the running event can be various, which can be adjusted according to actual conditions, and the embodiments of the present application are not limited.

[0138] The above running event can be triggered based on a touch operation of the user on the user interaction interface. The touch operation can include a click operation or a touch operation of the user on a running switch on the user interaction interface, which can be adjusted according to actual conditions, and the embodiments of the present application are not limited. The running switch can be a total switch of the electroencephalogram acquisition and information processing system 1, or a switch on the interface of a certain function module 420 in the electroencephalogram acquisition and information processing system 1.

[0139] The above running event can also be a specific voice received by the user interaction interface, which wakes up the electroencephalogram acquisition and information processing system 1 based on the specific voice to send a running start signal to each function module 420 through the system control module 410 to trigger the function module 420 to start running.

[0140] Exemplarily, after the user clicks the run button through the user interaction interface, the system control module 410 sends a run start signal to each functional module 420, and the thread corresponding to each functional module 420 starts polling the data amount of the corresponding buffer. The device control module 421 sends an instruction to the hardware device to start data collection, and parses the data frame according to the protocol and sends it to the buffer of the lead calculation module 422. The lead calculation module 422, the filtering module 423, the noise reduction module 425, etc. poll the buffer in turn, perform corresponding calculation after reaching the processing threshold, and transmit the result to the target functional module buffer. The waveform drawing module 427 and the data visualization module 426 draw waveforms and charts according to the buffer data. When the save module 424 polls to the storage length threshold, it reads the buffer data and stores it as an EDF format file based on the lead calculation result. Asynchronous communication is realized through independent buffers to ensure the continuity and real-time performance of data processing. The system control module 410 coordinates the operation of each module through state checking and control instructions.

[0141] Optionally, in some embodiments, referring to Figure 5 The information processing method provided by the application is applied to the electroencephalogram acquisition and information processing system 1, and the specific structure of the electroencephalogram acquisition and information processing system 1 corresponds to the foregoing structure, which will not be described here. The information processing method can include the following steps S01 to S02.

[0142] Step S01, through the system control module 410 of the host computer 400, the operation instruction is sent to the control module 300 to control a plurality of electroencephalogram electrodes 100 to start collecting electroencephalogram signals.

[0143] Step S02, the collected electroencephalogram signals are transmitted to the host computer 400 after pre-processing by the acquisition front end 200 and secondary processing by the control module 300, and the host computer 400 stores the received electroencephalogram signals in the buffer, and performs data processing based on the data in the corresponding buffer through the functional module 420.

[0144] Optionally, the processing flow of the information processing method of the entire electroencephalogram acquisition and information processing system 1 is further briefly described, and the specific content is as follows:

[0145] First step: control the system control module 410 of the host computer 400, and send the operation instruction of starting running to each functional module 420. According to the running state checking, the thread corresponding to each functional module 420 starts polling the buffer data amount in the corresponding buffer, and starts working;

[0146] Second step: the device control module 421 sends start running instructions to the hardware devices (i.e. the control module 300, the acquisition front end 200, and the electroencephalogram electrode 100, etc.) in turn, that is, the electroencephalogram electrode 100 starts to continuously collect electroencephalogram signals through the control flow thread;

[0147] Third step: the electroencephalogram signals collected by the electroencephalogram electrode 100 are subjected to digital pretreatment such as amplification, filtering, analog-to-digital conversion, etc. of weak electroencephalogram signals by the acquisition front end 200, and secondary processing such as data serial-to-parallel conversion, data preliminary screening, data frame construction, data caching, data transmission conversion, etc. of the data after digital pretreatment by the control module 300, that is, the data after data processing is continuously sent to the device control module 421 through the data flow thread;

[0148] Fourth step: the device control module 421 continuously receives data, parses, verifies and repairs the received data frames according to the data protocol, and sends them into the corresponding buffer area of the lead calculation module 422 in the form of data flow;

[0149] Fifth step: when the lead calculation module 422 polls the data amount in the corresponding buffer area to reach the single processing threshold, it reads the data from the corresponding buffer area, completes lead calculation, and sends the data into the buffer area of the filtering module 423;

[0150] Sixth step: when the filtering module 423 polls the data amount in the corresponding buffer area to reach the single processing threshold, it reads the data from the corresponding buffer area, completes filtering calculation, and sends the data into the buffer area of the noise reduction module 425 and the buffer area of the data visualization module 426 respectively;

[0151] Seventh step: when the noise reduction module 425 polls the data amount in the corresponding buffer area to reach the single processing threshold, it reads the data from the corresponding buffer area, performs noise reduction processing, and sends the data into the buffer area of the waveform drawing module 427;

[0152] Eighth step: when the data visualization module 426 polls the data amount in the corresponding buffer area to reach the single processing threshold, it reads the data from the corresponding buffer area, and draws the corresponding data analysis chart;

[0153] Ninth step: when the waveform drawing module 427 polls the data amount in the corresponding buffer area to reach the single processing threshold, it reads the data from the corresponding buffer area, and draws the corresponding waveform;

[0154] Tenth step: when the saving module 424 polls the data amount in the corresponding buffer area to reach the single storage length, it reads the data from the corresponding buffer area, and stores the data as a file in EDF format, etc.

[0155] It needs to be emphasized that in the whole brain electrical signal acquisition and information processing system 1, when the acquired brain electrical signals are processed by the foregoing information processing method, the system control module 410 coordinates the operation of each module through state checking and control instructions; each functional module 420 is configured with a corresponding buffer by setting different threads among the functional modules 420, and the threads among the different functional modules 420 are parallel, and the control and data among the plurality of functional modules 420 are completely decoupled, which can well realize asynchronous communication and ensure the continuity and real-time performance of data processing.

[0156] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by a computer program, or by a computer program controlling related hardware, which can be stored in a storage medium and loaded and executed by a processor.

[0157] To this end, the present application provides a computer readable storage medium, which stores a computer program capable of being loaded by a processor to execute the steps in any information processing method provided by the embodiments of the present application.

[0158] For example, the computer program can execute the following steps:

[0159] The system control module 410 of the host computer 400 sends the operation instruction to the control module 300 to control a plurality of brain electrical signal electrodes 100 to start collecting brain electrical signals.

[0160] The collected brain electrical signals are transmitted to the host computer 400 after pre-processing by the acquisition front end 200 and secondary processing by the control module 300, and the host computer 400 stores the received brain electrical signals in the buffer area and performs data processing based on the data in the corresponding buffer area by the functional module 420.

[0161] The specific implementation and corresponding benefits of the above operations can be referred to the foregoing embodiments, which will not be described here.

[0162] The computer readable storage medium can include a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0163] According to an aspect of the present application, a computer program product or computer program is provided, which includes computer instructions stored in a storage medium. The processor of the computer device reads the computer instructions from the storage medium, and the processor executes the computer instructions to make the computer device execute the above information processing method.

[0164] The above describes in detail the electroencephalogram acquisition and information processing system 1, the information processing method and the computer readable storage medium provided by the present application. The principles and implementation modes of the present application are described by applying specific examples. The above example is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A brainwave acquisition and information processing system, characterized in that, The system includes: Several EEG electrodes are connected to the brain of an organism to detect brain electrical signals; Several acquisition front-ends are connected to the corresponding EEG electrodes to acquire EEG signals and preprocess the acquired EEG signals; The control module is connected to several of the aforementioned acquisition front-ends and performs secondary processing on the preprocessed EEG signals. The host computer communicates and interacts with the control module, receiving the secondary processed EEG signals and performing data processing, wherein... The host computer includes a system control module and several functional modules that communicate and interact with the system control module. The system control module sends operation instructions to each of the functional modules, triggering the functional modules to start running and process the data; The functional modules correspond to different threads, which run in parallel. Each functional module is configured with a corresponding independent buffer, which is used to store the data that the corresponding functional module needs to process. After a single functional module completes data processing in its corresponding thread, it can send the processing result to the buffer of the target functional module.

2. The electroencephalogram acquisition and information processing system according to claim 1, wherein, After the aforementioned functional modules start running, they need to first detect the data storage association information of the corresponding buffer. When the data storage association information meets the predetermined conditions, data processing is performed on the data stored in the buffer. The data in the buffer of the functional module is sent by the hardware device or other functional modules, and the data sent by the other functional modules is the data obtained after the other functional modules have performed data processing.

3. The EEG acquisition and information processing system according to claim 2, characterized in that, The data storage association information is the data volume, and the predetermined conditions include that the data volume in the buffer is not less than the data volume threshold.

4. The EEG acquisition and information processing system according to claim 1, characterized in that, The target functional module corresponding to each of the aforementioned functional modules is determined based on the data flow relationship between the functional modules, and the data flow relationship is unidirectional.

5. The EEG acquisition and information processing system according to claim 4, characterized in that, The functional modules include one or more of the following: device control module, lead calculation module, filtering module, storage module, noise reduction module, data visualization module, and waveform drawing module; The data flow relationship includes at least one of the following: The data flow relationship between the device control module and the lead calculation module, wherein the target functional module is the lead calculation module; The data flow relationship between the lead calculation module and the filtering module, wherein the target functional module is the filtering module; The data flow relationship between the lead calculation module and the storage module, wherein the target functional module is the storage module; The data flow relationship between the filtering module and the noise reduction module, wherein the target functional module is the noise reduction module; The data flow relationship between the filtering module and the data visualization module, wherein the target functional module is the data visualization module; The data flow relationship between the noise reduction module and the waveform drawing module, wherein the target functional module is the waveform drawing module.

6. The EEG acquisition and information processing system according to claim 1, characterized in that, The control module includes an ARM part and an FPGA part. The control module is configured with its own independent control flow thread and data flow thread. In the control flow thread, the ARM part receives the operation instructions sent by the host computer and configures the corresponding parameters of the FPGA part according to the operation instructions. In the data flow thread, the ARM part receives the execution result of the operation instructions, converts the execution result and sends it to the host computer.

7. The EEG acquisition and information processing system according to claim 6, characterized in that, The ARM portion includes an FPGA control module and a data control module. The FPGA portion includes an instruction sending state machine and a data reading state machine. The FPGA control module communicates with the instruction sending state machine via an AXI bus to implement the control flow thread. The data reading state machine communicates with the data control module via DMA data transfer to implement the data flow thread.

8. The EEG acquisition and information processing system according to claim 7, characterized in that, The control module further includes a storage submodule and a data buffer submodule to ensure sufficient buffer space for temporary data storage during high-speed real-time signal acquisition. The storage submodule is connected to the ARM section, and the data buffer submodule is connected to the FPGA section.

9. The EEG acquisition and information processing system according to claim 1, characterized in that, The preprocessing of the EEG signals includes amplification, filtering, and digital processing of weak EEG signals through analog-to-digital conversion; the secondary processing of the EEG signals includes serial-to-parallel conversion of data, preliminary data screening, construction of data frames, data buffering, and data transmission conversion.

10. An information processing method, characterized in that, The information processing method is applied to the EEG acquisition and information processing system as described in any one of claims 1-9, and the method includes: The operation command is sent to the control module through the system control module of the host computer to control the several EEG electrodes to start collecting EEG signals. The acquired EEG signals are preprocessed by the acquisition front-end and then processed by the control module before being transmitted to the host computer. The host computer stores the received EEG signals in the buffer and performs data processing based on the data in the corresponding buffer through the functional module.

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